OpenCores
URL https://opencores.org/ocsvn/mlite/mlite/trunk

Subversion Repositories mlite

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 72 to Rev 73
    ↔ Reverse comparison
  •

Rev 72 → Rev 73

/trunk/vhdl/mlite_cpu.vhd
30,11 → 30,14
-- c_bus onto reg_dest.
-- 8. Based on the rd_index control signal, "reg_bank" saves
-- reg_dest into the correct register.
-- The CPU is implemented as a two stage pipeline with step #1 in the
-- first stage and steps #2-8 occuring the second stage.
-- The CPU is implemented as a two/three stage pipeline with step #1 in
-- the first stage and steps #2-#8 occuring the second stage. When
-- operating with a three stage pipeline, steps #6-#8 occur in the
-- third stage.
--
-- Writing to memory takes four cycles to meet RAM address hold times.
-- Addresses with a(31)='1' take two cycles (assumed to be clocked).
-- Writing to high memory where a(31)='1' takes four cycles to meet RAM
-- address hold times.
-- Addresses with a(31)='0' are assumed to be clocked and take two cycles.
-- Here are the signals for writing a character to address 0xffff:
--
-- mem_write
44,21 → 47,18
-- ===========================================
-- 6700 0 0 0 000002A4 ZZZZZZZZ A0AE0000 0 0 ( fetch write opcode)
-- 6800 0 0 0 000002B0 ZZZZZZZZ 0443FFF6 0 0 (1 fetch NEXT opcode)
-- 6900 0 0 1 0000FFFF 31313131 ZZZZZZZZ 0 0 (2 address hold)
-- 7000 0 0 1 0000FFFF 31313131 ZZZZZZZZ 0 1 (3 write the low byte)
-- 7100 0 0 1 0000FFFF 31313131 ZZZZZZZZ 0 0 (4 address hold)
-- 7200 0 0 0 000002B4 ZZZZZZZZ 00441806 0 0 ( execute NEXT opcode)
--
-- The CPU core was synthesized for 0.13 um line widths with an area
-- of 0.2 millimeters squared. The maximum latency was less than 6 ns
-- for a maximum clock speed of 150 MHz.
-- 6900 0 0 1 0000FFFF 31313131 ZZZZZZZZ 0 1 (2 write the low byte)
-- 7000 0 0 0 000002B4 ZZZZZZZZ 00441806 0 0 ( execute NEXT opcode)
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
 
entity mlite_cpu is
generic(memory_type : string := "ALTERA");
generic(memory_type : string := "ALTERA";
pipeline_stages : natural := 3;
accurate_timing : boolean := false);
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
72,20 → 72,39
end; --entity mlite_cpu
 
architecture logic of mlite_cpu is
--When using a two stage pipeline "sigD <= sig".
--When using a three stage pipeline "sigD <= sig when rising_edge(clk)",
-- so sigD is delayed by one clock cycle.
signal opcode : std_logic_vector(31 downto 0);
signal rs_index, rt_index, rd_index : std_logic_vector(5 downto 0);
signal reg_source, reg_target, reg_dest : std_logic_vector(31 downto 0);
signal a_bus, b_bus, c_bus : std_logic_vector(31 downto 0);
signal c_alu, c_shift, c_mult, c_memory
: std_logic_vector(31 downto 0);
signal rs_index : std_logic_vector(5 downto 0);
signal rt_index : std_logic_vector(5 downto 0);
signal rd_index : std_logic_vector(5 downto 0);
signal rd_indexD : std_logic_vector(5 downto 0);
signal reg_source : std_logic_vector(31 downto 0);
signal reg_target : std_logic_vector(31 downto 0);
signal reg_dest : std_logic_vector(31 downto 0);
signal reg_destD : std_logic_vector(31 downto 0);
signal a_bus : std_logic_vector(31 downto 0);
signal a_busD : std_logic_vector(31 downto 0);
signal b_bus : std_logic_vector(31 downto 0);
signal b_busD : std_logic_vector(31 downto 0);
signal c_bus : std_logic_vector(31 downto 0);
signal c_alu : std_logic_vector(31 downto 0);
signal c_shift : std_logic_vector(31 downto 0);
signal c_mult : std_logic_vector(31 downto 0);
signal c_memory : std_logic_vector(31 downto 0);
signal imm : std_logic_vector(15 downto 0);
signal pc : std_logic_vector(31 downto 0);
signal pc_plus4 : std_logic_vector(31 downto 0);
signal alu_function : alu_function_type;
signal shift_function : shift_function_type;
signal mult_function : mult_function_type;
signal branch_function: branch_function_type;
signal alu_func : alu_function_type;
signal alu_funcD : alu_function_type;
signal shift_func : shift_function_type;
signal shift_funcD : shift_function_type;
signal mult_func : mult_function_type;
signal mult_funcD : mult_function_type;
signal branch_func : branch_function_type;
signal take_branch : std_logic;
signal take_branchD : std_logic;
signal a_source : a_source_type;
signal b_source : b_source_type;
signal c_source : c_source_type;
92,84 → 111,94
signal pc_source : pc_source_type;
signal mem_source : mem_source_type;
signal pause_mult : std_logic;
signal pause_memory : std_logic;
signal pause : std_logic;
signal pause_ctrl : std_logic;
signal pause_pipeline : std_logic;
signal pause_any : std_logic;
signal pause_non_ctrl : std_logic;
signal pause_bank : std_logic;
signal nullify_op : std_logic;
signal intr_enable : std_logic;
signal intr_signal : std_logic;
signal reset_reg : std_logic;
signal reset_reg : std_logic_vector(3 downto 0);
signal reset : std_logic;
begin --architecture
 
pause <= pause_mult or pause_memory;
pause_any <= (mem_pause or pause_ctrl) or (pause_mult or pause_pipeline);
pause_non_ctrl <= (mem_pause or pause_mult) or pause_pipeline;
pause_bank <= (mem_pause or pause_ctrl or pause_mult) and not pause_pipeline;
nullify_op <= '1' when pc_source = from_lbranch and
(take_branch = '0' or branch_function = branch_yes) else
(take_branchD = '0' or branch_func = branch_yes) else
'0';
c_bus <= c_alu or c_shift or c_mult;
reset <= reset_in or reset_reg;
reset <= '1' when reset_in = '1' or reset_reg /= "1111" else '0';
 
--synchronize reset and interrupt pins
intr_proc: process(clk, reset_in, intr_in, intr_enable, pc_source, pc, pause)
begin
if rising_edge(clk) then
reset_reg <= reset_in;
--don't try to interrupt a multi-cycle instruction
if intr_in = '1' and intr_enable = '1' and
pc_source = from_inc4 and
pc(2) = '0' and
pause = '0' then
--the epc will be backed up one opcode (pc-4)
intr_signal <= '1';
else
intr_signal <= '0';
--synchronize reset and interrupt pins
intr_proc: process(clk, reset_in, intr_in, intr_enable, pc_source, pc, pause_any)
begin
if reset_in = '1' then
reset_reg <= "0000";
elsif rising_edge(clk) then
if reset_reg /= "1111" then
reset_reg <= reset_reg + 1;
end if;
end if;
end if;
end process;
if rising_edge(clk) then
--don't try to interrupt a multi-cycle instruction
if intr_in = '1' and intr_enable = '1' and
pc_source = from_inc4 and pc(2) = '0' and
pause_any = '0' then
--the epc will be backed up one opcode (pc-4)
intr_signal <= '1';
else
intr_signal <= '0';
end if;
end if;
end process;
 
u1_pc_next: pc_next PORT MAP (
clk => clk,
reset_in => reset,
take_branch => take_branch,
pause_in => pause,
pc_new => c_alu(31 downto 2),
take_branch => take_branchD,
pause_in => pause_any,
pc_new => c_bus(31 downto 2),
opcode25_0 => opcode(25 downto 0),
pc_source => pc_source,
pc_out => pc,
pc_out_plus4 => pc_plus4);
 
u2_mem_ctrl: mem_ctrl PORT MAP (
u2_mem_ctrl: mem_ctrl
generic map (ACCURATE_TIMING => accurate_timing)
PORT MAP (
clk => clk,
reset_in => reset,
pause_in => pause,
pause_in => pause_non_ctrl,
nullify_op => nullify_op,
address_pc => pc,
opcode_out => opcode,
 
address_data => c_alu,
address_data => c_bus,
mem_source => mem_source,
data_write => reg_target,
data_read => c_memory,
pause_out => pause_memory,
pause_out => pause_ctrl,
mem_address => mem_address,
mem_data_w => mem_data_w,
mem_data_r => mem_data_r,
mem_byte_sel => mem_byte_sel,
mem_write => mem_write,
mem_pause => mem_pause);
mem_write => mem_write);
 
u3_control: control PORT MAP (
opcode => opcode,
intr_signal => intr_signal,
pause_in => pause,
rs_index => rs_index,
rt_index => rt_index,
rd_index => rd_index,
imm_out => imm,
alu_func => alu_function,
shift_func => shift_function,
mult_func => mult_function,
branch_func => branch_function,
alu_func => alu_func,
shift_func => shift_func,
mult_func => mult_func,
branch_func => branch_func,
a_source_out => a_source,
b_source_out => b_source,
c_source_out => c_source,
181,12 → 210,13
port map (
clk => clk,
reset_in => reset,
pause => pause_bank,
rs_index => rs_index,
rt_index => rt_index,
rd_index => rd_index,
rd_index => rd_indexD,
reg_source_out => reg_source,
reg_target_out => reg_target,
reg_dest_new => reg_dest,
reg_dest_new => reg_destD,
intr_enable => intr_enable);
 
u5_bus_mux: bus_mux port map (
206,21 → 236,21
c_mux => c_source,
reg_dest_out => reg_dest,
 
branch_func => branch_function,
branch_func => branch_func,
take_branch => take_branch);
 
u6_alu: alu
generic map (adder_type => memory_type)
port map (
a_in => a_bus,
b_in => b_bus,
alu_function => alu_function,
a_in => a_busD,
b_in => b_busD,
alu_function => alu_funcD,
c_alu => c_alu);
 
u7_shifter: shifter port map (
value => b_bus,
shift_amount => a_bus(4 downto 0),
shift_func => shift_function,
value => b_busD,
shift_amount => a_busD(4 downto 0),
shift_func => shift_funcD,
c_shift => c_shift);
 
u8_mult: mult
227,11 → 257,60
generic map (adder_type => memory_type)
port map (
clk => clk,
a => a_bus,
b => b_bus,
mult_func => mult_function,
a => a_busD,
b => b_busD,
mult_func => mult_funcD,
c_mult => c_mult,
pause_out => pause_mult);
 
pipeline2: if pipeline_stages <= 2 generate
a_busD <= a_bus;
b_busD <= b_bus;
alu_funcD <= alu_func;
shift_funcD <= shift_func;
mult_funcD <= mult_func;
rd_indexD <= rd_index;
 
reg_destD <= reg_dest;
take_branchD <= take_branch;
pause_pipeline <= '0';
end generate; --pipeline2
 
pipeline3: if pipeline_stages >= 3 generate
--When operating in three stage pipeline mode, the following signals
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
--c_source, and rd_index.
u9_pipeline: pipeline port map (
clk => clk,
reset => reset,
a_bus => a_bus,
a_busD => a_busD,
b_bus => b_bus,
b_busD => b_busD,
alu_func => alu_func,
alu_funcD => alu_funcD,
shift_func => shift_func,
shift_funcD => shift_funcD,
mult_func => mult_func,
mult_funcD => mult_funcD,
reg_dest => reg_dest,
reg_destD => reg_destD,
rd_index => rd_index,
rd_indexD => rd_indexD,
 
rs_index => rs_index,
rt_index => rt_index,
pc_source => pc_source,
mem_source => mem_source,
a_source => a_source,
b_source => b_source,
c_source => c_source,
c_bus => c_bus,
take_branch => take_branch,
take_branchD => take_branchD,
pause_any => pause_any,
pause_pipeline => pause_pipeline);
end generate; --pipeline3
 
end; --architecture logic
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.