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URL https://opencores.org/ocsvn/pci/pci/trunk

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Rev 72 → Rev 73

/trunk/bench/verilog/pci_unsupported_commands_master.v
15,37 → 15,68
PAR
);
 
parameter normal = 0 ;
parameter disconnect = 1 ;
parameter retry = 2 ;
parameter target_abort = 3 ;
parameter master_abort = 4 ;
parameter error = 5 ;
 
input CLK ;
output [31:0] AD ;
output [3:0] CBE ;
inout [31:0] AD ;
inout [3:0] CBE ;
input RST ;
output REQ ;
input GNT ;
output FRAME ;
output IRDY ;
inout FRAME ;
inout IRDY ;
input DEVSEL ;
input TRDY ;
input STOP ;
output PAR ;
inout PAR ;
 
reg [31:0] AD ;
reg [3:0] CBE ;
reg [31:0] AD_int ;
reg AD_en ;
 
reg [3:0] CBE_int ;
reg CBE_en ;
 
reg FRAME_int ;
reg FRAME_en ;
 
reg IRDY_int ;
reg IRDY_en ;
 
reg PAR_int ;
reg PAR_en ;
 
assign AD = AD_en ? AD_int : 32'hzzzz_zzzz ;
assign CBE = CBE_en ? CBE_int : 4'hz ;
assign FRAME = FRAME_en ? FRAME_int : 1'bz ;
assign IRDY = IRDY_en ? IRDY_int : 1'bz ;
assign PAR = PAR_en ? PAR_int : 1'bz ;
 
reg REQ ;
reg FRAME ;
reg IRDY ;
reg PAR ;
 
event e_finish_transaction ;
event e_transfers_done ;
 
reg write ;
reg make_parity_error_after_last_dataphase ;
 
initial
begin
REQ = 1'b1 ;
AD = 32'hzzzz_zzzz ;
CBE = 4'bzzzz ;
FRAME = 1'bz ;
IRDY = 1'bz ;
PAR = 1'bz ;
REQ = 1'b1 ;
AD_en = 1'b0 ;
CBE_en = 1'b0 ;
FRAME_en = 1'b0 ;
IRDY_en = 1'b0 ;
PAR_en = 1'b0 ;
write = 1'b0 ;
make_parity_error_after_last_dataphase = 1'b0 ;
end
 
task master_reference ;
task unsupported_reference ;
input [31:0] addr1 ;
input [31:0] addr2 ;
input [3:0] bc1 ;
57,88 → 88,360
output ok ;
integer i ;
reg dual_address ;
begin
reg [2:0] received_termination ;
begin:main
ok = 1 ;
dual_address = (bc1 == `BC_DUAL_ADDR_CYC) ;
@(posedge CLK) ;
while( GNT == 1 )
 
get_bus_ownership(ok) ;
if (ok !== 1'b1)
disable main ;
 
addr_phase1(addr1, bc1) ;
 
if ( dual_address )
begin
REQ <= #1 1'b0 ;
@(posedge CLK) ;
write = bc2[0] ;
addr_phase2(addr2, bc2, make_addr_perr1) ;
first_and_last_data_phase(bc2[0], data, be, make_addr_perr2, 1'b0, received_termination) ;
finish_transaction(bc2[0], 1'b0) ;
end
else
begin
write = bc1[0] ;
first_and_last_data_phase(bc1[0], data, be, make_addr_perr1, 1'b0, received_termination) ;
finish_transaction(bc1[0], 1'b0) ;
end
 
REQ <= #1 1'b1 ;
FRAME <= #1 1'b0 ;
AD <= #1 addr1 ;
CBE <= #1 bc1 ;
if (received_termination !== master_abort)
begin
ok = 0 ;
end
end
endtask // master_reference
 
// end of first address cycle
@(posedge CLK) ;
PAR <= #1 ^{AD, CBE, make_addr_perr1} ;
if ( dual_address )
// task added for target overflow testing
// master writes the addresses to the coresponding locations
task normal_write_transfer ;
input [31:0] start_address ;
input [3:0] bus_command ;
input [31:0] size ;
input [2:0] wait_cycles ;
output [31:0] actual_transfer ;
output [2:0] received_termination ;
reg ok ;
reg [31:0] current_address ;
begin:main
 
write = 1'b1 ;
get_bus_ownership (ok) ;
if (ok !== 1'b1)
begin
IRDY <= #1 1'b1 ;
AD <= #1 addr2 ;
CBE <= #1 bc2 ;
received_termination = error ;
disable main ;
end
 
make_parity_error_after_last_dataphase = 1'b0 ;
 
addr_phase1(start_address, bus_command) ;
actual_transfer = 0 ;
if (size == 1)
begin
first_and_last_data_phase (1'b1, ~start_address, 4'hF, 1'b0, 1'b0, received_termination) ;
if ((received_termination == normal) || (received_termination == disconnect))
actual_transfer = 1 ;
 
-> e_finish_transaction ;
end
else
begin
IRDY <= #1 1'b0 ;
FRAME <= #1 1'b1 ;
CBE <= #1 be ;
if ( bc1[0] )
AD <= #1 data ;
current_address = start_address ;
first_data_phase (1'b1, ~start_address, 4'hF, 1'b0, 1'b0, received_termination) ;
if ((received_termination == normal) || (received_termination == disconnect))
actual_transfer = 1 ;
 
if (received_termination == master_abort)
begin
-> e_transfers_done ;
end
 
while ((actual_transfer < (size - 1)) && (received_termination == normal))
begin
current_address = current_address + 4 ;
insert_waits(1'b1, wait_cycles, received_termination) ;
if (received_termination === normal)
begin
subsequent_data_phase(1'b1, ~current_address, 4'hF, 1'b0, received_termination) ;
if ((received_termination == normal) || (received_termination == disconnect))
actual_transfer = actual_transfer + 1 ;
end
end
 
if (received_termination == normal)
begin
insert_waits(1'b1, wait_cycles, received_termination) ;
if (received_termination === normal)
begin
last_data_phase(1'b1, ~current_address, 4'hF, 1'b0, received_termination) ;
if ((received_termination == normal) || (received_termination == disconnect))
actual_transfer = actual_transfer + 1 ;
-> e_finish_transaction ;
end
else
-> e_transfers_done ;
end
else
AD <= #1 32'hzzzz_zzzz ;
-> e_transfers_done ;
end
end
endtask // normal_write_transfer
 
task get_bus_ownership ;
output ok ;
integer deadlock ;
begin
deadlock = 0 ;
@(posedge CLK) ;
CBE <= #1 be ;
if ( dual_address )
while( ((GNT !== 0) || (FRAME !== 1'b1) || (IRDY !== 1'b1)) && (deadlock < 5000) )
begin
PAR <= #1 ^{AD, CBE, make_addr_perr2} ;
IRDY <= #1 1'b0 ;
FRAME <= #1 1'b1 ;
if ( bc2[0] )
AD <= #1 data ;
else
AD <= #1 32'hzzzz_zzzz ;
REQ <= #6 1'b0 ;
@(posedge CLK) ;
deadlock = deadlock + 1 ;
end
 
if (GNT !== 0)
begin
$display("*E, PCI Master could not get ownership of the bus in 5000 cycles") ;
ok = 0 ;
end
else
begin
if ( bc1[0] )
PAR <= #1 ^{AD, CBE} ;
else
PAR <= #1 1'bz ;
ok = 1 ;
end
 
REQ <= #6 1'b1 ;
end
endtask // get_bus_ownership
 
task addr_phase1 ;
input [31:0] address ;
input [3:0] bus_command ;
begin
FRAME_en <= #6 1'b1 ;
FRAME_int <= #6 1'b0 ;
 
AD_en <= #6 1'b1 ;
AD_int <= #6 address ;
 
CBE_en <= #6 1'b1 ;
CBE_int <= #6 bus_command ;
@(posedge CLK) ;
if ( AD[31] !== 1'bz )
PAR <= #1 ^{AD, CBE} ;
end
endtask // addr_phase1
 
task addr_phase2 ;
input [31:0] address ;
input [3:0] bus_command ;
input make_parity_error;
begin
PAR_int <= #6 ^{AD, CBE, make_parity_error} ;
PAR_en <= #6 1'b1 ;
AD_int <= #6 address ;
CBE_int <= #6 bus_command ;
@(posedge CLK) ;
end
endtask
 
task first_and_last_data_phase ;
input rw ;
input [31:0] data ;
input [3:0] be ;
input make_addr_parity_error ;
input make_data_parity_error ;
output [2:0] received_termination ;
integer i ;
begin
FRAME_int <= #6 1'b1 ;
first_data_phase (rw, data, be, make_addr_parity_error, make_data_parity_error, received_termination) ;
end
endtask // first_and_last_data_phase
 
task first_data_phase ;
input rw ;
input [31:0] data ;
input [3:0] be ;
input make_addr_parity_error ;
input make_data_parity_error ;
output [2:0] received_termination ;
integer i ;
begin
PAR_int <= #6 ^{AD, CBE, make_addr_parity_error} ;
PAR_en <= #6 1'b1 ;
IRDY_en <= #6 1'b1 ;
IRDY_int <= #6 1'b0 ;
CBE_int <= #6 be ;
if (rw)
AD_int <= #6 data ;
else
PAR <= #1 1'bz ;
AD_en <= #6 1'b0 ;
 
i = 0 ; // Checking for Master Abort
while ( (DEVSEL === 1) && (STOP === 1) && (i < 6) )
@(posedge CLK) ;
if (!rw)
PAR_en <= #6 1'b0 ;
else
PAR_int <= #6 ^{AD, CBE, make_data_parity_error} ;
 
i = 1 ;
while ( (i < 5) && (DEVSEL === 1'b1) )
begin
@(posedge CLK) ;
i = i + 1 ;
end
 
if ( (DEVSEL !== 1) || (STOP !== 1) )
if (DEVSEL === 1'b1)
begin
ok = 0 ; // If NO Master abort, then NOT OK!
received_termination = master_abort ;
end
else
begin
get_termination(received_termination);
end
end
endtask // first_data_phase
 
FRAME <= #1 1'bz ;
IRDY <= #1 1'b1 ;
AD <= #1 32'hzzzz_zzzz ;
CBE <= #1 4'hz ;
task subsequent_data_phase ;
input rw ;
input [31:0] data ;
input [3:0] be ;
input make_parity_error ;
output [2:0] received_termination ;
begin
if (rw)
begin
PAR_int <= #6 ^{AD, CBE, make_parity_error} ;
AD_int <= #6 data ;
end
 
IRDY_int <= #6 1'b0 ;
CBE_int <= #6 be ;
@(posedge CLK);
get_termination(received_termination);
end
endtask // subsequent_data_phase
 
task last_data_phase ;
input rw ;
input [31:0] data ;
input [3:0] be ;
input make_parity_error ;
output [2:0] received_termination ;
begin
FRAME_int <= #6 1'b1 ;
IRDY_int <= #6 1'b0 ;
if (rw)
begin
PAR_int <= #6 ^{AD, CBE, make_parity_error} ;
AD_int <= #6 data ;
end
 
CBE_int <= #6 be ;
 
@(posedge CLK);
get_termination(received_termination);
end
endtask // subsequent_data_phase
 
task get_termination ;
output [2:0] received_termination ;
begin
while ((TRDY === 1'b1) && (STOP === 1'b1))
@(posedge CLK) ;
 
if ( DEVSEL !== 1'b0 )
received_termination = target_abort ;
else if (TRDY !== 1'b1)
begin
if (STOP !== 1'b1)
received_termination = disconnect ;
else
received_termination = normal ;
end
else
received_termination = retry ;
end
endtask // get_termination
 
task finish_transaction ;
input rw ;
input make_parity_error ;
begin
if (rw)
PAR_int <= #6 ^{AD, CBE, make_parity_error} ;
 
IRDY_int <= #6 1'b1 ;
FRAME_en <= #6 1'b0 ;
AD_en <= #6 1'b0 ;
CBE_en <= #6 1'b0 ;
@(posedge CLK) ;
IRDY <= #1 1'bz ;
PAR <= #1 1'bz ;
PAR_en <= #6 1'b0 ;
IRDY_en <= #6 1'b0 ;
end
endtask // master_reference
endtask // finish_transaction
 
always@(e_finish_transaction)
begin
finish_transaction (write, make_parity_error_after_last_dataphase) ;
end
 
always@(e_transfers_done)
begin
 
if (FRAME !== 1'b1)
begin
FRAME_int <= #6 1'b1 ;
IRDY_int <= #6 1'b0 ;
if (write)
PAR_int <= #6 ^{CBE, AD} ;
 
@(posedge CLK) ;
end
 
-> e_finish_transaction ;
end
 
task insert_waits ;
input rw ;
input [2:0] wait_cycles ;
output [2:0] termination ;
reg [2:0] wait_cycles_left ;
reg stop_without_trdy_received ;
begin
stop_without_trdy_received = 1'b0 ;
wait_cycles_left = wait_cycles ;
 
termination = normal ;
 
PAR_int <= #6 ^{AD, CBE} ;
 
for (wait_cycles_left = wait_cycles ; (wait_cycles_left > 0) && !stop_without_trdy_received ; wait_cycles_left = wait_cycles_left - 1'b1)
begin
IRDY_int <= #6 1'b1 ;
@(posedge CLK) ;
 
PAR_int <= #6 ^{AD, CBE, 1'b1} ;
 
if ((STOP !== 1'b1) && (TRDY !== 1'b0))
begin
stop_without_trdy_received = 1'b1 ;
if (DEVSEL !== 1'b0)
termination = target_abort ;
else
termination = retry ;
end
end
end
endtask // insert_waits
endmodule
 
/trunk/bench/verilog/system.v
39,6 → 39,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.12 2002/10/21 13:04:30 mihad
// Changed BIST signal names etc..
//
// Revision 1.11 2002/10/11 12:03:12 mihad
// The testcase I just added in previous revision repaired
//
847,7 → 850,8
 
// if BIST is implemented, give it a go
`ifdef PCI_BIST
run_bist_test ;
// run_bist_test ;
scanb_rst <= #1 1'b1 ;
`endif
test_initial_conf_values ;
 
922,6 → 926,8
iack_cycle ;
`endif
 
test_master_overload ;
 
end
 
`ifdef DISABLE_COMPLETION_EXPIRED_TESTS
944,7 → 950,6
 
$display("Testing PCI target images' features!") ;
configure_bridge_target_base_addresses ;
 
`ifdef TEST_CONF_CYCLE_TYPE1_REFERENCE
test_conf_cycle_type1_reference ;
`endif
998,6 → 1003,8
target_fast_back_to_back ;
target_disconnects ;
 
test_target_overload ;
 
if ( target_io_image !== -1 )
test_target_abort( target_io_image ) ;
$display(" ") ;
1015,6 → 1022,9
end
end
 
tb_init_waits = 0 ;
tb_subseq_waits = 0 ;
 
`ifdef WB_CLOCK_FOLLOWS_PCI_CLOCK
test_target_response[`TARGET_ENCODED_PARAMATERS_ENABLE] = 1 ;
test_target_response[`TARGET_ENCODED_INIT_WAITSTATES] = 0 ;
1037,6 → 1047,9
target_special_corner_case_test ;
`endif
 
tb_init_waits = 0 ;
tb_subseq_waits = 0 ;
 
test_summary ;
 
$fclose(wbu_mon_log_file_desc | pciu_mon_log_file_desc | pci_mon_log_file_desc) ;
4965,7 → 4978,7
test_name = "ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLED" ;
fork
begin
ipci_unsupported_commands_master.master_reference
ipci_unsupported_commands_master.unsupported_reference
(
32'hAAAA_AAAA, // first part of address in dual address cycle
32'h5555_5555, // second part of address in dual address cycle
4999,7 → 5012,7
test_name = "ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLED" ;
fork
begin
ipci_unsupported_commands_master.master_reference
ipci_unsupported_commands_master.unsupported_reference
(
32'hAAAA_AAAA, // first part of address in dual address cycle
32'h5555_5555, // second part of address in dual address cycle
5067,7 → 5080,7
test_name = "ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLED" ;
fork
begin
ipci_unsupported_commands_master.master_reference
ipci_unsupported_commands_master.unsupported_reference
(
32'hAAAA_AAAA, // first part of address in dual address cycle
32'h5555_5555, // second part of address in dual address cycle
5333,7 → 5346,7
test_name = "ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLED" ;
fork
begin
ipci_unsupported_commands_master.master_reference
ipci_unsupported_commands_master.unsupported_reference
(
32'hAAAA_AAAA, // first part of address in dual address cycle
32'h5555_5555, // second part of address in dual address cycle
5471,7 → 5484,7
test_name = "ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLED" ;
fork
begin
ipci_unsupported_commands_master.master_reference
ipci_unsupported_commands_master.unsupported_reference
(
32'hAAAA_AAAA, // first part of address in dual address cycle
32'h5555_5555, // second part of address in dual address cycle
5609,7 → 5622,7
test_name = "ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLED" ;
fork
begin
ipci_unsupported_commands_master.master_reference
ipci_unsupported_commands_master.unsupported_reference
(
32'hAAAA_AAAA, // first part of address in dual address cycle
32'h5555_5555, // second part of address in dual address cycle
5876,7 → 5889,7
test_name = "ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLED" ;
fork
begin
ipci_unsupported_commands_master.master_reference
ipci_unsupported_commands_master.unsupported_reference
(
32'hAAAA_AAAA, // first part of address in dual address cycle
32'h5555_5555, // second part of address in dual address cycle
5910,7 → 5923,7
test_name = "ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLED" ;
fork
begin
ipci_unsupported_commands_master.master_reference
ipci_unsupported_commands_master.unsupported_reference
(
32'hAAAA_AAAA, // first part of address in dual address cycle
32'h5555_5555, // second part of address in dual address cycle
5978,7 → 5991,7
test_name = "ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLED" ;
fork
begin
ipci_unsupported_commands_master.master_reference
ipci_unsupported_commands_master.unsupported_reference
(
32'hAAAA_AAAA, // first part of address in dual address cycle
32'h5555_5555, // second part of address in dual address cycle
8649,7 → 8662,7
do_pause( 1 ) ;
end
begin
pci_transaction_progress_monitor( pci_image_base, `BC_MEM_WRITE, 0, 0, 1'b1, 1'b0, 1'b0, ok ) ;
pci_transaction_progress_monitor( pci_image_base, ((target_mem_image == 1) ? `BC_MEM_WRITE : `BC_IO_WRITE), 0, 0, 1'b1, 1'b0, 1'b0, ok ) ;
end
join
 
9197,6 → 9210,8
integer deadlock_counter ;
integer transfer_counter ;
integer deadlock_max_val ;
reg [2:0] slave_termination ;
reg cab_asserted ;
begin:main
if ( in_use === 1 )
begin
9220,8 → 9235,9
// maximum wb clock cycles
deadlock_max_val = deadlock_max_val / (1/`WB_FREQ) ;
 
in_use = 1 ;
ok = 1 ;
in_use = 1 ;
ok = 1 ;
cab_asserted = 0 ;
 
fork
begin:wait_start
9296,11 → 9312,50
 
while( (CYC_O === 1) && ((transfer_counter <= `PCIW_DEPTH) || (transfer_counter <= `PCIR_DEPTH)) )
begin
if ( (STB_O === 1) && (ACK_I === 1) )
transfer_counter = transfer_counter + 1 ;
 
if (!cab_asserted)
cab_asserted = (CAB_O !== 1'b0) ;
 
if (STB_O === 1)
begin
slave_termination = {ACK_I, ERR_I, RTY_I} ;
if (ACK_I)
transfer_counter = transfer_counter + 1 ;
end
@(posedge wb_clock) ;
end
 
if (cab_asserted)
begin
// cab was sampled asserted
// if number of transfers was less than 2 - check for extraordinary terminations
if (transfer_counter < 2)
begin
// if cycle was terminated because of no response, error or retry, than it is OK to have CAB_O asserted while transfering 0 or 1 data.
// any other cases are wrong
case (slave_termination)
3'b000:begin end
3'b001:begin end
3'b010:begin end
default:begin
ok = 0 ;
$display("Time %t", $time) ;
$display("WB_MASTER asserted CAB_O for single transfer") ;
end
endcase
end
end
else
begin
// if cab is not asserted, then WB_MASTER should not read more than one data.
if (transfer_counter > 1)
begin
ok = 0 ;
$display("Time %t", $time) ;
$display("WB_MASTER didn't assert CAB_O for consecutive block transfer") ;
end
end
 
if ( check_transfers === 1 )
begin
if ( transfer_counter !== num_of_transfers )
17062,10 → 17117,10
DO_REF ("MEM_WRITE ", `Test_Master_1, pci_address[PCI_BUS_DATA_RANGE:0],
PCI_COMMAND_MEMORY_WRITE, data[PCI_BUS_DATA_RANGE:0],
byte_enables,
(tb_subseq_waits != 4) ? expect_length : (expect_length + 1), `Test_No_Addr_Perr, `Test_No_Data_Perr,
expect_length + 1, `Test_No_Addr_Perr, `Test_No_Data_Perr,
8'h0_0, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_No_Fast_B2B,
(tb_subseq_waits != 4) ? `Test_Target_Disc_On : `Test_Target_Retry_On, `Test_Expect_No_Master_Abort);
`Test_Target_Retry_On, `Test_Expect_No_Master_Abort);
do_pause( 3 ) ;
 
while ( FRAME !== 1 || IRDY !== 1 )
17105,10 → 17160,10
DO_REF ("MEM_WRITE ", `Test_Master_1, pci_address[PCI_BUS_DATA_RANGE:0],
PCI_COMMAND_MEMORY_WRITE, data[PCI_BUS_DATA_RANGE:0],
byte_enables,
(tb_subseq_waits != 4) ? (expect_length + 1) : (expect_length + 2) , `Test_No_Addr_Perr, `Test_No_Data_Perr,
expect_length + 2, `Test_No_Addr_Perr, `Test_No_Data_Perr,
8'h0_0, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_No_Fast_B2B,
(tb_subseq_waits != 4) ? `Test_Target_Disc_Before : `Test_Target_Retry_Before, `Test_Expect_No_Master_Abort);
`Test_Target_Retry_Before, `Test_Expect_No_Master_Abort);
do_pause( 3 ) ;
 
while ( FRAME !== 1 || IRDY !== 1 )
17865,7 → 17920,7
32'h0000_0044 // data
) ;
 
ipci_unsupported_commands_master.master_reference
ipci_unsupported_commands_master.unsupported_reference
(
Address, // first part of address in dual address cycle
Address, // second part of address in dual address cycle
17887,7 → 17942,7
 
$display(" Master abort testing with unsuported bus command to image %d (BC is SPECIAL)!", image_num) ;
test_name = "MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIAL" ;
ipci_unsupported_commands_master.master_reference
ipci_unsupported_commands_master.unsupported_reference
(
Address, // first part of address in dual address cycle
Address, // second part of address in dual address cycle
17909,7 → 17964,7
 
$display(" Master abort testing with unsuported bus command to image %d (BC is RESERVED0)!", image_num) ;
test_name = "MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0" ;
ipci_unsupported_commands_master.master_reference
ipci_unsupported_commands_master.unsupported_reference
(
Address, // first part of address in dual address cycle
Address, // second part of address in dual address cycle
17931,7 → 17986,7
 
$display(" Master abort testing with unsuported bus command to image %d (BC is RESERVED1)", image_num) ;
test_name = "MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1" ;
ipci_unsupported_commands_master.master_reference
ipci_unsupported_commands_master.unsupported_reference
(
Address, // first part of address in dual address cycle
Address, // second part of address in dual address cycle
17953,7 → 18008,7
 
$display(" Master abort testing with unsuported bus command to image %d (BC is RESERVED2)!", image_num) ;
test_name = "MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2" ;
ipci_unsupported_commands_master.master_reference
ipci_unsupported_commands_master.unsupported_reference
(
Address, // first part of address in dual address cycle
Address, // second part of address in dual address cycle
17975,7 → 18030,7
 
$display(" Master abort testing with unsuported bus command to image %d (BC is RESERVED3)!", image_num) ;
test_name = "MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3" ;
ipci_unsupported_commands_master.master_reference
ipci_unsupported_commands_master.unsupported_reference
(
Address, // first part of address in dual address cycle
Address, // second part of address in dual address cycle
17999,7 → 18054,7
$display(" byte enables are different than first bus command (DUAL_ADDR_CYC)!") ;
$display(" Master abort testing with unsuported bus command to image %d (BC is DUAL_ADDR_CYC)!", image_num) ;
test_name = "MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYC" ;
ipci_unsupported_commands_master.master_reference
ipci_unsupported_commands_master.unsupported_reference
(
Address, // first part of address in dual address cycle
Address, // second part of address in dual address cycle
19893,6 → 19948,384
endtask // master_special_corner_case_test
`endif
 
task test_target_overload ;
reg ok_pci ;
reg ok_wb ;
reg ok ;
reg [2:0] test_image_num ;
reg addr_translated ;
integer transfered ;
reg [2:0] received_termination ;
integer total_transfers ;
reg [31:0] transaction_sizes [0:1024] ;
integer pci_transaction_num ;
integer wb_transaction_num ;
reg [31:0] current_wb_address ;
reg io_mapped ;
integer init_waits_backup ;
integer current_size ;
begin:main
init_waits_backup = tb_init_waits ;
tb_init_waits = 0 ;
`ifdef HOST
io_mapped = 1'b0 ;
`endif
 
test_image_num = 'd1 ;
`ifdef GUEST
io_mapped = `PCI_BA1_MEM_IO ;
`endif
 
`ifdef PCI_IMAGE2
test_image_num = 'd2 ;
`ifdef GUEST
io_mapped = `PCI_BA2_MEM_IO ;
`endif
`endif
 
`ifdef PCI_IMAGE3
test_image_num = 'd3 ;
`ifdef GUEST
io_mapped = `PCI_BA3_MEM_IO ;
`endif
`endif
 
`ifdef PCI_IMAGE4
test_image_num = 'd4 ;
`ifdef GUEST
io_mapped = `PCI_BA4_MEM_IO ;
`endif
`endif
 
`ifdef PCI_IMAGE5
test_image_num = 'd5 ;
`ifdef GUEST
io_mapped = `PCI_BA5_MEM_IO ;
`endif
`endif
 
test_name = "PCI TARGET OVERLOAD" ;
// configure target image 1 via bus accesses
pci_configure_pci_target_image
(
1'b1, // selects whether to configure image with bus accesses or directly with dot notation in the configuration space
test_image_num, // image number
Target_Base_Addr_R[test_image_num], // base address
Target_Addr_Mask_R[test_image_num], // address mask
Target_Tran_Addr_R[test_image_num], // translation address
1'b0, // io/mem mapping select
1'b0, // prefetch enable
1'b1, // address translation enable
ok // finished succesfully
);
if (ok !== 1'b1)
begin
test_fail("configuration of PCI Target Image didn't succeede") ;
tb_init_waits = init_waits_backup ;
#1 disable main ;
end
 
`ifdef ADDR_TRAN_IMPL
addr_translated = 1'b1 ;
`else
addr_translated = 1'b0 ;
`endif
 
// set wb slave's response to max wait cycles
wishbone_slave.cycle_response
(
3'b100, // ACK, ERR, RTY termination
tb_subseq_waits, // wait cycles before response
0 // number of retries before acknowledge
) ;
 
ok_pci = 1 ;
ok_wb = 1 ;
current_wb_address = pci_to_wb_addr_convert
(
Target_Base_Addr_R[test_image_num], // pci address
Target_Tran_Addr_R[test_image_num], // translation address
addr_translated
);
current_wb_address = current_wb_address & Target_Addr_Mask_R[test_image_num] ;
 
for (current_size = 2 ; (current_size <= 1024) && ok_pci && ok_wb && ok ; current_size = current_size * 2)
begin
total_transfers = 0 ;
pci_transaction_num = 0 ;
wb_transaction_num = 0 ;
 
current_wb_address = current_wb_address & Target_Addr_Mask_R[test_image_num] ;
current_wb_address = current_wb_address + (('d1024 - current_size) * 4) ;
fork
begin
while ((total_transfers < current_size) && ok_pci && ok_wb && ok)
begin
// try transfering 4kB with no wait cycles through the target
ipci_unsupported_commands_master.normal_write_transfer
(
// always write to the end of the 4kB window
(('d1024 - current_size) * 4) + Target_Base_Addr_R[test_image_num] + (4 * total_transfers), // start_address
io_mapped ? `BC_IO_WRITE : `BC_MEM_WRITE, // bus_command
(current_size - total_transfers), // size
4 - tb_subseq_waits[2:0], // subsequent wait cycles
transfered, // actual_transfer
received_termination // received_termination
);
if (transfered > 0)
begin
transaction_sizes[pci_transaction_num] = transfered ;
pci_transaction_num = pci_transaction_num + 1'b1 ;
end
total_transfers = total_transfers + transfered ;
if (received_termination > 2) // terminations with numbers 3(Target Abort), 4(Master Abort) and 5(Error) are not allowed
begin
ok_pci = 0 ;
if (received_termination == 3)
test_fail("PCI Target signalled Target Abort") ;
if (received_termination == 4)
test_fail("PCI Master generated Master Abort") ;
if (received_termination == 5)
test_fail("PCI behavioral master signaled severe error") ;
end
end
end
begin:wb_monitoring
while (((total_transfers < current_size) || (pci_transaction_num > wb_transaction_num)) && ok_pci && ok_wb && ok)
begin
wait(pci_transaction_num > wb_transaction_num) ;
wb_transaction_progress_monitor
(
current_wb_address, //address
1'b1, //write/read
transaction_sizes[wb_transaction_num], //num_of_transfers
1'b1, //check_transfers
ok_wb // success/fail
);
current_wb_address = current_wb_address + (transaction_sizes[wb_transaction_num] * 4) ;
wb_transaction_num = wb_transaction_num + 1'b1 ;
if (ok_wb !== 1'b1)
begin
test_fail("WB Transaction progress monitor detected invalid transaction or none at all on WB bus");
end
end
 
wb_transaction_num = wb_transaction_num - 1'b1 ;
current_wb_address = current_wb_address - (transaction_sizes[wb_transaction_num] * 4) ;
if (ok)
#1 disable pci_monitoring ;
end
begin:pci_monitoring
@(error_event_int) ;
test_fail("PCI Bus monitor detected invalid operation on PCI bus") ;
ok = 0 ;
ok_pci = 0 ;
ok_wb = 0 ;
end
join
end
 
if ((ok && ok_wb && ok_pci) === 1'b1)
test_ok ;
 
tb_init_waits = init_waits_backup ;
end
endtask // test_target_overload
 
task test_master_overload ;
reg ok_pci ;
reg ok_wb ;
reg ok ;
reg [2:0] test_image_num ;
integer transfered ;
reg [2:0] received_termination ;
integer total_transfers ;
reg [31:0] transaction_sizes [0:1024] ;
integer pci_transaction_num ;
integer wb_transaction_num ;
reg [31:0] current_pci_address ;
integer init_waits_backup ;
integer current_size ;
 
reg `WRITE_STIM_TYPE write_data ;
 
reg `WRITE_RETURN_TYPE write_status ;
reg `WB_TRANSFER_FLAGS write_flags ;
 
reg [31:0] image_base ;
reg [31:0] target_address ;
 
integer i ;
begin:main
 
// set behavioral target to respond normally
test_target_response[`TARGET_ENCODED_TERMINATION] = `Test_Target_Normal_Completion ;
test_target_response[`TARGET_ENCODED_TERMINATE_ON] = 0 ;
 
test_image_num = 'd1 ;
 
`ifdef WB_IMAGE2
test_image_num = 'd2 ;
`endif
 
`ifdef WB_IMAGE3
test_image_num = 'd3 ;
`endif
 
`ifdef WB_IMAGE4
test_image_num = 'd4 ;
`endif
 
`ifdef WB_IMAGE5
test_image_num = 'd5 ;
`endif
 
test_name = "MASTER OVERLOAD" ;
 
target_address = `BEH_TAR1_MEM_START ;
image_base = 0 ;
image_base[`PCI_BASE_ADDR0_MATCH_RANGE] = target_address[`PCI_BASE_ADDR0_MATCH_RANGE] ;
 
target_address[31:(32 - `WB_NUM_OF_DEC_ADDR_LINES)] = image_base[31:(32 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
target_address[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = image_base[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] ;
 
write_flags = 0 ;
write_flags`INIT_WAITS = tb_init_waits ;
write_flags`SUBSEQ_WAITS = tb_subseq_waits ;
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
write_flags`WB_TRANSFER_CAB = 1'b1 ;
 
pci_configure_wb_slave_image
(
1'b1, // use_bus
test_image_num, // image_num
image_base, // base address
32'hFFFF_FFFF, // address mask
32'h0000_0000, // translation address
1'b0, // io/mem mapping select
1'b1, // prefetch enable
1'b0, // address translation enable
1'b1, // memory read line enable
ok // finished succesfully
) ;
 
if (ok !== 1'b1)
begin
test_fail("WB image configuration failed") ;
disable main ;
end
// fill wishbone master's memory with data - inverted addresses
write_data = 0 ;
for (i = 0 ; i < 1024 ; i = i + 1)
begin
write_data`WRITE_ADDRESS = image_base + (4 * i) ;
write_data`WRITE_DATA = ~(write_data`WRITE_ADDRESS);
wishbone_master.blk_write_data[i] = write_data ;
end
 
ok_wb = 1 ;
ok_pci = 1 ;
 
total_transfers = 0 ;
 
for (current_size = 2 ; (current_size <= 1024) && ok_pci && ok_wb && ok ; current_size = current_size * 2)
begin
 
total_transfers = 0 ;
pci_transaction_num = 0 ;
wb_transaction_num = 0 ;
 
current_pci_address = image_base ;
fork
begin
while ((total_transfers < current_size) && ok_pci && ok_wb && ok)
begin
// try transfering 4kB with no wait cycles through the wb slave unit
write_flags`WB_TRANSFER_SIZE = current_size - total_transfers ;
wishbone_master.wb_block_write(write_flags, write_status) ;
if (write_status`CYC_ERR || ((write_status`CYC_ERR !== 1'b1) && (write_status`CYC_RTY !== 1'b1) && (write_status`CYC_ACK !== 1'b1)))
begin
test_fail("Wishbone slave signaled an error or did not respond to normal write access") ;
ok_wb = 0 ;
end
 
transfered = write_status`CYC_ACTUAL_TRANSFER ;
if (transfered > 0)
begin
transaction_sizes[wb_transaction_num] = transfered ;
wb_transaction_num = wb_transaction_num + 1'b1 ;
end
total_transfers = total_transfers + transfered ;
end
end
begin:pci_models_monitoring
while (((total_transfers < current_size) || (wb_transaction_num > pci_transaction_num)) && ok_pci && ok_wb && ok)
begin
wait(wb_transaction_num > pci_transaction_num) ;
pci_transaction_progress_monitor
(
current_pci_address, // address
`BC_MEM_WRITE, // bus_command
transaction_sizes[pci_transaction_num], // num_of_transfers
0, // num_of_cycles
1'b1, // check_transfers
1'b0, // check_cycles
1'b0, // doing_fast_back_to_back
ok_pci // ok
) ;
 
pci_transaction_num = pci_transaction_num + 1'b1 ;
if (ok_pci !== 1'b1)
begin
test_fail("PCI Transaction progress monitor detected invalid transaction or none at all on PCI bus");
end
end
 
if (ok)
#1 disable pci_monitoring ;
end
begin:pci_monitoring
@(error_event_int) ;
test_fail("PCI Bus monitor detected invalid operation on PCI bus") ;
ok = 0 ;
ok_pci = 0 ;
ok_wb = 0 ;
end
join
end
// disable the image
pci_configure_wb_slave_image
(
1'b1, // use_bus
test_image_num, // image_num
image_base, // base address
32'h0000_0000, // address mask
32'h0000_0000, // translation address
1'b0, // io/mem mapping select
1'b1, // prefetch enable
1'b0, // address translation enable
1'b1, // memory read line enable
ok // finished succesfully
) ;
 
if (ok !== 1'b1)
begin
test_fail("WB image configuration failed") ;
disable main ;
end
 
if ((ok && ok_wb && ok_pci) === 1'b1)
test_ok ;
end
endtask // test_master_overload
 
task test_fail ;
input [7999:0] failure_reason ;
reg [8007:0] display_failure ;
19974,4 → 20407,5
end
endtask
 
`include "pci_bench_common_tasks.v"
endmodule
/trunk/bench/verilog/pci_bench_common_tasks.v
0,0 → 1,396
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "pci_bench_common_tasks.v" ////
//// ////
//// This file is part of the "PCI bridge" project ////
//// http://www.opencores.org/cores/pci/ ////
//// ////
//// Author(s): ////
//// - Miha Dolenc (mihad@opencores.org) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2003 Miha Dolenc, mihad@opencores.org ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
task pci_configure_pci_target_image ;
input use_bus ; // selects whether to configure image with bus accesses or directly with dot notation in the configuration space
input [2:0] image_num ; // image number
input [31:0] ba ; // base address
input [31:0] am ; // address mask
input [31:0] ta ; // translation address
input io_nmem ; // io/mem mapping select
input pref_en ; // prefetch enable
input at_en ; // address translation enable
output ok ; // finished succesfully
 
reg in_use ;
reg [11:0] ctrl_offset ;
reg [11:0] ba_offset ;
reg [11:0] am_offset ;
reg [11:0] ta_offset ;
begin:main
if (in_use === 1'b1)
begin
$display("Time %t", $time) ;
$display("pci_configure_pci_target_image task re-entered") ;
ok = 0 ;
disable main ;
end
 
in_use = 1'b1 ;
if (use_bus !== 1'b0)
begin
if (image_num === 0)
begin
ctrl_offset = {4'h1, `P_IMG_CTRL0_ADDR, 2'b00} ;
ba_offset = {4'h1, `P_BA0_ADDR, 2'b00} ;
am_offset = {4'h1, `P_AM0_ADDR, 2'b00} ;
ta_offset = {4'h1, `P_TA0_ADDR, 2'b00} ;
end
else if (image_num === 1)
begin
ctrl_offset = {4'h1, `P_IMG_CTRL1_ADDR, 2'b00} ;
ba_offset = {4'h1, `P_BA1_ADDR, 2'b00} ;
am_offset = {4'h1, `P_AM1_ADDR, 2'b00} ;
ta_offset = {4'h1, `P_TA1_ADDR, 2'b00} ;
end
else if (image_num === 2)
begin
ctrl_offset = {4'h1, `P_IMG_CTRL2_ADDR, 2'b00} ;
ba_offset = {4'h1, `P_BA2_ADDR, 2'b00} ;
am_offset = {4'h1, `P_AM2_ADDR, 2'b00} ;
ta_offset = {4'h1, `P_TA2_ADDR, 2'b00} ;
end
else if (image_num === 3)
begin
ctrl_offset = {4'h1, `P_IMG_CTRL3_ADDR, 2'b00} ;
ba_offset = {4'h1, `P_BA3_ADDR, 2'b00} ;
am_offset = {4'h1, `P_AM3_ADDR, 2'b00} ;
ta_offset = {4'h1, `P_TA3_ADDR, 2'b00} ;
end
else if (image_num === 4)
begin
ctrl_offset = {4'h1, `P_IMG_CTRL4_ADDR, 2'b00} ;
ba_offset = {4'h1, `P_BA4_ADDR, 2'b00} ;
am_offset = {4'h1, `P_AM4_ADDR, 2'b00} ;
ta_offset = {4'h1, `P_TA4_ADDR, 2'b00} ;
end
else if (image_num === 5)
begin
ctrl_offset = {4'h1, `P_IMG_CTRL5_ADDR, 2'b00} ;
ba_offset = {4'h1, `P_BA5_ADDR, 2'b00} ;
am_offset = {4'h1, `P_AM5_ADDR, 2'b00} ;
ta_offset = {4'h1, `P_TA5_ADDR, 2'b00} ;
end
 
// Set Base Address of IMAGE
config_write( ba_offset, ba | {31'h0, io_nmem}, 4'hF, ok ) ;
if ( ok !== 1 )
begin
in_use = 1'b0 ;
disable main ;
end
 
// Set Address Mask of IMAGE
config_write( am_offset, am, 4'hF, ok ) ;
if ( ok !== 1 )
begin
in_use = 1'b0 ;
disable main ;
end
 
// Set Translation Address of IMAGE
config_write( ta_offset, ta, 4'hF, ok ) ;
if ( ok !== 1 )
begin
in_use = 1'b0 ;
disable main ;
end
 
// Set IMAGE Control Register
config_write( ctrl_offset, {29'd0, at_en, pref_en, 1'b0}, 4'hF, ok ) ;
if ( ok !== 1 )
begin
in_use = 1'b0 ;
disable main ;
end
end
else
begin
if (image_num === 0)
begin
`ifdef HOST
`ifdef NO_CNF_IMAGE
`ifdef PCI_IMAGE0 // if PCI bridge is HOST and IMAGE0 is assigned as general image space
// set base address
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba0_bit31_12 = ba[31:12] ;
// set control register
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl0_bit2_1 = {at_en, pref_en} ;
// set memory map - part of base address
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba0_bit0 = io_nmem ;
// set address mask
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am0 = am[31:12] ;
// set translation address
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta0 = ta[31:12] ;
`endif
`else // if PCI bridge is HOST and IMAGE0 is assigned to PCI configuration space
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba0_bit31_12 = ba[31:12] ;
`endif
`else // if PCI bridge is GUEST, then IMAGE0 is assigned to PCI configuration space
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba0_bit31_12 = ba[31:12] ;
`endif
end
else if (image_num === 1)
begin
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl1_bit2_1 = {at_en, pref_en} ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba1_bit31_12 = ba[31:12] ;
`ifdef HOST
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba1_bit0 = io_nmem ;
`endif
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am1 = am[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta1 = ta[31:12] ;
end
else if (image_num === 2)
begin
`ifdef PCI_IMAGE2
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl2_bit2_1 = {at_en, pref_en} ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba2_bit31_12 = ba[31:12] ;
`ifdef HOST
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba2_bit0 = io_nmem ;
`endif
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am2 = am[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta2 = ta[31:12] ;
`endif
end
else if (image_num === 3)
begin
`ifdef PCI_IMAGE3
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl3_bit2_1 = {at_en, pref_en} ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba3_bit31_12 = ba[31:12] ;
`ifdef HOST
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba3_bit0 = io_nmem ;
`endif
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am3 = am[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta3 = ta[31:12] ;
`endif
end
else if (image_num === 4)
begin
`ifdef PCI_IMAGE4
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl4_bit2_1 = {at_en, pref_en} ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba4_bit31_12 = ba[31:12] ;
`ifdef HOST
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba4_bit0 = io_nmem ;
`endif
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am4 = am[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta4 = ta[31:12] ;
`endif
end
else if (image_num === 5)
begin
`ifdef PCI_IMAGE5
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl5_bit2_1 = {at_en, pref_en} ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba5_bit31_12 = ba[31:12] ;
`ifdef HOST
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba5_bit0 = io_nmem ;
`endif
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am5 = am[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta5 = ta[31:12] ;
`endif
end
end
 
in_use = 1'b0 ;
end
endtask // pci_configure_pci_target_image
 
task pci_configure_wb_slave_image ;
input use_bus ; // selects whether to configure image with bus accesses or directly with dot notation in the configuration space
input [2:0] image_num ; // image number
input [31:0] ba ; // base address
input [31:0] am ; // address mask
input [31:0] ta ; // translation address
input io_nmem ; // io/mem mapping select
input pref_en ; // prefetch enable
input at_en ; // address translation enable
input mrl_en ; // memory read line enable
output ok ; // finished succesfully
 
reg in_use ;
reg [11:0] ctrl_offset ;
reg [11:0] ba_offset ;
reg [11:0] am_offset ;
reg [11:0] ta_offset ;
begin:main
if (in_use === 1'b1)
begin
$display("Time %t", $time) ;
$display("pci_configure_wb_slave_image task re-entered") ;
ok = 0 ;
disable main ;
end
 
in_use = 1'b1 ;
if (use_bus !== 1'b0)
begin
if (image_num === 1)
begin
ctrl_offset = {4'h1, `W_IMG_CTRL1_ADDR, 2'b00} ;
ba_offset = {4'h1, `W_BA1_ADDR, 2'b00} ;
am_offset = {4'h1, `W_AM1_ADDR, 2'b00} ;
ta_offset = {4'h1, `W_TA1_ADDR, 2'b00} ;
end
else if (image_num === 2)
begin
ctrl_offset = {4'h1, `W_IMG_CTRL2_ADDR, 2'b00} ;
ba_offset = {4'h1, `W_BA2_ADDR, 2'b00} ;
am_offset = {4'h1, `W_AM2_ADDR, 2'b00} ;
ta_offset = {4'h1, `W_TA2_ADDR, 2'b00} ;
end
else if (image_num === 3)
begin
ctrl_offset = {4'h1, `W_IMG_CTRL3_ADDR, 2'b00} ;
ba_offset = {4'h1, `W_BA3_ADDR, 2'b00} ;
am_offset = {4'h1, `W_AM3_ADDR, 2'b00} ;
ta_offset = {4'h1, `W_TA3_ADDR, 2'b00} ;
end
else if (image_num === 4)
begin
ctrl_offset = {4'h1, `W_IMG_CTRL4_ADDR, 2'b00} ;
ba_offset = {4'h1, `W_BA4_ADDR, 2'b00} ;
am_offset = {4'h1, `W_AM4_ADDR, 2'b00} ;
ta_offset = {4'h1, `W_TA4_ADDR, 2'b00} ;
end
else if (image_num === 5)
begin
ctrl_offset = {4'h1, `W_IMG_CTRL5_ADDR, 2'b00} ;
ba_offset = {4'h1, `W_BA5_ADDR, 2'b00} ;
am_offset = {4'h1, `W_AM5_ADDR, 2'b00} ;
ta_offset = {4'h1, `W_TA5_ADDR, 2'b00} ;
end
 
// Set Base Address of IMAGE
config_write( ba_offset, ba | {31'h0, io_nmem}, 4'hF, ok ) ;
if ( ok !== 1 )
begin
in_use = 1'b0 ;
disable main ;
end
 
// Set Address Mask of IMAGE
config_write( am_offset, am, 4'hF, ok ) ;
if ( ok !== 1 )
begin
in_use = 1'b0 ;
disable main ;
end
 
// Set Translation Address of IMAGE
config_write( ta_offset, ta, 4'hF, ok ) ;
if ( ok !== 1 )
begin
in_use = 1'b0 ;
disable main ;
end
 
// Set IMAGE Control Register
config_write( ctrl_offset, {29'd0, at_en, pref_en, 1'b0}, 4'hF, ok ) ;
if ( ok !== 1 )
begin
in_use = 1'b0 ;
disable main ;
end
end
else
begin
if (image_num === 1)
begin
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_img_ctrl1_bit2_0 = {at_en, pref_en, mrl_en} ;
 
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba1_bit31_12 = ba[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba1_bit0 = io_nmem ;
 
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_am1 = am[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ta1 = ta[31:12] ;
end
else if (image_num === 2)
begin
`ifdef WB_IMAGE2
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_img_ctrl2_bit2_0 = {at_en, pref_en, mrl_en} ;
 
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba2_bit31_12 = ba[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba2_bit0 = io_nmem ;
 
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_am2 = am[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ta2 = ta[31:12] ;
`endif
end
else if (image_num === 3)
begin
`ifdef WB_IMAGE3
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_img_ctrl3_bit2_0 = {at_en, pref_en, mrl_en} ;
 
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba3_bit31_12 = ba[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba3_bit0 = io_nmem ;
 
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_am3 = am[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ta3 = ta[31:12] ;
`endif
end
else if (image_num === 4)
begin
`ifdef WB_IMAGE4
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_img_ctrl4_bit2_0 = {at_en, pref_en, mrl_en} ;
 
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba4_bit31_12 = ba[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba4_bit0 = io_nmem ;
 
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_am4 = am[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ta4 = ta[31:12] ;
`endif
end
else if (image_num === 5)
begin
`ifdef WB_IMAGE5
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_img_ctrl5_bit2_0 = {at_en, pref_en, mrl_en} ;
 
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba5_bit31_12 = ba[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba5_bit0 = io_nmem ;
 
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_am5 = am[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ta5 = ta[31:12] ;
`endif
end
end
 
in_use = 1'b0 ;
end
endtask // pci_configure_wb_slave_image
/trunk/bench/verilog/pci_testbench_defines.v
13,7 → 13,7
// only one at the time can be defined, otherwise testbench won't work
// they are used to generate both clocks with same period and phase shift of define's value in nano seconds
 
`define PCI_CLOCK_FOLLOWS_WB_CLOCK 2
//`define PCI_CLOCK_FOLLOWS_WB_CLOCK 2
//`define WB_CLOCK_FOLLOWS_PCI_CLOCK 2
// wishbone frequncy in GHz
82,7 → 82,7
`define WAIT_FOR_RESPONSE 6
 
// maximum number of transactions allowed in single call to block or cab transfer routines
`define MAX_BLK_SIZE 512
`define MAX_BLK_SIZE 1024
 
// maximum retry terminations allows for WISHBONE master to repeat an access
`define WB_TB_MAX_RTY 10000
/trunk/rtl/verilog/pci_target32_sm.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2002/09/24 19:09:17 mihad
// Number of state bits define was removed
//
// Revision 1.6 2002/09/24 18:30:00 mihad
// Changed state machine encoding to true one-hot
//
520,7 → 523,7
wire trdy_w_frm = (
(state_transfere && !cnf_progress && !norm_access_to_conf_reg && rw_cbe0 && !disconect_wo_data) ||
(state_transfere && !cnf_progress && !norm_access_to_conf_reg && ~rw_cbe0 && !disconect_wo_data && ~pcir_fifo_data_err_in) ||
(state_transfere && !cnf_progress && !norm_access_to_conf_reg && disconect_w_data && pci_irdy_reg_in && (rw_cbe0 || !pcir_fifo_data_err_in))
(state_transfere && !cnf_progress && !norm_access_to_conf_reg && disconect_w_data && pci_irdy_reg_in && (!rw_cbe0 && !pcir_fifo_data_err_in))
) ;
// if not disconnect without data and not target abort (only during reads)
// MUST BE ANDED WITH CRITICAL ~FRAME AND IRDY
/trunk/rtl/verilog/pci_user_constants.v
39,6 → 39,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/09/30 17:22:45 mihad
// Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!
//
// Revision 1.3 2002/08/13 11:03:53 mihad
// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image
//
205,7 → 208,7
Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used
together by application.
-----------------------------------------------------------------------------------------------------------*/
`define HEADER_VENDOR_ID 16'h2321
`define HEADER_VENDOR_ID 16'h1895
`define HEADER_DEVICE_ID 16'h0001
`define HEADER_REVISION_ID 8'h01
 
/trunk/rtl/verilog/pci_master32_sm.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/02/01 15:25:12 mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
// Revision 1.2 2001/10/05 08:14:29 mihad
// Updated all files with inclusion of timescale file for simulation purposes.
//
221,9 → 224,9
// change state - clock enable for sm state register
wire change_state ;
// next state for state machine
reg [4:0] next_state ;
reg [3:0] next_state ;
// SM state register
reg [4:0] cur_state ;
reg [3:0] cur_state ;
 
// variables for indicating which state state machine is in
// this variables are used to reduce logic levels in case of heavily constrained PCI signals
/trunk/rtl/verilog/pci_target32_interface.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/08/22 13:28:04 mihad
// Updated for synthesis purposes. Gate level simulation was failing in some configurations
//
// Revision 1.4 2002/02/19 16:32:37 mihad
// Modified testbench and fixed some bugs
//
757,6 → 760,10
end
end
 
// when disconnect is signalled, the next data written to fifo will be the last
// also when this happens, disconnect must stay asserted until last data is written to the fifo
reg next_write_to_pciw_fifo_is_last ;
 
// selecting "fifo data" from medium registers or from PCIR_FIFO
wire [31:0] pcir_fifo_data = (sel_fifo_mreg_in && !pcir_fifo_empty_in) ? pcir_fifo_data_in : pcir_fifo_data_reg ;
wire [3:0] pcir_fifo_ctrl = (sel_fifo_mreg_in && !pcir_fifo_empty_in) ? pcir_fifo_control_input : pcir_fifo_ctrl_reg ;
769,7 → 776,7
assign disconect_wo_data_out = (
((/*pcir_fifo_ctrl[`LAST_CTRL_BIT] ||*/ pcir_fifo_empty_in || ~burst_ok_out/*addr_burst_ok*/ || io_memory_bus_command) &&
~bc0_in && ~frame_reg_in) ||
((pciw_fifo_full_in || pciw_fifo_almost_full_in || pciw_fifo_two_left_in || ~addr_burst_ok || io_memory_bus_command) &&
((pciw_fifo_full_in || pciw_fifo_almost_full_in || next_write_to_pciw_fifo_is_last || (pciw_fifo_two_left_in && pciw_fifo_wenable_out) || ~addr_burst_ok || io_memory_bus_command) &&
bc0_in && ~frame_reg_in)
) ;
assign disconect_w_data_out = (
816,6 → 823,16
.reset_in (reset_in)
) ;
 
always@(posedge clk_in or posedge reset_in)
begin
if (reset_in)
next_write_to_pciw_fifo_is_last <= #1 1'b0 ;
else if (next_write_to_pciw_fifo_is_last && pciw_fifo_wenable_out)
next_write_to_pciw_fifo_is_last <= #1 1'b0 ;
else if (pciw_fifo_wenable_out && disconect_wo_data_out)
next_write_to_pciw_fifo_is_last <= #1 1'b1 ;
end
 
// signal assignments from fifo to PCI Target FSM
assign wbw_fifo_empty_out = wbw_fifo_empty_in ;
assign wbu_del_read_comp_pending_out = wbu_del_read_comp_pending_in ;
828,8 → 845,8
assign pciw_fifo_control_out[`ADDR_CTRL_BIT] = ~rdy_in ;
assign pciw_fifo_control_out[`BURST_BIT] = rdy_in ? ~frame_reg_in : 1'b0 ;
assign pciw_fifo_control_out[`DATA_ERROR_CTRL_BIT] = 1'b0 ;
assign pciw_fifo_control_out[`LAST_CTRL_BIT] = rdy_in ?
(last_reg_in || pciw_fifo_almost_full_in || ~addr_burst_ok || io_memory_bus_command) : 1'b0 ;
assign pciw_fifo_control_out[`LAST_CTRL_BIT] = rdy_in &&
(next_write_to_pciw_fifo_is_last || last_reg_in || pciw_fifo_almost_full_in || ~addr_burst_ok || io_memory_bus_command);
 
`ifdef HOST
`ifdef NO_CNF_IMAGE
/trunk/sim/rtl_sim/run/run_pci_sim_regr.scr
523,6 → 523,7
echo "-hdlvar ../bin/hdl.var" >> ./ncsim.args
echo "-logfile ../log/ncsim.log" >> ./ncsim.args
echo "-messages" >> ./ncsim.args
echo "-tcl" >> ./ncsim.args
if ($arg_waves == 1) then
echo "-input ../bin/ncsim_waves.rc" >> ./ncsim.args
else

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