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  • This comparison shows the changes necessary to convert path 
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    from Rev 721 to Rev 722
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Rev 721 → Rev 722

/trunk/gen_or1k_isa/sources/or32.c
196,8 → 196,8
{ "lf.sub.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x1", EF(lf_sub_s), 0 },
{ "lf.mul.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x2", EF(lf_mul_s), 0 },
{ "lf.div.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x3", EF(lf_div_s), 0 },
{ "lf.itof.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x4", EF(lf_itof_s), 0 },
{ "lf.ftoi.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x5", EF(lf_ftoi_s), 0 },
/*{ "lf.itof.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x4", EF(lf_itof_s), 0 },
{ "lf.ftoi.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x5", EF(lf_ftoi_s), 0 },*/
{ "lf.rem.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x6", EF(lf_rem_s), 0 },
{ "lf.madd.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x7", EF(lf_madd_s), 0 },
{ "lf.sfeq.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0x8", EF(lf_sfeq_s), 0 },
212,8 → 212,8
{ "lf.sub.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
{ "lf.mul.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
{ "lf.div.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
{ "lf.itof.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
{ "lf.ftoi.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
/*{ "lf.itof.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
{ "lf.ftoi.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },*/
{ "lf.rem.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
{ "lf.madd.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
{ "lf.sfeq.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
/trunk/gen_or1k_isa/sources/opcode/or32.c
196,8 → 196,8
{ "lf.sub.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x1", EF(lf_sub_s), 0 },
{ "lf.mul.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x2", EF(lf_mul_s), 0 },
{ "lf.div.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x3", EF(lf_div_s), 0 },
{ "lf.itof.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x4", EF(lf_itof_s), 0 },
{ "lf.ftoi.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x5", EF(lf_ftoi_s), 0 },
/*{ "lf.itof.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x4", EF(lf_itof_s), 0 },
{ "lf.ftoi.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x5", EF(lf_ftoi_s), 0 },*/
{ "lf.rem.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x6", EF(lf_rem_s), 0 },
{ "lf.madd.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x7", EF(lf_madd_s), 0 },
{ "lf.sfeq.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0x8", EF(lf_sfeq_s), 0 },
212,8 → 212,8
{ "lf.sub.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
{ "lf.mul.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
{ "lf.div.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
{ "lf.itof.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
{ "lf.ftoi.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
/*{ "lf.itof.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
{ "lf.ftoi.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },*/
{ "lf.rem.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
{ "lf.madd.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
{ "lf.sfeq.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
/trunk/insight/opcodes/or32.c
196,8 → 196,8
{ "lf.sub.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x1", EF(lf_sub_s), 0 },
{ "lf.mul.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x2", EF(lf_mul_s), 0 },
{ "lf.div.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x3", EF(lf_div_s), 0 },
{ "lf.itof.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x4", EF(lf_itof_s), 0 },
{ "lf.ftoi.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x5", EF(lf_ftoi_s), 0 },
/*{ "lf.itof.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x4", EF(lf_itof_s), 0 },
{ "lf.ftoi.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x5", EF(lf_ftoi_s), 0 },*/
{ "lf.rem.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x6", EF(lf_rem_s), 0 },
{ "lf.madd.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x7", EF(lf_madd_s), 0 },
{ "lf.sfeq.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0x8", EF(lf_sfeq_s), 0 },
212,8 → 212,8
{ "lf.sub.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
{ "lf.mul.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
{ "lf.div.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
{ "lf.itof.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
{ "lf.ftoi.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
/*{ "lf.itof.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
{ "lf.ftoi.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },*/
{ "lf.rem.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
{ "lf.madd.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
{ "lf.sfeq.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
/trunk/or1ksim/cpu/or32/execute.c
44,9 → 44,6
/* General purpose registers. */
machword reg[MAX_GPRS];
 
/* Floating point registers. */
machword freg[MAX_GPRS];
 
/* Instruction queue */
struct iqueue_entry iqueue[20];
 
/trunk/or1ksim/cpu/or32/insnset.c
477,13 → 477,13
/* Single precision */
INSTRUCTION (lf_add_s) {
IFF (config.cpu.dependstats) current->func_unit = it_float;
freg[get_operand(0)] = (machword)((float)freg[get_operand(1)] + (float)freg[get_operand(2)]);
set_operand32(0, (machword)((float)eval_operand32(1, &breakpoint) + (float)eval_operand32(2, &breakpoint)), &breakpoint);
}
INSTRUCTION (lf_div_s) {
IFF (config.cpu.dependstats) current->func_unit = it_float;
freg[get_operand(0)] = (machword)((float)freg[get_operand(1)] / (float)freg[get_operand(2)]);
set_operand32(0, (machword)((float)eval_operand32(1, &breakpoint) / (float)eval_operand32(2, &breakpoint)), &breakpoint);
}
INSTRUCTION (lf_ftoi_s) {
/*INSTRUCTION (lf_ftoi_s) {
IFF (config.cpu.dependstats) current->func_unit = it_float;
set_operand32(0, freg[get_operand(1)], &breakpoint);
}
490,54 → 490,53
INSTRUCTION (lf_itof_s) {
IFF (config.cpu.dependstats) current->func_unit = it_float;
freg[get_operand(0)] = eval_operand32(1, &breakpoint);
}
}*/
INSTRUCTION (lf_madd_s) {
IFF (config.cpu.dependstats) current->func_unit = it_float;
freg[get_operand(0)] = (machword)((float)freg[get_operand(0)] + (float)freg[get_operand(1)] * (float)freg[get_operand(2)]);
set_operand32(0, (machword)((float)eval_operand32(0, &breakpoint) + (float)eval_operand32(1, &breakpoint) * (float)eval_operand32(2, &breakpoint)), &breakpoint);
}
INSTRUCTION (lf_mul_s) {
IFF (config.cpu.dependstats) current->func_unit = it_float;
freg[get_operand(0)] = (machword)((float)freg[get_operand(1)] * (float)freg[get_operand(2)]);
set_operand32(0, (machword)((float)eval_operand32(1, &breakpoint) * (float)eval_operand32(2, &breakpoint)), &breakpoint);
}
INSTRUCTION (lf_rem_s) {
float temp = (float)eval_operand32(1, &breakpoint) / (float)eval_operand32(2, &breakpoint);
IFF (config.cpu.dependstats) current->func_unit = it_float;
freg[get_operand(0)] = (machword)(
(float)freg[get_operand(1)] / (float)freg[get_operand(2)]
- (int)(float)freg[get_operand(1)] / (int)(float)freg[get_operand(2)]);
set_operand32(0, temp - (machword)temp, &breakpoint);
}
INSTRUCTION (lf_sfeq_s) {
IFF (config.cpu.dependstats) current->func_unit = it_float;
flag = (float)freg[get_operand(0)] == (float)freg[get_operand(1)];
flag = (float)eval_operand32(0, &breakpoint) == (float)eval_operand32(1, &breakpoint);
setsprbits(SPR_SR, SPR_SR_F, flag);
}
INSTRUCTION (lf_sfge_s) {
IFF (config.cpu.dependstats) current->func_unit = it_float;
flag = (float)freg[get_operand(0)] >= (float)freg[get_operand(1)];
flag = (float)eval_operand32(0, &breakpoint) >= (float)eval_operand32(1, &breakpoint);
setsprbits(SPR_SR, SPR_SR_F, flag);
}
INSTRUCTION (lf_sfgt_s) {
IFF (config.cpu.dependstats) current->func_unit = it_float;
flag = (float)freg[get_operand(0)] > (float)freg[get_operand(1)];
flag = (float)eval_operand32(0, &breakpoint) > (float)eval_operand32(1, &breakpoint);
setsprbits(SPR_SR, SPR_SR_F, flag);
}
INSTRUCTION (lf_sfle_s) {
IFF (config.cpu.dependstats) current->func_unit = it_float;
flag = (float)freg[get_operand(0)] <= (float)freg[get_operand(1)];
flag = (float)eval_operand32(0, &breakpoint) <= (float)eval_operand32(1, &breakpoint);
setsprbits(SPR_SR, SPR_SR_F, flag);
}
INSTRUCTION (lf_sflt_s) {
IFF (config.cpu.dependstats) current->func_unit = it_float;
flag = (float)freg[get_operand(0)] < (float)freg[get_operand(1)];
flag = (float)eval_operand32(0, &breakpoint) < (float)eval_operand32(1, &breakpoint);
setsprbits(SPR_SR, SPR_SR_F, flag);
}
INSTRUCTION (lf_sfne_s) {
IFF (config.cpu.dependstats) current->func_unit = it_float;
flag = (float)freg[get_operand(0)] != (float)freg[get_operand(1)];
flag = (float)eval_operand32(0, &breakpoint) != (float)eval_operand32(1, &breakpoint);
setsprbits(SPR_SR, SPR_SR_F, flag);
}
INSTRUCTION (lf_sub_s) {
IFF (config.cpu.dependstats) current->func_unit = it_float;
freg[get_operand(0)] = (machword)((float)freg[get_operand(1)] - (float)freg[get_operand(2)]);
set_operand32(0, (machword)((float)eval_operand32(1, &breakpoint) - (float)eval_operand32(2, &breakpoint)), &breakpoint);
}
 
/******* Custom instructions *******/
/trunk/or1ksim/cpu/or32/or32.c
196,8 → 196,8
{ "lf.sub.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x1", EF(lf_sub_s), 0 },
{ "lf.mul.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x2", EF(lf_mul_s), 0 },
{ "lf.div.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x3", EF(lf_div_s), 0 },
{ "lf.itof.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x4", EF(lf_itof_s), 0 },
{ "lf.ftoi.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x5", EF(lf_ftoi_s), 0 },
/*{ "lf.itof.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x4", EF(lf_itof_s), 0 },
{ "lf.ftoi.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x5", EF(lf_ftoi_s), 0 },*/
{ "lf.rem.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x6", EF(lf_rem_s), 0 },
{ "lf.madd.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x7", EF(lf_madd_s), 0 },
{ "lf.sfeq.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0x8", EF(lf_sfeq_s), 0 },
212,8 → 212,8
{ "lf.sub.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
{ "lf.mul.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
{ "lf.div.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
{ "lf.itof.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
{ "lf.ftoi.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
/*{ "lf.itof.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
{ "lf.ftoi.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },*/
{ "lf.rem.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
{ "lf.madd.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
{ "lf.sfeq.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 },

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