URL
https://opencores.org/ocsvn/8051/8051/trunk
Subversion Repositories 8051
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- This comparison shows the changes necessary to convert path
/
- from Rev 73 to Rev 74
- ↔ Reverse comparison
Rev 73 → Rev 74
/trunk/bench/verilog/oc8051_tb.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.6 2002/10/24 13:36:53 simont |
// add instruction cache and DELAY parameters for external ram, rom |
// |
// Revision 1.5 2002/10/17 19:00:50 simont |
// add external rom |
// |
114,13 → 117,13
// cache |
// |
// |
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`ifdef OC8051_CACHE |
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wire istb_i, icyc_i, iack_o; |
wire [15:0] iadr_i; |
wire [31:0] idat_o; |
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`ifdef OC8051_CACHE |
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oc8051_icache oc8051_icache1(.rst(rst), .clk(clk), |
// oc8051 |
.adr_i(iadr_o), .dat_o(idat_i), .stb_i(istb_o), .ack_o(iack_i), |
133,8 → 136,8
.stb_i(istb_i), .cyc_i(icyc_i), .ack_o(iack_o)); |
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defparam oc8051_icache1.ADR_WIDTH = 6; // cache address wihth |
defparam oc8051_icache1.LINE_WIDTH = 3; // line address width (2 => 4x32) |
defparam oc8051_icache1.BL_NUM = 7; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH |
defparam oc8051_icache1.LINE_WIDTH = 2; // line address width (2 => 4x32) |
defparam oc8051_icache1.BL_NUM = 15; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH |
defparam oc8051_icache1.CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH) |
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143,9 → 146,18
// |
`else |
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oc8051_xrom oc8051_xrom1(.rst(rst), .clk(clk), .addr(iadr_o), .data(idat_i), |
.stb_i(istb_o), .cyc_i(icyc_o), .ack_o(iack_i)); |
oc8051_wb_iinterface oc8051_wb_iinterface(.rst(rst), .clk(clk), |
// oc8051 |
.adr_i(iadr_o), .dat_o(idat_i), .stb_i(istb_o), .ack_o(iack_i), |
.cyc_i(icyc_o), |
// external rom |
.dat_i(idat_o), .stb_o(istb_i), .adr_o(iadr_i), .ack_i(iack_o), |
.cyc_o(icyc_i)); |
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oc8051_xrom oc8051_xrom1(.rst(rst), .clk(clk), .addr(iadr_i), .data(idat_o), |
.stb_i(istb_i), .cyc_i(icyc_i), .ack_o(iack_o)); |
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`endif |
// |
// |
153,8 → 165,38
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defparam oc8051_xrom1.DELAY = 5; |
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// |
// test wb interface |
// |
reg [31:0] log_file; |
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initial |
begin |
log_file = $fopen("log_file"); |
$fdisplay(log_file, "file open"); |
end |
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// cache/cpu to instruction rom |
// |
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WB_BUS_MON wb_bus_mon1(.CLK_I(clk), .RST_I(rst), .ACK_I(iack_o), .ADDR_O({16'h0000, iadr_i}), .CYC_O(icyc_i), |
.DAT_I(idat_o), .DAT_O(32'd0), .ERR_I(1'b0), .RTY_I(1'b0), .SEL_O(4'b0000), .STB_O(istb_i), |
.WE_O(1'b0), .TAG_I(4'h0), .TAG_O(4'h0), .CAB_O(1'b0), .log_file_desc(log_file)); |
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// cpu to data ram |
// |
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WB_BUS_MON wb_bus_mon3(.CLK_I(clk), .RST_I(rst), .ACK_I(ack_i), .ADDR_O({16'h0000, ext_addr}), .CYC_O(cyc_o), |
.DAT_I({24'h000000, data_in}), .DAT_O({24'h000000, data_out}), .ERR_I(1'b0), .RTY_I(1'b0), .SEL_O(4'b0000), .STB_O(stb_o), |
.WE_O(write), .TAG_I(4'h0), .TAG_O(4'h0), .CAB_O(1'b0), .log_file_desc(log_file)); |
// |
// |
// |
// |
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assign write_xram = p3_out[7] & write; |
assign write_uart = !p3_out[7] & write; |
assign data_in = p3_out[7] ? data_out_xram : data_out_uart; |
179,6 → 221,7
//#444000 |
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#7000000 |
$fclose(log_file); |
$display("time ",$time, "\n faulire: end of time\n \n"); |
$finish; |
end |
206,6 → 249,7
$display(" testvecp %h", buff[num]); |
$display(" p_out %h%h%h", p0_out, p1_out, p2_out); |
#22 |
$fclose(log_file); |
$finish; |
end |
else begin |
215,6 → 259,7
begin |
$display(""); |
$display(" Done!"); |
$fclose(log_file); |
$finish; |
end |
end |