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URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

Subversion Repositories s1_core

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  • This comparison shows the changes necessary to convert path
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    from Rev 73 to Rev 74
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Rev 73 → Rev 74

/trunk/hdl/filelist.dc
148,23 → 148,35
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/s1_top/int_ctrl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/s1_top/spc2wbm.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/s1_top/s1_top.v
# The Tcl script under $S1_ROOT/tools/src/build_dc.cmd is attached at the end of the filelist for DC;
# if you modify this file *REMEMBER* to run 'update_filelist' or you'll run the old version!!!
 
/* If you modify this file remember to run update_filelist so that filelist.dc gets updated!!! */
 
elaborate s1_top
link
uniquify
/* check_design */
check_design
 
create_clock -period 2.0 -name sys_clock_i find(port, "sys_clock_i")
set_input_delay 1 -max -clock sys_clock_i all_inputs() - find(port, "sys_clock_i")
set_output_delay 1 -max -clock sys_clock_i all_outputs()
# Constraints
 
compile -map_effort high
create_clock -name "sys_clock_i" -period 2.0 -waveform {0 1.0} [get_ports "sys_clock_i"]
set_dont_touch_network [get_clocks "sys_clock_i"]
set_input_delay 1.25 -max -rise -clock "sys_clock_i" [get_ports "sys_reset_i"]
set_input_delay 1.25 -max -fall -clock "sys_clock_i" [get_ports "sys_reset_i"]
set_output_delay 1.25 -clock sys_clock_i -max -rise [all_outputs]
set_output_delay 1.25 -clock sys_clock_i -max -fall [all_outputs]
set_wire_load_mode "enclosed"
 
write -format db -hierarchy -output s1_top.db
write -format verilog -hierarchy -output s1_top.v
# Compile
 
compile
 
# Export
 
write -format db -hierarchy -output "s1_top.db"
write -format verilog -hierarchy -output "s1_top.v"
 
# Report
 
report_area > report_area.txt
report_timing > report_timing.txt
report_constraint -all_violators > report_constraint.txt

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