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Rev 734 → Rev 735
/trunk/or1200/rtl/verilog/or1200_defines.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.8 2002/02/11 04:33:17 lampret |
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. |
// |
// Revision 1.7 2002/02/01 19:56:54 lampret |
// Fixed combinational loops. |
// |
134,7 → 137,7
// |
//`define OR1200_VERBOSE |
|
//`define OR1200_ASIC |
`define OR1200_ASIC |
//////////////////////////////////////////////////////// |
// |
// Typical configuration for an ASIC |
185,8 → 188,8
// |
// Select between ASIC optimized and generic multiplier |
// |
`define OR1200_ASIC_MULTP2_32X32 |
//`define OR1200_GENERIC_MULTP2_32X32 |
//`define OR1200_ASIC_MULTP2_32X32 |
`define OR1200_GENERIC_MULTP2_32X32 |
|
// |
// Size/type of insn/data cache if implemented |
995,10 → 998,10
// Cache inhibit while DMMU is not enabled/implemented |
// |
// cache inhibited 0GB-4GB 1'b1 |
// cache inhibited 0GB-2GB !dcpu_adr_[31] |
// cache inhibited 0GB-1GB 2GB-3GB !dcpu_adr_[30] |
// cache inhibited 1GB-2GB 3GB-4GB dcpu_adr_[30] |
// cache inhibited 2GB-4GB (default) dcpu_adr_[31] |
// cache inhibited 0GB-2GB !dcpu_adr_i[31] |
// cache inhibited 0GB-1GB 2GB-3GB !dcpu_adr_i[30] |
// cache inhibited 1GB-2GB 3GB-4GB dcpu_adr_i[30] |
// cache inhibited 2GB-4GB (default) dcpu_adr_i[31] |
// cached 0GB-4GB 1'b0 |
// |
`define OR1200_DMMU_CI dcpu_adr_i[31] |
1052,15 → 1055,16
|
// |
// Cache inhibit while IMMU is not enabled/implemented |
// Note: all combinations that use icpu_adr_i cause async loop |
// |
// cache inhibited 0GB-4GB 1'b1 |
// cache inhibited 0GB-2GB !icpu_adr_[31] |
// cache inhibited 0GB-1GB 2GB-3GB !icpu_adr_[30] |
// cache inhibited 1GB-2GB 3GB-4GB icpu_adr_[30] |
// cache inhibited 2GB-4GB (default) icpu_adr_[31] |
// cache inhibited 0GB-2GB !icpu_adr_i[31] |
// cache inhibited 0GB-1GB 2GB-3GB !icpu_adr_i[30] |
// cache inhibited 1GB-2GB 3GB-4GB icpu_adr_i[30] |
// cache inhibited 2GB-4GB (default) icpu_adr_i[31] |
// cached 0GB-4GB 1'b0 |
// |
`define OR1200_IMMU_CI icpu_adr_i[31] |
`define OR1200_IMMU_CI 1'b0 |
|
|
///////////////////////////////////////////////// |