URL
https://opencores.org/ocsvn/or1k/or1k/trunk
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- This comparison shows the changes necessary to convert path
/
- from Rev 736 to Rev 737
- ↔ Reverse comparison
Rev 736 → Rev 737
/trunk/or1200/rtl/verilog/or1200_du.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2002/02/11 04:33:17 lampret |
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. |
// |
// Revision 1.4 2002/01/28 01:16:00 lampret |
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. |
// |
151,8 → 154,13
// |
// Some connections go directly from the CPU through DU to Debug I/F |
// |
`ifdef OR1200_DU_STATUS_UNIMPLEMENTED |
assign dbg_lss_o = 4'b0000; |
assign dbg_is_o = 2'b00; |
`else |
assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000; |
assign dbg_is_o = {1'b0, icpu_cycstb_i}; |
`endif |
assign dbg_wp_o = 11'b000_0000_0000; |
assign dbg_dat_o = du_dat_i; |
|
/trunk/or1200/rtl/verilog/or1200_defines.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.9 2002/03/11 01:26:26 lampret |
// Fixed async loop. Changed multiplier type for ASIC. |
// |
// Revision 1.8 2002/02/11 04:33:17 lampret |
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. |
// |
137,7 → 140,7
// |
//`define OR1200_VERBOSE |
|
`define OR1200_ASIC |
//`define OR1200_ASIC |
//////////////////////////////////////////////////////// |
// |
// Typical configuration for an ASIC |
879,6 → 882,8
`define OR1200_DU_OP_READSPR 3'd4 |
`define OR1200_DU_OP_WRITESPR 3'd5 |
|
// Define if IF/LSU status is not needed by devel i/f |
`define OR1200_DU_STATUS_UNIMPLEMENTED |
|
///////////////////////////////////////////////////// |
// |