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URL https://opencores.org/ocsvn/or1k/or1k/trunk

1,6 → 1,6

#define DW 32 /* Data width of memory model generated by dumpverilog in bits */

#define DWQ (DW/8) /* Same as DW but units are bytes */

#define DISWIDTH 20 /* Width of disassembled message in bytes */

#define DISWIDTH 25 /* Width of disassembled message in bytes */

#define OR1K_MEM_VERILOG_HEADER(MODNAME, FROMADDR, TOADDR, DISWIDTH) "\n\

`include \"general.h\"\n\n\

10,7 → 10,7

 // Data out is not registered. Address bits specify dw-word (narrowest \n\
 // addressed data is not byte but dw-word !). \n
 // There are still some bugs in generated output (dump word aligned regions)\n\n\
-module %s(clk, data, addr, ce, we);\n\n\
+module %s(clk, data, addr, ce, we, disout);\n\n\
 parameter dw = 32;\n\
 parameter amin = %d;\n\n\
 parameter amax = %d;\n\n\

18,12 → 18,14

 inout [dw-1:0] data;\n\
 input [31:0] addr;\n\
 input ce;\n\
-input we;\n\n\
+input we;\n\
+output [%d:0] disout;\n\n\
+reg  [%d:0] disout;\n\
 reg  [dw-1:0] mem [amax:amin];\n\
-reg  [%d-1:0] dis [amax:amin];\n\
+reg  [%d:0] dis [amax:amin];\n\
 reg  [dw-1:0] dataout;\n\
 tri  [dw-1:0] data = (ce && ~we) ? dataout : 'bz;\n\n\
-initial begin\n", MODNAME, FROMADDR, TOADDR, DISWIDTH
+initial begin\n", MODNAME, FROMADDR, TOADDR, DISWIDTH-1, DISWIDTH-1, DISWIDTH-1
 #define OR1K_MEM_VERILOG_FOOTER "\n\
 end\n\n\

30,6 → 32,7

always @(posedge clk) begin\n\

if (ce && ~we) begin\n\

dataout <= #1 mem[addr];\n\

disout <= #1 dis[addr];\n\

$display(\"or1k_mem: reading mem[%%0d]:%%h dis: %%0s\", addr, dataout, dis[addr]);\n\

end else\n\

if (ce && we) begin\n\

33,10 → 33,11

 /* Length of printf format string */
 #define FMTLEN 2000
-void simprintf(unsigned long stackaddr, unsigned long regparam)
+char fmtstr[FMTLEN];
+char *simgetstr(unsigned long stackaddr, unsigned long regparam)
 {
         unsigned long fmtaddr;
-        char fmtstr[FMTLEN];
         FILE *f;
         int i;

55,6 → 56,17

         }
         fmtstr[i] = '\0';
+        return fmtstr;
+}
+void simprintf(unsigned long stackaddr, unsigned long regparam)
+{
+        unsigned long fmtaddr;
+        FILE *f;
+        int i = 0;
+        simgetstr(stackaddr, regparam);
         debug("simprintf: stackaddr: 0x%.8lx", stackaddr);
         if ((f = fopen("stdout.txt", "a+"))) {
                 unsigned long arg;

/trunk/or1ksim/support/dumpverilog.c

92,10 → 92,10

                         printf("\n%.8x:  ", i);
                 /* don't print ascii chars below 0x20. */
-                if (eval_mem32(i) < 0x20)
-                        printf("0x%.2x     ", (unsigned char)eval_mem32(i));
+                if (evalsim_mem32(i) < 0x20)
+                        printf("0x%.2x     ", (unsigned char)evalsim_mem32(i));
                 else
-                        printf("0x%.2x'%c'  ", (unsigned char)eval_mem32(i), (unsigned char)eval_mem32(i));
+                        printf("0x%.2x'%c'  ", (unsigned char)evalsim_mem32(i), (unsigned char)evalsim_mem32(i));
         }
         printf(OR1K_MEM_VERILOG_FOOTER);