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URL https://opencores.org/ocsvn/pci_blue_interface/pci_blue_interface/trunk

Subversion Repositories pci_blue_interface

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    from Rev 74 to Rev 75
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Rev 74 → Rev 75

/trunk/test_pci_target.dsk
0,0 → 1,10
<!DOCTYPE Desktop SYSTEM "hdl-prj.dtd">
<Desktop>
<ProjectWindow X="45" Y="29" W="692" H="554">
<Column>443</Column>
<Column>60</Column>
<Column>50</Column>
<Column>50</Column>
</ProjectWindow>
<SourceWindow X="170" Y="85" W="904" H="620" File="pci_blue_submodule_test\test_pci_target.v" Line="1051"></SourceWindow>
</Desktop>
/trunk/pci_blue_submodule_test/test_pci_target.v
1,5 → 1,5
//===========================================================================
// $Id: test_pci_target.v,v 1.5 2001-09-04 04:51:56 bbeaver Exp $
// $Id: test_pci_target.v,v 1.6 2001-09-07 11:28:53 bbeaver Exp $
//
// Copyright 2001 Blue Beaver. All Rights Reserved.
//
60,8 → 60,6
// The waveforms will be examined to determine pass
// or fail.
//
// NOTE: NOT WORKED ON YET. A copy of TEST_PCI_MASTER!
//
//===========================================================================
 
`timescale 1ns/1ps
153,6 → 151,7
output new_data;
output inc; // TEMPORARY
 
// `define TARGET_INCLUDED
`ifdef TARGET_INCLUDED
// GROSS debugging signal. Only here to put signal in waveform.
assign pci_state[4:0] = pci_blue_target.PCI_Master_State[4:0]; // TEMPORARY
360,6 → 359,9
task write_reg;
input [PCI_BUS_CBE_RANGE:0] ref_type;
begin
pci_ad_in_comb[PCI_BUS_DATA_RANGE:0] = `PCI_BUS_DATA_X;
pci_cbe_l_in_comb[PCI_BUS_CBE_RANGE:0] = ref_type[PCI_BUS_CBE_RANGE:0];
pci_frame;
end
endtask
 
367,6 → 369,10
input [PCI_BUS_CBE_RANGE:0] ref_type;
input serr_requested;
begin
pci_ad_in_comb[PCI_BUS_DATA_RANGE:0] = `PCI_BUS_DATA_X;
pci_cbe_l_in_comb[PCI_BUS_CBE_RANGE:0] = ref_type[PCI_BUS_CBE_RANGE:0];
pci_frame;
inc_ext_addr;
end
endtask
 
374,6 → 380,16
input [PCI_BUS_CBE_RANGE:0] byte_enables;
input last_requested;
begin
pci_ad_in_comb[PCI_BUS_DATA_RANGE:0] = `PCI_BUS_DATA_X;
pci_cbe_l_in_comb[PCI_BUS_CBE_RANGE:0] = byte_enables[PCI_BUS_CBE_RANGE:0];
if (last_requested == 1'b1)
begin
pci_irdy;
end
else
begin
pci_frame; pci_irdy;
end
end
endtask
 
382,6 → 398,17
input last_requested;
input perr_requested;
begin
pci_ad_in_comb[PCI_BUS_DATA_RANGE:0] = `PCI_BUS_DATA_X;
pci_cbe_l_in_comb[PCI_BUS_CBE_RANGE:0] = byte_enables[PCI_BUS_CBE_RANGE:0];
if (last_requested == 1'b1)
begin
pci_irdy;
end
else
begin
pci_frame; pci_irdy;
end
inc_ext_data;
end
endtask
 
787,19 → 814,6
end
endtask
 
// delay signals like the Pads delay them
always @(posedge pci_clk)
begin
pci_ad_in_prev[PCI_BUS_DATA_RANGE:0] <= pci_ad_in_comb[PCI_BUS_DATA_RANGE:0];
pci_cbe_l_in_prev[PCI_BUS_CBE_RANGE:0] <= pci_cbe_l_in_comb[PCI_BUS_CBE_RANGE:0];
pci_frame_in_prev <= pci_frame_in_critical;
pci_irdy_in_prev <= pci_irdy_in_critical;
pci_devsel_in_prev <= pci_devsel_in_critical;
pci_trdy_in_prev <= pci_trdy_in_critical;
pci_stop_in_prev <= pci_stop_in_critical;
pci_perr_in_prev <= pci_perr_in_comb;
end
 
// Initialize signals which are set for 1 clock by tasks to create activity
initial
begin
819,6 → 833,19
pci_perr_in_prev <= 1'b0;
end
 
// delay signals like the Pads delay them
always @(posedge pci_clk)
begin
pci_ad_in_prev[PCI_BUS_DATA_RANGE:0] <= pci_ad_in_comb[PCI_BUS_DATA_RANGE:0];
pci_cbe_l_in_prev[PCI_BUS_CBE_RANGE:0] <= pci_cbe_l_in_comb[PCI_BUS_CBE_RANGE:0];
pci_frame_in_prev <= pci_frame_in_critical;
pci_irdy_in_prev <= pci_irdy_in_critical;
pci_devsel_in_prev <= pci_devsel_in_critical;
pci_trdy_in_prev <= pci_trdy_in_critical;
pci_stop_in_prev <= pci_stop_in_critical;
pci_perr_in_prev <= pci_perr_in_comb;
end
 
// Remove signals which are set for 1 clock by tasks to create activity
always @(posedge pci_clk)
begin
969,7 → 996,9
 
`endif // NORMAL_OPS
 
`ifdef TARGET_INCLUDED
pci_blue_target.report_missing_transitions;
`endif // TARGET_INCLUDED
 
do_reset;
do_clocks (4'h4);
/trunk/pci_blue_submodule_test/test_pci_master.v
1,5 → 1,5
//===========================================================================
// $Id: test_pci_master.v,v 1.25 2001-09-02 11:32:42 bbeaver Exp $
// $Id: test_pci_master.v,v 1.26 2001-09-07 11:28:52 bbeaver Exp $
//
// Copyright 2001 Blue Beaver. All Rights Reserved.
//
449,27 → 449,27
 
// Make shorthand command task so that it is easier to set things up.
// CRITICAL WRITE must always be READ + 1. Used in _pair task below.
parameter noop = 0;
parameter REG_READ = 1;
parameter REG_WRITE = 2;
parameter FENCE = 3;
parameter CONFIG_READ = 4;
parameter CONFIG_WRITE = 5;
parameter MEM_READ = 6;
parameter MEM_WRITE = 7;
parameter MEM_READ_SERR = 8;
parameter MEM_WRITE_SERR = 9;
parameter noop = 0;
parameter REG_READ = 1;
parameter REG_WRITE = 2;
parameter FENCE = 3;
parameter CONFIG_READ = 4;
parameter CONFIG_WRITE = 5;
parameter MEM_READ = 6;
parameter MEM_WRITE = 7;
parameter MEM_READ_SERR = 8;
parameter MEM_WRITE_SERR = 9;
 
parameter DATA = 10;
parameter DATA_PERR = 11;
parameter DATA_LAST = 12;
parameter DATA_LAST_PERR = 13;
parameter DATA = 10;
parameter DATA_PERR = 11;
parameter DATA_LAST = 12;
parameter DATA_LAST_PERR = 13;
 
parameter DEV = 1;
parameter DEV_TRANSFER_DATA = 2;
parameter DEV_RETRY_WITH_OLD_DATA = 3;
parameter DEV_RETRY_WITH_NEW_DATA = 4;
parameter TARGET_ABORT = 5;
parameter DEV = 1;
parameter DEV_TRANSFER_DATA = 2;
parameter DEV_RETRY_WITH_OLD_DATA = 3;
parameter DEV_RETRY_WITH_NEW_DATA = 4;
parameter TARGET_ABORT = 5;
 
task do_master_test;
input [7:0] total_time;
773,7 → 773,7
if (target_time_5[7:0] != 8'h00)
begin
for (dts5 = 8'h00; dts5 <= target_time_5[7:0]; dts5 = dts5 + 8'h01) @(negedge pci_clk);
if (target_dts_1[2:0] == DEV)
if (target_dts_5[2:0] == DEV)
begin pci_devsel; end
else if (target_dts_5[2:0] == DEV_TRANSFER_DATA)
begin pci_devsel; pci_trdy; end
889,19 → 889,6
end
endtask
 
// delay signals like the Pads delay them
always @(posedge pci_clk)
begin
pci_gnt_in_prev <= pci_gnt_in_critical;
pci_ad_in_prev[PCI_BUS_DATA_RANGE:0] <= pci_ad_in_comb[PCI_BUS_DATA_RANGE:0];
pci_devsel_in_prev <= pci_devsel_in_critical;
pci_frame_in_prev <= pci_frame_in_critical;
pci_irdy_in_prev <= pci_irdy_in_critical;
pci_trdy_in_prev <= pci_trdy_in_critical;
pci_stop_in_prev <= pci_stop_in_critical;
pci_perr_in_prev <= pci_perr_in_comb;
end
 
// Initialize signals which are set for 1 clock by tasks to create activity
initial
begin
924,6 → 911,19
pci_perr_in_prev <= 1'b0;
end
 
// delay signals like the Pads delay them
always @(posedge pci_clk)
begin
pci_gnt_in_prev <= pci_gnt_in_critical;
pci_ad_in_prev[PCI_BUS_DATA_RANGE:0] <= pci_ad_in_comb[PCI_BUS_DATA_RANGE:0];
pci_devsel_in_prev <= pci_devsel_in_critical;
pci_frame_in_prev <= pci_frame_in_critical;
pci_irdy_in_prev <= pci_irdy_in_critical;
pci_trdy_in_prev <= pci_trdy_in_critical;
pci_stop_in_prev <= pci_stop_in_critical;
pci_perr_in_prev <= pci_perr_in_comb;
end
 
// Remove signals which are set for 1 clock by tasks to create activity
always @(posedge pci_clk)
begin
/trunk/test_pci_target.hpj
0,0 → 1,62
<!DOCTYPE SimulationProject SYSTEM "hdl-prj.dtd">
<SimulationProject Logfile="verilog.log" Keyfile="..\..\VLogger\verilog.key" Language="Verilog" DelayType="typical" AddTopLevelSignals="1" FileNamesShown="1" HideEmptyLists="1" ShowWatch="1" DumpWatch="0" InteractiveMode="1" ParametersAreWatchable="0" ClearLogBeforeCompile="1" AutoParseProject="0">
<UserSourceFileList>
<File IsIndirectlyAdded="0">pci_blue_submodule_test\test_pci_target.v</File>
<File IsIndirectlyAdded="0">pci_blue_fifos\pci_blue_fifos.v</File>
<File IsIndirectlyAdded="0">pci_blue_fifos\pci_blue_fifo_flags.v</File>
<File IsIndirectlyAdded="0">pci_vendor_lib\pci_vendor_lib.v</File>
<File IsIndirectlyAdded="0">pci_blue_target\pci_blue_config_regs.v</File>
<File IsIndirectlyAdded="0">..\misc\synchronizer_flop.v</File>
<File IsIndirectlyAdded="1">pci_blue_include\pci_blue_options.vh</File>
<File IsIndirectlyAdded="1">pci_blue_include\pci_blue_constants.vh</File>
</UserSourceFileList>
<DirList>
<Directory>..\..\SYNAPTICAD.7.9C</Directory>
<Directory>..\..\SYNAPTICAD.7.9C</Directory>
<Directory>..\..\SYNAPTICAD.7.4</Directory>
<Directory>..\..\SYNAPTICAD</Directory>
<Directory>..\..\VLOGGER</Directory>
<Directory>pci_blue_include</Directory>
</DirList>
<LibDirList>
<Directory>..\..\SYNAPTICAD.7.9C\lib\verilog</Directory>
<Directory>..\..\SYNAPTICAD.7.9C\lib\verilog</Directory>
<Directory>..\..\SYNAPTICAD.7.4\lib\verilog</Directory>
<Directory>..\..\SYNAPTICAD\lib\verilog</Directory>
<Directory>..\..\VLOGGER\lib\verilog</Directory>
</LibDirList>
<LibExtensionList>
<Extension>.v</Extension>
<Extension>.vo</Extension>
<Extension>.vh</Extension>
</LibExtensionList>
<TBenchProperties>
<TBenchProp Value="False">VerboseSamples</TBenchProp>
<TBenchProp Value="False">VerboseSequenceVerification</TBenchProp>
<TBenchProp Value="False">VerboseDelays</TBenchProp>
<TBenchProp Value="False">VerboseFileInput</TBenchProp>
<TBenchProp Value="Sample state matches">SampleIf</TBenchProp>
<TBenchProp Value="Do nothing">SampleThen</TBenchProp>
<TBenchProp Value="Display message">SampleElse</TBenchProp>
<TBenchProp Value="output">SignalDirection</TBenchProp>
<TBenchProp Value="True">GenerateSampleHdlCode</TBenchProp>
<TBenchProp Value="True">GenerateMarkerHdlCode</TBenchProp>
<TBenchProp Value="True">GenerateDelayHdlCode</TBenchProp>
<TBenchProp Value="True">ExecuteFromTopLevel</TBenchProp>
<TBenchProp Value="SysClock">CycleClock</TBenchProp>
<TBenchProp Value="neg">CycleClockEdge</TBenchProp>
<TBenchProp Value="Never">VerilogTimeOutLength</TBenchProp>
<TBenchProp Value="Never">VhdlTimeOutLength</TBenchProp>
<TBenchProp Value="Never">SystemCTimeOutLength</TBenchProp>
<TBenchProp Value="Never">VeraTimeOutLength</TBenchProp>
<TBenchProp Value="True">VerilogIncludeDelayTime</TBenchProp>
<TBenchProp Value="True">VhdlIncludeDelayTime</TBenchProp>
<TBenchProp Value="False">SystemCIncludeDelayTime</TBenchProp>
<TBenchProp Value="False">VeraIncludeDelayTime</TBenchProp>
<TBenchProp Value="wire">VerilogSignalType</TBenchProp>
<TBenchProp Value="std_logic">VhdlSignalType</TBenchProp>
<TBenchProp Value="sc_bit">SystemCSignalType</TBenchProp>
<TBenchProp Value="True">VhdlGenerateAbortCode</TBenchProp>
<TBenchProp Value="True">SystemCGenerateAbortCode</TBenchProp>
</TBenchProperties>
</SimulationProject>
/trunk/function_lib/crc32_lib.v File deleted

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