OpenCores
URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 74 to Rev 75
    ↔ Reverse comparison
  •

Rev 74 → Rev 75

/trunk/vhdl/barrel.vhd
0,0 → 1,99
-------------------------------------------------------------------------------
-- File: ex_stage.vhd
-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
-- Created: 2006-11-29
-- Last updated: 2006-11-29
 
-- Description:
-- Barrel shifter
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_ARITH.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use WORK.RISE_PACK.all;
use WORK.RISE_PACK_SPECIFIC.all;
 
library UNISIM;
use UNISIM.VComponents.all;
 
 
use WORK.RISE_PACK.all;
use work.RISE_PACK_SPECIFIC.all;
 
entity barrel_shifter is
port (reg_a : in std_logic_vector(15 downto 0);
reg_b : in REGISTER_T;
left : in std_logic;
arithmetic : in std_logic;
reg_q : out REGISTER_T);
end barrel_shifter;
 
 
architecture barrel_shifter_rtl of barrel_shifter is
signal shifter_value : REGISTER_T;
signal mult_b_in : std_logic_vector(17 downto 0);
signal mult_a_in : std_logic_vector(17 downto 0);
signal mult_p_out : std_logic_vector(35 downto 0);
 
component MULT18X18
port (A : in std_logic_vector(17 downto 0);
B : in std_logic_vector(17 downto 0);
P : out std_logic_vector(35 downto 0)
);
end component;
 
function reverse_register (reg_in : REGISTER_T) return REGISTER_T is
variable reversed : REGISTER_T;
begin
for i in 0 to (ARCHITECTURE_WIDTH - 1) loop
reversed(i) := reg_in (ARCHITECTURE_WIDTH - 1 - i);
end loop;
return reversed;
end reverse_register;
begin
MULT18X18_inst : MULT18X18
port map (
P => mult_p_out, -- 36-bit multiplier output
A => mult_b_in, -- 18-bit multiplier input
B => mult_a_in -- 18-bit multiplier input
);
 
process(reg_b)
variable index : integer range 0 to 15;
begin
shifter_value <= x"0000";
index := to_integer(ieee.numeric_std.unsigned(reg_b(3 downto 0)));
shifter_value(index) <= '1';
end process;
 
process(shifter_value, reg_a, left)
begin
mult_b_in <= "00" & shifter_value;
if left = '1' then
mult_a_in <= "00" & reg_a;
else
mult_a_in <= "00" & reverse_register(reg_a);
end if;
end process;
 
process(mult_p_out, left, arithmetic, reg_a, reg_b)
begin
if left = '1' then
reg_q <= mult_p_out(ARCHITECTURE_WIDTH - 1 downto 0);
else
reg_q <= reverse_register(mult_p_out(ARCHITECTURE_WIDTH - 1 downto 0));
if arithmetic = '1' and reg_a(ARCHITECTURE_WIDTH - 1) = '1' then
for index in 0 to ARCHITECTURE_WIDTH - 1 loop
if index < reg_b then
reg_q(ARCHITECTURE_WIDTH - 1 - index) <= '1';
end if;
end loop;
end if;
end if;
end process;
end architecture;
/trunk/vhdl/tb_barrel.vhd
0,0 → 1,92
-------------------------------------------------------------------------------
-- File: tb_barrel.vhd
-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
-- Created: 2007-01-24
-- Last updated: 2006-11-29
 
-- Description:
-- Execute stage
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
 
entity tb_barrel_vhd is
end tb_barrel_vhd;
 
architecture behavior of tb_barrel_vhd is
 
-- Component Declaration for the Unit Under Test (UUT)
component barrel_shifter
port(
reg_a : in std_logic_vector(15 downto 0);
reg_b : in std_logic_vector(15 downto 0);
left : in std_logic;
arithmetic : in std_logic;
reg_q : out std_logic_vector(15 downto 0)
);
end component;
 
--Inputs
signal left : std_logic := '0';
signal arithmetic : std_logic := '0';
signal reg_a : std_logic_vector(15 downto 0) := (others => '0');
signal reg_b : std_logic_vector(15 downto 0) := (others => '0');
 
--Outputs
signal reg_q : std_logic_vector(15 downto 0);
 
begin
 
-- Instantiate the Unit Under Test (UUT)
uut : barrel_shifter port map(
reg_a => reg_a,
reg_b => reg_b,
left => left,
arithmetic => arithmetic,
reg_q => reg_q
);
 
tb : process
begin
 
-- Wait 100 ns for global reset to finish
wait for 100 ns;
 
-- shift left one bit
left <= '1';
arithmetic <= '0';
reg_a <= x"0020";
reg_b <= x"0001";
wait for 10 ns;
assert reg_q = x"0040";
 
-- shift left four bits
left <= '1';
arithmetic <= '0';
reg_a <= x"0021";
reg_b <= x"0004";
wait for 10 ns;
assert reg_q = x"0210";
 
-- shift right two bits
left <= '0';
arithmetic <= '0';
reg_a <= x"0300";
reg_b <= x"0002";
wait for 10 ns;
assert reg_q = x"00C0";
 
-- shift right two bits with arithmetic shift
left <= '0';
arithmetic <= '1';
reg_a <= x"8010";
reg_b <= x"0002";
wait for 10 ns;
assert reg_q = x"E004";
wait; -- will wait forever
end process;
 
end;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.