URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 74 to Rev 75
- ↔ Reverse comparison
Rev 74 → Rev 75
/socgen/trunk/bench/verilog/TestBench.ver
0,0 → 1,65
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* Testbench file used for all simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
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module TB( |
input wire clk, |
input wire reset |
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); |
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`include "./params.sim" |
`include "./dat.sim" |
`include "./dut" |
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endmodule |
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/socgen/trunk/bench/verilator/TestBench
0,0 → 1,59
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* Testbench file used for all simulations */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
|
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module TB( |
input wire clk, |
input wire reset |
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); |
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`include "./params.ver" |
`include "./dat.ver" |
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endmodule |
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/socgen/trunk/bench/verilator/sim_main.cpp
0,0 → 1,54
#include "VTB.h" |
#include "verilated.h" |
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VTB *TB; |
unsigned int main_time = 0; |
double sc_time_stamp () { |
return main_time; |
} |
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int main(int argc, char **argv) { |
Verilated::commandArgs(argc, argv); |
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TB = new VTB; |
TB-> reset = 1; |
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while (!Verilated::gotFinish()) |
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{ |
if (main_time > 100) { |
TB->reset = 0; |
// Deassert reset |
} |
if ((main_time % 10) == 1) { |
TB->clk = 1; |
// Toggle clock |
} |
if ((main_time % 10) == 6) { |
TB->clk = 0; |
} |
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TB->eval(); |
// Evaluate model |
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main_time++; |
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} |
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exit(0); |
} |
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/socgen/trunk/tools/install/Ubuntu_10.10/Makefile
34,6 → 34,7
sudo apt-get install -y build-essential;\ |
sudo apt-get install -y tkdiff;\ |
sudo apt-get install -y librxtx-java;\ |
sudo apt-get install -y verilator;\ |
) |
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/socgen/trunk/tools/bin/Makefile.root
14,8 → 14,48
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################################################################################ |
# Run verilator for lint check |
################################################################################ |
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.PHONY lint: |
lint: |
echo "################################################################################"; \ |
echo; \ |
chmod 755 filelist.ver ;\ |
./filelist.ver ;\ |
verilator --cc TB.v --exe ../../bench/verilator/sim_main.cpp -top-module TB -Wno-WIDTH 2> lint.log;\ |
echo "################################################################################"; \ |
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################################################################################ |
# preform linting for each variant |
################################################################################ |
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.PHONY build_lint: |
build_lint: |
@for VARIANT in `ls $(CUR_DIR)/../lint`; do \ |
echo "################################################################################"; \ |
echo; \ |
echo "Coverage: $$VARIANT ####"; echo; \ |
cd $(CUR_DIR)/../lint/$$VARIANT/;\ |
rm -f *.log;\ |
chmod 755 filelist.ver ;\ |
./filelist.ver ;\ |
verilator --cc TB.v --exe ../../bench/verilator/sim_main.cpp -top-module TB -Wno-WIDTH 2> lint.log;\ |
cd $(CUR_DIR) ;\ |
done; \ |
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################################################################################ |
# run simulation suite |
################################################################################ |
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42,11 → 82,11
echo "Coverage: $$VARIANT ####"; echo; \ |
cd $(CUR_DIR)/../cov/$$VARIANT/;\ |
rm -f *.log;\ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > coverage.v ;\ |
make build_cdd ;\ |
cd $(CUR_DIR) ;\ |
done; \ |
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################################################################################ |
# run coverage report after all sims |
################################################################################ |
72,7 → 112,7
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.PHONY run_sims: |
run_sims: clean_sims build_cov |
run_sims: clean_sims build_cov build_lint |
@for VARIANT_PROG in `ls $(CUR_DIR)/../run`; do \ |
echo "################################################################################"; \ |
echo; \ |
/socgen/trunk/tools/bin/soc_link
123,15 → 123,12
print " work/${project}/ip/${component}/rtl/\n"; |
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my $path = "work/${project}/ip/${component}/rtl/gen"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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my $path = "work/${project}/ip/${component}/rtl/gen/sim"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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my $path = "work/${project}/ip/${component}/rtl/gen/syn"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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142,8 → 139,69
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print "CREATING sim and cov filelists for $project $component $name $variant \n"; |
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#/*********************************************************************************************/ |
#/ */ |
#/ Create a params.ver file in every lint directory */ |
#/ */ |
#/ Read each variants parameters and defaults into an array and their order into an array */ |
#/ order must be preservered so that parameters can use the values of other parameters */ |
#/ */ |
#/*********************************************************************************************/ |
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$path = "work/${project}/ip/${component}/sim/lint"; |
mkdir $path,0755 unless( -e $path ); |
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$path = "work/${project}/ip/${component}/sim/lint/${variant}"; |
mkdir $path,0755 unless( -e $path ); |
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symlink( "${home}/tools/bin/Makefile.lint", "${home}/work/${project}/ip/${component}/sim/lint/${variant}/Makefile"); |
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my %default_parameters = (); |
my @parameter_order = (); |
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foreach my $i_name ($doc->findnodes("//component[name/text() = '$name']/parameters/parameter/name")) |
{ |
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my($parameter_name) = $i_name ->findnodes('./text()')->to_literal ; |
my($parameter_default) = $i_name ->findnodes('../default/text()')->to_literal ; |
$default_parameters{$parameter_name} = $parameter_default; |
push @parameter_order ,$parameter_name ; |
} |
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$outfile ="work/${project}/ip/${component}/sim/lint/${variant}/params.ver"; |
open VER_PARM_FILE,">$outfile" or die "unable to open $outfile"; |
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foreach my $parameter_name (@parameter_order) |
{ |
my($parameter_default) = $default_parameters{$parameter_name}; |
$default_parameters{$parameter_name} = $parameter_default; |
print VER_PARM_FILE "parameter ${parameter_name} = ${parameter_default};\n"; |
} |
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#/*********************************************************************************************/ |
#/ */ |
#/ Create filelists for sim cov lint and synthesis */ |
#/ */ |
#/ */ |
#/*********************************************************************************************/ |
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print "CREATING filelists for $project $component $name $variant \n"; |
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my $outfile ="work/${project}/ip/${component}/sim/cov/${variant}/filelist.cov"; |
open COVFILE,">$outfile" or die "unable to open $outfile"; |
158,8 → 216,15
open SYNFILE,">$outfile" or die "unable to open $outfile"; |
print SYNFILE "verilog work ../../../../../ip/${component}/rtl/gen/syn/${variant}.v \n"; |
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$outfile ="work/${project}/ip/${component}/sim/lint/${variant}/filelist.ver"; |
open VERFILE,">$outfile" or die "unable to open $outfile"; |
print VERFILE "cp ../../bench/verilator/TestBench TB.v\n"; |
print VERFILE "cat ../../../../../ip/${component}/rtl/gen/syn/${variant}.v >> TB.v \n"; |
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foreach my $i_name ($doc->findnodes("//component[name/text() = '$name']/brothers/module/name")) |
{ |
my($child) = $i_name ->findnodes('./text()')->to_literal ; |
166,6 → 231,7
my($child_parent) = $i_name ->findnodes('../component/text()')->to_literal ; |
print COVFILE "-v ../../../../${child_parent}/rtl/gen/syn/${child}.v\n"; |
print SIMFILE "../../../../${child_parent}/rtl/gen/sim/${child}.v\n"; |
print VERFILE "cat ../../../../${child_parent}/rtl/gen/syn/${child}.v >> TB.v\n"; |
print SYNFILE "verilog work ../../../../../ip/${child_parent}/rtl/gen/syn/${child}.v\n"; |
} |
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177,6 → 243,7
my($child_family) = $i_name ->findnodes('../project/text()')->to_literal ; |
print COVFILE "-v ../../../../../children/${child_family}/ip/${child_parent}/rtl/gen/syn/${child}.v\n"; |
print SIMFILE "../../../../../children/${child_family}/ip/${child_parent}/rtl/gen/sim/${child}.v\n"; |
print VERFILE "cat ../../../../../children/${child_family}/ip/${child_parent}/rtl/gen/syn/${child}.v >> TB.v\n"; |
print SYNFILE "verilog work ../../../../../children/${child_family}/ip/${child_parent}/rtl/gen/syn/${child}.v\n"; |
} |
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187,6 → 254,7
my($child_parent) = $i_name ->findnodes('../component/text()')->to_literal ; |
print COVFILE "-v ../../lib/${child_parent}/${child}.v\n"; |
print SIMFILE "../../lib/${child_parent}/${child}.v\n"; |
print VERFILE "cat ../../lib/${child_parent}/${child}.v >> TB.v\n"; |
print SYNFILE "verilog work ./target/lib/syn/${child_parent}/${child}.v\n"; |
} |
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194,9 → 262,6
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print "CREATING dut for $project $component $name $variant \n"; |
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204,6 → 269,10
open DUTFILE,">$outfile" or die "unable to open $outfile"; |
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my $outfile ="work/${project}/ip/${component}/sim/lint/${variant}/dat.ver"; |
open VDUTFILE,">$outfile" or die "unable to open $outfile"; |
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foreach my $i_name ($doc->findnodes("//component[name/text() = '$name']/interfaces/interface/name")) |
210,27 → 279,30
{ |
my($interface_name) = $i_name ->findnodes('./text()')->to_literal ; |
my($width) = $i_name ->findnodes('../width/text()')->to_literal ; |
print DUTFILE "wire ${width} ${interface_name};\n"; |
print DUTFILE "wire ${width} ${interface_name};\n"; |
print VDUTFILE "wire ${width} ${interface_name};\n"; |
} |
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print DUTFILE "\n\n\n $variant \n "; |
print VDUTFILE "\n\n\n $variant \n "; |
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my $first = 1; |
foreach my $i_name ($doc->findnodes("//component[name/text() = '$name']/parameters/parameter/name")) |
{ |
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my($interface_name) = $i_name ->findnodes('./text()')->to_literal ; |
my($parameter_name) = $i_name ->findnodes('./text()')->to_literal ; |
if($first) |
{ |
print DUTFILE " #(.${interface_name}(${interface_name})"; |
print DUTFILE " #(.${parameter_name}(${parameter_name})"; |
print VDUTFILE " #(.${parameter_name}(${parameter_name})"; |
$first=0; |
} |
else |
{ |
print DUTFILE ",\n .${interface_name}(${interface_name})"; |
print DUTFILE ",\n .${parameter_name}(${parameter_name})"; |
print VDUTFILE ",\n .${parameter_name}(${parameter_name})"; |
} |
} |
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237,12 → 309,14
if($first == 0) |
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{ |
print DUTFILE ")\n"; |
print DUTFILE ")\n"; |
print VDUTFILE ")\n"; |
} |
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print DUTFILE " dut \n ( \n"; |
print VDUTFILE " dut \n ( \n"; |
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$first = 1; |
foreach my $i_name ($doc->findnodes("//component[name/text() = '$name']/interfaces/interface/name")) |
252,16 → 326,19
if($first) |
{ |
print DUTFILE " .${interface_name} (${interface_name})"; |
print VDUTFILE " .${interface_name} (${interface_name})"; |
$first=0; |
} |
else |
{ |
print DUTFILE ",\n .${interface_name} (${interface_name})"; |
print VDUTFILE ",\n .${interface_name} (${interface_name})"; |
} |
} |
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print DUTFILE "\n );\n\n\n\n"; |
print VDUTFILE "\n );\n\n\n\n"; |
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279,6 → 356,12
"cp $infile $outfile" ; |
if (system($cmd)) {} |
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my $infile ="work/${project}/ip/${component}/sim/cov/${variant}/dut"; |
my $outfile ="work/${project}/ip/${component}/sim/run/${chip}/dat.sim"; |
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305,7 → 388,7
if (system($cmd)) {} |
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my $path = "work/${project}/ip/${component}/syn/${chip}/target"; |
print "Creating $path\n" unless( -e $path ); |
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mkdir $path,0755 unless( -e $path ); |
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334,15 → 417,12
my($child_family) = $i_name ->findnodes('../project/text()')->to_literal ; |
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my $path = "work/${project}/children"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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my $path = "work/${project}/children/${child_family}"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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my $path = "work/${project}/children/${child_family}/bin"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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357,7 → 437,6
symlink( "${home}/tools/bin/Makefile", "${home}/work/${project}/children/${child_family}/bin/Makefile"); |
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my $path = "work/${project}/children/${child_family}/sw"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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$root = "${home}/projects/${child_family}/sw"; |
367,11 → 446,9
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my $path = "work/${project}/children/${child_family}/ip"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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my $path = "work/${project}/children/${child_family}/ip/${child_parent}"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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$root = "${home}/projects/${child_family}/ip/${child_parent}"; |
380,15 → 457,12
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my $path = "${home}/work/${project}/children/${child_family}/ip/${child_parent}/rtl/gen"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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my $path = "${home}/work/${project}/children/${child_family}/ip/${child_parent}/rtl/gen/sim"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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my $path = "${home}/work/${project}/children/${child_family}/ip/${child_parent}/rtl/gen/syn"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
} |
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405,15 → 479,12
my($child_family) = $i_name ->findnodes('../project/text()')->to_literal ; |
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my $path = "work/${project}/children"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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my $path = "work/${project}/children/${child_family}"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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my $path = "work/${project}/children/${child_family}/bin"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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$root = "${home}/projects/${child_family}/bin"; |
424,7 → 495,6
symlink( "${home}/tools/bin/Makefile", "${home}/work/${project}/children/${child_family}/bin/Makefile"); |
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my $path = "work/${project}/children/${child_family}/sw"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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$root = "${home}/projects/${child_family}/sw"; |
432,11 → 502,9
&link_dir( "$root", "$dest" ); |
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my $path = "work/${project}/children/${child_family}/ip"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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my $path = "work/${project}/children/${child_family}/ip/${child_parent}"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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$root = "${home}/projects/${child_family}/ip/${child_parent}"; |
444,15 → 512,12
&link_dir( "$root", "$dest" ); |
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my $path = "${home}/work/${project}/children/${child_family}/ip/${child_parent}/rtl/gen"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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my $path = "${home}/work/${project}/children/${child_family}/ip/${child_parent}/rtl/gen/sim"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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my $path = "${home}/work/${project}/children/${child_family}/ip/${child_parent}/rtl/gen/syn"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
} |
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474,15 → 539,11
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} |
print "Done1\n"; |
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} |
print "Done2\n"; |
} |
print "Done3\n"; |
} |
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print "Done4\n"; |
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@target_list = trim_sort(@target_list); |
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492,12 → 553,12
} |
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print "Done \n" ; |
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# recursively map directory information |
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515,11 → 576,9
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if( -d $path ) { |
print "Creating $dest_path\n" unless( -e $dest_path ); |
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mkdir $dest_path,0755; |
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my @contents = ( ); |
opendir( DIR, $path ); |
while( my $item = readdir( DIR )) { |
533,7 → 592,7
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} else { |
print "Linking $dest_path\n" unless( -e $dest_path ); |
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symlink( "${home}/${path}", $dest_path); |
} |
} |
550,7 → 609,7
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if( -d $src ) |
{ |
print "Creating $dest\n" unless( -e $dest ); |
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mkdir $dest,0755; |
my @contents = ( ); |
opendir( DIR, $src ); |
/socgen/trunk/tools/bin/Makefile.lint
0,0 → 1,5
SHELL=/bin/sh |
MAKE=make |
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include ../../../../../bin/Makefile.root |
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/socgen/trunk/lib/cde_serial_rcvr/cde_serial_rcvr.v
93,13 → 93,13
else |
if ( shift_cnt == WIDTH) |
case( parity_enable ) |
(2'b0): |
(1'b0): |
begin |
shift_cnt <= {SIZE{1'b1}}; |
last_cnt <= 1'b1; |
end |
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(2'b1): |
(1'b1): |
begin |
shift_cnt <= shift_cnt + 1'b1; |
last_cnt <= 1'b0; |
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu.xml
22,9 → 22,6
<interface><direction>output</direction><type>reg</type><name>porta_we</name></interface> |
<interface><direction>output</direction><type>reg</type><name>portb_we</name></interface> |
<interface><direction>output</direction><type>reg</type><name>portc_we</name></interface> |
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</interfaces> |
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/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/cov/mrisc_cpu/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
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/socgen/trunk/projects/pic_micro/ip/soc_mouse/rtl/xml/soc_mouse_mrisc.xml
1,266 → 1,413
<?xml version="1.0" encoding="UTF-8"?> |
<components> |
<component> |
<name>soc_mouse</name> |
<variant>soc_mouse_mrisc</variant> <type>leaf</type> |
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<parameters> |
<parameter><name>ROM_FILE</name><default>"NONE"</default></parameter> |
<parameter><name>ROM_WORDS</name><default>0</default></parameter> |
<parameter><name>ROM_ADDR</name><default>0</default></parameter> |
<parameter><name>ROM_WIDTH</name><default>0</default></parameter> |
<parameter><name>TX_FIFO</name><default>0</default></parameter> |
<parameter><name>TX_FIFO_SIZE</name><default>3</default></parameter> |
<parameter><name>TX_FIFO_WORDS</name><default>8</default></parameter> |
<parameter><name>RX_FIFO</name><default>0</default></parameter> |
<parameter><name>RX_FIFO_SIZE</name><default>3</default></parameter> |
<parameter><name>RX_FIFO_WORDS</name><default>8</default></parameter> |
</parameters> |
|
|
<interfaces> |
<interface><direction>input</direction><type>wire</type><name>clk</name></interface> |
<interface><direction>input</direction><type>wire</type><name>reset</name></interface> |
<interface><direction>output</direction><type>wire</type><width>[10:0]</width><name>inst_addr</name></interface> |
<interface><direction>output</direction><type>wire</type><width>[7:0]</width><name>portaout</name></interface> |
<interface><direction>output</direction><type>wire</type><width>[7:0]</width><name>portbout</name></interface> |
<interface><direction>output</direction><type>wire</type><width>[7:0]</width><name>portcout</name></interface> |
<interface><direction>output</direction><type>wire</type><name>ps2_data_pad_oe</name></interface> |
<interface><direction>output</direction><type>wire</type><name>ps2_clk_pad_oe</name></interface> |
<interface><direction>input</direction><type>wire</type><name>ps2_data_pad_in</name></interface> |
<interface><direction>input</direction><type>wire</type><name>ps2_clk_pad_in</name></interface> |
<interface><direction>output</direction><type>wire</type><width>[9:0]</width><name>y_pos</name></interface> |
<interface><direction>output</direction><type>wire</type><width>[9:0]</width><name>x_pos</name></interface> |
<interface><direction>output</direction><type>wire</type><name>new_packet</name></interface> |
<interface><direction>output</direction><type>wire</type><name>ms_mid</name></interface> |
<interface><direction>output</direction><type>wire</type><name>ms_right</name></interface> |
<interface><direction>output</direction><type>wire</type><name>ms_left</name></interface> |
<interface><direction>output</direction><type>wire</type><name>txd_pad_out</name></interface> |
<interface><direction>input</direction><type>wire</type><name>rxd_pad_in</name></interface> |
<interface><direction>input</direction><type>wire</type><name>cts_pad_in</name></interface> |
<interface><direction>output</direction><type>wire</type><name>rts_pad_out</name></interface> |
</interfaces> |
|
|
<brothers> |
<module> |
<name>mrisc</name> |
<component>mrisc</component> |
</module> |
<module> |
<name>mrisc_cpu</name> |
<component>mrisc_cpu</component> |
</module> |
|
</brothers> |
|
|
<children> |
<module> |
<name>ps2_interface</name> |
<component>ps2_interface</component> |
<project>logic</project> |
</module> |
<module> |
<name>io_module_mouse</name> |
<component>io_module</component> |
<project>io</project> |
</module> |
|
|
|
<module> |
<name>io_uart</name> |
<component>io_uart</component> |
<project>io</project> |
</module> |
|
<module> |
<name>io_ps2</name> |
<component>io_ps2</component> |
<project>io</project> |
</module> |
|
<module> |
<name>io_pic</name> |
<component>io_pic</component> |
<project>io</project> |
</module> |
|
<module> |
<name>io_timer</name> |
<component>io_timer</component> |
<project>io</project> |
</module> |
|
|
<module> |
<name>io_utimer</name> |
<component>io_utimer</component> |
<project>io</project> |
</module> |
|
|
|
<module> |
<name>io_gpio</name> |
<component>io_gpio</component> |
<project>io</project> |
</module> |
|
|
<module> |
<name>io_vic</name> |
<component>io_vic</component> |
<project>io</project> |
</module> |
|
|
|
|
|
|
<module> |
<name>serial_rcvr</name> |
<component>serial_rcvr</component> |
<project>logic</project> |
</module> |
|
|
<module> |
<name>uart</name> |
<component>uart</component> |
<project>logic</project> |
</module> |
|
|
<module> |
<name>vga_char_ctrl</name> |
<component>vga_char_ctrl</component> |
<project>logic</project> |
</module> |
|
|
|
|
</children> |
|
|
|
<library> |
<module> |
<name>cde_sram</name> |
<component>cde_sram</component> |
|
</module> |
|
|
<module> |
<name>cde_fifo</name> |
<component>cde_fifo</component> |
|
</module> |
|
<module> |
<name>cde_divider</name> |
<component>cde_divider</component> |
|
</module> |
|
<module> |
<name>cde_serial_xmit</name> |
<component>cde_serial_xmit</component> |
|
</module> |
|
<module> |
<name>cde_serial_rcvr</name> |
<component>cde_serial_rcvr</component> |
|
</module> |
|
|
|
<module> |
<name>cde_sync_with_hysteresis</name> |
<component>cde_synchronizers</component> |
|
</module> |
|
</library> |
|
|
|
|
<chips> |
<chip> |
<name>Nexys2_mouse_mrisc</name> |
<target>Nexys2</target> |
<children> |
<module> |
<name>disp_io</name> |
<component>disp_io</component> |
<project>logic</project> |
</module> |
<module> |
<name>flash_memcontrl</name> |
<component>flash_memcontrl</component> |
<project>logic</project> |
</module> |
<module> |
<name>usb_epp</name> |
<component>usb_epp</component> |
<project>logic</project> |
</module> |
</children> |
|
|
|
</chip> |
<chip> |
<name>Basys_mouse_mrisc</name> |
<target>Basys</target> |
|
<children> |
<module> |
<name>disp_io</name> |
<component>disp_io</component> |
<project>logic</project> |
</module> |
</children> |
|
|
|
</chip> |
</chips> |
|
<sims> |
<sim> |
<name>mouse_mrisc</name> |
</sim> |
</sims> |
|
|
|
<syn_children> |
<module> |
<name>disp_io</name> |
<component>disp_io</component> |
<project>logic</project> |
</module> |
<module> |
<name>flash_memcontrl</name> |
<component>flash_memcontrl</component> |
<project>logic</project> |
</module> |
<module> |
<name>usb_epp</name> |
<component>usb_epp</component> |
<project>logic</project> |
</module> |
</syn_children> |
|
</component> |
</components> |
<?xml version="1.0" encoding="UTF-8"?> |
<components> |
<component> |
<name>soc_mouse</name> |
<variant>soc_mouse_mrisc</variant> |
<type>hier</type> |
|
|
|
<parameters> |
<parameter><name>ROM_FILE</name><default>"NONE"</default></parameter> |
<parameter><name>ROM_WORDS</name><default>0</default></parameter> |
<parameter><name>ROM_ADDR</name><default>0</default></parameter> |
<parameter><name>ROM_WIDTH</name><default>0</default></parameter> |
<parameter><name>TX_FIFO</name><default>0</default></parameter> |
<parameter><name>TX_FIFO_SIZE</name><default>3</default></parameter> |
<parameter><name>TX_FIFO_WORDS</name><default>8</default></parameter> |
<parameter><name>RX_FIFO</name><default>0</default></parameter> |
<parameter><name>RX_FIFO_SIZE</name><default>3</default></parameter> |
<parameter><name>RX_FIFO_WORDS</name><default>8</default></parameter> |
</parameters> |
|
|
<interfaces> |
<interface><direction>input</direction><type>wire</type><name>clk</name></interface> |
<interface><direction>input</direction><type>wire</type><name>reset</name></interface> |
<interface><direction>output</direction><type>wire</type><width>[10:0]</width><name>inst_addr</name></interface> |
<interface><direction>output</direction><type>wire</type><width>[7:0]</width><name>portaout</name></interface> |
<interface><direction>output</direction><type>wire</type><width>[7:0]</width><name>portbout</name></interface> |
<interface><direction>output</direction><type>wire</type><width>[7:0]</width><name>portcout</name></interface> |
<interface><direction>output</direction><type>wire</type><name>ps2_data_pad_oe</name></interface> |
<interface><direction>output</direction><type>wire</type><name>ps2_clk_pad_oe</name></interface> |
<interface><direction>input</direction><type>wire</type><name>ps2_data_pad_in</name></interface> |
<interface><direction>input</direction><type>wire</type><name>ps2_clk_pad_in</name></interface> |
<interface><direction>output</direction><type>wire</type><width>[9:0]</width><name>y_pos</name></interface> |
<interface><direction>output</direction><type>wire</type><width>[9:0]</width><name>x_pos</name></interface> |
<interface><direction>output</direction><type>wire</type><name>new_packet</name></interface> |
<interface><direction>output</direction><type>wire</type><name>ms_mid</name></interface> |
<interface><direction>output</direction><type>wire</type><name>ms_right</name></interface> |
<interface><direction>output</direction><type>wire</type><name>ms_left</name></interface> |
<interface><direction>output</direction><type>wire</type><name>txd_pad_out</name></interface> |
<interface><direction>input</direction><type>wire</type><name>rxd_pad_in</name></interface> |
<interface><direction>input</direction><type>wire</type><name>cts_pad_in</name></interface> |
<interface><direction>output</direction><type>wire</type><name>rts_pad_out</name></interface> |
</interfaces> |
|
|
<brothers> |
<module> |
<name>mrisc</name> |
<component>mrisc</component> |
</module> |
<module> |
<name>mrisc_cpu</name> |
<component>mrisc_cpu</component> |
</module> |
|
</brothers> |
|
|
<children> |
<module> |
<name>ps2_interface</name> |
<component>ps2_interface</component> |
<project>logic</project> |
</module> |
<module> |
<name>io_module_mouse</name> |
<component>io_module</component> |
<project>io</project> |
</module> |
|
|
|
<module> |
<name>io_uart</name> |
<component>io_uart</component> |
<project>io</project> |
</module> |
|
<module> |
<name>io_ps2</name> |
<component>io_ps2</component> |
<project>io</project> |
</module> |
|
<module> |
<name>io_pic</name> |
<component>io_pic</component> |
<project>io</project> |
</module> |
|
<module> |
<name>io_timer</name> |
<component>io_timer</component> |
<project>io</project> |
</module> |
|
|
<module> |
<name>io_utimer</name> |
<component>io_utimer</component> |
<project>io</project> |
</module> |
|
|
|
<module> |
<name>io_gpio</name> |
<component>io_gpio</component> |
<project>io</project> |
</module> |
|
|
<module> |
<name>io_vic</name> |
<component>io_vic</component> |
<project>io</project> |
</module> |
|
|
|
|
|
|
<module> |
<name>serial_rcvr</name> |
<component>serial_rcvr</component> |
<project>logic</project> |
</module> |
|
|
<module> |
<name>uart</name> |
<component>uart</component> |
<project>logic</project> |
</module> |
|
|
<module> |
<name>vga_char_ctrl</name> |
<component>vga_char_ctrl</component> |
<project>logic</project> |
</module> |
|
|
|
|
</children> |
|
|
|
<library> |
<module> |
<name>cde_sram</name> |
<component>cde_sram</component> |
|
</module> |
|
|
<module> |
<name>cde_fifo</name> |
<component>cde_fifo</component> |
|
</module> |
|
<module> |
<name>cde_divider</name> |
<component>cde_divider</component> |
|
</module> |
|
<module> |
<name>cde_serial_xmit</name> |
<component>cde_serial_xmit</component> |
|
</module> |
|
<module> |
<name>cde_serial_rcvr</name> |
<component>cde_serial_rcvr</component> |
|
</module> |
|
|
|
<module> |
<name>cde_sync_with_hysteresis</name> |
<component>cde_synchronizers</component> |
|
</module> |
|
</library> |
|
|
|
|
<chips> |
<chip> |
<name>Nexys2_mouse_mrisc</name> |
<target>Nexys2</target> |
<children> |
<module> |
<name>disp_io</name> |
<component>disp_io</component> |
<project>logic</project> |
</module> |
<module> |
<name>flash_memcontrl</name> |
<component>flash_memcontrl</component> |
<project>logic</project> |
</module> |
<module> |
<name>usb_epp</name> |
<component>usb_epp</component> |
<project>logic</project> |
</module> |
</children> |
|
|
|
</chip> |
<chip> |
<name>Basys_mouse_mrisc</name> |
<target>Basys</target> |
|
<children> |
<module> |
<name>disp_io</name> |
<component>disp_io</component> |
<project>logic</project> |
</module> |
</children> |
|
|
|
</chip> |
</chips> |
|
<sims> |
<sim> |
<name>mouse_mrisc</name> |
</sim> |
</sims> |
|
|
|
<syn_children> |
<module> |
<name>disp_io</name> |
<component>disp_io</component> |
<project>logic</project> |
</module> |
<module> |
<name>flash_memcontrl</name> |
<component>flash_memcontrl</component> |
<project>logic</project> |
</module> |
<module> |
<name>usb_epp</name> |
<component>usb_epp</component> |
<project>logic</project> |
</module> |
</syn_children> |
|
|
|
|
|
|
|
<nodes> |
<node><type>wire</type><width>[7:0]</width><name>portain</name></node> |
<node><type>wire</type><width>[7:0]</width><name>portbin</name></node> |
<node><type>wire</type><width>[7:0]</width><name>portcin</name></node> |
<node><type>wire</type><name>porta_we</name></node> |
<node><type>wire</type><name>portb_we</name></node> |
<node><type>wire</type><name>portc_we</name></node> |
<node><type>wire</type><width>[7:0]</width><name>trisa</name></node> |
<node><type>wire</type><width>[7:0]</width><name>trisb</name></node> |
<node><type>wire</type><width>[7:0]</width><name>trisc</name></node> |
<node><type>reg</type><name>wr</name></node> |
<node><type>wire</type><name>rd</name></node> |
<node><type>wire</type><width>[15:0]</width><name>addr</name></node> |
<node><type>wire</type><width>[7:0]</width><name>wdata</name></node> |
<node><type>wire</type><width>[7:0]</width><name>rdata</name></node> |
<node><type>wire</type><width>[7:0]</width><name>gpio_0_out</name></node> |
<node><type>wire</type><width>[7:0]</width><name>gpio_0_oe</name></node> |
<node><type>wire</type><width>[7:0]</width><name>gpio_0_lat</name></node> |
<node><type>wire</type><width>[7:0]</width><name>gpio_1_out</name></node> |
<node><type>wire</type><width>[7:0]</width><name>gpio_1_oe</name></node> |
<node><type>wire</type><width>[7:0]</width><name>gpio_1_lat</name></node> |
<node><type>wire</type><name>ps2_data_avail</name></node> |
<node><type>wire</type><name>rx_irq</name></node> |
<node><type>wire</type><name>tx_irq</name></node> |
<node><type>wire</type><width>[7:0]</width><name>dummy</name></node> |
|
</nodes> |
|
<instances> |
<instance> |
<instance_name>pic</instance_name> |
<component_name>mrisc</component_name> |
<parameters> |
<parameter><name>ROM_WORDS</name><value>ROM_WORDS</value></parameter> |
<parameter><name>ROM_ADDR</name><value>ROM_ADDR</value></parameter> |
<parameter><name>ROM_WIDTH</name><value>ROM_WIDTH</value></parameter> |
<parameter><name>ROM_FILE</name><value>ROM_FILE</value></parameter> |
</parameters> |
<interfaces> |
<interface><name>clk</name><value>clk</value></interface> |
<interface><name>rst_in</name><value>reset</value></interface> |
<interface><name>inst_addr</name><value>inst_addr</value></interface> |
<interface><name>portain</name><value>portain</value></interface> |
<interface><name>portbin</name><value>portbin</value></interface> |
<interface><name>portcin</name><value>portcin</value></interface> |
<interface><name>portaout</name><value>portaout</value></interface> |
<interface><name>portbout</name><value>portbout</value></interface> |
<interface><name>portcout</name><value>portcout</value></interface> |
<interface><name>porta_we</name><value>porta_we</value></interface> |
<interface><name>portb_we</name><value>portb_we</value></interface> |
<interface><name>portc_we</name><value>portc_we</value></interface> |
<interface><name>trisa</name><value>trisa</value></interface> |
<interface><name>trisb</name><value>trisb</value></interface> |
<interface><name>trisc</name><value>trisc</value></interface> |
<interface><name>tcki</name><value>1'b0 </value></interface> |
<interface><name>wdt_en</name><value>1'b0</value></interface> |
</interfaces> |
</instance> |
|
|
|
|
|
|
<instance> |
<instance_name>io_module</instance_name> |
<component_name>io_module_mouse</component_name> |
<parameters> |
<parameter><name>BASE_WIDTH</name><value>0</value></parameter> |
<parameter><name>ADDR_WIDTH</name><value>8</value></parameter> |
<parameter><name>TX_FIFO</name><value>TX_FIFO</value></parameter> |
<parameter><name>TX_FIFO_SIZE</name><value>TX_FIFO_SIZE</value></parameter> |
<parameter><name>TX_FIFO_WORDS</name><value>TX_FIFO_WORDS</value></parameter> |
<parameter><name>RX_FIFO</name><value>RX_FIFO</value></parameter> |
<parameter><name>RX_FIFO_SIZE</name><value>RX_FIFO_SIZE</value></parameter> |
<parameter><name>RX_FIFO_WORDS</name><value>RX_FIFO_WORDS</value></parameter> |
</parameters> |
<interfaces> |
<interface><name>clk</name><value>clk</value></interface> |
<interface><name>reset</name><value>reset</value></interface> |
<interface><name>enable</name><value>1'b1</value></interface> |
<interface><name>cs_i</name><value>1'b1</value></interface> |
<interface><name>wr</name><value>wr</value></interface> |
<interface><name>rd</name><value>!wr</value></interface> |
<interface><name>cs_m</name><value>1'b0</value></interface> |
<interface><name>wait_n</name><value></value></interface> |
<interface><name>addr</name><value>portbout</value></interface> |
<interface><name>waddr</name><value>portbout</value></interface> |
<interface><name>wdata</name><value>portaout</value></interface> |
<interface><name>rdata</name><value>{dummy,portain}</value></interface> |
<interface><name>ps2_data_pad_in</name><value>ps2_data_pad_in</value></interface> |
<interface><name>ps2_data_pad_oe</name><value>ps2_data_pad_oe</value></interface> |
<interface><name>ps2_clk_pad_in</name><value>ps2_clk_pad_in</value></interface> |
<interface><name>ps2_clk_pad_oe</name><value>ps2_clk_pad_oe</value></interface> |
<interface><name>ps2_data_avail</name><value>ps2_data_avail</value></interface> |
<interface><name>y_pos</name><value>y_pos</value></interface> |
<interface><name>x_pos</name><value>x_pos</value></interface> |
<interface><name>new_packet</name><value>new_packet</value></interface> |
<interface><name>ms_mid</name><value>ms_mid</value></interface> |
<interface><name>ms_right</name><value>ms_right</value></interface> |
<interface><name>ms_left</name><value>ms_left</value></interface> |
<interface><name>txd_pad_out</name><value>txd_pad_out</value></interface> |
<interface><name>rxd_pad_in</name><value>rxd_pad_in</value></interface> |
<interface><name>cts_pad_in</name><value>cts_pad_in</value></interface> |
<interface><name>rts_pad_out</name><value>rts_pad_out</value></interface> |
<interface><name>rx_irq</name><value>rx_irq</value></interface> |
<interface><name>tx_irq</name><value>tx_irq</value></interface> |
<interface><name>pic_irq_in</name><value>{3'b000,ps2_data_avail,tx_irq,rx_irq,2'b00}</value></interface> |
<interface><name>pic_irq</name><value></value></interface> |
<interface><name>pic_nmi</name><value></value></interface> |
</interfaces> |
</instance> |
|
</instances> |
|
<rtl> |
|
assign portbin = portbout; |
assign portcin = portcout; |
|
|
always@(posedge clk) |
if (reset) wr <= 1'b0; |
else wr <= porta_we; |
|
</rtl> |
|
|
|
|
|
</component> |
</components> |
|
|
|
|
|
|
|
|
|
/socgen/trunk/projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse_mrisc/Makefile
14,9 → 14,8
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > soc_mouse_mrisc.v ;\ |
covered score -f filelist.cov -i TB.dut.pic -t mrisc -I ./ -v ./soc_mouse_mrisc.v -o soc_mouse_mrisc_cpu.cdd 2> soc_mouse_mrisc_cpu_cov.log | tee >> soc_mouse_mrisc_cpu_cov.log ;\ |
covered score -f filelist.cov -i TB.dut.io_module -t io_module_mouse -I ./ -v ./soc_mouse_mrisc.v -o io_module.cdd 2> io_module_cov.log | tee >> io_module_cov.log ;\ |
covered score -f filelist.cov -i TB.dut.pic -t mrisc -I ./ -v ./coverage.v -o soc_mouse_mrisc_cpu.cdd 2> cpu_cov.log | tee >> cpu_cov.log ;\ |
covered score -f filelist.cov -i TB.dut.io_module -t io_module_mouse -I ./ -v ./coverage.v -o io_module.cdd 2> io_module_cov.log | tee >> io_module_cov.log ;\ |
echo "################################################################################"; \ |
|
|
/socgen/trunk/projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse/Makefile
14,9 → 14,8
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > soc_mouse.v ;\ |
covered score -f filelist.cov -i TB.dut.pic -t pic16c5x -I ./ -v ./soc_mouse.v -o soc_mouse_cpu.cdd 2> soc_mouse_cpu_cov.log | tee >> soc_mouse_cpu_cov.log ;\ |
covered score -f filelist.cov -i TB.dut.io_module -t io_module_mouse -I ./ -v ./soc_mouse.v -o io_module.cdd 2> io_module_cov.log | tee >> io_module_cov.log ;\ |
covered score -f filelist.cov -i TB.dut.pic -t pic16c5x -I ./ -v ./coverage.v -o soc_mouse_cpu.cdd 2> cpu_cov.log | tee >> cpu_cov.log ;\ |
covered score -f filelist.cov -i TB.dut.io_module -t io_module_mouse -I ./ -v ./coverage.v -o io_module.cdd 2> io_module_cov.log | tee >> io_module_cov.log ;\ |
echo "################################################################################"; \ |
|
|
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/ind_mem/copyright
0,0 → 1,42
/**********************************************************************/ |
/* */ |
/* ------- */ |
/* / SOC \ */ |
/* / GEN \ */ |
/* / SIM \ */ |
/* ============== */ |
/* | | */ |
/* |____________| */ |
/* */ |
/* Simulation fileset */ |
/* */ |
/* */ |
/* Author(s): */ |
/* - John Eaton, jt_eaton@opencores.org */ |
/* */ |
/**********************************************************************/ |
/* */ |
/* Copyright (C) <2010> <Ouabache Design Works> */ |
/* */ |
/* This source file may be used and distributed without */ |
/* restriction provided that this copyright statement is not */ |
/* removed from the file and that any derivative work contains */ |
/* the original copyright notice and the associated disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it */ |
/* and/or modify it under the terms of the GNU Lesser General */ |
/* Public License as published by the Free Software Foundation; */ |
/* either version 2.1 of the License, or (at your option) any */ |
/* later version. */ |
/* */ |
/* This source is distributed in the hope that it will be */ |
/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
/* PURPOSE. See the GNU Lesser General Public License for more */ |
/* details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General */ |
/* Public License along with this source; if not, download it */ |
/* from http://www.opencores.org/lgpl.shtml */ |
/* */ |
/**********************************************************************/ |
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/ind_mem/test_define
0,0 → 1,34
|
initial |
begin |
$display ("\n\nMini-RISC. Sanity 2 Version 1.0\n\n"); |
$display ("========== Starting Test ========== \n"); |
repeat(10) @(posedge clk); |
cg.reset_off; |
|
repeat(40) @(posedge clk); |
|
while(portaout == 8'h00) @(posedge clk); |
|
if(portaout == 8'h01) |
begin |
|
end |
else |
if(portaout == 8'hff) |
begin |
$display("Test FAILED in test %d !!!", portb); |
end |
else |
$display("Test status UNKNOWN (%h test: %d) !!!", portaout, portbout); |
|
|
repeat(4) @(posedge clk); |
$display("\n=============================================\n\n\n"); |
|
|
|
cg.exit; |
end |
|
|
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/ind_mem/dmp_define
0,0 → 1,4
$dumpfile ("./TestBench.vcd"); |
$dumpvars (0, TB); |
|
|
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/ind_mem/params.sim
0,0 → 1,18
|
|
parameter PC_RST_VECTOR = 11'h000; |
parameter STAT_RST_VALUE = 8'h18; |
parameter OPT_RST_VALUE = 8'h3f; |
parameter FSR_RST_VALUE = 7'h0; |
parameter TRIS_RST_VALUE = 8'hff; |
|
parameter ROM_WORDS = 51; |
parameter ROM_ADDR = 11; |
parameter ROM_WIDTH = 12; |
parameter ROM_FILE = "../../../../../sw/ind_mem/ind_mem.abs12"; |
|
|
|
|
|
|
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/ind_mem/modellist
0,0 → 1,18
`include "../../bench/verilog/models/clock_gen.v" |
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/ind_mem/dut
0,0 → 1,49
|
|
wire [7:0] porta; // I/O Port A |
wire [7:0] portb; // I/O Port B |
wire [7:0] portc; // I/O Port C |
|
assign rst_in =reset; |
|
assign wdt_en =1'b1; |
|
// IO buffers for IO Ports |
assign porta = trisa ? 8'bz : portaout; |
assign portain = porta; |
|
assign portb = trisb ? 8'bz : portbout; |
assign portbin = portb; |
|
assign portc = trisc ? 8'bz : portcout; |
assign portcin = portc; |
|
// Pullups for IO Ports |
pullup ua0(porta[0]); |
pullup ua1(porta[1]); |
pullup ua2(porta[2]); |
pullup ua3(porta[3]); |
pullup ua4(porta[4]); |
pullup ua5(porta[5]); |
pullup ua6(porta[6]); |
pullup ua7(porta[7]); |
|
pullup ub0(portb[0]); |
pullup ub1(portb[1]); |
pullup ub2(portb[2]); |
pullup ub3(portb[3]); |
pullup ub4(portb[4]); |
pullup ub5(portb[5]); |
pullup ub6(portb[6]); |
pullup ub7(portb[7]); |
|
pullup uc0(portc[0]); |
pullup uc1(portc[1]); |
pullup uc2(portc[2]); |
pullup uc3(portc[3]); |
pullup uc4(portc[4]); |
pullup uc5(portc[5]); |
pullup uc6(portc[6]); |
pullup uc7(portc[7]); |
|
|
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/ind_mem/Makefile
0,0 → 1,3
include ../../../../../bin/Makefile.root |
comp=mrisc |
test=ind_mem |
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/cov/mrisc/Makefile
14,8 → 14,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > mrisc.v ;\ |
covered score -f filelist.cov -i TB.dut -t mrisc -I ./ -v ./mrisc.v -o mrisc.cdd 2> mrisc_cov.log | tee >> mrisc_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t mrisc -I ./ -v ./coverage.v -o mrisc.cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
################################################################################ |
/socgen/trunk/projects/pic_micro/sw/loop2/loop2.asm
0,0 → 1,93
;/**********************************************************************/ |
;/* */ |
;/* ------- */ |
;/* / SOC \ */ |
;/* / GEN \ */ |
;/* / FIRMWARE \ */ |
;/* ============== */ |
;/* | | */ |
;/* |____________| */ |
;/* */ |
;/* Simple loop for outputing data on porta */ |
;/* */ |
;/* */ |
;/* Author(s): */ |
;/* - John Eaton, jt_eaton@opencores.org */ |
;/* */ |
;/**********************************************************************/ |
;/* */ |
;/* Copyright (C) <2010> <Ouabache Design Works> */ |
;/* */ |
;/* This source file may be used and distributed without */ |
;/* restriction provided that this copyright statement is not */ |
;/* removed from the file and that any derivative work contains */ |
;/* the original copyright notice and the associated disclaimer. */ |
;/* */ |
;/* This source file is free software; you can redistribute it */ |
;/* and/or modify it under the terms of the GNU Lesser General */ |
;/* Public License as published by the Free Software Foundation; */ |
;/* either version 2.1 of the License, or (at your option) any */ |
;/* later version. */ |
;/* */ |
;/* This source is distributed in the hope that it will be */ |
;/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
;/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
;/* PURPOSE. See the GNU Lesser General Public License for more */ |
;/* details. */ |
;/* */ |
;/* You should have received a copy of the GNU Lesser General */ |
;/* Public License along with this source; if not, download it */ |
;/* from http://www.opencores.org/lgpl.shtml */ |
;/* */ |
;/**********************************************************************/ |
|
|
|
|
|
list p=16c57 |
#include p16c5x.inc |
|
|
main ; Main code entry |
|
clrw |
movwf PORTA |
movwf PORTB |
movwf PORTC |
|
|
loop |
call foo |
nop |
goto loop |
|
|
|
foo |
incfsz PORTA |
goto foo |
call foo1 |
retlw 1 |
|
|
foo1 |
incfsz PORTB |
retlw 1 |
call foo2 |
retlw 1 |
|
foo2 |
incfsz PORTC |
retlw 1 |
|
infin |
goto infin |
nop |
nop |
nop |
|
|
|
END |
|
/socgen/trunk/projects/pic_micro/sw/loop2/Makefile
0,0 → 1,6
include ../../bin/Makefile.pic |
code=loop2 |
|
all: asm_pic |
|
|
/socgen/trunk/projects/pic_micro/sw/rf4/rf4.asm
0,0 → 1,338
;///////////////////////////////////////////////////////////////////// |
;//// //// |
;//// Mini-RISC-1 //// |
;//// Register File Test 3 //// |
;//// Tests Register File //// |
;//// //// |
;//// Author: Rudolf Usselmann //// |
;//// russelmann@hotmail.com //// |
;//// //// |
;///////////////////////////////////////////////////////////////////// |
;//// //// |
;//// Copyright (C) 2000 Rudolf Usselmann //// |
;//// russelmann@hotmail.com //// |
;//// //// |
;//// This source file may be used and distributed without //// |
;//// restriction provided that this copyright statement is not //// |
;//// removed from the file and that any derivative work contains //// |
;//// the original copyright notice and the associated disclaimer.//// |
;//// //// |
;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// |
;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// |
;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// |
;//// FITNESS FOR A PARTICULAR PURPOSE. //// |
;//// //// |
;///////////////////////////////////////////////////////////////////// |
|
list p=16c57 |
#include p16c5x.inc |
|
; global Registers |
r0 equ 0x8 |
r1 equ 0x9 |
r2 equ 0xa |
r3 equ 0xb |
r4 equ 0xc |
r5 equ 0xd |
r6 equ 0xe |
r7 equ 0xf |
|
; banked Registers |
br0 equ 0x10 |
br1 equ 0x11 |
br2 equ 0x12 |
br3 equ 0x13 |
br4 equ 0x14 |
br5 equ 0x15 |
br6 equ 0x16 |
br7 equ 0x17 |
br8 equ 0x18 |
br9 equ 0x19 |
br10 equ 0x1a |
br11 equ 0x1b |
br12 equ 0x1c |
br13 equ 0x1d |
br14 equ 0x1e |
br15 equ 0x1f |
|
|
; PORTB Indicates Test Number |
; PORTA Indicates Status: 0 - Running; 1 - done OK; ff - stoped on error |
|
main ; Main code entry |
; Port IO Test |
; All ports have a Pull up resistor |
|
; SETUP all ports |
clrw |
movwf FSR |
movwf PORTA |
movwf PORTB |
movwf PORTC |
tris PORTA |
tris PORTB |
tris PORTC |
|
; --------------------------------------- |
; ---- Test RMW on Register fil ---- |
; --------------------------------------- |
|
movlw 0x01 ; TEST 1 |
movwf PORTB ; Set Test Number |
|
movlw 0xfc |
movwf r0 |
incf r0,F |
incf r0,F |
incf r0,F |
incf r0,F |
btfss STATUS,Z |
goto lerr |
|
movlw 0xfc |
movwf br8 |
incf br8,F |
incf br8,F |
incf br8,F |
incf br8,F |
btfss STATUS,Z |
goto lerr |
|
movlw 0x02 ; TEST 2 |
movwf PORTB ; Set Test Number |
|
movlw r1 |
movwf FSR |
movlw 0xfc |
movwf INDF |
incf INDF,F |
incf INDF,F |
incf INDF,F |
incf INDF,F |
btfss STATUS,Z |
goto lerr |
|
movlw br9 |
movwf FSR |
movlw 0xfc |
movwf INDF |
incf INDF,F |
incf INDF,F |
incf INDF,F |
incf INDF,F |
btfss STATUS,Z |
goto lerr |
|
|
|
movlw 0x03 ; TEST 3 |
movwf PORTB ; Set Test Number |
|
movlw 0x04 |
movwf r0 |
decf r0,F |
decf r0,F |
decf r0,F |
decf r0,F |
btfss STATUS,Z |
goto lerr |
|
|
movlw 0x04 |
movwf br0 |
decf br0,F |
decf br0,F |
decf br0,F |
decf br0,F |
btfss STATUS,Z |
goto lerr |
|
|
movlw 0x04 ; TEST 4 |
movwf PORTB ; Set Test Number |
|
movlw r1 |
movwf FSR |
movlw 0x04 |
movwf INDF |
decf INDF,F |
decf INDF,F |
decf INDF,F |
decf INDF,F |
btfss STATUS,Z |
goto lerr |
|
movlw br9 |
movwf FSR |
movlw 0x04 |
movwf INDF |
decf INDF,F |
decf INDF,F |
decf INDF,F |
decf INDF,F |
btfss STATUS,Z |
goto lerr |
|
|
movlw 0x05 ; TEST 5 |
movwf PORTB ; Set Test Number |
|
movlw 0xfc |
movwf r4 |
incfsz r4,F |
incfsz r4,F |
incfsz r4,F |
incfsz r4,F |
goto lerr |
|
movlw 0xfc |
movwf br8 |
incfsz br8,F |
incfsz br8,F |
incfsz br8,F |
incfsz br8,F |
goto lerr |
|
|
movlw 0x06 ; TEST 6 |
movwf PORTB ; Set Test Number |
|
movlw r1 |
movwf FSR |
movlw 0xfc |
movwf INDF |
incfsz INDF,F |
incfsz INDF,F |
incfsz INDF,F |
incfsz INDF,F |
goto lerr |
|
movlw br9 |
movwf FSR |
movlw 0xfc |
movwf INDF |
incfsz INDF,F |
incfsz INDF,F |
incfsz INDF,F |
incfsz INDF,F |
goto lerr |
|
movlw 0x07 ; TEST 7 |
movwf PORTB ; Set Test Number |
|
movlw 0x04 |
movwf r0 |
decfsz r0,F |
decfsz r0,F |
decfsz r0,F |
decfsz r0,F |
goto lerr |
|
|
movlw 0x04 |
movwf br0 |
decfsz br0,F |
decfsz br0,F |
decfsz br0,F |
decfsz br0,F |
goto lerr |
|
|
movlw 0x08 ; TEST 8 |
movwf PORTB ; Set Test Number |
|
movlw r1 |
movwf FSR |
movlw 0x04 |
movwf INDF |
decfsz INDF,F |
decfsz INDF,F |
decfsz INDF,F |
decfsz INDF,F |
goto lerr |
|
movlw br9 |
movwf FSR |
movlw 0x04 |
movwf INDF |
decfsz INDF,F |
decfsz INDF,F |
decfsz INDF,F |
decfsz INDF,F |
goto lerr |
|
|
movlw 0x09 ; TEST 9 |
movwf PORTB ; Set Test Number |
|
movlw 0xfc |
movwf FSR |
incf FSR,F |
incf FSR,F |
incf FSR,F |
incf FSR,F |
btfss STATUS,Z |
goto lerr |
|
movlw 0x04 |
movwf FSR |
movlw 0x7f |
decf FSR,F |
decf FSR,F |
decf FSR,F |
decf FSR,F |
andwf FSR,F |
btfss STATUS,Z |
goto lerr |
|
movlw 0x0a ; TEST 10 |
movwf PORTB ; Set Test Number |
|
movlw 0xfc |
movwf STATUS |
movlw 0x00 |
incf STATUS,F |
incf STATUS,F |
incf STATUS,F |
incf STATUS,F |
subwf STATUS,W |
btfss STATUS,Z |
goto lerr |
|
|
|
|
nop |
nop |
nop |
nop |
movlw 0x01 |
movwf PORTA |
nop |
nop |
nop |
nop |
good ; Loop in good on success |
goto good |
nop |
nop |
nop |
nop |
|
lerr |
movlw 0xff |
movwf PORTA |
|
nop |
nop |
nop |
nop |
lerr_loop ; Loop in lerr on failure |
goto lerr_loop |
nop |
nop |
nop |
nop |
|
END |
|
/socgen/trunk/projects/pic_micro/sw/rf4/Makefile
0,0 → 1,7
include ../../bin/Makefile.pic |
code=rf4 |
|
all: asm_pic |
|
|
|
/socgen/trunk/projects/io/ip/io_pic/rtl/xml/io_pic.xml
5,8 → 5,8
<variant>io_pic</variant> <type>leaf</type> |
<parameters> |
<parameter><name>BASE_ADDR</name><default>4'h0</default></parameter> |
<parameter><name>BASE_WIDTH</name><default>8</default></parameter> |
<parameter><name>ADDR_WIDTH</name><default>16</default></parameter> |
<parameter><name>BASE_WIDTH</name><default>4</default></parameter> |
<parameter><name>ADDR_WIDTH</name><default>8</default></parameter> |
<parameter><name>IRQ_MODE</name><default>8'h00</default></parameter> |
<parameter><name>NMI_MODE</name><default>8'h00</default></parameter> |
</parameters> |
21,8 → 21,8
<interface><direction>input</direction><type>wire</type><width>[ADDR_WIDTH-BASE_WIDTH-1:0]</width><name>raddr</name></interface> |
<interface><direction>input</direction><type>wire</type><width>[7:0]</width><name>wdata</name></interface> |
<interface><direction>output</direction><type>wire</type><width>[7:0]</width><name>rdata</name></interface> |
<interface><direction>output</direction><type>wire</type><name>irq</name></interface> |
<interface><direction>output</direction><type>wire</type><name>nmi</name></interface> |
<interface><direction>output</direction><type>reg</type><name>irq_out</name></interface> |
<interface><direction>output</direction><type>reg</type><name>nmi_out</name></interface> |
<interface><direction>input</direction><type>wire</type><width>[7:0]</width><name>int_in</name></interface> |
</interfaces> |
|
/socgen/trunk/projects/io/ip/io_pic/sim/cov/io_pic/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
|
/socgen/trunk/projects/io/ip/io_uart/rtl/xml/io_uart.xml
4,9 → 4,9
<name>io_uart</name> |
<variant>io_uart</variant> <type>leaf</type> |
<parameters> |
<parameter><name>BASE_ADDR</name><default>8</default></parameter> |
<parameter><name>BASE_WIDTH</name><default>8</default></parameter> |
<parameter><name>ADDR_WIDTH</name><default>16</default></parameter> |
<parameter><name>BASE_ADDR</name><default>4</default></parameter> |
<parameter><name>BASE_WIDTH</name><default>4</default></parameter> |
<parameter><name>ADDR_WIDTH</name><default>8</default></parameter> |
<parameter><name>TX_FIFO</name><default>0</default></parameter> |
<parameter><name>TX_FIFO_SIZE</name><default>3</default></parameter> |
<parameter><name>TX_FIFO_WORDS</name><default>8</default></parameter> |
/socgen/trunk/projects/io/ip/io_uart/sim/cov/io_uart/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
|
/socgen/trunk/projects/io/ip/io_vga/rtl/xml/io_vga.xml
5,8 → 5,8
<variant>io_vga</variant> <type>leaf</type> |
<parameters> |
<parameter><name>BASE_ADDR</name><default>4'h0</default></parameter> |
<parameter><name>BASE_WIDTH</name><default>8</default></parameter> |
<parameter><name>ADDR_WIDTH</name><default>16</default></parameter> |
<parameter><name>BASE_WIDTH</name><default>4</default></parameter> |
<parameter><name>ADDR_WIDTH</name><default>8</default></parameter> |
<parameter><name>STARTUP</name><default>"NONE"</default></parameter> |
<parameter><name>FONT</name><default>"NONE"</default></parameter> |
</parameters> |
/socgen/trunk/projects/io/ip/io_vga/sim/cov/io_vga/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
|
/socgen/trunk/projects/io/ip/io_ext_mem_interface/rtl/xml/io_ext_mem_interface.xml
5,8 → 5,8
<variant>io_ext_mem_interface</variant> <type>leaf</type> |
<parameters> |
<parameter><name>BASE_ADDR</name><default>4'h0</default></parameter> |
<parameter><name>BASE_WIDTH</name><default>8</default></parameter> |
<parameter><name>ADDR_WIDTH</name><default>16</default></parameter> |
<parameter><name>BASE_WIDTH</name><default>4</default></parameter> |
<parameter><name>ADDR_WIDTH</name><default>8</default></parameter> |
<parameter><name>MEM_WIDTH</name><default>23</default></parameter> |
<parameter><name>MEM_FRAME</name><default>10</default></parameter> |
</parameters> |
/socgen/trunk/projects/io/ip/io_ext_mem_interface/sim/cov/io_ext_mem_interface/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
|
/socgen/trunk/projects/io/ip/io_gpio/rtl/xml/io_gpio.xml
5,8 → 5,8
<variant>io_gpio</variant> <type>leaf</type> |
<parameters> |
<parameter><name>BASE_ADDR</name><default>4'h0</default></parameter> |
<parameter><name>BASE_WIDTH</name><default>8</default></parameter> |
<parameter><name>ADDR_WIDTH</name><default>16</default></parameter> |
<parameter><name>BASE_WIDTH</name><default>4</default></parameter> |
<parameter><name>ADDR_WIDTH</name><default>8</default></parameter> |
</parameters> |
<interfaces> |
<interface><direction>input</direction><type>wire</type><name>clk</name></interface> |
/socgen/trunk/projects/io/ip/io_gpio/sim/cov/io_gpio/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
|
/socgen/trunk/projects/io/ip/io_timer/sim/cov/io_timer/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
|
/socgen/trunk/projects/io/ip/io_vic/sim/cov/io_vic/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
|
/socgen/trunk/projects/io/ip/io_ps2/rtl/xml/io_ps2.xml
5,8 → 5,8
<variant>io_ps2</variant> <type>leaf</type> |
<parameters> |
<parameter><name>BASE_ADDR</name><default>4'h0</default></parameter> |
<parameter><name>BASE_WIDTH</name><default>8</default></parameter> |
<parameter><name>ADDR_WIDTH</name><default>16</default></parameter> |
<parameter><name>BASE_WIDTH</name><default>4</default></parameter> |
<parameter><name>ADDR_WIDTH</name><default>8</default></parameter> |
</parameters> |
<interfaces> |
<interface><direction>input</direction><type>wire</type><name>clk</name></interface> |
/socgen/trunk/projects/io/ip/io_ps2/sim/cov/io_ps2/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
|
/socgen/trunk/projects/io/ip/io_module/sim/cov/io_module_mouse/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
|
/socgen/trunk/projects/io/ip/io_module/sim/cov/io_module/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
|
/socgen/trunk/projects/io/ip/io_utimer/sim/cov/io_utimer/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
|
/socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/rtl/variants/T6502_state_fsm/defines.v
File deleted
/socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/doc/spec.odt
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/doc/spec.odt
Property changes :
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-application/octet-stream
\ No newline at end of property
Index: socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/doc/geda/drawing/filelist
===================================================================
--- socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/doc/geda/drawing/filelist (revision 74)
+++ socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/doc/geda/drawing/filelist (nonexistent)
@@ -1,14 +0,0 @@
-`include "../../../rtl/gen/syn/T6502.v"
-`include "../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module.v"
-`include "../../../../../children/logic/ip/uart/rtl/gen/syn/uart.v"
-`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/syn/ps2_interface.v"
-
-`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v"
-`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/syn/serial_rcvr.v"
-
-`include "../../../../../../../../socgen/lib/cde_sram/cde_sram.v"
-`include "../../../../../../../../socgen/lib/cde_serial_xmit/cde_serial_xmit.v"
-`include "../../../../../../../../socgen/lib/cde_serial_rcvr/cde_serial_rcvr.v"
-`include "../../../../../../../../socgen/lib/cde_synchronizers/cde_sync_with_hysteresis.v"
-`include "../../../../../../../../socgen/lib/cde_fifo/cde_fifo.v"
-`include "../../../../../../../../socgen/lib/cde_divider/cde_divider.v"
\ No newline at end of file
Index: socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/doc/T6502_doc.txt
===================================================================
--- socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/doc/T6502_doc.txt (revision 74)
+++ socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/doc/T6502_doc.txt (nonexistent)
@@ -1,1689 +0,0 @@
-T6502 Embedded Microprocessor
-==================================================================================
-
-The T6502 IP is a processor that uses most of MosTechnology M6502 processor instructions
-and processor registers.It has been updated for a synthesized embedded design in a FGPA or ASIC.
-
-
-It differs from the original Mos6502 in the following ways
-
-
-
-1) Changed memory interface from asynchronous to synchronous.
-
-2) Number of clock cycles to execute instructions has changed
-
-3) Page Zero is fully filled with SRAM. Page zero is not usable as I/O space
-
-
-
-
-
-
-
-
-An extended version is also avaiable. Before we can extend we must first remove some features that either
-did not make sense at the time or made only made sense for a 40 pin part sitting in a sea or ttl parts.
-
-
-
-1) Remove Binary Coded Decimal mode. The D bit in the PSR does nothing.
-
-2) Moved stack from Page 01 into a seperate RAM. Stack size is now parameterized and only accessable via
- pushes and pulls.Removed the TSX and TXS commands. If you need to manipulate the stack pointer and stack
- data then you really should get a more powerfull processor
-
-3) Replaced old interrupt/brk system with vectored interrupt. Masking is done externally and vectors provide
- as many interrupts as you like. PSR is not pushed on interrupt and rts/rti become one instruction
-
-4) Indirect addresses stored in page 00 MUST be aligned on even addresses. This is done by shifting a
- page zero indirect address bu one bit and using both page 00 and 01.
-
-5) Bit (5) of the PSR is now a run bit. Forcing it to 0 will halt the processor until the next reset/interrupt
-
-6) Added Debugging logic and error checking
-
-7) self modifying code is no longer supported. You must provide a single rom image with all executable code
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-History
-=========================================================================================
-
-
-
-
-This component is derived from the opencores t6507lp project.
-
-The original project checked in by Gabriel Oshiro Zardo and Samuel Nascimento Pagliarini
-was a atari 2600 on a chip. This takes the t6507 portion and turns it into a fully functional updated 6502.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-Processor Model
-===============================================================================================
-
- +----------+
- | Acc | Accumulator (A)
- +----------+
- | X | X Index Register (X)
- +----------+
- | Y | Y Index Register (Y)
- +----------+----------+
- | PCH | PCL | Program Counter (PC)
- +----------+----------+
- | 00000001 | SP | Stack Pointer (SP)
- +----------+----------+
- | P | Processor Status Word (P)
- +----------+
- NV1BDIZC
- |||||||+---- Carry Flag 1 = True
- ||||||+----- Zero Flag 1 = Result == 8'h00
- |||||+------ IRQ Disable 1 = Disable
- ||||+------- Decimal Mode Not used
- |||+-------- Break Command 1 = In break routine
- ||+--------- Run Mode 1 = Processor is running
- |+---------- Overflow Flag 1 = True
- +----------- Negative 1 = Negative Number
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-Memory Model
-===============================================================================================
-
-0000-00FF | Page Zero RAM
-0010-01FF | Stack RAM
-0200-FFF9 | Program and Data RAM
- FFFA | NMI Vector Low
- FFFB | NMI Vector High
- FFFC | Boot Vector Low
- FFFD | Boot Vector High
- FFFE | IRQ/BRK Vector Low
- FFFF | IRQ/BRK Vector High
-
-
-
-
-
-
-
-
-
-Definitions
-===============================================================================================
-Opcode Current Instruction byte
-New_opcode Next Instruction byte
-Opc_Add Address of current instruction
-Next_Op_Add Address of next instruction byte
-Operand Data operand
-Address Address of data operand if in memory
-Offset Value added to Opc_Add if branch is taken
-Pointer Address to store the address of data opeand if in memory
-Vector Address to store the Next_Op_Add
-
-
-
-
-
-
-
-
-
-Instruction Set
-===============================================================================================
-
-Inst Description Effect on flags
------------------------------------------------------------------------------------------------
-ADC Operand Add Acc to Operand with Carry NZCV
-SBC Operand Subract Operand from Acc with Borrow NZXV
-AND Operand Logical AND Acc and Operand NZ
-CMP Operand Compare Acc with Operand NZC
-CPX Operand Compare X_index with Operand NZC
-CPY Operand Compare Y_index with Operand NZC
-EOR Operand Exclusive Or Acc with Operand NZ
-LDA Operand Load Operand into Acc NZ
-LDX Operand Load Operand into X_index NZ
-LDY Operand Load Operand into Y_index NZ
-ORA Operand Logical Or Acc with Operand NZ
-BIT Operand Bit Test Acc with operand Z67
-STA Address Store Acc @ address NONE
-STX Address Store X_Index @ address NONE
-STY Address Store Y_Index @ address NONE
-ASL Operand Arithmetic Shift Left Operand into Carry NZC
-DEC Operand Decrement Operand NZ
-INC Operand Incremement Operand NZ
-DEX Decrement X Index NZ
-INX Incremement X Index NZ
-DEY Decrement Y Index NZ
-INY Incremement Y Index NZ
-LSR Operand Logical Shift Right Operand into Carry NZC
-ROL Operand Rotate Left Operand thru Carry NZC
-ROR Operand Rotate Right Operand thru Carry NZC
-NOP No Operation NONE
-SEC Set Carry Flag 1 -> C
-SED Set Decimal Flag 1 -> D
-SEI Set Interrupt Flag 1 -> I
-CLC Clear Carry Flag 0 -> C
-CLD Clear Decimal Flag 0 -> D
-CLI Clear Interrupt Flag 0 -> I
-CLV Clear Overflow Flag 0 -> V
-TAX Transfer Acc into X_Index NZ
-TAY Transfer Acc into Y_Index NZ
-TXA Transfer X_Index into Acc NZ
-TYA Transfer Y_Index into Acc NZ
-BCC Offset Branch if C == 0 NONE
-BCS Offset Branch if C == 1 NONE
-BNE Offset Branch if Z == 0 NONE
-BEQ Offset Branch if Z == 1 NONE
-BVC Offset Branch if V == 0 NONE
-BVS Offset Branch if V == 1 NONE
-BPL Offset Branch if N == 0 NONE
-BMI Offset Branch if N == 1 NONE
-PLA Pull Acc from Stack NZ
-PLP Pull PSR from Stack RESTORE
-PHA Push Acc onto Stack NONE
-PHP Push PSR onto Stack NONE
-JMP Next_Op_Add Jump to New Address NONE
-JMP Vector Jump to New Address found by vector NONE
-JSR Next_Op_Add Save PC+2 on stack and jump to New Address NONE
-BRK Save status and PC+1 on stack and jump to New Address set 1 -> B
-RTI Pull Status and PC from stack RESTORED
-RTS Pull PC from stack NONE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-Definitions
-===============================================================================================
-Opcode Current Instruction byte
-New_opcode Next Instruction byte
-Opc_Add Address of current instruction
-Next_Op_Add Address of next instruction byte
-Operand Data operand
-Address Address of data operand if in memory
-Offset Value added to Opc_Add if branch is taken
-Pointer Address to store the address of data opeand if in memory
-Vector Address to store the Next_Op_Add
-
-
-
-
-
-
-
-
-
-
-Addressing Modes
-===============================================================================================
-
-
-Immediate Read
------------------------------------------------------------------------------------------------------
-Operand is located in memory following the opcode
-
-
-Opcode Operand
-
-
-
-
-Absolute Read/Write/ReadModifyWrite
------------------------------------------------------------------------------------------------------
-16 bit address of operand is located in memory following opcode (low byte,high byte)
-
-Opcode Address_l,Address_h
-
-
-
-Absolute Indexed Read/Write/ReadModifyWrite
------------------------------------------------------------------------------------------------------
-Operand is found by adding index value to 16 bit address following opcode.(no wraparound)
-
-Opcode Address_l,Address_h
-
-
-
-Page Zero Read/Write/ReadModifyWrite
------------------------------------------------------------------------------------------------------
-8 bit page zero address of operand is located in memory following opcode.
-
-
-Opcode Address_l
-
-
-
-Page Zero Indexed Read/Write/ReadModifyWrite
------------------------------------------------------------------------------------------------------
-Operand is found in page zero by adding index value to 8 bit address following opcode.(wraps around)
-
-
-Opcode Address_l
-
-
-
-Page Zero Indirect X Read/Write
------------------------------------------------------------------------------------------------------
-Operand address lower byte is read from the address found by adding X index value to 8 bit address following opcode and
-the upper byte is read from the address found by adding X index value to 8 bit address plus 1 (no wraparound)
-
-Opcode Pointer_l
-
-
-
-
-Page Zero Indirect Y Read/Write
------------------------------------------------------------------------------------------------------
-8 bit page zero address containing a 16 bit address is located in memory following opcode. Y index is added to this address
-(no wraparound).
-
-
-Opcode Pointer_l
-
-
-Implied Read/Write/Read_Modify_Write
------------------------------------------------------------------------------------------------------
-Operand is specified in the Opcode
-
-Opcode
-
-
-Branch Read
------------------------------------------------------------------------------------------------------
-Opcode is followed by the relative offset for the branch
-
-Opcode Offset
-
-
-Stack StackRead/StackWrite
------------------------------------------------------------------------------------------------------
-Operation uses the Stack
-
-Opcode
-
-
-Stack_Pointer
------------------------------------------------------------------------------------------------------
-Transfer between Stack_pointer and X index
-
-Opcode
-
-
-Jump Absolute Read
------------------------------------------------------------------------------------------------------
-16 bit destination address follows opcode
-
-
-Opcode Next_Op_add_l,Next_Op_add_h
-
-
-
-Jump Indirect Read
------------------------------------------------------------------------------------------------------
-16 bit Address following opcode points to destination address
-
-Opcode Vector_l, Vector_h
-
-
-JumpSub Absolute Read_Stackwrite
------------------------------------------------------------------------------------------------------
-16 bit destination address follows opcode. Return address is pushed on stack
-
-Opcode Next_Op_add_l,Next_Op_add_h
-
-
-Break Read_Stackwrite
------------------------------------------------------------------------------------------------------
-Return address is pushed on stack and the IRQ vector is taken
-
-Opcode
-
-
-Return from Interrupt Read_Stackread
------------------------------------------------------------------------------------------------------
-PSR and Prog_counter are pulled from stack
-
-
-Opcode
-
-
-
-
-
-Return from Subroutine Read_Stackread
------------------------------------------------------------------------------------------------------
-Prog_counter is pulled from stack
-
-
-Opcode
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-Instruction Opcodes (hex)
-====================================================================================================
-
-
-
- ADC abs 6D
- ADC abs,X 7D
- ADC abs,Y 79
- ADC #n 69
- ADC zp 65
- ADC (zp,X) 61
- ADC zp,X 75
- ADC (zp),Y 71
-
- AND abs 2D
- AND abs,X 3D
- AND abs,Y 39
- AND #n 29
- AND zp 25
- AND (zp,X) 21
- AND zp,X 35
- AND (zp),Y 31
-
- ASL A 0A
- ASL abs 0E
- ASL abs,X 1E
- ASL zp 06
- ASL zp,X 16
-
- BCC rel 90
- BCS rel B0
- BEQ rel F0
-
- BIT abs 2C
- BIT zp 24
-
- BMI rel 30
- BNE rel D0
- BPL rel 10
-
- BRK 00
-
- BVC rel 50
- BVS rel 70
-
-
- CLC 18
- CLD D8
- CLI 58
- CLV B8
-
- CMP abs CD
- CMP abs,X DD
- CMP abs,Y D9
- CMP #n C9
- CMP zp C5
- CMP (zp,X) C1
- CMP zp,X D5
- CMP (zp),Y D1
-
- CPX abs EC
- CPX #n E0
- CPX zp E4
- CPY abs CC
- CPY #n C0
- CPY zp C4
-
- DEC abs CE
- DEC abs,X DE
- DEC zp C6
- DEC zp,X D6
-
- DEX CA
- DEY 88
-
- EOR abs 4D
- EOR abs,X 5D
- EOR abs,Y 59
- EOR #n 49
- EOR zp 45
- EOR (zp,X) 41
- EOR zp,X 55
- EOR (zp),Y 51
-
- INC abs EE
- INC abs,X FE
- INC zp E6
- INC zp,X F6
- INX E8
- INY C8
-
- JMP abs 4C
- JMP (abs) 6C
- JSR abs 20
-
- LDA abs AD
- LDA abs,X BD
- LDA abs,Y B9
- LDA #n A9
- LDA zp A5
- LDA (zp,X) A1
- LDA zp,X B5
- LDA (zp),Y B1
-
- LDX abs AE
- LDX abs,Y BE
- LDX #n A2
- LDX zp A6
- LDX zp,Y B6
-
- LDY abs AC
- LDY abs,X BC
- LDY #n A0
- LDY zp A4
- LDY zp,X B4
-
- LSR A 4A
- LSR abs 4E
- LSR abs,X 5E
- LSR zp 46
- LSR zp,X 56
-
- NOP EA
-
- ORA abs 0D
- ORA abs,X 1D
- ORA abs,Y 19
- ORA #n 09
- ORA zp 05
- ORA (zp,X) 01
- ORA zp,X 15
- ORA (zp),Y 11
-
- PHA 48
- PHP 08
-
- PLA 68
- PLP 28
-
- ROL A 2A
- ROL abs 2E
- ROL abs,X 3E
- ROL zp 26
- ROL zp,X 36
-
- ROR A 6A
- ROR abs 6E
- ROR abs,X 7E
- ROR zp 66
- ROR zp,X 76
-
- RTI 40
-
- RTS 60
-
- SBC abs ED
- SBC abs,X FD
- SBC abs,Y F9
- SBC #n E9
- SBC zp E5
- SBC (zp,X) E1
- SBC zp,X F5
- SBC (zp),Y F1
-
- SEC 38
- SED F8
- SEI 78
-
- STA abs 8D
- STA abs,X 9D
- STA abs,Y 99
- STA zp 85
- STA (zp,X) 81
- STA zp,X 95
- STA (zp),Y 91
-
- STX abs 8E
- STX zp 86
- STX zpy 96
-
- STY abs 8C
- STY zp 84
- STY zp,X 94
-
- TAX AA
- TAY A8
- TXA 8A
- TYA 98
-
-
-
-
-
-
-
-
-
-Instruction Decode
-======================================================================================================================================================
-
-
-
-
-
-
-
-
-
-
-// alu_mode
-`define alu_mode_add 3'b000
-`define alu_mode_and 3'b001
-`define alu_mode_orr 3'b010
-`define alu_mode_eor 3'b011
-`define alu_mode_sfl 3'b100
-`define alu_mode_sfr 3'b101
-`define alu_mode_afl 3'b110
-`define alu_mode_afr 3'b111
-
-// alu_op_a_sel
-
-`define alu_op_a_00 3'b000
-`define alu_op_a_acc 3'b001
-`define alu_op_a_x 3'b010
-`define alu_op_a_y 3'b011
-`define alu_op_a_ff 3'b100
-`define alu_op_a_psr 3'b101
-
-// alu_op_b_sel
-
-`define alu_op_b_00 2'b00
-`define alu_op_b_prog 2'b01
-`define alu_op_b_sp 2'b10
-`define alu_op_b_temp 2'b11
-
-// alu_op_b_inv 1=invert
-
-
-
-// alu_op_c_sel
-
-`define alu_op_c_00 2'b00
-`define alu_op_c_01 2'b01
-`define alu_op_c_cin 2'b10
-`define alu_op_c_xx 2'b11
-
-
-// alu_status_update
-`define alu_status_update_none 3'b000
-`define alu_status_update_nz 3'b001
-`define alu_status_update_nzc 3'b010
-`define alu_status_update_nzcv 3'b011
-`define alu_status_update_wr 3'b100
-`define alu_status_update_z67 3'b101
-`define alu_status_update_res 3'b110
-
-
-
-// dest
-`define dest_none 3'b000
-`define dest_alu_a 3'b001
-`define dest_alu_x 3'b010
-`define dest_alu_y 3'b011
-`define dest_mem 3'b100
-
-
-// ctrl
-`define ctrl_none 3'b000
-`define ctrl_jsr 3'b001
-`define ctrl_jmp 3'b010
-`define ctrl_jmp_ind 3'b011
-`define ctrl_brk 3'b100
-`define ctrl_rti 3'b101
-`define ctrl_rts 3'b110
-`define ctrl_branch 3'b111
-
-// cmd
-`define cmd_none 2'b00
-`define cmd_push_psr 2'b01
-`define cmd_push_pc 2'b10
-`define cmd_load_vec 2'b11
-
-
-// ins_type
-`define ins_type_none 2'b00
-`define ins_type_read 2'b01
-`define ins_type_write 2'b10
-`define ins_type_rmw 2'b11
-
-
-// idx_sel
-`define idx_sel_00 2'b00
-`define idx_sel_x 2'b01
-`define idx_sel_y 2'b10
-
-
-
-// branch_value
-
-
-// branch_enable
-
-
-
-
-
-
-
-
-
-
-Immediate
-
- alu alu alu alu alu
- op_a op_b op_b op_c status alu ins idx branch branch
- src src inv src update mode type sel value enable dest ctrl cmd
-------------------------------------------------------------------------------------------------------------------------------------------------------
- ADC #n | | alu_a prog 0 cin NZCV ADD R 0 00 00 A none none
- AND #n | | alu_a prog 0 0 NZ AND R 0 00 00 A none none
- CMP #n | | alu_a prog 1 1 NZC ADD R 0 00 00 0 none none
- CPX #n | | alu_x prog 1 1 NZC ADD R 0 00 00 0 none none
- CPY #n | | alu_y prog 1 1 NZC ADD R 0 00 00 0 none none
- EOR #n | | alu_a prog 0 0 NZ EOR R 0 00 00 A none none
- LDA #n | | 00 prog 0 0 NZ ADD R 0 00 00 A none none
- LDX #n | | 00 prog 0 0 NZ ADD R 0 00 00 X none none
- LDY #n | | 00 prog 0 0 NZ ADD R 0 00 00 Y none none
- ORA #n | | alu_a prog 0 0 NZ ORR R 0 00 00 A none none
- SBC #n | | alu_a prog 1 cin NZXV ADD R 0 00 00 A none none
-
-
-
-
-Absolute
-
-------------------------------------------------------------------------------------------------------------------------------------------------------
- ADC abs | | alu_a temp 0 cin NZCV ADD R 0 00 00 A none none
- AND abs | | alu_a temp 0 0 NZ AND R 0 00 00 A none none
- BIT abs | | alu_a temp 0 0 Z67 AND R 0 00 00 0 none none
- CMP abs | | alu_a temp 1 1 NZC ADD R 0 00 00 0 none none
- CPX abs | | alu_x temp 1 1 NZC ADD R 0 00 00 0 none none
- CPY abs | | alu_y temp 1 1 NZC ADD R 0 00 00 0 none none
- EOR abs | | alu_a temp 0 0 NZ EOR R 0 00 00 A none none
- LDA abs | | 00 temp 0 0 NZ ADD R 0 00 00 A none none
- LDX abs | | 00 temp 0 0 NZ ADD R 0 00 00 X none none
- LDY abs | | 00 temp 0 0 NZ ADD R 0 00 00 Y none none
- ORA abs | | alu_a temp 0 0 NZ ORR R 0 00 00 A none none
- SBC abs | | alu_a temp 1 cin NZXV ADD R 0 00 00 A none none
- STA abs | | alu_a temp 0 0 NONE ADD W 0 00 00 M none none
- STX abs | | alu_x temp 0 0 NONE ADD W 0 00 00 M none none
- STY abs | | alu_y temp 0 0 NONE ADD W 0 00 00 M none none
- ASL abs | | 00 temp 0 0 NZC SFL RMW 0 00 00 M none none
- DEC abs | | FF temp 0 0 NZ ADD RMW 0 00 00 M none none
- INC abs | | 00 temp 0 1 NZ ADD RMW 0 00 00 M none none
- LSR abs | | 00 temp 0 0 NZC SFR RMW 0 00 00 M none none
- ROL abs | | 00 temp 0 cin NZC SFL RMW 0 00 00 M none none
- ROR abs | | 00 temp 0 cin NZC SFR RMW 0 00 00 M none none
-
-
-Absolute indexed
-
-------------------------------------------------------------------------------------------------------------------------------------------------------
- ADC abs,X | | alu_a temp 0 cin NZCV ADD R X 00 00 A none none
- AND abs,X | | alu_a temp 0 0 NZ AND R X 00 00 A none none
- CMP abs,X | | alu_a temp 1 1 NZC ADD R X 00 00 0 none none
- EOR abs,X | | alu_a temp 0 0 NZ EOR R X 00 00 A none none
- LDA abs,X | | 00 temp 0 0 NZ ADD R X 00 00 A none none
- LDY abs,X | | 00 temp 0 0 NZ ADD R X 00 00 Y none none
- ORA abs,X | | alu_a temp 0 0 NZ ORR R X 00 00 A none none
- SBC abs,X | | alu_a temp 1 cin NZXV ADD R X 00 00 A none none
- ADC abs,Y | | alu_a temp 0 cin NZCV ADD R Y 00 00 A none none
- AND abs,Y | | alu_a temp 0 0 NZ AND R Y 00 00 A none none
- CMP abs,Y | | alu_a temp 1 1 NZC ADD R Y 00 00 0 none none
- EOR abs,Y | | alu_a temp 0 0 NZ EOR R Y 00 00 A none none
- LDA abs,Y | | 00 temp 0 0 NZ ADD R Y 00 00 A none none
- LDX abs,Y | | 00 temp 0 0 NZ ADD R Y 00 00 X none none
- ORA abs,Y | | alu_a temp 0 0 NZ ORR R Y 00 00 A none none
- SBC abs,Y | | alu_a temp 1 cin NZXV ADD R Y 00 00 A none none
- STA abs,X | | alu_a temp 0 0 NONE ADD W X 00 00 M none none
- STA abs,Y | | alu_a temp 0 0 NONE ADD W Y 00 00 M none none
- ASL abs,X | | 00 temp 0 0 NZC SFL RMW X 00 00 M none none
- DEC abs,X | | FF temp 0 0 NZ ADD RMW X 00 00 M none none
- INC abs,X | | 00 temp 0 1 NZ ADD RMW X 00 00 M none none
- LSR abs,X | | 00 temp 0 0 NZC SFR RMW X 00 00 M none none
- ROL abs,X | | 00 temp 0 cin NZC SFL RMW X 00 00 M none none
- ROR abs,X | | 00 temp 0 cin NZC SFR RMW X 00 00 M none none
-
-
-
-
-
-
-Page Zero
-
-------------------------------------------------------------------------------------------------------------------------------------------------------
- ADC zp | | alu_a temp 0 cin NZCV ADD R 0 00 00 A none none
- AND zp | | alu_a temp 0 0 NZ AND R 0 00 00 A none none
- BIT zp | | alu_a temp 0 0 Z67 AND R 0 00 00 0 none none
- CMP zp | | alu_a temp 1 1 NZC ADD R 0 00 00 0 none none
- CPX zp | | alu_x temp 1 1 NZC ADD R 0 00 00 0 none none
- CPY zp | | alu_y temp 1 1 NZC ADD R 0 00 00 0 none none
- EOR zp | | alu_a temp 0 0 NZ EOR R 0 00 00 A none none
- LDA zp | | 00 temp 0 0 NZ ADD R 0 00 00 A none none
- LDX zp | | 00 temp 0 0 NZ ADD R 0 00 00 X none none
- LDY zp | | 00 temp 0 0 NZ ADD R 0 00 00 Y none none
- ORA zp | | alu_a temp 0 0 NZ ORR R 0 00 00 A none none
- SBC zp | | alu_a temp 1 cin NZXV ADD R 0 00 00 A none none
- STA zp | | alu_a temp 0 0 NONE ADD W 0 00 00 M none none
- STX zp | | alu_x temp 0 0 NONE ADD W 0 00 00 M none none
- STY zp | | alu_y temp 0 0 NONE ADD W 0 00 00 M none none
- ASL zp | | 00 temp 0 0 NZC SFL RMW 0 00 00 M none none
- DEC zp | | FF temp 0 0 NZ ADD RMW 0 00 00 M none none
- INC zp | | 00 temp 0 1 NZ ADD RMW 0 00 00 M none none
- LSR zp | | 00 temp 0 0 NZC SFR RMW 0 00 00 M none none
- ROL zp | | 00 temp 0 cin NZC SFL RMW 0 00 00 M none none
- ROR zp | | 00 temp 0 cin NZC SFR RMW 0 00 00 M none none
-
-
-
-Page Zero indexed
-
-------------------------------------------------------------------------------------------------------------------------------------------------------
- ADC zp,X | | alu_a temp 0 cin NZCV ADD R X 00 00 A none none
- AND zp,X | | alu_a temp 0 0 NZ AND R X 00 00 A none none
- CMP zp,X | | alu_a temp 1 1 NZC ADD R X 00 00 0 none none
- EOR zp,X | | alu_a temp 0 0 NZ EOR R X 00 00 A none none
- LDA zp,X | | 00 temp 0 0 NZ ADD R X 00 00 A none none
- LDY zp,X | | 00 temp 0 0 NZ ADD R X 00 00 Y none none
- ORA zp,X | | alu_a temp 0 0 NZ ORR R X 00 00 A none none
- SBC zp,X | | alu_a temp 1 cin NZXV ADD R X 00 00 A none none
- LDX zp,Y | | 00 temp 0 0 NZ ADD R Y 00 00 X none none
- STA zp,X | | alu_a temp 0 0 NONE ADD W X 00 00 M none none
- STY zp,X | | alu_y temp 0 0 NONE ADD W X 00 00 M none none
- STX zp,Y | | alu_x temp 0 0 NONE ADD W Y 00 00 M none none
- ASL zp,X | | 00 temp 0 0 NZC SFL RMW X 00 00 M none none
- DEC zp,X | | FF temp 0 0 NZ ADD RMW X 00 00 M none none
- INC zp,X | | 00 temp 0 1 NZ ADD RMW X 00 00 M none none
- LSR zp,X | | 00 temp 0 0 NZC SFR RMW X 00 00 M none none
- ROR zp,X | | 00 temp 0 cin NZC SFR RMW X 00 00 M none none
- ROL zp,X | | 00 temp 0 cin NZC SFL RMW X 00 00 M none none
-
-
-
-Page Zero indirectX
-
-------------------------------------------------------------------------------------------------------------------------------------------------------
- ADC (zp,X) | | alu_a temp 0 cin NZCV ADD R X 00 00 A none none
- AND (zp,X) | | alu_a temp 0 0 NZ AND R X 00 00 A none none
- CMP (zp,X) | | alu_a temp 1 1 NZC ADD R X 00 00 0 none none
- EOR (zp,X) | | alu_a temp 0 0 NZ EOR R X 00 00 A none none
- LDA (zp,X) | | 00 temp 0 0 NZ ADD R X 00 00 A none none
- ORA (zp,X) | | alu_a temp 0 0 NZ ORR R X 00 00 A none none
- SBC (zp,X) | | alu_a temp 1 cin NZXV ADD R X 00 00 A none none
- STA (zp,X) | | alu_a temp 0 0 NONE ADD W X 00 00 M none none
-
-
-
-======================================================================================================================================================
-
-
-Page Zero IndirectY
-
-------------------------------------------------------------------------------------------------------------------------------------------------------
- ADC (zp),Y | | alu_a temp 0 cin NZCV ADD R Y 00 00 A none none
- AND (zp),Y | | alu_a temp 0 0 NZ AND R Y 00 00 A none none
- CMP (zp),Y | | alu_a temp 1 1 NZC ADD R Y 00 00 0 none none
- EOR (zp),Y | | alu_a temp 0 0 NZ EOR R Y 00 00 A none none
- LDA (zp),Y | | 00 temp 0 0 NZ ADD R Y 00 00 A none none
- ORA (zp),Y | | alu_a temp 0 0 NZ ORR R Y 00 00 A none none
- SBC (zp),Y | | alu_a temp 1 cin NZXV ADD R Y 00 00 A none none
- STA (zp),Y | | alu_a temp 0 0 NONE ADD W Y 00 00 M none none
-
-
-
-
-
-Implied
-
-------------------------------------------------------------------------------------------------------------------------------------------------------
- NOP | | 00 00 0 0 NONE ADD 0 0 00 00 0 none none
- SEC | | 00 00 0 0 WR ADD 0 0 01 01 0 none none
- SED | | 00 00 0 0 WR ADD 0 0 08 08 0 none none
- SEI | | 00 00 0 0 WR ADD 0 0 04 04 0 none none
- CLC | | 00 00 0 0 WR ADD 0 0 00 01 0 none none
- CLD | | 00 00 0 0 WR ADD 0 0 00 08 0 none none
- CLI | | 00 00 0 0 WR ADD 0 0 00 04 0 none none
- CLV | | 00 00 0 0 WR ADD 0 0 00 40 0 none none
- ASL A | | alu_a 00 0 0 NZC SFL RMW 0 00 00 A none none
- DEX | | alu_x 00 0 0 NZ ADD RMW 0 00 00 X none none
- DEY | | alu_y 00 0 0 NZ ADD RMW 0 00 00 Y none none
- INX | | alu_x 00 0 1 NZ ADD RMW 0 00 00 X none none
- INY | | alu_y 00 0 1 NZ ADD RMW 0 00 00 Y none none
- LSR A | | alu_a 00 0 0 NZC SFR RMW 0 00 00 A none none
- ROL A | | alu_a 00 0 cin NZC SFL RMW 0 00 00 A none none
- ROR A | | alu_a 00 0 cin NZC SFR RMW 0 00 00 A none none
- TAX | | alu_a 00 0 0 NZ ADD RMW 0 00 00 A none none
- TAY | | alu_a 00 0 0 NZ ADD RMW 0 00 00 X none none
- TXA | | alu_x 00 0 0 NZ ADD RMW 0 00 00 A none none
- TYA | | alu_y 00 0 0 NZ ADD RMW 0 00 00 A none none
-
-
-
-Branch
- alu alu alu alu alu
- op_a op_b op_b op_c status alu branch branch
- src src inv src update mode type index value enable dest
-------------------------------------------------------------------------------------------------------------------------------------------------------
- BCC rel | | 00 00 0 0 NONE ADD 0 0 00 01 0 branch none
- BCS rel | | 00 00 0 0 NONE ADD 0 0 01 01 0 branch none
- BNE rel | | 00 00 0 0 NONE ADD 0 0 00 02 0 branch none
- BEQ rel | | 00 00 0 0 NONE ADD 0 0 02 02 0 branch none
- BVC rel | | 00 00 0 0 NONE ADD 0 0 00 40 0 branch none
- BVS rel | | 00 00 0 0 NONE ADD 0 0 40 40 0 branch none
- BPL rel | | 00 00 0 0 NONE ADD 0 0 00 80 0 branch none
- BMI rel | | 00 00 0 0 NONE ADD 0 0 80 80 0 branch none
-
-
-
-Stack
-------------------------------------------------------------------------------------------------------------------------------------------------------
- PLA | | 00 00 0 0 NZ ADD R 0 00 00 A
- PLP | | 00 00 0 0 RESTORE ADD R 0 00 00 PSR
- PHA | | alu_a 00 0 0 NONE ADD W 0 00 00 M
- PHP | | psr 00 0 0 NONE ADD W 0 00 00 M
-
-
-
-Jump absolute
-------------------------------------------------------------------------------------------------------------------------------------------------------
- JMP abs | | 00 00 0 0 NONE ADD 0 0 00 00 0
-
-
-
-Jump indirect
-------------------------------------------------------------------------------------------------------------------------------------------------------
- JMP (abs) | | 00 00 0 0 NONE ADD 0 0 00 00 0
-
-
-
-Jump Sub absolute
-------------------------------------------------------------------------------------------------------------------------------------------------------
- JSR abs | | 00 00 0 0 NONE ADD 0 0 00 00 0
-
-
-
-Break
-------------------------------------------------------------------------------------------------------------------------------------------------------
- BRK | | alu_a 00 0 0 WR ADD 0 0 10 10 0
-
-
-
-Return from
-Interrupt
-------------------------------------------------------------------------------------------------------------------------------------------------------
- RTI | | 00 00 0 0 RESTORE ADD 0 0 00 00 P
-
-
-
-Return from
-Subroutine
-------------------------------------------------------------------------------------------------------------------------------------------------------
- RTS | | 00 00 0 0 NONE ADD 0 0 00 00 0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-Opcode Current Instruction byte
-New_opcode Next Instruction byte
-Opc_Add Address of current instruction
-Next_Op_Add Address of next instruction byte
-Operand Data operand
-Address Address of data operand if in memory
-Offset Value added to Opc_Add if branch is taken
-Pointer Address to store the address of data opeand if in memory
-Vector Address to store the Next_Op_Add
-
-
-
-
-
-
-
-
-
-Address Sequence Decodes
-=========================================================================
-
-
-
-
-
-
-Implied Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-______________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add Opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 Opcode 1 Set
-3 1 Opc_Add+1 New_Opcode opcode 1 Set
---------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+2 New_Opcode updated
-
-
-
-
-Immediate Addressing Mode
-
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-____________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
-----------------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+1 operand operand Set
-----------------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+2 operand 1 Set
-5 1 Opc_Add+2 new_op opcode 1 Set
-----------------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+3 new_op updated
-
-
-
-
-
-
-
-Absolute Read Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+2 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+3 add_hi add_hi Set
-5 1 Opc_Add+3 new_op addr r 00 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+3 new_op addr r 00 operand Set
-7 1 Opc_Add+3 new_op addr r 00 operand Set
---------------------------------------------------------------------------------------------------------------------------------------------
-8 0 Opc_Add+3 new_op 1 Set
-9 1 Opc_Add+3 new_op opcode 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-10 0 updated
-
-
-
-
-
-
-Absolute Write Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+2 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+3 add_hi add_hi Set
-5 1 Opc_Add+3 new_op opcode addr w operand 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+4 new_op updated
-7 1 Opc_Add+4
-
-
-
-
-
-Absolute Read/Modify/Write Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+2 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+3 add_hi add_hi Set
-5 1 Opc_Add+3 new_op addr r Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+3 new_op operand Set
-7 1 Opc_Add+3 new_op Set
---------------------------------------------------------------------------------------------------------------------------------------------
-8 0 Opc_Add+3 new_op addr w result 1 Set
-9 1 Opc_Add+3 new_op opcode 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-10 0 updated
-
-
-
-
-
-
-
-Absolute Indexed Read Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+2 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+3 add_hi add_hi Set
-5 1 Opc_Add+3 new_op addr+i r 00 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+3 new_op addr+i r 00 operand Set
-7 1 Opc_Add+3 new_op addr+i r 00 operand Set
---------------------------------------------------------------------------------------------------------------------------------------------
-8 0 Opc_Add+3 new_op 1 Set
-9 1 Opc_Add+3 new_op opcode 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-10 0 updated
-
-
-
-Absolute Indexed Write Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+2 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+3 add_hi add_hi 1 Set
-5 1 Opc_Add+3 new_op opcode addr+i w operand 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+4 new_op updated
-7 1 Opc_Add+4
-
-
-
-
-
-Absolute Indexed Read/Modify/Write Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+2 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+3 add_hi add_hi Set
-5 1 Opc_Add+3 new_op addr+i r Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+3 new_op operand Set
-7 1 Opc_Add+3 new_op Set
---------------------------------------------------------------------------------------------------------------------------------------------
-8 0 Opc_Add+3 new_op addr+i w result 1 Set
-9 1 Opc_Add+3 new_op opcode 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-10 0 updated
-
-
-
-
-
-
-
-
-
-
-
-
-Page Zero Read Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+1 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+2 add_lo addr r Set
-5 1 Opc_Add+2 new_op operand Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+2 new_op 1 Set
-7 1 Opc_Add+2 new_op opcode 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-8 0 Opc_Add+3 new_op updated
-
-
-
-
-
-
-
-
-Page Zero Write Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+1 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+2 add_lo 1 Set
-5 1 Opc_Add+2 new_op opcode addr w operand 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+3 new_op updated
-7 1 Opc_Add+3
-
-
-
-
-
-
-
-Page Zero Read/Modify/Write Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+1 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+2 add_lo addr r Set
-5 1 Opc_Add+2 new_op operand Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+2 new_op 1 Set
-7 1 Opc_Add+2 new_op opcode addr w result 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-8 0 Opc_Add+3 new_op updated
-
-
-
-
-
-
-
-
-
-
-Page Zero Indexed Read Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+1 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+2 add_lo addr+i r Set
-5 1 Opc_Add+2 new_op operand Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+2 new_op 1 Set
-7 1 Opc_Add+2 new_op opcode 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-8 0 Opc_Add+3 new_op updated
-
-
-
-
-
-Page Zero Indexed Write Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+1 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+2 add_lo 1 Set
-5 1 Opc_Add+2 new_op opcode addr w operand 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+3 new_op updated
-7 1 Opc_Add+3
-
-
-
-
-
-
-
-Page Zero Indexed Read/Modify/Write Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+1 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+2 add_lo addr r Set
-5 1 Opc_Add+2 new_op operand Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+2 new_op 1 Set
-7 1 Opc_Add+2 new_op opcode addr w result 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-8 0 Opc_Add+3 new_op updated
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-Page Zero Indirect X Read
--------------------------------------------------------
-Operand address lower byte is read from the address found by adding X index value to 8 bit address following opcode and
-the upper byte is read from the address found by adding X index value to 8 bit address plus 1 (no wraparound)
-
-
-
-
-Page Zero IndirectX Read Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+1 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+2 add_lo addr+i r Set
-5 1 Opc_Add+2 new_op addr+i+1 r add_l Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+2 new_op add_h Set
-7 1 Opc_Add+2 new_op addr r Set
---------------------------------------------------------------------------------------------------------------------------------------------
-8 0 Opc_Add+2 new_op operand 1 Set
-9 1 opcode 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-10 0 updated
-
-
-
-
-
-Page Zero IndirectX Write Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+1 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+2 add_lo addr+i r Set
-5 1 Opc_Add+2 new_op addr+i+1 add_l Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+2 new_op add_h 1 Set
-7 1 Opc_Add+2 new_op opcode addr w result 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-8 0 Opc_Add+3 new_op updated
-9 1
-
-
-
-
-
-
-
-
-
-Page Zero IndirectY Read Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+1 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+2 add_lo addr_lo r Set
-5 1 Opc_Add+2 new_op addr Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+2 new_op addr+i r Set
-7 1 Opc_Add+2 new_op addr+i r operand Set
---------------------------------------------------------------------------------------------------------------------------------------------
-8 0 Opc_Add+2 new_op 1 Set
-9 1 opcode 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-10 0 updated
-
-
-
-
-Page Zero IndirectX Write Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+1 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+2 add_lo add_lo r 1 Set
-5 1 Opc_Add+2 new_op addr 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+2 new_op addr+i w result Set
-7 1 Opc_Add+2 new_op opcode Set updated
---------------------------------------------------------------------------------------------------------------------------------------------
-8 0 Opc_Add+3 new_op
-9 1
-
-
-
-
-
-
-Relative Addressing Mode
-
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-____________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
-----------------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+1 offset offset Set
-----------------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Next_Op_Add offset 1
-5 1 Next_Op_Add new_op opcode 1
-----------------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Next_Op_Add+1 new_op
-
-
-
-
-
-Addressing Modes
-===============================================================================================
-
-
-
-
-
-Stack StackRead/StackWrite
--------------------------------------------------------
-Operation uses the Stack
-
-
-
-Jump Absolute Read
--------------------------------------------------------
-16 bit destination address follows opcode
-
-
-Jump Indirect Read
--------------------------------------------------------
-16 bit Address following opcode points to destination address
-
-
-
-
-Jump Sub Absolute Read_Stackwrite
--------------------------------------------------------
-16 bit destination address follows opcode. Return address is pushed on stack
-
-
-
-Break Read_Stackwrite
--------------------------------------------------------
-Return address is pushed on stack and the IRQ vector is taken
-
-
-
-Return from Interrupt Read_Stackread
--------------------------------------------------------
-PSR and Prog_counter are pulled from stack
-
-
-
-
-Return from Subroutine Read_Stackread
--------------------------------------------------------
-Prog_counter is pulled from stack
-
-
-
-
-
-
-
-
-
-
-
-
-
-Interrupts
-===============================================================================================
-
-Non-Maskable (NMI)
-
- 1) Finish current instruction
- 2) Push Address of next instruction on stack
- 3) Read Vector Address from FFFA
- 4) Execute code @ vector address
-
-
-
-Maskable (IRQ) ( if I bit is clear)
-
- 1) Finish current instruction
- 2) Push Address of next instruction on stack
- 3) Push PSR on stack
- 4) Read Vector Address from FFFE
- 5) Execute code @ vector address
-
-
-Reset
-
- 1) Clear A,X,Y: Set PSR to 20h
- 2) Wait for Reset to deassert
- 3) Read Vector Address from FFFC
- 4) Execute code @ vector address
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Index: socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/doc/Readme.txt
===================================================================
--- socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/doc/Readme.txt (revision 74)
+++ socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/doc/Readme.txt (nonexistent)
@@ -1,57 +0,0 @@
-
-
-
-
-This component comes from the opencores t6507lp project and makes it socgen compatible. The original project checked in by Gabriel Oshiro Zardo and Samuel Nascimento Pagliarini was a atari 2600 on a chip. This project only takes the t6507 processor and uses it as a 6502. It had some documentation and a test suite that was somewhat working.
-
-I chose it because a 6502 is a useful module and had clean partitioning. The following changes were made:
-
-
-
-1) Converted to a full 16 bit address bus.
-
- also hardcoded the 8 bit data bus. Hasn't changed in thirty five years.
-
-2) Converted parameters to `defines
-
-3) Converted reset to synchronous active high
-
-4) Converted test suite to socgen format
-
- Each test is in it's own subdirectory and any needed code is assembled and loaded into sram
-
-5) Design had no reset/interrupt vectors. Added reset vector. May add interupt(s) later.
-
-6) Added enable logic so that it could work with synchronous sram
-
-7) Design doesn't appear to be fully functional.
- CLC followed by BCC missed the offset by one clock cycle.
- JSR doesn't push high address on stack. puts wrong data in page 00
- Branch backwards doesn't work.
- read/modify/write did not work
- pha pushed onto page 0
- pha data latched one clock to late
- jmp indirect didn't work
-
-8) Split T6502_fsm into smaller blocks for ease of documenting and verifying
-
-9) Move branch decision logic into sequencer block
-
-10) removed BCD logic
-
-11) moved alu_opcode to instr_decode block
-
-12) created datapath logic for alu_operand_a, alu_operand_b and alu_operand_c
-
-13) split alu into alu_control and alu blocks
-
-14) reworked the inst_decode signals to alu and pulled datapath out of sequencer
-
-15) removed the latched alu_result. Outside of alu now uses raw
-
-
-
-
-This appears to be a work in progress with numerous issues. I fixed enough of them so that I can
-synthesize into an fpga and it runs the io_poll program on a Nexys2 Board. I will commit this as
-a start but it is alpha code and will have bugs.
Index: socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/doc/orig6502.txt
===================================================================
--- socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/doc/orig6502.txt (revision 74)
+++ socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/doc/orig6502.txt (nonexistent)
@@ -1,151 +0,0 @@
- ADC abs | 6D | ADC abs |
- ADC abs,X | 7D | ADC abs,X |
- ADC abs,Y | 79 | ADC abs,Y |
- ADC #n | 69 | ADC #n |
- ADC zp | 65 | ADC zp |
- ADC (zp,X) | 61 | ADC (zp,X) |
- ADC zp,X | 75 | ADC zp,X |
- ADC (zp),Y | 71 | ADC (zp),Y |
- AND abs | 2D | AND abs |
- AND abs,X | 3D | AND abs,X |
- AND abs,Y | 39 | AND abs,Y |
- AND #n | 29 | AND #n |
- AND zp | 25 | AND zp |
- AND (zp,X) | 21 | AND (zp,X) |
- AND zp,X | 35 | AND zp,X |
- AND (zp),Y | 31 | AND (zp),Y |
- ASL A | 0A | ASL A |
- ASL abs | 0E | ASL abs |
- ASL abs,X | 1E | ASL abs,X |
- ASL zp | 06 | ASL zp |
- ASL zp,X | 16 | ASL zp,X |
- BCC rel | 90 | BCC rel |
- BCS rel | B0 | BCS rel |
- BEQ rel | F0 | BEQ rel |
- BIT abs | 2C | BIT abs |
- BIT zp | 24 | BIT zp |
- BMI rel | 30 | BMI rel |
- BNE rel | D0 | BNE rel |
- BPL rel | 10 | BPL rel |
- BRK | 00 | BRK |
- BVC rel | 50 | BVC rel |
- BVS rel | 70 | BVS rel |
- CLC | 18 | CLC |
- CLD | D8 | CLD |
- CLI | 58 | CLI |
- CLV | B8 | CLV |
- CMP abs | CD | CMP abs |
- CMP abs,X | DD | CMP abs,X |
- CMP abs,Y | D9 | CMP abs,Y |
- CMP #n | C9 | CMP #n |
- CMP zp | C5 | CMP zp |
- CMP (zp,X) | C1 | CMP (zp,X) |
- CMP zp,X | D5 | CMP zp,X |
- CMP (zp),Y | D1 | CMP (zp),Y |
- CPX abs | EC | CPX abs |
- CPX #n | E0 | CPX #n |
- CPX zp | E4 | CPX zp |
- CPY abs | CC | CPY abs |
- CPY #n | C0 | CPY #n |
- CPY zp | C4 | CPY zp |
- DEC abs | CE | DEC abs |
- DEC abs,X | DE | DEC abs,X |
- DEC zp | C6 | DEC zp |
- DEC zp,X | D6 | DEC zp,X |
- DEX | CA | DEX |
- DEY | 88 | DEY |
- EOR abs | 4D | EOR abs |
- EOR abs,X | 5D | EOR abs,X |
- EOR abs,Y | 59 | EOR abs,Y |
- EOR #n | 49 | EOR #n |
- EOR zp | 45 | EOR zp |
- EOR (zp,X) | 41 | EOR (zp,X) |
- EOR zp,X | 55 | EOR zp,X |
- EOR (zp),Y | 51 | EOR (zp),Y |
- INC abs | EE | INC abs |
- INC abs,X | FE | INC abs,X |
- INC zp | E6 | INC zp |
- INC zp,X | F6 | INC zp,X |
- INX | E8 | INX |
- INY | C8 | INY |
- JMP abs | 4C | JMP abs |
- JMP (abs) | 6C | JMP (abs) |
- JSR abs | 20 | JSR abs |
- LDA abs | AD | LDA abs |
- LDA abs,X | BD | LDA abs,X |
- LDA abs,Y | B9 | LDA abs,Y |
- LDA #n | A9 | LDA #n |
- LDA zp | A5 | LDA zp |
- LDA (zp,X) | A1 | LDA (zp,X) |
- LDA zp,X | B5 | LDA zp,X |
- LDA (zp),Y | B1 | LDA (zp),Y |
- LDX abs | AE | LDX abs |
- LDX abs,Y | BE | LDX abs,Y |
- LDX #n | A2 | LDX #n |
- LDX zp | A6 | LDX zp |
- LDX zp,Y | B6 | LDX zp,Y |
- LDY abs | AC | LDY abs |
- LDY abs,X | BC | LDY abs,X |
- LDY #n | A0 | LDY #n |
- LDY zp | A4 | LDY zp |
- LDY zp,X | B4 | LDY zp,X |
- LSR A | 4A | LSR A |
- LSR abs | 4E | LSR abs |
- LSR abs,X | 5E | LSR abs,X |
- LSR zp | 46 | LSR zp |
- LSR zp,X | 56 | LSR zp,X |
- NOP | EA | NOP |
- ORA abs | 0D | ORA abs |
- ORA abs,X | 1D | ORA abs,X |
- ORA abs,Y | 19 | ORA abs,Y |
- ORA #n | 09 | ORA #n |
- ORA zp | 05 | ORA zp |
- ORA (zp,X) | 01 | ORA (zp,X) |
- ORA zp,X | 15 | ORA zp,X |
- ORA (zp),Y | 11 | ORA (zp),Y |
- PHA | 48 | PHA |
- PHP | 08 | PHP |
- PLA | 68 | PLA |
- PLP | 28 | PLP |
- ROL A | 2A | ROL A |
- ROL abs | 2E | ROL abs |
- ROL abs,X | 3E | ROL abs,X |
- ROL zp | 26 | ROL zp |
- ROL zp,X | 36 | ROL zp,X |
- ROR A | 6A | ROR A |
- ROR abs | 6E | ROR abs |
- ROR abs,X | 7E | ROR abs,X |
- ROR zp | 66 | ROR zp |
- ROR zp,X | 76 | ROR zp,X |
- RTI | 40 | RTI |
- RTS | 60 | RTS |
- SBC abs | ED | SBC abs |
- SBC abs,X | FD | SBC abs,X |
- SBC abs,Y | F9 | SBC abs,Y |
- SBC #n | E9 | SBC #n |
- SBC zp | E5 | SBC zp |
- SBC (zp,X) | E1 | SBC (zp,X) |
- SBC zp,X | F5 | SBC zp,X |
- SBC (zp),Y | F1 | SBC (zp),Y |
- SEC | 38 | SEC |
- SED | F8 | SED |
- SEI | 78 | SEI |
- STA abs | 8D | STA abs |
- STA abs,X | 9D | STA abs,X |
- STA abs,Y | 99 | STA abs,Y |
- STA zp | 85 | STA zp |
- STA (zp,X) | 81 | STA (zp,X) |
- STA zp,X | 95 | STA zp,X |
- STA (zp),Y | 91 | STA (zp),Y |
- STX abs | 8E | STX abs |
- STX zp | 86 | STX zp |
- STX zpy | 96 | STX zpy |
- STY abs | 8C | STY abs |
- STY zp | 84 | STY zp |
- STY zp,X | 94 | STY zp,X |
- TAX | AA | TAX |
- TAY | A8 | TAY |
- TSX | BA | TSX |
- TXA | 8A | TXA |
- TXS | 9A | TXS |
- TYA | 98 | TYA |
Index: socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/doc/copyright.v
===================================================================
--- socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/doc/copyright.v (revision 74)
+++ socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/doc/copyright.v (nonexistent)
@@ -1,80 +0,0 @@
-////////////////////////////////////////////////////////////////////
-// -------------- //
-// / SOC \ //
-// / GEN \ //
-// / COMPONENT \ //
-// ==================== //
-// |digital done right| //
-// |__________________| //
-// //
-// //
-// //
-// Copyright (C) <2010> //
-// //
-// //
-// This source file may be used and distributed without //
-// restriction provided that this copyright statement is not //
-// removed from the file and that any derivative work contains //
-// the original copyright notice and the associated disclaimer. //
-// //
-// This source file is free software; you can redistribute it //
-// and/or modify it under the terms of the GNU Lesser General //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any //
-// later version. //
-// //
-// This source is distributed in the hope that it will be //
-// useful, but WITHOUT ANY WARRANTY; without even the implied //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
-// PURPOSE. See the GNU Lesser General Public License for more //
-// details. //
-// //
-// You should have received a copy of the GNU Lesser General //
-// Public License along with this source; if not, download it //
-// from http://www.opencores.org/lgpl.shtml //
-// //
-////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////////
-//// ////
-//// T6507LP IP Core ////
-//// ////
-//// This file is part of the T6507LP project ////
-//// http://www.opencores.org/cores/t6507lp/ ////
-//// ////
-//// Description ////
-//// Implementation of a 6507-compatible microprocessor ////
-//// ////
-//// To Do: ////
-//// - Everything ////
-//// ////
-//// Author(s): ////
-//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
-//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
-//// ////
-////////////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-////////////////////////////////////////////////////////////////////////////
Index: socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/bin/Makefile
===================================================================
--- socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/bin/Makefile (revision 74)
+++ socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/bin/Makefile (nonexistent)
@@ -1,2 +0,0 @@
-include ../../../bin/Makefile.root
-
Index: socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/sim/bin/Makefile
===================================================================
--- socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/sim/bin/Makefile (revision 74)
+++ socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/sim/bin/Makefile (nonexistent)
@@ -1,3 +0,0 @@
-include ../../../../bin/Makefile.root
-
-
Index: socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/sim/cov/T6502_state_fsm/Makefile
===================================================================
--- socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/sim/cov/T6502_state_fsm/Makefile (revision 74)
+++ socgen/trunk/projects/Mos6502/ip/T6502_state_fsm/sim/cov/T6502_state_fsm/Makefile (nonexistent)
@@ -1,46 +0,0 @@
-SHELL=/bin/sh
-MAKE=make
-VARIANT=T6502_state_fsm
-VPP_NAME=vppreproc
-
-
-
-################################################################################
-# set up coverage
-################################################################################
-
-
-
-.PHONY build_cdd:
-build_cdd:
- echo "################################################################################"; \
- echo; \
- $(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\
- covered score -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\
- echo "################################################################################"; \
-
-
-################################################################################
-# score coverage from vcd
-################################################################################
-
-
-
-.PHONY score_cov:
-score_cov:
- echo "################################################################################"; \
- echo " Scoring ${$TEST} ";\
- covered score -cdd $(VARIANT).cdd -vcd ../../out/$(TEST).vcd 2>> $(VARIANT)_sco_cov.log | tee >> $(VARIANT)_sco_cov.log ;\
-
-
-
-################################################################################
-# run coverage report
-################################################################################
-
-
-
-.PHONY report_cov:
-report_cov:
- echo "################################################################################"; \
- covered report -cdd $(VARIANT).cdd 2> $(VARIANT)_rep_cov.log | tee >> $(VARIANT)_rep_cov.log ;\
Index: socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/bin/Makefile
===================================================================
--- socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/bin/Makefile (revision 74)
+++ socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/bin/Makefile (nonexistent)
@@ -1,2 +0,0 @@
-include ../../../bin/Makefile.root
-
Index: socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/sim/cov/T6502_inst_decode/Makefile
===================================================================
--- socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/sim/cov/T6502_inst_decode/Makefile (revision 74)
+++ socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/sim/cov/T6502_inst_decode/Makefile (nonexistent)
@@ -1,46 +0,0 @@
-SHELL=/bin/sh
-MAKE=make
-VARIANT=T6502_inst_decode
-VPP_NAME=vppreproc
-
-
-
-################################################################################
-# set up coverage
-################################################################################
-
-
-
-.PHONY build_cdd:
-build_cdd:
- echo "################################################################################"; \
- echo; \
- $(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\
- covered score -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\
- echo "################################################################################"; \
-
-
-################################################################################
-# score coverage from vcd
-################################################################################
-
-
-
-.PHONY score_cov:
-score_cov:
- echo "################################################################################"; \
- echo " Scoring ${$TEST} ";\
- covered score -cdd $(VARIANT).cdd -vcd ../../out/$(TEST).vcd 2>> $(VARIANT)_sco_cov.log | tee >> $(VARIANT)_sco_cov.log ;\
-
-
-
-################################################################################
-# run coverage report
-################################################################################
-
-
-
-.PHONY report_cov:
-report_cov:
- echo "################################################################################"; \
- covered report -cdd $(VARIANT).cdd 2> $(VARIANT)_rep_cov.log | tee >> $(VARIANT)_rep_cov.log ;\
Index: socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/sim/bin/Makefile
===================================================================
--- socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/sim/bin/Makefile (revision 74)
+++ socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/sim/bin/Makefile (nonexistent)
@@ -1,3 +0,0 @@
-include ../../../../bin/Makefile.root
-
-
Index: socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/rtl/verilog/top.v
===================================================================
--- socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/rtl/verilog/top.v (revision 74)
+++ socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/rtl/verilog/top.v (nonexistent)
@@ -1,2342 +0,0 @@
-
-`include "defines.v"
-
-module `VARIANT
-#(parameter STATE_SIZE=3)
-
-(
-
- input wire clk,
- input wire reset,
- input wire enable,
- input wire disable_ir,
- input wire fetch_op,
- input wire [STATE_SIZE:0] state,
- input wire [7:0] prog_data,
-
- output reg now_fetch_op,
-
- output reg [7:0] ir,
- output reg [1:0] length,
-
- output reg immediate,
- output reg absolute,
- output reg zero_page,
- output reg indirectx,
- output reg indirecty,
- output reg implied,
- output reg relative,
- output reg stack,
-
- output reg jsr,
- output reg jump,
- output reg jump_indirect,
- output reg brk,
- output reg rti,
- output reg rts,
-
- output reg invalid,
-
- output reg [1:0] ins_type,
-
- output reg [2:0] ctrl,
- output reg [2:0] dest,
-
- output reg [2:0] alu_op_a_sel,
- output reg [1:0] alu_op_b_sel,
- output reg alu_op_b_inv,
- output reg [1:0] alu_op_c_sel,
-
- output reg [1:0] idx_sel,
-
-
- output reg [2:0] alu_mode,
- output reg [4:0] alu_status_update,
-
- output reg [7:0] brn_value,
- output reg [7:0] brn_enable
-);
-
-
-
-reg [1:0] n_length;
-
-reg n_immediate;
-reg n_absolute;
-reg n_zero_page;
-reg n_indirectx;
-reg n_indirecty;
-reg n_implied;
-reg n_relative;
-reg n_stack;
-reg n_jsr;
-reg n_jump;
-reg n_jump_indirect;
-reg n_brk;
-reg n_rti;
-reg n_rts;
-reg n_invalid;
-reg [1:0] n_ins_type;
-
-reg [2:0] n_ctrl;
-reg [2:0] n_dest;
-reg [2:0] n_alu_op_a_sel;
-reg [1:0] n_alu_op_b_sel;
-reg [1:0] n_idx_sel;
-reg n_alu_op_b_inv;
-reg [1:0] n_alu_op_c_sel;
-reg [2:0] n_alu_mode;
-reg [4:0] n_alu_status_update;
-reg [7:0] n_brn_value;
-reg [7:0] n_brn_enable;
-
-
-
-
-always@(*)
- now_fetch_op = (state == `FETCH_OP) || fetch_op || implied || stack ;
-
-
-
-always@(posedge clk)
- if (reset || disable_ir)
- begin
- ir <= 8'h00;
- length <= 2'b00;
- absolute <= 1'b0;
- immediate <= 1'b0;
- implied <= 1'b0;
- indirectx <= 1'b0;
- indirecty <= 1'b0;
- relative <= 1'b0;
- zero_page <= 1'b0;
- stack <= 1'b0;
- jump <= 1'b0;
- jump_indirect <= 1'b0;
- jsr <= 1'b0;
- brk <= 1'b0;
- rti <= 1'b0;
- rts <= 1'b0;
- ins_type <= `ins_type_none;
- alu_mode <= `alu_mode_add;
- alu_op_a_sel <= `alu_op_a_00;
- alu_op_b_sel <= `alu_op_b_00;
- alu_op_b_inv <= 1'b0;
- alu_op_c_sel <= `alu_op_c_00;
- idx_sel <= `idx_sel_00;
- alu_status_update <= `alu_status_update_none;
- brn_value <= 8'h00;
- brn_enable <= 8'h00;
- dest <= `dest_none;
- ctrl <= `ctrl_none;
- invalid <= 1'b0;
- end
- else
- if((!enable) || (!now_fetch_op) )
- begin
- ir <= ir ;
- length <= length ;
- absolute <= absolute ;
- immediate <= immediate ;
- implied <= implied ;
- indirectx <= indirectx ;
- indirecty <= indirecty ;
- relative <= relative ;
- zero_page <= zero_page ;
- stack <= stack ;
- jump <= jump ;
- jump_indirect <= jump_indirect ;
- jsr <= jsr ;
- brk <= brk ;
- rti <= rti ;
- rts <= rts ;
- ins_type <= ins_type ;
- alu_mode <= alu_mode ;
- alu_op_a_sel <= alu_op_a_sel ;
- alu_op_b_sel <= alu_op_b_sel ;
- alu_op_b_inv <= alu_op_b_inv ;
- alu_op_c_sel <= alu_op_c_sel ;
- idx_sel <= idx_sel ;
- alu_status_update <= alu_status_update ;
- brn_value <= brn_value ;
- brn_enable <= brn_enable ;
- dest <= dest ;
- ctrl <= ctrl ;
- invalid <= invalid ;
- end
- else
- begin
- ir <= prog_data ;
- length <= n_length ;
- absolute <= n_absolute ;
- immediate <= n_immediate ;
- implied <= n_implied ;
- indirectx <= n_indirectx ;
- indirecty <= n_indirecty ;
- relative <= n_relative ;
- zero_page <= n_zero_page ;
- stack <= n_stack ;
- jump <= n_jump ;
- jump_indirect <= n_jump_indirect ;
- jsr <= n_jsr ;
- brk <= n_brk ;
- rti <= n_rti ;
- rts <= n_rts ;
- ins_type <= n_ins_type ;
- alu_mode <= n_alu_mode ;
- alu_op_a_sel <= n_alu_op_a_sel ;
- alu_op_b_sel <= n_alu_op_b_sel ;
- alu_op_b_inv <= n_alu_op_b_inv ;
- alu_op_c_sel <= n_alu_op_c_sel ;
- idx_sel <= n_idx_sel ;
- alu_status_update <= n_alu_status_update ;
- brn_value <= n_brn_value ;
- brn_enable <= n_brn_enable ;
- dest <= n_dest ;
- ctrl <= n_ctrl ;
- invalid <= n_invalid ;
- end
-
-
-
-always @ (*)
- begin
- n_length = 2'b00;
- n_absolute = 1'b0;
- n_immediate = 1'b0;
- n_implied = 1'b0;
- n_indirectx = 1'b0;
- n_indirecty = 1'b0;
- n_relative = 1'b0;
- n_zero_page = 1'b0;
- n_stack = 1'b0;
- n_jump = 1'b0;
- n_jump_indirect = 1'b0;
- n_jsr = 1'b0;
- n_brk = 1'b0;
- n_rti = 1'b0;
- n_rts = 1'b0;
- n_ins_type = `ins_type_none;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_00;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_idx_sel = `idx_sel_00;
- n_alu_status_update = `alu_status_update_none;
- n_brn_value = 8'h00;
- n_brn_enable = 8'h00;
- n_dest = `dest_none;
- n_ctrl = `ctrl_none;
- n_invalid = 1'b0;
-
- case (prog_data)
-
-// implied
-
-
- `CLC_IMP:
- begin
- n_length = 2'b01;
- n_implied = 1'b1;
- n_alu_status_update = `alu_status_update_wr;
- n_brn_value = 8'h00;
- n_brn_enable = 8'h01;
- n_dest = `dest_none;
- end
-
- `CLD_IMP:
- begin
- n_length = 2'b01;
- n_implied = 1'b1;
- n_alu_status_update = `alu_status_update_wr;
- n_brn_value = 8'h00;
- n_brn_enable = 8'h08;
- n_dest = `dest_none;
- end
-
- `CLI_IMP:
- begin
- n_length = 2'b01;
- n_implied = 1'b1;
- n_alu_status_update = `alu_status_update_wr;
- n_brn_value = 8'h00;
- n_brn_enable = 8'h04;
- n_dest = `dest_none;
- end
-
- `CLV_IMP:
- begin
- n_length = 2'b01;
- n_implied = 1'b1;
- n_alu_status_update = `alu_status_update_wr;
- n_brn_value = 8'h00;
- n_brn_enable = 8'h40;
- n_dest = `dest_none;
- end
-
- `DEX_IMP:
- begin
- n_length = 2'b01;
- n_implied = 1'b1;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_x;
- n_alu_op_b_inv = 1'b1;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_x;
- end
-
- `DEY_IMP:
- begin
- n_length = 2'b01;
- n_implied = 1'b1;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_y;
- n_alu_op_b_inv = 1'b1;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_y;
- end
-
- `INX_IMP:
- begin
- n_length = 2'b01;
- n_implied = 1'b1;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_x;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_01;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_x;
- end
-
- `INY_IMP:
- begin
- n_length = 2'b01;
- n_implied = 1'b1;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_y;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_01;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_y;
- end
-
- `SEC_IMP:
- begin
- n_length = 2'b01;
- n_implied = 1'b1;
- n_alu_status_update = `alu_status_update_wr;
- n_brn_value = 8'h01;
- n_brn_enable = 8'h01;
- n_dest = `dest_none;
- end
-
- `SED_IMP:
- begin
- n_length = 2'b01;
- n_implied = 1'b1;
- n_alu_status_update = `alu_status_update_wr;
- n_brn_value = 8'h08;
- n_brn_enable = 8'h08;
- n_dest = `dest_none;
- end
-
- `SEI_IMP:
- begin
- n_length = 2'b01;
- n_implied = 1'b1;
- n_alu_status_update = `alu_status_update_wr;
- n_brn_value = 8'h04;
- n_brn_enable = 8'h04;
- n_dest = `dest_none;
- end
-
- `TAX_IMP:
- begin
- n_length = 2'b01;
- n_implied = 1'b1;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_x;
- end
-
- `TAY_IMP:
- begin
- n_length = 2'b01;
- n_implied = 1'b1;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_y;
- end
-
- `TXA_IMP:
- begin
- n_length = 2'b01;
- n_implied = 1'b1;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_x;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
- `TYA_IMP:
- begin
- n_length = 2'b01;
- n_implied = 1'b1;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_y;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
-
- `NOP_IMP:
- begin
- n_length = 2'b01;
- n_implied = 1'b1;
- n_dest = `dest_none;
- end
-
- `ASL_ACC:
- begin
- n_length = 2'b01;
- n_implied = 1'b1;
- n_alu_mode = `alu_mode_sfl;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_alu_a;
- end
-
- `LSR_ACC:
- begin
- n_length = 2'b01;
- n_implied = 1'b1;
- n_alu_mode = `alu_mode_sfr;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_alu_a;
- end
-
-
- `ROL_ACC:
- begin
- n_length = 2'b01;
- n_implied = 1'b1;
- n_alu_mode = `alu_mode_sfl;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_cin;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_alu_a;
- end
-
- `ROR_ACC:
- begin
- n_length = 2'b01;
- n_implied = 1'b1;
- n_alu_mode = `alu_mode_sfr;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_cin;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_alu_a;
- end
-
-// immediate
-
- `ADC_IMM:
- begin
- n_length = 2'b10;
- n_immediate = 1'b1;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_imm;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_cin;
- n_alu_status_update = `alu_status_update_nzcv;
- n_dest = `dest_alu_a;
- end
-
- `AND_IMM:
- begin
- n_length = 2'b10;
- n_immediate = 1'b1;
- n_alu_mode = `alu_mode_and;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_imm;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
- `CMP_IMM:
- begin
- n_length = 2'b10;
- n_immediate = 1'b1;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_imm;
- n_alu_op_b_inv = 1'b1;
- n_alu_op_c_sel = `alu_op_c_01;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_none;
- end
-
- `CPX_IMM:
- begin
- n_length = 2'b10;
- n_immediate = 1'b1;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_x;
- n_alu_op_b_sel = `alu_op_b_imm;
- n_alu_op_b_inv = 1'b1;
- n_alu_op_c_sel = `alu_op_c_01;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_none;
- end
-
- `CPY_IMM:
- begin
- n_length = 2'b10;
- n_immediate = 1'b1;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_y;
- n_alu_op_b_sel = `alu_op_b_imm;
- n_alu_op_b_inv = 1'b1;
- n_alu_op_c_sel = `alu_op_c_01;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_none;
- end
-
- `EOR_IMM:
- begin
- n_length = 2'b10;
- n_immediate = 1'b1;
- n_alu_mode = `alu_mode_eor;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_imm;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
- `LDA_IMM:
- begin
- n_length = 2'b10;
- n_immediate = 1'b1;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_imm;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
- `LDX_IMM:
- begin
- n_length = 2'b10;
- n_immediate = 1'b1;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_imm;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_x;
- end
-
- `LDY_IMM:
- begin
- n_length = 2'b10;
- n_immediate = 1'b1;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_imm;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_y;
- end
-
- `ORA_IMM:
- begin
- n_length = 2'b10;
- n_immediate = 1'b1;
- n_alu_mode = `alu_mode_orr;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_imm;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
- `SBC_IMM:
- begin
- n_length = 2'b10;
- n_immediate = 1'b1;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_imm;
- n_alu_op_b_inv = 1'b1;
- n_alu_op_c_sel = `alu_op_c_cin;
- n_alu_status_update = `alu_status_update_nzcv;
- n_dest = `dest_alu_a;
- end
-
-// zero_page
-
-
- `ADC_ZPG:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_cin;
- n_alu_status_update = `alu_status_update_nzcv;
- n_dest = `dest_alu_a;
- end
-
-
- `AND_ZPG:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_and;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
-
- `ASL_ZPG:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_ins_type = `ins_type_rmw;
- n_alu_mode = `alu_mode_sfl;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_mem;
- end
-
-
- `BIT_ZPG:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_and;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_z67;
- n_dest = `dest_mem;
- end
-
-
- `CMP_ZPG:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b1;
- n_alu_op_c_sel = `alu_op_c_01;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_mem;
- end
-
-
- `CPX_ZPG:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_x;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b1;
- n_alu_op_c_sel = `alu_op_c_01;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_mem;
- end
-
-
- `CPY_ZPG:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_y;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b1;
- n_alu_op_c_sel = `alu_op_c_01;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_mem;
- end
-
-
- `DEC_ZPG:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_ins_type = `ins_type_rmw;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_ff;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_mem;
- end
-
-
- `EOR_ZPG:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_eor;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_mem;
- end
-
-
- `INC_ZPG:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_ins_type = `ins_type_rmw;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_01;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_mem;
- end
-
-
- `LDA_ZPG:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
-
- `LDX_ZPG:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_x;
- end
-
-
- `LDY_ZPG:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_y;
- end
-
-
- `LSR_ZPG:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_ins_type = `ins_type_rmw;
- n_alu_mode = `alu_mode_sfr;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_mem;
- end
-
-
- `ORA_ZPG:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_orr;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_mem;
- end
-
-
- `ROL_ZPG:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_ins_type = `ins_type_rmw;
- n_alu_mode = `alu_mode_sfl;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_cin;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_mem;
- end
-
-
- `ROR_ZPG:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_ins_type = `ins_type_rmw;
- n_alu_mode = `alu_mode_sfr;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_cin;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_mem;
- end
-
-
- `SBC_ZPG:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b1;
- n_alu_op_c_sel = `alu_op_c_cin;
- n_alu_status_update = `alu_status_update_nzcv;
- n_dest = `dest_mem;
- end
-
-
- `STA_ZPG:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_ins_type = `ins_type_write;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_none;
- n_dest = `dest_mem;
- end
-
-
- `STX_ZPG:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_x;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_none;
- n_dest = `dest_mem;
- end
-
-
- `STY_ZPG:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_ins_type = `ins_type_write;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_y;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_none;
- n_dest = `dest_mem;
- end
-
-// zero_page_indexed
-
-
- `ADC_ZPX:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_cin;
- n_alu_status_update = `alu_status_update_nzcv;
- n_dest = `dest_alu_a;
- end
-
- `AND_ZPX:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_and;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
- `ASL_ZPX:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_rmw;
- n_alu_mode = `alu_mode_sfl;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_mem;
- end
-
- `CMP_ZPX:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b1;
- n_alu_op_c_sel = `alu_op_c_01;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_none;
- end
-
- `DEC_ZPX:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_rmw;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_ff;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_mem;
- end
-
- `EOR_ZPX:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_eor;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_mem;
- end
-
- `INC_ZPX:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_rmw;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_01;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_mem;
- end
-
- `LDA_ZPX:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_rmw;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
- `LDY_ZPX:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_y;
- end
-
- `LSR_ZPX:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_rmw;
- n_alu_mode = `alu_mode_sfr;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_mem;
- end
-
- `ORA_ZPX:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_orr;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_mem;
- end
-
- `ROL_ZPX:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_rmw;
- n_alu_mode = `alu_mode_sfl;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_cin;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_mem;
- end
-
- `ROR_ZPX:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_rmw;
- n_alu_mode = `alu_mode_sfr;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_cin;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_mem;
- end
-
- `SBC_ZPX:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b1;
- n_alu_op_c_sel = `alu_op_c_cin;
- n_alu_status_update = `alu_status_update_nzcv;
- n_dest = `dest_mem;
- end
-
- `STA_ZPX:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_write;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_none;
- n_dest = `dest_mem;
- end
-
- `STY_ZPX:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_write;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_y;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_none;
- n_dest = `dest_mem;
- end
-
-
- `LDX_ZPY:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_idx_sel = `idx_sel_y;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_x;
- end
-
- `STX_ZPY:
- begin
- n_length = 2'b10;
- n_zero_page = 1'b1;
- n_idx_sel = `idx_sel_y;
- n_ins_type = `ins_type_write;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_x;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_none;
- n_dest = `dest_mem;
- end
-
-// Branch
-
- `BCC_REL:
- begin
- n_length = 2'b10;
- n_relative = 1'b1;
- n_ctrl = `ctrl_branch;
- n_brn_enable[`C] = 1'b1;
- n_brn_value[`C] = 1'b0;
- n_dest = `dest_none;
- end
-
-
-
- `BCS_REL:
- begin
- n_length = 2'b10;
- n_relative = 1'b1;
- n_ctrl = `ctrl_branch;
- n_brn_enable[`C] = 1'b1;
- n_brn_value[`C] = 1'b1;
- n_dest = `dest_none;
- end
-
-
- `BNE_REL:
- begin
- n_length = 2'b10;
- n_relative = 1'b1;
- n_ctrl = `ctrl_branch;
- n_brn_enable[`Z] = 1'b1;
- n_brn_value[`Z] = 1'b0;
- n_dest = `dest_none;
- end
-
-
-
- `BEQ_REL:
- begin
- n_length = 2'b10;
- n_relative = 1'b1;
- n_ctrl = `ctrl_branch;
- n_brn_enable[`Z] = 1'b1;
- n_brn_value[`Z] = 1'b1;
- n_dest = `dest_none;
- end
-
-
-
-
-
-
-
- `BPL_REL:
- begin
- n_length = 2'b10;
- n_relative = 1'b1;
- n_ctrl = `ctrl_branch;
- n_brn_enable[`N] = 1'b1;
- n_brn_value[`N] = 1'b0;
- n_dest = `dest_none;
- end
-
-
-
- `BMI_REL:
- begin
- n_length = 2'b10;
- n_relative = 1'b1;
- n_ctrl = `ctrl_branch;
- n_brn_enable[`N] = 1'b1;
- n_brn_value[`N] = 1'b1;
- n_dest = `dest_none;
- end
-
-
-
- `BVC_REL:
- begin
- n_length = 2'b10;
- n_relative = 1'b1;
- n_ctrl = `ctrl_branch;
- n_brn_enable[`V] = 1'b1;
- n_brn_value[`V] = 1'b0;
- n_dest = `dest_none;
- end
-
-
-
- `BVS_REL:
- begin
- n_length = 2'b10;
- n_relative = 1'b1;
- n_ctrl = `ctrl_branch;
- n_brn_enable[`V] = 1'b1;
- n_brn_value[`V] = 1'b1;
- n_dest = `dest_none;
- end
-
-// absolute
-
- `ADC_ABS:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_cin;
- n_alu_status_update = `alu_status_update_nzcv;
- n_dest = `dest_alu_a;
- end
-
- `AND_ABS:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_and;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
- `ASL_ABS:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_ins_type = `ins_type_rmw;
- n_alu_mode = `alu_mode_sfl;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_mem;
- end
-
- `BIT_ABS:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_and;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_z67;
- n_dest = `dest_none;
- end
-
- `CMP_ABS:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b1;
- n_alu_op_c_sel = `alu_op_c_01;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_none;
- end
-
- `CPX_ABS:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_x;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b1;
- n_alu_op_c_sel = `alu_op_c_01;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_none;
- end
-
- `CPY_ABS:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_y;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b1;
- n_alu_op_c_sel = `alu_op_c_01;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_none;
- end
-
- `DEC_ABS:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_ins_type = `ins_type_rmw;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_ff;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_mem;
- end
-
- `EOR_ABS:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_eor;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
- `INC_ABS:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_ins_type = `ins_type_rmw;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_01;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_mem;
- end
-
- `LDA_ABS:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
- `LDX_ABS:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_x;
- end
-
- `LDY_ABS:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_y;
- end
-
- `LSR_ABS:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_ins_type = `ins_type_rmw;
- n_alu_mode = `alu_mode_sfr;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_mem;
- end
-
- `ORA_ABS:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_orr;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
- `ROL_ABS:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_ins_type = `ins_type_rmw;
- n_alu_mode = `alu_mode_sfl;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_cin;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_mem;
- end
-
- `ROR_ABS:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_ins_type = `ins_type_rmw;
- n_alu_mode = `alu_mode_sfr;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_cin;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_mem;
- end
-
- `SBC_ABS:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b1;
- n_alu_op_c_sel = `alu_op_c_cin;
- n_alu_status_update = `alu_status_update_nzcv;
- n_dest = `dest_alu_a;
- end
-
- `STA_ABS:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_ins_type = `ins_type_write;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_none;
- n_dest = `dest_mem;
- end
-
- `STX_ABS:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_ins_type = `ins_type_write;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_x;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_none;
- n_dest = `dest_mem;
- end
-
- `STY_ABS:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_ins_type = `ins_type_write;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_y;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_none;
- n_dest = `dest_mem;
- end
-
-// absolute_indexed
-
- `ADC_ABX:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_cin;
- n_alu_status_update = `alu_status_update_nzcv;
- n_dest = `dest_alu_a;
- end
-
- `AND_ABX:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_and;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
- `ASL_ABX:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_rmw;
- n_alu_mode = `alu_mode_sfl;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_mem;
- end
-
- `CMP_ABX:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b1;
- n_alu_op_c_sel = `alu_op_c_01;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_none;
- end
-
- `DEC_ABX:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_rmw;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_ff;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_mem;
- end
-
- `EOR_ABX:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_eor;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
- `INC_ABX:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_rmw;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_01;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_mem;
- end
-
- `LDA_ABX:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
- `LDY_ABX:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_y;
- end
-
- `LSR_ABX:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_rmw;
- n_alu_mode = `alu_mode_sfr;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_mem;
- end
-
- `ORA_ABX:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_orr;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_mem;
- end
-
- `ROL_ABX:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_rmw;
- n_alu_mode = `alu_mode_sfl;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_cin;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_mem;
- end
-
- `ROR_ABX:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_rmw;
- n_alu_mode = `alu_mode_sfr;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_cin;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_mem;
- end
-
- `SBC_ABX:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b1;
- n_alu_op_c_sel = `alu_op_c_cin;
- n_alu_status_update = `alu_status_update_nzcv;
- n_dest = `dest_alu_a;
- end
-
- `STA_ABX:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_write;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_none;
- n_dest = `dest_mem;
- end
-
- `ADC_ABY:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_idx_sel = `idx_sel_y;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_cin;
- n_alu_status_update = `alu_status_update_nzcv;
- n_dest = `dest_alu_a;
- end
-
-
- `AND_ABY:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_idx_sel = `idx_sel_y;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_and;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
-
- `CMP_ABY:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_idx_sel = `idx_sel_y;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b1;
- n_alu_op_c_sel = `alu_op_c_01;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_none;
- end
-
-
- `EOR_ABY:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_idx_sel = `idx_sel_y;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_eor;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
-
- `LDA_ABY:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_idx_sel = `idx_sel_y;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
-
- `LDX_ABY:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_idx_sel = `idx_sel_y;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_x;
- end
-
-
- `ORA_ABY:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_idx_sel = `idx_sel_y;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_orr;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
-
- `SBC_ABY:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_idx_sel = `idx_sel_y;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b1;
- n_alu_op_c_sel = `alu_op_c_cin;
- n_alu_status_update = `alu_status_update_nzcv;
- n_dest = `dest_alu_a;
- end
-
-
- `STA_ABY:
- begin
- n_length = 2'b11;
- n_absolute = 1'b1;
- n_idx_sel = `idx_sel_y;
- n_ins_type = `ins_type_write;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_none;
- n_dest = `dest_mem;
- end
-// indirectx
-
- `ADC_IDX:
- begin
- n_length = 2'b10;
- n_indirectx = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_cin;
- n_alu_status_update = `alu_status_update_nzcv;
- n_dest = `dest_alu_a;
- end
-
- `AND_IDX:
- begin
- n_length = 2'b10;
- n_indirectx = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_and;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
- `CMP_IDX:
- begin
- n_length = 2'b10;
- n_indirectx = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b1;
- n_alu_op_c_sel = `alu_op_c_01;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_none;
- end
-
- `EOR_IDX:
- begin
- n_length = 2'b10;
- n_indirectx = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_eor;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
- `LDA_IDX:
- begin
- n_length = 2'b10;
- n_indirectx = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
- `ORA_IDX:
- begin
- n_length = 2'b10;
- n_indirectx = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_orr;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
- `SBC_IDX:
- begin
- n_length = 2'b10;
- n_indirectx = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b1;
- n_alu_op_c_sel = `alu_op_c_cin;
- n_alu_status_update = `alu_status_update_nzcv;
- n_dest = `dest_alu_a;
- end
-
- `STA_IDX:
- begin
- n_length = 2'b10;
- n_indirectx = 1'b1;
- n_idx_sel = `idx_sel_x;
- n_ins_type = `ins_type_write;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_none;
- n_dest = `dest_mem;
- end
-
-// indirecty
-
- `ADC_IDY:
- begin
- n_length = 2'b10;
- n_indirecty = 1'b1;
- n_idx_sel = `idx_sel_y;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_cin;
- n_alu_status_update = `alu_status_update_nzcv;
- n_dest = `dest_alu_a;
- end
-
- `AND_IDY:
- begin
- n_length = 2'b10;
- n_indirecty = 1'b1;
- n_idx_sel = `idx_sel_y;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_and;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
- `CMP_IDY:
- begin
- n_length = 2'b10;
- n_indirecty = 1'b1;
- n_idx_sel = `idx_sel_y;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b1;
- n_alu_op_c_sel = `alu_op_c_01;
- n_alu_status_update = `alu_status_update_nzc;
- n_dest = `dest_none;
- end
-
- `EOR_IDY:
- begin
- n_length = 2'b10;
- n_indirecty = 1'b1;
- n_idx_sel = `idx_sel_y;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_eor;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
- `LDA_IDY:
- begin
- n_length = 2'b10;
- n_indirecty = 1'b1;
- n_idx_sel = `idx_sel_y;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
- `ORA_IDY:
- begin
- n_length = 2'b10;
- n_indirecty = 1'b1;
- n_idx_sel = `idx_sel_y;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_orr;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
- `SBC_IDY:
- begin
- n_length = 2'b10;
- n_indirecty = 1'b1;
- n_idx_sel = `idx_sel_y;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b1;
- n_alu_op_c_sel = `alu_op_c_cin;
- n_alu_status_update = `alu_status_update_nzcv;
- n_dest = `dest_alu_a;
- end
-
- `STA_IDY:
- begin
- n_length = 2'b10;
- n_indirecty = 1'b1;
- n_idx_sel = `idx_sel_y;
- n_ins_type = `ins_type_write;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_none;
- n_dest = `dest_mem;
- end
-
-
-
-// stack
-
-
-
- `PHA_IMP:
- begin
- n_length = 2'b01;
- n_stack = 1'b1;
- n_ins_type = `ins_type_write;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_acc;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_none;
- n_dest = `dest_none;
- end
-
- `PHP_IMP:
- begin
- n_length = 2'b01;
- n_stack = 1'b1;
- n_ins_type = `ins_type_write;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_psr;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_none;
- n_dest = `dest_mem;
- end
-
- `PLA_IMP:
- begin
- n_length = 2'b01;
- n_stack = 1'b1;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_stk;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_nz;
- n_dest = `dest_alu_a;
- end
-
- `PLP_IMP:
- begin
- n_length = 2'b01;
- n_stack = 1'b1;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_stk;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_res;
- n_dest = `dest_none;
- end
-
-
-
-// jump
-
- `JMP_ABS:
- begin
- n_length = 2'b11;
- n_jump = 1'b1;
- n_ctrl = `ctrl_jmp;
- end
-
-// jump_indirect
- `JMP_IND:
- begin
- n_length = 2'b11;
- n_jump_indirect = 1'b1;
- n_ctrl = `ctrl_jmp_ind;
- end
-
-// jump_subroutine
-
- `JSR_ABS:
- begin
- n_length = 2'b11;
- n_jsr = 1'b1;
- n_ctrl = `ctrl_jsr;
- end
-
-
-// break
-// ?????????? Need to update alu_status at the end of this instruction
-
- `BRK_IMP:
- begin
- n_length = 2'b01;
- n_brk = 1'b1;
- n_ctrl = `ctrl_brk;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_psr;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_wr;
- n_brn_value = 8'h10; // BRK bit in psr
- n_brn_enable = 8'h10;
- n_dest = `dest_none;
- end
-
-
-// return for int
-
- `RTI_IMP:
- begin
- n_length = 2'b01;
- n_rti = 1'b1;
- n_ctrl = `ctrl_rti;
- n_ins_type = `ins_type_read;
- n_alu_mode = `alu_mode_add;
- n_alu_op_a_sel = `alu_op_a_00;
- n_alu_op_b_sel = `alu_op_b_opnd;
- n_alu_op_b_inv = 1'b0;
- n_alu_op_c_sel = `alu_op_c_00;
- n_alu_status_update = `alu_status_update_res;
- n_dest = `dest_none;
- end
-
-// return from sub
-
- `RTS_IMP:
- begin
- n_length = 2'b01;
- n_rts = 1'b1;
- n_ctrl = `ctrl_rts;
- end
-
-
-
-
- default:
- begin
- n_invalid = 1'b1;
- n_ins_type = `ins_type_none;
- end
-
- endcase
-
- end // always @ (*)
-
-
-
-
-
-
-endmodule
-
-
-
Index: socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/rtl/variants/T6502_inst_decode/defines.v
===================================================================
--- socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/rtl/variants/T6502_inst_decode/defines.v (revision 74)
+++ socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/rtl/variants/T6502_inst_decode/defines.v (nonexistent)
@@ -1,338 +0,0 @@
-
-
-`define RESET 4'b0000
-`define HALT 4'b0001
-
-`define AXE_1 4'b0011
-`define FETCH_OP 4'b0100
-`define EXECUTE 4'b0101
-`define EXE_1 4'b0110
-`define AXE_2 4'b0111
-`define IDX_1 4'b1000
-`define IDX_2 4'b1001
-`define IDX_3 4'b1010
-`define IDY_1 4'b1011
-`define IDY_2 4'b1100
-`define IDY_3 4'b1101
-`define INT_1 4'b1110
-`define INT_2 4'b1111
-
-
-
-
-
-
-
-// alu_mode
-`define alu_mode_add 3'b000
-`define alu_mode_and 3'b001
-`define alu_mode_orr 3'b010
-`define alu_mode_eor 3'b011
-`define alu_mode_sfl 3'b100
-`define alu_mode_sfr 3'b101
-`define alu_mode_afl 3'b110
-`define alu_mode_afr 3'b111
-
-// alu_op_a_sel
-
-`define alu_op_a_00 3'b000
-`define alu_op_a_acc 3'b001
-`define alu_op_a_x 3'b010
-`define alu_op_a_y 3'b011
-`define alu_op_a_ff 3'b100
-`define alu_op_a_psr 3'b101
-
-// alu_op_b_sel
-
-`define alu_op_b_00 2'b00
-`define alu_op_b_imm 2'b01
-`define alu_op_b_stk 2'b10
-`define alu_op_b_opnd 2'b11
-
-// alu_op_b_inv
-
-
-
-// alu_op_c_sel
-
-`define alu_op_c_00 2'b00
-`define alu_op_c_01 2'b01
-`define alu_op_c_cin 2'b10
-`define alu_op_c_xx 2'b11
-
-
-// alu_status_update
-`define alu_status_update_none 5'b00000
-`define alu_status_update_nz 5'b00001
-`define alu_status_update_nzc 5'b00011
-`define alu_status_update_nzcv 5'b00111
-`define alu_status_update_wr 5'b01000
-`define alu_status_update_z67 5'b10000
-`define alu_status_update_res 5'b11000
-
-
-
-// dest
-`define dest_none 3'b000
-`define dest_alu_a 3'b001
-`define dest_alu_x 3'b010
-`define dest_alu_y 3'b011
-`define dest_mem 3'b100
-
-
-// ctrl
-`define ctrl_none 3'b000
-`define ctrl_jsr 3'b001
-`define ctrl_jmp 3'b010
-`define ctrl_jmp_ind 3'b011
-`define ctrl_brk 3'b100
-`define ctrl_rti 3'b101
-`define ctrl_rts 3'b110
-`define ctrl_branch 3'b111
-
-// cmd
-`define cmd_none 2'b00
-`define cmd_run 2'b01
-`define cmd_load_add 2'b10
-`define cmd_load_vec 2'b11
-
-
-// ins_type
-`define ins_type_none 2'b00
-`define ins_type_read 2'b01
-`define ins_type_write 2'b10
-`define ins_type_rmw 2'b11
-
-
-// idx_sel
-`define idx_sel_00 2'b00
-`define idx_sel_x 2'b01
-`define idx_sel_y 2'b10
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////
-//// ////
-//// Processor Status Register ////
-//// ////
-////////////////////////////////////////////////////////////////////////////
-//// ////
-//// C - Carry Flag ////
-//// Z - Zero Flag ////
-//// I - Interrupt Disable ////
-//// D - Decimal Mode ////
-//// B - Break Command ////
-//// 1 - Constant One ////
-//// V - oVerflow Flag ////
-//// N - Negative Flag ////
-//// ////
-////////////////////////////////////////////////////////////////////////////
-//// ////
-//// ------------------------------------------------- ////
-//// | N | V | 1 | B | D | I | Z | C | ////
-//// ------------------------------------------------- ////
-//// ////
-////////////////////////////////////////////////////////////////////////////
-
-`define C 3'b000
-`define Z 3'b001
-`define I 3'b010
-`define D 3'b011
-`define B 3'b100
-`define V 3'b110
-`define N 3'b111
-
-
-
-`define ADC_IMM 8'h69
-`define ADC_ZPG 8'h65
-`define ADC_ZPX 8'h75
-`define ADC_ABS 8'h6D
-`define ADC_ABX 8'h7D
-`define ADC_ABY 8'h79
-`define ADC_IDX 8'h61
-`define ADC_IDY 8'h71
-
-`define AND_IMM 8'h29
-`define AND_ZPG 8'h25
-`define AND_ZPX 8'h35
-`define AND_ABS 8'h2D
-`define AND_ABX 8'h3D
-`define AND_ABY 8'h39
-`define AND_IDX 8'h21
-`define AND_IDY 8'h31
-
-`define ASL_ACC 8'h0A
-`define ASL_ZPG 8'h06
-`define ASL_ZPX 8'h16
-`define ASL_ABS 8'h0E
-`define ASL_ABX 8'h1E
-
-
-`define BCC_REL 8'h90
-`define BCS_REL 8'hB0
-`define BEQ_REL 8'hF0
-`define BMI_REL 8'h30
-`define BNE_REL 8'hD0
-`define BPL_REL 8'h10
-`define BVC_REL 8'h50
-`define BVS_REL 8'h70
-
-
-`define BIT_ZPG 8'h24
-`define BIT_ABS 8'h2C
-
-`define BRK_IMP 8'h00
-
-
-`define CLC_IMP 8'h18
-`define CLD_IMP 8'hD8
-`define CLI_IMP 8'h58
-`define CLV_IMP 8'hB8
-
-`define CMP_IMM 8'hC9
-`define CMP_ZPG 8'hC5
-`define CMP_ZPX 8'hD5
-`define CMP_ABS 8'hCD
-`define CMP_ABX 8'hDD
-`define CMP_ABY 8'hD9
-`define CMP_IDX 8'hC1
-`define CMP_IDY 8'hD1
-
-`define CPX_IMM 8'hE0
-`define CPX_ZPG 8'hE4
-`define CPX_ABS 8'hEC
-
-`define CPY_IMM 8'hC0
-`define CPY_ZPG 8'hC4
-`define CPY_ABS 8'hCC
-
-`define DEC_ZPG 8'hC6
-`define DEC_ZPX 8'hD6
-`define DEC_ABS 8'hCE
-`define DEC_ABX 8'hDE
-
-`define DEX_IMP 8'hCA
-
-`define DEY_IMP 8'h88
-
-`define EOR_IMM 8'h49
-`define EOR_ZPG 8'h45
-`define EOR_ZPX 8'h55
-`define EOR_ABS 8'h4D
-`define EOR_ABX 8'h5D
-`define EOR_ABY 8'h59
-`define EOR_IDX 8'h41
-`define EOR_IDY 8'h51
-
-`define INC_ZPG 8'hE6
-`define INC_ZPX 8'hF6
-`define INC_ABS 8'hEE
-`define INC_ABX 8'hFE
-
-`define INX_IMP 8'hE8
-
-`define INY_IMP 8'hC8
-
-`define JMP_ABS 8'h4C
-`define JMP_IND 8'h6C
-
-`define JSR_ABS 8'h20
-
-`define LDA_IMM 8'hA9
-`define LDA_ZPG 8'hA5
-`define LDA_ZPX 8'hB5
-`define LDA_ABS 8'hAD
-`define LDA_ABX 8'hBD
-`define LDA_ABY 8'hB9
-`define LDA_IDX 8'hA1
-`define LDA_IDY 8'hB1
-
-`define LDX_IMM 8'hA2
-`define LDX_ZPG 8'hA6
-`define LDX_ZPY 8'hB6
-`define LDX_ABS 8'hAE
-`define LDX_ABY 8'hBE
-
-`define LDY_IMM 8'hA0
-`define LDY_ZPG 8'hA4
-`define LDY_ZPX 8'hB4
-`define LDY_ABS 8'hAC
-`define LDY_ABX 8'hBC
-
-`define LSR_ACC 8'h4A
-`define LSR_ZPG 8'h46
-`define LSR_ZPX 8'h56
-`define LSR_ABS 8'h4E
-`define LSR_ABX 8'h5E
-
-`define NOP_IMP 8'hEA
-
-`define ORA_IMM 8'h09
-`define ORA_ZPG 8'h05
-`define ORA_ZPX 8'h15
-`define ORA_ABS 8'h0D
-`define ORA_ABX 8'h1D
-`define ORA_ABY 8'h19
-`define ORA_IDX 8'h01
-`define ORA_IDY 8'h11
-
-`define PHA_IMP 8'h48
-`define PHP_IMP 8'h08
-`define PLA_IMP 8'h68
-`define PLP_IMP 8'h28
-
-
-`define ROL_ACC 8'h2A
-`define ROL_ZPG 8'h26
-`define ROL_ZPX 8'h36
-`define ROL_ABS 8'h2E
-`define ROL_ABX 8'h3E
-
-`define ROR_ACC 8'h6A
-`define ROR_ZPG 8'h66
-`define ROR_ZPX 8'h76
-`define ROR_ABS 8'h6E
-`define ROR_ABX 8'h7E
-
-`define RTI_IMP 8'h40
-
-`define RTS_IMP 8'h60
-
-`define SBC_IMM 8'hE9
-`define SBC_ZPG 8'hE5
-`define SBC_ZPX 8'hF5
-`define SBC_ABS 8'hED
-`define SBC_ABX 8'hFD
-`define SBC_ABY 8'hF9
-`define SBC_IDX 8'hE1
-`define SBC_IDY 8'hF1
-
-`define SEC_IMP 8'h38
-`define SED_IMP 8'hF8
-`define SEI_IMP 8'h78
-
-`define STA_ZPG 8'h85
-`define STA_ZPX 8'h95
-`define STA_ABS 8'h8D
-`define STA_ABX 8'h9D
-`define STA_ABY 8'h99
-`define STA_IDX 8'h81
-`define STA_IDY 8'h91
-
-`define STX_ZPG 8'h86
-`define STX_ZPY 8'h96
-`define STX_ABS 8'h8E
-
-`define STY_ZPG 8'h84
-`define STY_ZPX 8'h94
-`define STY_ABS 8'h8C
-
-`define TAX_IMP 8'hAA
-`define TAY_IMP 8'hA8
-`define TXA_IMP 8'h8A
-`define TYA_IMP 8'h98
-
-
Index: socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/rtl/xml/T6502_inst_decode.xml
===================================================================
--- socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/rtl/xml/T6502_inst_decode.xml (revision 74)
+++ socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/rtl/xml/T6502_inst_decode.xml (nonexistent)
@@ -1,287 +0,0 @@
-
-
-
- T6502_inst_decode
- T6502_inst_decode
-
-
-
-
-
- STATE_SIZE
- 3
-
-
-
-
-
-
-
- input
- wire
- clk
-
-
- input
- wire
- reset
-
-
-
- input
- wire
- enable
-
-
-
- input
- wire
- [STATE_SIZE:0]
- state
-
-
-
-
- input
- wire
- [7:0]
- prog_data
-
-
-
-
- input
- wire
- disable_ir
-
-
-
- input
- wire
- fetch_op
-
-
-
-
-
-
- output
- reg
- [7:0]
- ir
-
-
-
- output
- reg
- [1:0]
- length
-
-
-
-
- output
- reg
- now_fetch_op
-
-
-
- output
- reg
- immediate
-
-
-
-
- output
- reg
- absolute
-
-
-
-
- output
- reg
- zero_page
-
-
-
-
- output
- reg
- indirectx
-
-
-
-
- output
- reg
- indirecty
-
-
-
-
- output
- reg
- implied
-
-
-
-
- output
- reg
- relative
-
-
-
- output
- reg
- stack
-
-
-
-
- output
- reg
- jsr
-
-
-
- output
- reg
- jump
-
-
-
- output
- reg
- jump_indirect
-
-
-
- output
- reg
- brk
-
-
-
- output
- reg
- rti
-
-
-
- output
- reg
- rts
-
-
-
-
- output
- reg
- invalid
-
-
-
-
-
- output
- reg
- [1:0]
- ins_type
-
-
-
-
- output
- reg
- [2:0]
- ctrl
-
-
-
- output
- reg
- [:0]
-
-
-
- output
- reg
- [2:0]
- dest
-
-
- output
- reg
- [2:0]
- alu_op_a_sel
-
-
- output
- reg
- [1:0]
- alu_op_b_sel
-
-
-
- output
- reg
- alu_op_b_inv
-
-
-
- output
- reg
- [1:0]
- alu_op_c_sel
-
-
-
- output
- reg
- [1:0]
- idx_sel
-
-
-
- output
- reg
- [2:0]
- alu_mode
-
-
-
-
- output
- reg
- [4:0]
- alu_status_update
-
-
-
-
- output
- reg
- [7:0]
- brn_value
-
-
-
-
- output
- reg
- [7:0]
- brn_enable
-
-
-
-
-
-
-
-
-
-
Index: socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/doc/Readme.txt
===================================================================
--- socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/doc/Readme.txt (revision 74)
+++ socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/doc/Readme.txt (nonexistent)
@@ -1,57 +0,0 @@
-
-
-
-
-This component comes from the opencores t6507lp project and makes it socgen compatible. The original project checked in by Gabriel Oshiro Zardo and Samuel Nascimento Pagliarini was a atari 2600 on a chip. This project only takes the t6507 processor and uses it as a 6502. It had some documentation and a test suite that was somewhat working.
-
-I chose it because a 6502 is a useful module and had clean partitioning. The following changes were made:
-
-
-
-1) Converted to a full 16 bit address bus.
-
- also hardcoded the 8 bit data bus. Hasn't changed in thirty five years.
-
-2) Converted parameters to `defines
-
-3) Converted reset to synchronous active high
-
-4) Converted test suite to socgen format
-
- Each test is in it's own subdirectory and any needed code is assembled and loaded into sram
-
-5) Design had no reset/interrupt vectors. Added reset vector. May add interupt(s) later.
-
-6) Added enable logic so that it could work with synchronous sram
-
-7) Design doesn't appear to be fully functional.
- CLC followed by BCC missed the offset by one clock cycle.
- JSR doesn't push high address on stack. puts wrong data in page 00
- Branch backwards doesn't work.
- read/modify/write did not work
- pha pushed onto page 0
- pha data latched one clock to late
- jmp indirect didn't work
-
-8) Split T6502_fsm into smaller blocks for ease of documenting and verifying
-
-9) Move branch decision logic into sequencer block
-
-10) removed BCD logic
-
-11) moved alu_opcode to instr_decode block
-
-12) created datapath logic for alu_operand_a, alu_operand_b and alu_operand_c
-
-13) split alu into alu_control and alu blocks
-
-14) reworked the inst_decode signals to alu and pulled datapath out of sequencer
-
-15) removed the latched alu_result. Outside of alu now uses raw
-
-
-
-
-This appears to be a work in progress with numerous issues. I fixed enough of them so that I can
-synthesize into an fpga and it runs the io_poll program on a Nexys2 Board. I will commit this as
-a start but it is alpha code and will have bugs.
Index: socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/doc/orig6502.txt
===================================================================
--- socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/doc/orig6502.txt (revision 74)
+++ socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/doc/orig6502.txt (nonexistent)
@@ -1,151 +0,0 @@
- ADC abs | 6D | ADC abs |
- ADC abs,X | 7D | ADC abs,X |
- ADC abs,Y | 79 | ADC abs,Y |
- ADC #n | 69 | ADC #n |
- ADC zp | 65 | ADC zp |
- ADC (zp,X) | 61 | ADC (zp,X) |
- ADC zp,X | 75 | ADC zp,X |
- ADC (zp),Y | 71 | ADC (zp),Y |
- AND abs | 2D | AND abs |
- AND abs,X | 3D | AND abs,X |
- AND abs,Y | 39 | AND abs,Y |
- AND #n | 29 | AND #n |
- AND zp | 25 | AND zp |
- AND (zp,X) | 21 | AND (zp,X) |
- AND zp,X | 35 | AND zp,X |
- AND (zp),Y | 31 | AND (zp),Y |
- ASL A | 0A | ASL A |
- ASL abs | 0E | ASL abs |
- ASL abs,X | 1E | ASL abs,X |
- ASL zp | 06 | ASL zp |
- ASL zp,X | 16 | ASL zp,X |
- BCC rel | 90 | BCC rel |
- BCS rel | B0 | BCS rel |
- BEQ rel | F0 | BEQ rel |
- BIT abs | 2C | BIT abs |
- BIT zp | 24 | BIT zp |
- BMI rel | 30 | BMI rel |
- BNE rel | D0 | BNE rel |
- BPL rel | 10 | BPL rel |
- BRK | 00 | BRK |
- BVC rel | 50 | BVC rel |
- BVS rel | 70 | BVS rel |
- CLC | 18 | CLC |
- CLD | D8 | CLD |
- CLI | 58 | CLI |
- CLV | B8 | CLV |
- CMP abs | CD | CMP abs |
- CMP abs,X | DD | CMP abs,X |
- CMP abs,Y | D9 | CMP abs,Y |
- CMP #n | C9 | CMP #n |
- CMP zp | C5 | CMP zp |
- CMP (zp,X) | C1 | CMP (zp,X) |
- CMP zp,X | D5 | CMP zp,X |
- CMP (zp),Y | D1 | CMP (zp),Y |
- CPX abs | EC | CPX abs |
- CPX #n | E0 | CPX #n |
- CPX zp | E4 | CPX zp |
- CPY abs | CC | CPY abs |
- CPY #n | C0 | CPY #n |
- CPY zp | C4 | CPY zp |
- DEC abs | CE | DEC abs |
- DEC abs,X | DE | DEC abs,X |
- DEC zp | C6 | DEC zp |
- DEC zp,X | D6 | DEC zp,X |
- DEX | CA | DEX |
- DEY | 88 | DEY |
- EOR abs | 4D | EOR abs |
- EOR abs,X | 5D | EOR abs,X |
- EOR abs,Y | 59 | EOR abs,Y |
- EOR #n | 49 | EOR #n |
- EOR zp | 45 | EOR zp |
- EOR (zp,X) | 41 | EOR (zp,X) |
- EOR zp,X | 55 | EOR zp,X |
- EOR (zp),Y | 51 | EOR (zp),Y |
- INC abs | EE | INC abs |
- INC abs,X | FE | INC abs,X |
- INC zp | E6 | INC zp |
- INC zp,X | F6 | INC zp,X |
- INX | E8 | INX |
- INY | C8 | INY |
- JMP abs | 4C | JMP abs |
- JMP (abs) | 6C | JMP (abs) |
- JSR abs | 20 | JSR abs |
- LDA abs | AD | LDA abs |
- LDA abs,X | BD | LDA abs,X |
- LDA abs,Y | B9 | LDA abs,Y |
- LDA #n | A9 | LDA #n |
- LDA zp | A5 | LDA zp |
- LDA (zp,X) | A1 | LDA (zp,X) |
- LDA zp,X | B5 | LDA zp,X |
- LDA (zp),Y | B1 | LDA (zp),Y |
- LDX abs | AE | LDX abs |
- LDX abs,Y | BE | LDX abs,Y |
- LDX #n | A2 | LDX #n |
- LDX zp | A6 | LDX zp |
- LDX zp,Y | B6 | LDX zp,Y |
- LDY abs | AC | LDY abs |
- LDY abs,X | BC | LDY abs,X |
- LDY #n | A0 | LDY #n |
- LDY zp | A4 | LDY zp |
- LDY zp,X | B4 | LDY zp,X |
- LSR A | 4A | LSR A |
- LSR abs | 4E | LSR abs |
- LSR abs,X | 5E | LSR abs,X |
- LSR zp | 46 | LSR zp |
- LSR zp,X | 56 | LSR zp,X |
- NOP | EA | NOP |
- ORA abs | 0D | ORA abs |
- ORA abs,X | 1D | ORA abs,X |
- ORA abs,Y | 19 | ORA abs,Y |
- ORA #n | 09 | ORA #n |
- ORA zp | 05 | ORA zp |
- ORA (zp,X) | 01 | ORA (zp,X) |
- ORA zp,X | 15 | ORA zp,X |
- ORA (zp),Y | 11 | ORA (zp),Y |
- PHA | 48 | PHA |
- PHP | 08 | PHP |
- PLA | 68 | PLA |
- PLP | 28 | PLP |
- ROL A | 2A | ROL A |
- ROL abs | 2E | ROL abs |
- ROL abs,X | 3E | ROL abs,X |
- ROL zp | 26 | ROL zp |
- ROL zp,X | 36 | ROL zp,X |
- ROR A | 6A | ROR A |
- ROR abs | 6E | ROR abs |
- ROR abs,X | 7E | ROR abs,X |
- ROR zp | 66 | ROR zp |
- ROR zp,X | 76 | ROR zp,X |
- RTI | 40 | RTI |
- RTS | 60 | RTS |
- SBC abs | ED | SBC abs |
- SBC abs,X | FD | SBC abs,X |
- SBC abs,Y | F9 | SBC abs,Y |
- SBC #n | E9 | SBC #n |
- SBC zp | E5 | SBC zp |
- SBC (zp,X) | E1 | SBC (zp,X) |
- SBC zp,X | F5 | SBC zp,X |
- SBC (zp),Y | F1 | SBC (zp),Y |
- SEC | 38 | SEC |
- SED | F8 | SED |
- SEI | 78 | SEI |
- STA abs | 8D | STA abs |
- STA abs,X | 9D | STA abs,X |
- STA abs,Y | 99 | STA abs,Y |
- STA zp | 85 | STA zp |
- STA (zp,X) | 81 | STA (zp,X) |
- STA zp,X | 95 | STA zp,X |
- STA (zp),Y | 91 | STA (zp),Y |
- STX abs | 8E | STX abs |
- STX zp | 86 | STX zp |
- STX zpy | 96 | STX zpy |
- STY abs | 8C | STY abs |
- STY zp | 84 | STY zp |
- STY zp,X | 94 | STY zp,X |
- TAX | AA | TAX |
- TAY | A8 | TAY |
- TSX | BA | TSX |
- TXA | 8A | TXA |
- TXS | 9A | TXS |
- TYA | 98 | TYA |
Index: socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/doc/copyright.v
===================================================================
--- socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/doc/copyright.v (revision 74)
+++ socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/doc/copyright.v (nonexistent)
@@ -1,80 +0,0 @@
-////////////////////////////////////////////////////////////////////
-// -------------- //
-// / SOC \ //
-// / GEN \ //
-// / COMPONENT \ //
-// ==================== //
-// |digital done right| //
-// |__________________| //
-// //
-// //
-// //
-// Copyright (C) <2010> //
-// //
-// //
-// This source file may be used and distributed without //
-// restriction provided that this copyright statement is not //
-// removed from the file and that any derivative work contains //
-// the original copyright notice and the associated disclaimer. //
-// //
-// This source file is free software; you can redistribute it //
-// and/or modify it under the terms of the GNU Lesser General //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any //
-// later version. //
-// //
-// This source is distributed in the hope that it will be //
-// useful, but WITHOUT ANY WARRANTY; without even the implied //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
-// PURPOSE. See the GNU Lesser General Public License for more //
-// details. //
-// //
-// You should have received a copy of the GNU Lesser General //
-// Public License along with this source; if not, download it //
-// from http://www.opencores.org/lgpl.shtml //
-// //
-////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////////
-//// ////
-//// T6507LP IP Core ////
-//// ////
-//// This file is part of the T6507LP project ////
-//// http://www.opencores.org/cores/t6507lp/ ////
-//// ////
-//// Description ////
-//// Implementation of a 6507-compatible microprocessor ////
-//// ////
-//// To Do: ////
-//// - Everything ////
-//// ////
-//// Author(s): ////
-//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
-//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
-//// ////
-////////////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-////////////////////////////////////////////////////////////////////////////
Index: socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/doc/spec.odt
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/doc/spec.odt
===================================================================
--- socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/doc/spec.odt (revision 74)
+++ socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/doc/spec.odt (nonexistent)
socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/doc/spec.odt
Property changes :
Deleted: svn:mime-type
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-application/octet-stream
\ No newline at end of property
Index: socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/doc/geda/drawing/filelist
===================================================================
--- socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/doc/geda/drawing/filelist (revision 74)
+++ socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/doc/geda/drawing/filelist (nonexistent)
@@ -1,14 +0,0 @@
-`include "../../../rtl/gen/syn/T6502.v"
-`include "../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module.v"
-`include "../../../../../children/logic/ip/uart/rtl/gen/syn/uart.v"
-`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/syn/ps2_interface.v"
-
-`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v"
-`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/syn/serial_rcvr.v"
-
-`include "../../../../../../../../socgen/lib/cde_sram/cde_sram.v"
-`include "../../../../../../../../socgen/lib/cde_serial_xmit/cde_serial_xmit.v"
-`include "../../../../../../../../socgen/lib/cde_serial_rcvr/cde_serial_rcvr.v"
-`include "../../../../../../../../socgen/lib/cde_synchronizers/cde_sync_with_hysteresis.v"
-`include "../../../../../../../../socgen/lib/cde_fifo/cde_fifo.v"
-`include "../../../../../../../../socgen/lib/cde_divider/cde_divider.v"
\ No newline at end of file
Index: socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/doc/T6502_doc.txt
===================================================================
--- socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/doc/T6502_doc.txt (revision 74)
+++ socgen/trunk/projects/Mos6502/ip/T6502_inst_decode/doc/T6502_doc.txt (nonexistent)
@@ -1,1689 +0,0 @@
-T6502 Embedded Microprocessor
-==================================================================================
-
-The T6502 IP is a processor that uses most of MosTechnology M6502 processor instructions
-and processor registers.It has been updated for a synthesized embedded design in a FGPA or ASIC.
-
-
-It differs from the original Mos6502 in the following ways
-
-
-
-1) Changed memory interface from asynchronous to synchronous.
-
-2) Number of clock cycles to execute instructions has changed
-
-3) Page Zero is fully filled with SRAM. Page zero is not usable as I/O space
-
-
-
-
-
-
-
-
-An extended version is also avaiable. Before we can extend we must first remove some features that either
-did not make sense at the time or made only made sense for a 40 pin part sitting in a sea or ttl parts.
-
-
-
-1) Remove Binary Coded Decimal mode. The D bit in the PSR does nothing.
-
-2) Moved stack from Page 01 into a seperate RAM. Stack size is now parameterized and only accessable via
- pushes and pulls.Removed the TSX and TXS commands. If you need to manipulate the stack pointer and stack
- data then you really should get a more powerfull processor
-
-3) Replaced old interrupt/brk system with vectored interrupt. Masking is done externally and vectors provide
- as many interrupts as you like. PSR is not pushed on interrupt and rts/rti become one instruction
-
-4) Indirect addresses stored in page 00 MUST be aligned on even addresses. This is done by shifting a
- page zero indirect address bu one bit and using both page 00 and 01.
-
-5) Bit (5) of the PSR is now a run bit. Forcing it to 0 will halt the processor until the next reset/interrupt
-
-6) Added Debugging logic and error checking
-
-7) self modifying code is no longer supported. You must provide a single rom image with all executable code
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-History
-=========================================================================================
-
-
-
-
-This component is derived from the opencores t6507lp project.
-
-The original project checked in by Gabriel Oshiro Zardo and Samuel Nascimento Pagliarini
-was a atari 2600 on a chip. This takes the t6507 portion and turns it into a fully functional updated 6502.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-Processor Model
-===============================================================================================
-
- +----------+
- | Acc | Accumulator (A)
- +----------+
- | X | X Index Register (X)
- +----------+
- | Y | Y Index Register (Y)
- +----------+----------+
- | PCH | PCL | Program Counter (PC)
- +----------+----------+
- | 00000001 | SP | Stack Pointer (SP)
- +----------+----------+
- | P | Processor Status Word (P)
- +----------+
- NV1BDIZC
- |||||||+---- Carry Flag 1 = True
- ||||||+----- Zero Flag 1 = Result == 8'h00
- |||||+------ IRQ Disable 1 = Disable
- ||||+------- Decimal Mode Not used
- |||+-------- Break Command 1 = In break routine
- ||+--------- Run Mode 1 = Processor is running
- |+---------- Overflow Flag 1 = True
- +----------- Negative 1 = Negative Number
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-Memory Model
-===============================================================================================
-
-0000-00FF | Page Zero RAM
-0010-01FF | Stack RAM
-0200-FFF9 | Program and Data RAM
- FFFA | NMI Vector Low
- FFFB | NMI Vector High
- FFFC | Boot Vector Low
- FFFD | Boot Vector High
- FFFE | IRQ/BRK Vector Low
- FFFF | IRQ/BRK Vector High
-
-
-
-
-
-
-
-
-
-Definitions
-===============================================================================================
-Opcode Current Instruction byte
-New_opcode Next Instruction byte
-Opc_Add Address of current instruction
-Next_Op_Add Address of next instruction byte
-Operand Data operand
-Address Address of data operand if in memory
-Offset Value added to Opc_Add if branch is taken
-Pointer Address to store the address of data opeand if in memory
-Vector Address to store the Next_Op_Add
-
-
-
-
-
-
-
-
-
-Instruction Set
-===============================================================================================
-
-Inst Description Effect on flags
------------------------------------------------------------------------------------------------
-ADC Operand Add Acc to Operand with Carry NZCV
-SBC Operand Subract Operand from Acc with Borrow NZXV
-AND Operand Logical AND Acc and Operand NZ
-CMP Operand Compare Acc with Operand NZC
-CPX Operand Compare X_index with Operand NZC
-CPY Operand Compare Y_index with Operand NZC
-EOR Operand Exclusive Or Acc with Operand NZ
-LDA Operand Load Operand into Acc NZ
-LDX Operand Load Operand into X_index NZ
-LDY Operand Load Operand into Y_index NZ
-ORA Operand Logical Or Acc with Operand NZ
-BIT Operand Bit Test Acc with operand Z67
-STA Address Store Acc @ address NONE
-STX Address Store X_Index @ address NONE
-STY Address Store Y_Index @ address NONE
-ASL Operand Arithmetic Shift Left Operand into Carry NZC
-DEC Operand Decrement Operand NZ
-INC Operand Incremement Operand NZ
-DEX Decrement X Index NZ
-INX Incremement X Index NZ
-DEY Decrement Y Index NZ
-INY Incremement Y Index NZ
-LSR Operand Logical Shift Right Operand into Carry NZC
-ROL Operand Rotate Left Operand thru Carry NZC
-ROR Operand Rotate Right Operand thru Carry NZC
-NOP No Operation NONE
-SEC Set Carry Flag 1 -> C
-SED Set Decimal Flag 1 -> D
-SEI Set Interrupt Flag 1 -> I
-CLC Clear Carry Flag 0 -> C
-CLD Clear Decimal Flag 0 -> D
-CLI Clear Interrupt Flag 0 -> I
-CLV Clear Overflow Flag 0 -> V
-TAX Transfer Acc into X_Index NZ
-TAY Transfer Acc into Y_Index NZ
-TXA Transfer X_Index into Acc NZ
-TYA Transfer Y_Index into Acc NZ
-BCC Offset Branch if C == 0 NONE
-BCS Offset Branch if C == 1 NONE
-BNE Offset Branch if Z == 0 NONE
-BEQ Offset Branch if Z == 1 NONE
-BVC Offset Branch if V == 0 NONE
-BVS Offset Branch if V == 1 NONE
-BPL Offset Branch if N == 0 NONE
-BMI Offset Branch if N == 1 NONE
-PLA Pull Acc from Stack NZ
-PLP Pull PSR from Stack RESTORE
-PHA Push Acc onto Stack NONE
-PHP Push PSR onto Stack NONE
-JMP Next_Op_Add Jump to New Address NONE
-JMP Vector Jump to New Address found by vector NONE
-JSR Next_Op_Add Save PC+2 on stack and jump to New Address NONE
-BRK Save status and PC+1 on stack and jump to New Address set 1 -> B
-RTI Pull Status and PC from stack RESTORED
-RTS Pull PC from stack NONE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-Definitions
-===============================================================================================
-Opcode Current Instruction byte
-New_opcode Next Instruction byte
-Opc_Add Address of current instruction
-Next_Op_Add Address of next instruction byte
-Operand Data operand
-Address Address of data operand if in memory
-Offset Value added to Opc_Add if branch is taken
-Pointer Address to store the address of data opeand if in memory
-Vector Address to store the Next_Op_Add
-
-
-
-
-
-
-
-
-
-
-Addressing Modes
-===============================================================================================
-
-
-Immediate Read
------------------------------------------------------------------------------------------------------
-Operand is located in memory following the opcode
-
-
-Opcode Operand
-
-
-
-
-Absolute Read/Write/ReadModifyWrite
------------------------------------------------------------------------------------------------------
-16 bit address of operand is located in memory following opcode (low byte,high byte)
-
-Opcode Address_l,Address_h
-
-
-
-Absolute Indexed Read/Write/ReadModifyWrite
------------------------------------------------------------------------------------------------------
-Operand is found by adding index value to 16 bit address following opcode.(no wraparound)
-
-Opcode Address_l,Address_h
-
-
-
-Page Zero Read/Write/ReadModifyWrite
------------------------------------------------------------------------------------------------------
-8 bit page zero address of operand is located in memory following opcode.
-
-
-Opcode Address_l
-
-
-
-Page Zero Indexed Read/Write/ReadModifyWrite
------------------------------------------------------------------------------------------------------
-Operand is found in page zero by adding index value to 8 bit address following opcode.(wraps around)
-
-
-Opcode Address_l
-
-
-
-Page Zero Indirect X Read/Write
------------------------------------------------------------------------------------------------------
-Operand address lower byte is read from the address found by adding X index value to 8 bit address following opcode and
-the upper byte is read from the address found by adding X index value to 8 bit address plus 1 (no wraparound)
-
-Opcode Pointer_l
-
-
-
-
-Page Zero Indirect Y Read/Write
------------------------------------------------------------------------------------------------------
-8 bit page zero address containing a 16 bit address is located in memory following opcode. Y index is added to this address
-(no wraparound).
-
-
-Opcode Pointer_l
-
-
-Implied Read/Write/Read_Modify_Write
------------------------------------------------------------------------------------------------------
-Operand is specified in the Opcode
-
-Opcode
-
-
-Branch Read
------------------------------------------------------------------------------------------------------
-Opcode is followed by the relative offset for the branch
-
-Opcode Offset
-
-
-Stack StackRead/StackWrite
------------------------------------------------------------------------------------------------------
-Operation uses the Stack
-
-Opcode
-
-
-Stack_Pointer
------------------------------------------------------------------------------------------------------
-Transfer between Stack_pointer and X index
-
-Opcode
-
-
-Jump Absolute Read
------------------------------------------------------------------------------------------------------
-16 bit destination address follows opcode
-
-
-Opcode Next_Op_add_l,Next_Op_add_h
-
-
-
-Jump Indirect Read
------------------------------------------------------------------------------------------------------
-16 bit Address following opcode points to destination address
-
-Opcode Vector_l, Vector_h
-
-
-JumpSub Absolute Read_Stackwrite
------------------------------------------------------------------------------------------------------
-16 bit destination address follows opcode. Return address is pushed on stack
-
-Opcode Next_Op_add_l,Next_Op_add_h
-
-
-Break Read_Stackwrite
------------------------------------------------------------------------------------------------------
-Return address is pushed on stack and the IRQ vector is taken
-
-Opcode
-
-
-Return from Interrupt Read_Stackread
------------------------------------------------------------------------------------------------------
-PSR and Prog_counter are pulled from stack
-
-
-Opcode
-
-
-
-
-
-Return from Subroutine Read_Stackread
------------------------------------------------------------------------------------------------------
-Prog_counter is pulled from stack
-
-
-Opcode
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-Instruction Opcodes (hex)
-====================================================================================================
-
-
-
- ADC abs 6D
- ADC abs,X 7D
- ADC abs,Y 79
- ADC #n 69
- ADC zp 65
- ADC (zp,X) 61
- ADC zp,X 75
- ADC (zp),Y 71
-
- AND abs 2D
- AND abs,X 3D
- AND abs,Y 39
- AND #n 29
- AND zp 25
- AND (zp,X) 21
- AND zp,X 35
- AND (zp),Y 31
-
- ASL A 0A
- ASL abs 0E
- ASL abs,X 1E
- ASL zp 06
- ASL zp,X 16
-
- BCC rel 90
- BCS rel B0
- BEQ rel F0
-
- BIT abs 2C
- BIT zp 24
-
- BMI rel 30
- BNE rel D0
- BPL rel 10
-
- BRK 00
-
- BVC rel 50
- BVS rel 70
-
-
- CLC 18
- CLD D8
- CLI 58
- CLV B8
-
- CMP abs CD
- CMP abs,X DD
- CMP abs,Y D9
- CMP #n C9
- CMP zp C5
- CMP (zp,X) C1
- CMP zp,X D5
- CMP (zp),Y D1
-
- CPX abs EC
- CPX #n E0
- CPX zp E4
- CPY abs CC
- CPY #n C0
- CPY zp C4
-
- DEC abs CE
- DEC abs,X DE
- DEC zp C6
- DEC zp,X D6
-
- DEX CA
- DEY 88
-
- EOR abs 4D
- EOR abs,X 5D
- EOR abs,Y 59
- EOR #n 49
- EOR zp 45
- EOR (zp,X) 41
- EOR zp,X 55
- EOR (zp),Y 51
-
- INC abs EE
- INC abs,X FE
- INC zp E6
- INC zp,X F6
- INX E8
- INY C8
-
- JMP abs 4C
- JMP (abs) 6C
- JSR abs 20
-
- LDA abs AD
- LDA abs,X BD
- LDA abs,Y B9
- LDA #n A9
- LDA zp A5
- LDA (zp,X) A1
- LDA zp,X B5
- LDA (zp),Y B1
-
- LDX abs AE
- LDX abs,Y BE
- LDX #n A2
- LDX zp A6
- LDX zp,Y B6
-
- LDY abs AC
- LDY abs,X BC
- LDY #n A0
- LDY zp A4
- LDY zp,X B4
-
- LSR A 4A
- LSR abs 4E
- LSR abs,X 5E
- LSR zp 46
- LSR zp,X 56
-
- NOP EA
-
- ORA abs 0D
- ORA abs,X 1D
- ORA abs,Y 19
- ORA #n 09
- ORA zp 05
- ORA (zp,X) 01
- ORA zp,X 15
- ORA (zp),Y 11
-
- PHA 48
- PHP 08
-
- PLA 68
- PLP 28
-
- ROL A 2A
- ROL abs 2E
- ROL abs,X 3E
- ROL zp 26
- ROL zp,X 36
-
- ROR A 6A
- ROR abs 6E
- ROR abs,X 7E
- ROR zp 66
- ROR zp,X 76
-
- RTI 40
-
- RTS 60
-
- SBC abs ED
- SBC abs,X FD
- SBC abs,Y F9
- SBC #n E9
- SBC zp E5
- SBC (zp,X) E1
- SBC zp,X F5
- SBC (zp),Y F1
-
- SEC 38
- SED F8
- SEI 78
-
- STA abs 8D
- STA abs,X 9D
- STA abs,Y 99
- STA zp 85
- STA (zp,X) 81
- STA zp,X 95
- STA (zp),Y 91
-
- STX abs 8E
- STX zp 86
- STX zpy 96
-
- STY abs 8C
- STY zp 84
- STY zp,X 94
-
- TAX AA
- TAY A8
- TXA 8A
- TYA 98
-
-
-
-
-
-
-
-
-
-Instruction Decode
-======================================================================================================================================================
-
-
-
-
-
-
-
-
-
-
-// alu_mode
-`define alu_mode_add 3'b000
-`define alu_mode_and 3'b001
-`define alu_mode_orr 3'b010
-`define alu_mode_eor 3'b011
-`define alu_mode_sfl 3'b100
-`define alu_mode_sfr 3'b101
-`define alu_mode_afl 3'b110
-`define alu_mode_afr 3'b111
-
-// alu_op_a_sel
-
-`define alu_op_a_00 3'b000
-`define alu_op_a_acc 3'b001
-`define alu_op_a_x 3'b010
-`define alu_op_a_y 3'b011
-`define alu_op_a_ff 3'b100
-`define alu_op_a_psr 3'b101
-
-// alu_op_b_sel
-
-`define alu_op_b_00 2'b00
-`define alu_op_b_prog 2'b01
-`define alu_op_b_sp 2'b10
-`define alu_op_b_temp 2'b11
-
-// alu_op_b_inv 1=invert
-
-
-
-// alu_op_c_sel
-
-`define alu_op_c_00 2'b00
-`define alu_op_c_01 2'b01
-`define alu_op_c_cin 2'b10
-`define alu_op_c_xx 2'b11
-
-
-// alu_status_update
-`define alu_status_update_none 3'b000
-`define alu_status_update_nz 3'b001
-`define alu_status_update_nzc 3'b010
-`define alu_status_update_nzcv 3'b011
-`define alu_status_update_wr 3'b100
-`define alu_status_update_z67 3'b101
-`define alu_status_update_res 3'b110
-
-
-
-// dest
-`define dest_none 3'b000
-`define dest_alu_a 3'b001
-`define dest_alu_x 3'b010
-`define dest_alu_y 3'b011
-`define dest_mem 3'b100
-
-
-// ctrl
-`define ctrl_none 3'b000
-`define ctrl_jsr 3'b001
-`define ctrl_jmp 3'b010
-`define ctrl_jmp_ind 3'b011
-`define ctrl_brk 3'b100
-`define ctrl_rti 3'b101
-`define ctrl_rts 3'b110
-`define ctrl_branch 3'b111
-
-// cmd
-`define cmd_none 2'b00
-`define cmd_push_psr 2'b01
-`define cmd_push_pc 2'b10
-`define cmd_load_vec 2'b11
-
-
-// ins_type
-`define ins_type_none 2'b00
-`define ins_type_read 2'b01
-`define ins_type_write 2'b10
-`define ins_type_rmw 2'b11
-
-
-// idx_sel
-`define idx_sel_00 2'b00
-`define idx_sel_x 2'b01
-`define idx_sel_y 2'b10
-
-
-
-// branch_value
-
-
-// branch_enable
-
-
-
-
-
-
-
-
-
-
-Immediate
-
- alu alu alu alu alu
- op_a op_b op_b op_c status alu ins idx branch branch
- src src inv src update mode type sel value enable dest ctrl cmd
-------------------------------------------------------------------------------------------------------------------------------------------------------
- ADC #n | | alu_a prog 0 cin NZCV ADD R 0 00 00 A none none
- AND #n | | alu_a prog 0 0 NZ AND R 0 00 00 A none none
- CMP #n | | alu_a prog 1 1 NZC ADD R 0 00 00 0 none none
- CPX #n | | alu_x prog 1 1 NZC ADD R 0 00 00 0 none none
- CPY #n | | alu_y prog 1 1 NZC ADD R 0 00 00 0 none none
- EOR #n | | alu_a prog 0 0 NZ EOR R 0 00 00 A none none
- LDA #n | | 00 prog 0 0 NZ ADD R 0 00 00 A none none
- LDX #n | | 00 prog 0 0 NZ ADD R 0 00 00 X none none
- LDY #n | | 00 prog 0 0 NZ ADD R 0 00 00 Y none none
- ORA #n | | alu_a prog 0 0 NZ ORR R 0 00 00 A none none
- SBC #n | | alu_a prog 1 cin NZXV ADD R 0 00 00 A none none
-
-
-
-
-Absolute
-
-------------------------------------------------------------------------------------------------------------------------------------------------------
- ADC abs | | alu_a temp 0 cin NZCV ADD R 0 00 00 A none none
- AND abs | | alu_a temp 0 0 NZ AND R 0 00 00 A none none
- BIT abs | | alu_a temp 0 0 Z67 AND R 0 00 00 0 none none
- CMP abs | | alu_a temp 1 1 NZC ADD R 0 00 00 0 none none
- CPX abs | | alu_x temp 1 1 NZC ADD R 0 00 00 0 none none
- CPY abs | | alu_y temp 1 1 NZC ADD R 0 00 00 0 none none
- EOR abs | | alu_a temp 0 0 NZ EOR R 0 00 00 A none none
- LDA abs | | 00 temp 0 0 NZ ADD R 0 00 00 A none none
- LDX abs | | 00 temp 0 0 NZ ADD R 0 00 00 X none none
- LDY abs | | 00 temp 0 0 NZ ADD R 0 00 00 Y none none
- ORA abs | | alu_a temp 0 0 NZ ORR R 0 00 00 A none none
- SBC abs | | alu_a temp 1 cin NZXV ADD R 0 00 00 A none none
- STA abs | | alu_a temp 0 0 NONE ADD W 0 00 00 M none none
- STX abs | | alu_x temp 0 0 NONE ADD W 0 00 00 M none none
- STY abs | | alu_y temp 0 0 NONE ADD W 0 00 00 M none none
- ASL abs | | 00 temp 0 0 NZC SFL RMW 0 00 00 M none none
- DEC abs | | FF temp 0 0 NZ ADD RMW 0 00 00 M none none
- INC abs | | 00 temp 0 1 NZ ADD RMW 0 00 00 M none none
- LSR abs | | 00 temp 0 0 NZC SFR RMW 0 00 00 M none none
- ROL abs | | 00 temp 0 cin NZC SFL RMW 0 00 00 M none none
- ROR abs | | 00 temp 0 cin NZC SFR RMW 0 00 00 M none none
-
-
-Absolute indexed
-
-------------------------------------------------------------------------------------------------------------------------------------------------------
- ADC abs,X | | alu_a temp 0 cin NZCV ADD R X 00 00 A none none
- AND abs,X | | alu_a temp 0 0 NZ AND R X 00 00 A none none
- CMP abs,X | | alu_a temp 1 1 NZC ADD R X 00 00 0 none none
- EOR abs,X | | alu_a temp 0 0 NZ EOR R X 00 00 A none none
- LDA abs,X | | 00 temp 0 0 NZ ADD R X 00 00 A none none
- LDY abs,X | | 00 temp 0 0 NZ ADD R X 00 00 Y none none
- ORA abs,X | | alu_a temp 0 0 NZ ORR R X 00 00 A none none
- SBC abs,X | | alu_a temp 1 cin NZXV ADD R X 00 00 A none none
- ADC abs,Y | | alu_a temp 0 cin NZCV ADD R Y 00 00 A none none
- AND abs,Y | | alu_a temp 0 0 NZ AND R Y 00 00 A none none
- CMP abs,Y | | alu_a temp 1 1 NZC ADD R Y 00 00 0 none none
- EOR abs,Y | | alu_a temp 0 0 NZ EOR R Y 00 00 A none none
- LDA abs,Y | | 00 temp 0 0 NZ ADD R Y 00 00 A none none
- LDX abs,Y | | 00 temp 0 0 NZ ADD R Y 00 00 X none none
- ORA abs,Y | | alu_a temp 0 0 NZ ORR R Y 00 00 A none none
- SBC abs,Y | | alu_a temp 1 cin NZXV ADD R Y 00 00 A none none
- STA abs,X | | alu_a temp 0 0 NONE ADD W X 00 00 M none none
- STA abs,Y | | alu_a temp 0 0 NONE ADD W Y 00 00 M none none
- ASL abs,X | | 00 temp 0 0 NZC SFL RMW X 00 00 M none none
- DEC abs,X | | FF temp 0 0 NZ ADD RMW X 00 00 M none none
- INC abs,X | | 00 temp 0 1 NZ ADD RMW X 00 00 M none none
- LSR abs,X | | 00 temp 0 0 NZC SFR RMW X 00 00 M none none
- ROL abs,X | | 00 temp 0 cin NZC SFL RMW X 00 00 M none none
- ROR abs,X | | 00 temp 0 cin NZC SFR RMW X 00 00 M none none
-
-
-
-
-
-
-Page Zero
-
-------------------------------------------------------------------------------------------------------------------------------------------------------
- ADC zp | | alu_a temp 0 cin NZCV ADD R 0 00 00 A none none
- AND zp | | alu_a temp 0 0 NZ AND R 0 00 00 A none none
- BIT zp | | alu_a temp 0 0 Z67 AND R 0 00 00 0 none none
- CMP zp | | alu_a temp 1 1 NZC ADD R 0 00 00 0 none none
- CPX zp | | alu_x temp 1 1 NZC ADD R 0 00 00 0 none none
- CPY zp | | alu_y temp 1 1 NZC ADD R 0 00 00 0 none none
- EOR zp | | alu_a temp 0 0 NZ EOR R 0 00 00 A none none
- LDA zp | | 00 temp 0 0 NZ ADD R 0 00 00 A none none
- LDX zp | | 00 temp 0 0 NZ ADD R 0 00 00 X none none
- LDY zp | | 00 temp 0 0 NZ ADD R 0 00 00 Y none none
- ORA zp | | alu_a temp 0 0 NZ ORR R 0 00 00 A none none
- SBC zp | | alu_a temp 1 cin NZXV ADD R 0 00 00 A none none
- STA zp | | alu_a temp 0 0 NONE ADD W 0 00 00 M none none
- STX zp | | alu_x temp 0 0 NONE ADD W 0 00 00 M none none
- STY zp | | alu_y temp 0 0 NONE ADD W 0 00 00 M none none
- ASL zp | | 00 temp 0 0 NZC SFL RMW 0 00 00 M none none
- DEC zp | | FF temp 0 0 NZ ADD RMW 0 00 00 M none none
- INC zp | | 00 temp 0 1 NZ ADD RMW 0 00 00 M none none
- LSR zp | | 00 temp 0 0 NZC SFR RMW 0 00 00 M none none
- ROL zp | | 00 temp 0 cin NZC SFL RMW 0 00 00 M none none
- ROR zp | | 00 temp 0 cin NZC SFR RMW 0 00 00 M none none
-
-
-
-Page Zero indexed
-
-------------------------------------------------------------------------------------------------------------------------------------------------------
- ADC zp,X | | alu_a temp 0 cin NZCV ADD R X 00 00 A none none
- AND zp,X | | alu_a temp 0 0 NZ AND R X 00 00 A none none
- CMP zp,X | | alu_a temp 1 1 NZC ADD R X 00 00 0 none none
- EOR zp,X | | alu_a temp 0 0 NZ EOR R X 00 00 A none none
- LDA zp,X | | 00 temp 0 0 NZ ADD R X 00 00 A none none
- LDY zp,X | | 00 temp 0 0 NZ ADD R X 00 00 Y none none
- ORA zp,X | | alu_a temp 0 0 NZ ORR R X 00 00 A none none
- SBC zp,X | | alu_a temp 1 cin NZXV ADD R X 00 00 A none none
- LDX zp,Y | | 00 temp 0 0 NZ ADD R Y 00 00 X none none
- STA zp,X | | alu_a temp 0 0 NONE ADD W X 00 00 M none none
- STY zp,X | | alu_y temp 0 0 NONE ADD W X 00 00 M none none
- STX zp,Y | | alu_x temp 0 0 NONE ADD W Y 00 00 M none none
- ASL zp,X | | 00 temp 0 0 NZC SFL RMW X 00 00 M none none
- DEC zp,X | | FF temp 0 0 NZ ADD RMW X 00 00 M none none
- INC zp,X | | 00 temp 0 1 NZ ADD RMW X 00 00 M none none
- LSR zp,X | | 00 temp 0 0 NZC SFR RMW X 00 00 M none none
- ROR zp,X | | 00 temp 0 cin NZC SFR RMW X 00 00 M none none
- ROL zp,X | | 00 temp 0 cin NZC SFL RMW X 00 00 M none none
-
-
-
-Page Zero indirectX
-
-------------------------------------------------------------------------------------------------------------------------------------------------------
- ADC (zp,X) | | alu_a temp 0 cin NZCV ADD R X 00 00 A none none
- AND (zp,X) | | alu_a temp 0 0 NZ AND R X 00 00 A none none
- CMP (zp,X) | | alu_a temp 1 1 NZC ADD R X 00 00 0 none none
- EOR (zp,X) | | alu_a temp 0 0 NZ EOR R X 00 00 A none none
- LDA (zp,X) | | 00 temp 0 0 NZ ADD R X 00 00 A none none
- ORA (zp,X) | | alu_a temp 0 0 NZ ORR R X 00 00 A none none
- SBC (zp,X) | | alu_a temp 1 cin NZXV ADD R X 00 00 A none none
- STA (zp,X) | | alu_a temp 0 0 NONE ADD W X 00 00 M none none
-
-
-
-======================================================================================================================================================
-
-
-Page Zero IndirectY
-
-------------------------------------------------------------------------------------------------------------------------------------------------------
- ADC (zp),Y | | alu_a temp 0 cin NZCV ADD R Y 00 00 A none none
- AND (zp),Y | | alu_a temp 0 0 NZ AND R Y 00 00 A none none
- CMP (zp),Y | | alu_a temp 1 1 NZC ADD R Y 00 00 0 none none
- EOR (zp),Y | | alu_a temp 0 0 NZ EOR R Y 00 00 A none none
- LDA (zp),Y | | 00 temp 0 0 NZ ADD R Y 00 00 A none none
- ORA (zp),Y | | alu_a temp 0 0 NZ ORR R Y 00 00 A none none
- SBC (zp),Y | | alu_a temp 1 cin NZXV ADD R Y 00 00 A none none
- STA (zp),Y | | alu_a temp 0 0 NONE ADD W Y 00 00 M none none
-
-
-
-
-
-Implied
-
-------------------------------------------------------------------------------------------------------------------------------------------------------
- NOP | | 00 00 0 0 NONE ADD 0 0 00 00 0 none none
- SEC | | 00 00 0 0 WR ADD 0 0 01 01 0 none none
- SED | | 00 00 0 0 WR ADD 0 0 08 08 0 none none
- SEI | | 00 00 0 0 WR ADD 0 0 04 04 0 none none
- CLC | | 00 00 0 0 WR ADD 0 0 00 01 0 none none
- CLD | | 00 00 0 0 WR ADD 0 0 00 08 0 none none
- CLI | | 00 00 0 0 WR ADD 0 0 00 04 0 none none
- CLV | | 00 00 0 0 WR ADD 0 0 00 40 0 none none
- ASL A | | alu_a 00 0 0 NZC SFL RMW 0 00 00 A none none
- DEX | | alu_x 00 0 0 NZ ADD RMW 0 00 00 X none none
- DEY | | alu_y 00 0 0 NZ ADD RMW 0 00 00 Y none none
- INX | | alu_x 00 0 1 NZ ADD RMW 0 00 00 X none none
- INY | | alu_y 00 0 1 NZ ADD RMW 0 00 00 Y none none
- LSR A | | alu_a 00 0 0 NZC SFR RMW 0 00 00 A none none
- ROL A | | alu_a 00 0 cin NZC SFL RMW 0 00 00 A none none
- ROR A | | alu_a 00 0 cin NZC SFR RMW 0 00 00 A none none
- TAX | | alu_a 00 0 0 NZ ADD RMW 0 00 00 A none none
- TAY | | alu_a 00 0 0 NZ ADD RMW 0 00 00 X none none
- TXA | | alu_x 00 0 0 NZ ADD RMW 0 00 00 A none none
- TYA | | alu_y 00 0 0 NZ ADD RMW 0 00 00 A none none
-
-
-
-Branch
- alu alu alu alu alu
- op_a op_b op_b op_c status alu branch branch
- src src inv src update mode type index value enable dest
-------------------------------------------------------------------------------------------------------------------------------------------------------
- BCC rel | | 00 00 0 0 NONE ADD 0 0 00 01 0 branch none
- BCS rel | | 00 00 0 0 NONE ADD 0 0 01 01 0 branch none
- BNE rel | | 00 00 0 0 NONE ADD 0 0 00 02 0 branch none
- BEQ rel | | 00 00 0 0 NONE ADD 0 0 02 02 0 branch none
- BVC rel | | 00 00 0 0 NONE ADD 0 0 00 40 0 branch none
- BVS rel | | 00 00 0 0 NONE ADD 0 0 40 40 0 branch none
- BPL rel | | 00 00 0 0 NONE ADD 0 0 00 80 0 branch none
- BMI rel | | 00 00 0 0 NONE ADD 0 0 80 80 0 branch none
-
-
-
-Stack
-------------------------------------------------------------------------------------------------------------------------------------------------------
- PLA | | 00 00 0 0 NZ ADD R 0 00 00 A
- PLP | | 00 00 0 0 RESTORE ADD R 0 00 00 PSR
- PHA | | alu_a 00 0 0 NONE ADD W 0 00 00 M
- PHP | | psr 00 0 0 NONE ADD W 0 00 00 M
-
-
-
-Jump absolute
-------------------------------------------------------------------------------------------------------------------------------------------------------
- JMP abs | | 00 00 0 0 NONE ADD 0 0 00 00 0
-
-
-
-Jump indirect
-------------------------------------------------------------------------------------------------------------------------------------------------------
- JMP (abs) | | 00 00 0 0 NONE ADD 0 0 00 00 0
-
-
-
-Jump Sub absolute
-------------------------------------------------------------------------------------------------------------------------------------------------------
- JSR abs | | 00 00 0 0 NONE ADD 0 0 00 00 0
-
-
-
-Break
-------------------------------------------------------------------------------------------------------------------------------------------------------
- BRK | | alu_a 00 0 0 WR ADD 0 0 10 10 0
-
-
-
-Return from
-Interrupt
-------------------------------------------------------------------------------------------------------------------------------------------------------
- RTI | | 00 00 0 0 RESTORE ADD 0 0 00 00 P
-
-
-
-Return from
-Subroutine
-------------------------------------------------------------------------------------------------------------------------------------------------------
- RTS | | 00 00 0 0 NONE ADD 0 0 00 00 0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-Opcode Current Instruction byte
-New_opcode Next Instruction byte
-Opc_Add Address of current instruction
-Next_Op_Add Address of next instruction byte
-Operand Data operand
-Address Address of data operand if in memory
-Offset Value added to Opc_Add if branch is taken
-Pointer Address to store the address of data opeand if in memory
-Vector Address to store the Next_Op_Add
-
-
-
-
-
-
-
-
-
-Address Sequence Decodes
-=========================================================================
-
-
-
-
-
-
-Implied Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-______________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add Opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 Opcode 1 Set
-3 1 Opc_Add+1 New_Opcode opcode 1 Set
---------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+2 New_Opcode updated
-
-
-
-
-Immediate Addressing Mode
-
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-____________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
-----------------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+1 operand operand Set
-----------------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+2 operand 1 Set
-5 1 Opc_Add+2 new_op opcode 1 Set
-----------------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+3 new_op updated
-
-
-
-
-
-
-
-Absolute Read Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+2 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+3 add_hi add_hi Set
-5 1 Opc_Add+3 new_op addr r 00 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+3 new_op addr r 00 operand Set
-7 1 Opc_Add+3 new_op addr r 00 operand Set
---------------------------------------------------------------------------------------------------------------------------------------------
-8 0 Opc_Add+3 new_op 1 Set
-9 1 Opc_Add+3 new_op opcode 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-10 0 updated
-
-
-
-
-
-
-Absolute Write Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+2 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+3 add_hi add_hi Set
-5 1 Opc_Add+3 new_op opcode addr w operand 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+4 new_op updated
-7 1 Opc_Add+4
-
-
-
-
-
-Absolute Read/Modify/Write Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+2 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+3 add_hi add_hi Set
-5 1 Opc_Add+3 new_op addr r Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+3 new_op operand Set
-7 1 Opc_Add+3 new_op Set
---------------------------------------------------------------------------------------------------------------------------------------------
-8 0 Opc_Add+3 new_op addr w result 1 Set
-9 1 Opc_Add+3 new_op opcode 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-10 0 updated
-
-
-
-
-
-
-
-Absolute Indexed Read Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+2 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+3 add_hi add_hi Set
-5 1 Opc_Add+3 new_op addr+i r 00 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+3 new_op addr+i r 00 operand Set
-7 1 Opc_Add+3 new_op addr+i r 00 operand Set
---------------------------------------------------------------------------------------------------------------------------------------------
-8 0 Opc_Add+3 new_op 1 Set
-9 1 Opc_Add+3 new_op opcode 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-10 0 updated
-
-
-
-Absolute Indexed Write Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+2 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+3 add_hi add_hi 1 Set
-5 1 Opc_Add+3 new_op opcode addr+i w operand 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+4 new_op updated
-7 1 Opc_Add+4
-
-
-
-
-
-Absolute Indexed Read/Modify/Write Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+2 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+3 add_hi add_hi Set
-5 1 Opc_Add+3 new_op addr+i r Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+3 new_op operand Set
-7 1 Opc_Add+3 new_op Set
---------------------------------------------------------------------------------------------------------------------------------------------
-8 0 Opc_Add+3 new_op addr+i w result 1 Set
-9 1 Opc_Add+3 new_op opcode 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-10 0 updated
-
-
-
-
-
-
-
-
-
-
-
-
-Page Zero Read Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+1 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+2 add_lo addr r Set
-5 1 Opc_Add+2 new_op operand Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+2 new_op 1 Set
-7 1 Opc_Add+2 new_op opcode 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-8 0 Opc_Add+3 new_op updated
-
-
-
-
-
-
-
-
-Page Zero Write Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+1 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+2 add_lo 1 Set
-5 1 Opc_Add+2 new_op opcode addr w operand 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+3 new_op updated
-7 1 Opc_Add+3
-
-
-
-
-
-
-
-Page Zero Read/Modify/Write Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+1 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+2 add_lo addr r Set
-5 1 Opc_Add+2 new_op operand Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+2 new_op 1 Set
-7 1 Opc_Add+2 new_op opcode addr w result 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-8 0 Opc_Add+3 new_op updated
-
-
-
-
-
-
-
-
-
-
-Page Zero Indexed Read Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+1 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+2 add_lo addr+i r Set
-5 1 Opc_Add+2 new_op operand Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+2 new_op 1 Set
-7 1 Opc_Add+2 new_op opcode 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-8 0 Opc_Add+3 new_op updated
-
-
-
-
-
-Page Zero Indexed Write Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+1 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+2 add_lo 1 Set
-5 1 Opc_Add+2 new_op opcode addr w operand 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+3 new_op updated
-7 1 Opc_Add+3
-
-
-
-
-
-
-
-Page Zero Indexed Read/Modify/Write Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+1 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+2 add_lo addr r Set
-5 1 Opc_Add+2 new_op operand Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+2 new_op 1 Set
-7 1 Opc_Add+2 new_op opcode addr w result 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-8 0 Opc_Add+3 new_op updated
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-Page Zero Indirect X Read
--------------------------------------------------------
-Operand address lower byte is read from the address found by adding X index value to 8 bit address following opcode and
-the upper byte is read from the address found by adding X index value to 8 bit address plus 1 (no wraparound)
-
-
-
-
-Page Zero IndirectX Read Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+1 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+2 add_lo addr+i r Set
-5 1 Opc_Add+2 new_op addr+i+1 r add_l Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+2 new_op add_h Set
-7 1 Opc_Add+2 new_op addr r Set
---------------------------------------------------------------------------------------------------------------------------------------------
-8 0 Opc_Add+2 new_op operand 1 Set
-9 1 opcode 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-10 0 updated
-
-
-
-
-
-Page Zero IndirectX Write Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+1 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+2 add_lo addr+i r Set
-5 1 Opc_Add+2 new_op addr+i+1 add_l Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+2 new_op add_h 1 Set
-7 1 Opc_Add+2 new_op opcode addr w result 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-8 0 Opc_Add+3 new_op updated
-9 1
-
-
-
-
-
-
-
-
-
-Page Zero IndirectY Read Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+1 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+2 add_lo addr_lo r Set
-5 1 Opc_Add+2 new_op addr Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+2 new_op addr+i r Set
-7 1 Opc_Add+2 new_op addr+i r operand Set
---------------------------------------------------------------------------------------------------------------------------------------------
-8 0 Opc_Add+2 new_op 1 Set
-9 1 opcode 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-10 0 updated
-
-
-
-
-Page Zero IndirectX Write Addressing Mode
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-___________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
---------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+1 add_lo add_lo Set
---------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Opc_Add+2 add_lo add_lo r 1 Set
-5 1 Opc_Add+2 new_op addr 1 Set
---------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Opc_Add+2 new_op addr+i w result Set
-7 1 Opc_Add+2 new_op opcode Set updated
---------------------------------------------------------------------------------------------------------------------------------------------
-8 0 Opc_Add+3 new_op
-9 1
-
-
-
-
-
-
-Relative Addressing Mode
-
-
-c e ALU
-l n prog prog prog data memory page zero stack Control Processsor
-k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
-____________________________________________________________________________________________________________________________________________________________
-0 0 Opc_Add
-1 1 Opc_Add opcode opcode
-----------------------------------------------------------------------------------------------------------------------------------------------------
-2 0 Opc_Add+1 opcode Set
-3 1 Opc_Add+1 offset offset Set
-----------------------------------------------------------------------------------------------------------------------------------------------------
-4 0 Next_Op_Add offset 1
-5 1 Next_Op_Add new_op opcode 1
-----------------------------------------------------------------------------------------------------------------------------------------------------
-6 0 Next_Op_Add+1 new_op
-
-
-
-
-
-Addressing Modes
-===============================================================================================
-
-
-
-
-
-Stack StackRead/StackWrite
--------------------------------------------------------
-Operation uses the Stack
-
-
-
-Jump Absolute Read
--------------------------------------------------------
-16 bit destination address follows opcode
-
-
-Jump Indirect Read
--------------------------------------------------------
-16 bit Address following opcode points to destination address
-
-
-
-
-Jump Sub Absolute Read_Stackwrite
--------------------------------------------------------
-16 bit destination address follows opcode. Return address is pushed on stack
-
-
-
-Break Read_Stackwrite
--------------------------------------------------------
-Return address is pushed on stack and the IRQ vector is taken
-
-
-
-Return from Interrupt Read_Stackread
--------------------------------------------------------
-PSR and Prog_counter are pulled from stack
-
-
-
-
-Return from Subroutine Read_Stackread
--------------------------------------------------------
-Prog_counter is pulled from stack
-
-
-
-
-
-
-
-
-
-
-
-
-
-Interrupts
-===============================================================================================
-
-Non-Maskable (NMI)
-
- 1) Finish current instruction
- 2) Push Address of next instruction on stack
- 3) Read Vector Address from FFFA
- 4) Execute code @ vector address
-
-
-
-Maskable (IRQ) ( if I bit is clear)
-
- 1) Finish current instruction
- 2) Push Address of next instruction on stack
- 3) Push PSR on stack
- 4) Read Vector Address from FFFE
- 5) Execute code @ vector address
-
-
-Reset
-
- 1) Clear A,X,Y: Set PSR to 20h
- 2) Wait for Reset to deassert
- 3) Read Vector Address from FFFC
- 4) Execute code @ vector address
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Index: socgen/trunk/projects/Mos6502/ip/T6502/rtl/xml/T6502.xml
===================================================================
--- socgen/trunk/projects/Mos6502/ip/T6502/rtl/xml/T6502.xml (revision 74)
+++ socgen/trunk/projects/Mos6502/ip/T6502/rtl/xml/T6502.xml (revision 75)
@@ -519,6 +519,8 @@
wire [15:0] addr_pin wire [7:0] pg0_add wire [15:0] prog_counter wire pg0_rd wire pg0_wr wire [15:0] io_rdata wire [15:0] boot_data wire [15:0] prog_data wire [15:0] shadow_data wire [15:0] din wire dout_oe wire nmi_in wire rx_irq wire tx_irq wire ps2_data_avail wire enable wire rd_pin wire [1:0] timer_irq
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/inst_2_test/modellist
1,5 → 1,7
`include "../../bench/verilog/models/clock_gen.v" |
`include "../../bench/verilog/models/ps2_model.v" |
`include "../../bench/verilog/models/iobuftri.v" |
`include "../../bench/verilog/models/uart_model.v" |
`include "../../bench/verilog/models/io_probe.v" |
/socgen/trunk/projects/Mos6502/ip/T6502/sim/cov/T6502/Makefile
14,9 → 14,8
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > T6502.v ;\ |
covered score -f filelist.cov -i TB.dut.cpu -t T6502_cpu -I ./ -v ./T6502.v -o T6502_cpu.cdd 2> T6502_cpu_cov.log | tee >> T6502_cpu_cov.log ;\ |
covered score -f filelist.cov -i TB.dut.io_module -t io_module -I ./ -v ./T6502.v -o io_module.cdd 2> io_module_cov.log | tee >> io_module_cov.log ;\ |
covered score -f filelist.cov -i TB.dut.cpu -t T6502_cpu -I ./ -v ./coverage.v -o T6502_cpu.cdd 2> cpu_cov.log | tee >> cpu_cov.log ;\ |
covered score -f filelist.cov -i TB.dut.io_module -t io_module -I ./ -v ./coverage.v -o io_module.cdd 2> io_module_cov.log | tee >> io_module_cov.log ;\ |
echo "################################################################################"; \ |
|
|
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_sequencer/sim/cov/T6502_cpu_sequencer/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
|
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/sim/cov/T6502_cpu_alu_logic/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
|
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/rtl/verilog/top.v
351,7 → 351,12
|
|
`ifndef SYNTHESIS |
|
|
|
|
|
|
reg [7*8-1:0] A_instr; |
reg [10*8-1:0] A_state; |
reg [3*8-1:0] A_alu_mode; |
365,6 → 370,9
reg [8*8-1:0] A_cmd; |
reg [5*8-1:0] A_ins_type; |
reg [3*8-1:0] A_idx_sel; |
|
|
always@(posedge clk) $display("--- %h",prog_counter); |
|
|
always @(*) begin |
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/sim/cov/T6502_cpu/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
|
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_control/sim/cov/T6502_cpu_control/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
|
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_inst_decode/sim/cov/T6502_cpu_inst_decode/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
|
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu/sim/cov/T6502_cpu_alu/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
|
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_state_fsm/sim/cov/T6502_cpu_state_fsm/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
|
/socgen/trunk/projects/logic/ip/micro_bus/sim/cov/micro_bus/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
|
/socgen/trunk/projects/logic/ip/ps2_interface/sim/cov/ps2_interface/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
|
/socgen/trunk/projects/logic/ip/disp_io/sim/cov/disp_io/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
|
/socgen/trunk/projects/logic/ip/serial_rcvr/sim/cov/serial_rcvr/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
|
/socgen/trunk/projects/logic/ip/uart/rtl/verilog/top.v
93,8 → 93,9
wire fifo_under_run; |
wire cde_buffer_empty; |
reg xmit_start; |
|
wire xmit_enable; |
|
|
always@(posedge clk) |
if(reset) rts_pad_out <= 1'b0; |
else rts_pad_out <= rts_in; |
/socgen/trunk/projects/logic/ip/uart/sim/cov/uart/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
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/socgen/trunk/projects/logic/ip/flash_memcontrl/sim/cov/flash_memcontrl/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
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/socgen/trunk/projects/logic/ip/usb_epp/sim/cov/usb_epp/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
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/socgen/trunk/projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl_600x432/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
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/socgen/trunk/projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl/Makefile
15,8 → 15,7
build_cdd: |
echo "################################################################################"; \ |
echo; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\ |
covered score -f filelist.cov -i TB.dut -t $(VARIANT) -I ./ -v ./coverage.v -o $(VARIANT).cdd 2> cov.log | tee >> cov.log ;\ |
echo "################################################################################"; \ |
|
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