OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

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    from Rev 742 to Rev 743
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  •

Rev 742 → Rev 743

/trunk/uclinux/uClinux-2.0.x/include/asm-or32/irq.h
14,8 → 14,9
* "Generic" interrupt sources
*/
 
#define IRQ_SCHED_TIMER (0) /* interrupt source for scheduling timer */
#define IRQ_UART_0 (15) /* interrupt source for UART dvice 0 */
#define IRQ_SCHED_TIMER (0) /* interrupt source for scheduling timer */
#define IRQ_ETH_0 (16) /* interrupt source for Ethernet dvice 0 */
 
/*
* various flags for request_irq()
/trunk/uclinux/uClinux-2.0.x/include/asm-or32/board.h
11,6 → 11,7
#define MC_BASE_ADD 0xa0000000
#define CRT_BASE_ADD 0xb0000000
#define KBD_BASE_ADD 0xb1000000
#define ETH_BASE_ADD 0xb2000000
 
/* Define this if you want to use I and/or D cache */
#define ICACHE 0
38,4 → 39,12
/* Define this if you are using MC */
#define MC_INIT 0
 
/* Define ethernet MAC address */
#define MACADDR0 0x00
#define MACADDR1 0x01
#define MACADDR2 0x02
#define MACADDR3 0x03
#define MACADDR4 0x04
#define MACADDR5 0x05
 
#endif
/trunk/uclinux/uClinux-2.0.x/sim.cfg
107,7 → 107,7
name = "FLASH"
ce = 0
baseaddr = 0x04000000
size = 0x00200000
size = 0x00400000
delayr = 10
delayw = -1
/* log = "flash.log"*/
291,8 → 291,8
/* iprompt = 0 */
exe_log = 0
exe_log_type = software
exe_log_start = 0000000
exe_log_end = 20000000
exe_log_start = 39000000
/* exe_log_end = 20000000*/
exe_log_marker = 100
exe_log_fn = "executed.log"
end
532,16 → 532,18
*/
 
section ethernet
enabled = 0
nethernets = 1
 
device 0
baseaddr = 0x88000000
baseaddr = 0xb2000000
dma = 0
irq = 16
rtx_type = 1
tx_channel = 0
rx_channel = 1
rxfile = "/tmp/eth0.rx"
txfile = "/tmp/eth0.tx"
sockif = "eth0"
enddevice
end
 
/trunk/uclinux/uClinux-2.0.x/init/main.c
280,7 → 280,8
 
extern void dquot_init(void);
 
static char * argv_init[MAX_INIT_ARGS+2] = { NULL, };
//static char * argv_init[MAX_INIT_ARGS+2] = { "ping", "10.1.1.2", NULL, };
static char * argv_init[MAX_INIT_ARGS+2] = { NULL, };
static char * envp_init[MAX_INIT_ENVS+2] = { "HOME=/", "TERM=linux", NULL, };
 
static char * argv_rc[] = { "/bin/sh", NULL };
1204,15 → 1205,17
(void) dup(0);
 
#if 0
printf("Executing sash\n");
execve("/bin/sash",argv_init,envp_init);
#else
printf("Executing nano-X\n");
printf("Executing ping... ");
execve("/bin/ping",argv_init,envp_init);
printf("failed\n");
 
printf("Executing nano-X... ");
execve("/bin/landmine",argv_init,envp_init);
 
printf("Executing sash\n");
printf("failed\n");
#endif
printf("Executing sash... ");
execve("/bin/sash",argv_init,envp_init);
#endif
printf("failed\n");
 
if (!execute_command) {
execve("/etc/init",argv_init,envp_init);
/trunk/uclinux/uClinux-2.0.x/arch/or32/kernel/signal.c
86,7 → 86,7
(int)regs->result == -ERESTARTNOINTR))
{
regs->gprs[1] = regs->orig_gpr3;
regs->pc -= 4; /* Back up & retry system call */
regs->pc -= 8; /* Back up & retry system call */
regs->result = 0;
}
return (regs->result);
/trunk/uclinux/uClinux-2.0.x/arch/or32/kernel/head.S
245,6 → 245,12
l.j _tick
l.nop
 
.org 0x600
 
l.nop
l.j _align
l.nop
 
.org 0x800
 
l.nop
307,6 → 313,12
l.j _tick
l.nop
 
.org 0x600
 
l.nop
l.j _align
l.nop
 
.org 0x800
 
l.nop
515,6 → 527,214
l.nop
RETURN_FROM_INT(0x500)
 
_align:
l.addi r1,r1,-128
l.sw 0x08(r1),r2
l.sw 0x0c(r1),r3
l.sw 0x10(r1),r4
l.sw 0x14(r1),r5
l.sw 0x18(r1),r6
l.sw 0x1c(r1),r7
l.sw 0x20(r1),r8
l.sw 0x24(r1),r9
l.sw 0x28(r1),r10
l.sw 0x2c(r1),r11
l.sw 0x30(r1),r12
l.sw 0x34(r1),r13
l.sw 0x38(r1),r14
l.sw 0x3c(r1),r15
l.sw 0x40(r1),r16
l.sw 0x44(r1),r17
l.sw 0x48(r1),r18
l.sw 0x4c(r1),r19
l.sw 0x50(r1),r20
l.sw 0x54(r1),r21
l.sw 0x58(r1),r22
l.sw 0x5c(r1),r23
l.sw 0x60(r1),r24
l.sw 0x64(r1),r25
l.sw 0x68(r1),r26
l.sw 0x6c(r1),r27
l.sw 0x70(r1),r28
l.sw 0x74(r1),r29
l.sw 0x78(r1),r30
l.sw 0x7c(r1),r31
l.mfspr r2,r0,SPR_EEAR_BASE /* Load the efective addres */
l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */
 
l.lwz r3,0(r5) /* Load insn */
l.srli r4,r3,26 /* Shift left to get the insn opcode */
 
l.sfeqi r4,0x00 /* Check if the load/store insn is in delay slot */
l.bf jmp
l.sfeqi r4,0x01
l.bf jmp
l.sfeqi r4,0x03
l.bf jmp
l.sfeqi r4,0x04
l.bf jmp
l.sfeqi r4,0x11
l.bf jr
l.sfeqi r4,0x12
l.bf jr
l.nop
l.j 1f
l.addi r5,r5,4 /* Increment PC to get return insn address */
jmp:
l.slli r4,r3,6 /* Get the signed extended jump length */
l.srai r4,r4,4
 
l.lwz r3,4(r5) /* Load the real load/store insn */
 
l.add r5,r5,r4 /* Calculate jump target address */
l.j 1f
l.srli r4,r3,26 /* Shift left to get the insn opcode */
 
jr:
l.slli r4,r3,9 /* Shift to get the reg nb */
l.andi r4,r4,0x7c
 
l.lwz r3,4(r5) /* Load the real load/store insn */
 
l.add r4,r4,r1 /* Load the jump register value from the stack */
l.lwz r5,0(r4)
 
l.srli r4,r3,26 /* Shift left to get the insn opcode */
1: l.mtspr r0,r5,SPR_EPCR_BASE
 
l.sfeqi r4,0x26
l.bf lhs
l.sfeqi r4,0x25
l.bf lhz
l.sfeqi r4,0x22
l.bf lws
l.sfeqi r4,0x21
l.bf lwz
l.sfeqi r4,0x37
l.bf sh
l.sfeqi r4,0x35
l.bf sw
l.nop
 
1: l.j 1b /* I don't know what to do */
l.nop
 
lhs: l.lbs r5,0(r2)
l.slli r5,r5,8
l.lbz r6,1(r2)
l.or r5,r5,r6
l.srli r4,r3,19
l.andi r4,r4,0x7c
l.add r4,r4,r1
l.j align_end
l.sw 0(r4),r5
lhz: l.lbz r5,0(r2)
l.slli r5,r5,8
l.lbz r6,1(r2)
l.or r5,r5,r6
l.srli r4,r3,19
l.andi r4,r4,0x7c
l.add r4,r4,r1
l.j align_end
l.sw 0(r4),r5
lws: l.lbs r5,0(r2)
l.slli r5,r5,24
l.lbz r6,1(r2)
l.slli r6,r6,16
l.or r5,r5,r6
l.lbz r6,2(r2)
l.slli r6,r6,8
l.or r5,r5,r6
l.lbz r6,3(r2)
l.or r5,r5,r6
l.srli r4,r3,19
l.andi r4,r4,0x7c
l.add r4,r4,r1
l.j align_end
l.sw 0(r4),r5
lwz: l.lbz r5,0(r2)
l.slli r5,r5,24
l.lbz r6,1(r2)
l.slli r6,r6,16
l.or r5,r5,r6
l.lbz r6,2(r2)
l.slli r6,r6,8
l.or r5,r5,r6
l.lbz r6,3(r2)
l.or r5,r5,r6
l.srli r4,r3,19
l.andi r4,r4,0x7c
l.add r4,r4,r1
l.j align_end
l.sw 0(r4),r5
sh:
l.srli r4,r3,9
l.andi r4,r4,0x7c
l.add r4,r4,r1
l.lwz r5,0(r4)
l.sb 1(r2),r5
l.slli r5,r5,8
l.j align_end
l.sb 0(r2),r5
 
sw:
l.srli r4,r3,9
l.andi r4,r4,0x7c
l.add r4,r4,r1
l.lwz r5,0(r4)
l.sb 3(r2),r5
l.slli r5,r5,8
l.sb 2(r2),r5
l.slli r5,r5,8
l.sb 1(r2),r5
l.slli r5,r5,8
l.j align_end
l.sb 0(r2),r5
 
align_end:
l.lwz r2,0x08(r1)
l.lwz r3,0x0c(r1)
l.lwz r4,0x10(r1)
l.lwz r5,0x14(r1)
l.lwz r6,0x18(r1)
l.lwz r7,0x1c(r1)
l.lwz r8,0x20(r1)
l.lwz r9,0x24(r1)
l.lwz r10,0x28(r1)
l.lwz r11,0x2c(r1)
l.lwz r12,0x30(r1)
l.lwz r13,0x34(r1)
l.lwz r14,0x38(r1)
l.lwz r15,0x3c(r1)
l.lwz r16,0x40(r1)
l.lwz r17,0x44(r1)
l.lwz r18,0x48(r1)
l.lwz r19,0x4c(r1)
l.lwz r20,0x50(r1)
l.lwz r21,0x54(r1)
l.lwz r22,0x58(r1)
l.lwz r23,0x5c(r1)
l.lwz r24,0x60(r1)
l.lwz r25,0x64(r1)
l.lwz r26,0x68(r1)
l.lwz r27,0x6c(r1)
l.lwz r28,0x70(r1)
l.lwz r29,0x74(r1)
l.lwz r30,0x78(r1)
l.lwz r31,0x7c(r1)
l.addi r1,r1,128
l.rfe
 
 
_ext_int:
SAVE_INT_REGS(0x0800)
l.addi r3,r1,0
/trunk/uclinux/uClinux-2.0.x/arch/or32/defconfig
38,13 → 38,13
# General setup
#
# CONFIG_PCI is not set
# CONFIG_NET is not set
CONFIG_NET=y
# CONFIG_SYSVIPC is not set
# CONFIG_REDUCED_MEMORY is not set
# CONFIG_BINFMT_FLAT is not set
# CONFIG_KERNEL_ELF is not set
CONFIG_BINFMT_ELF=y
# CONFIG_CONSOLE=y
# CONFIG_CONSOLE is not set
# CONFIG_FRAMEBUFFER=y
 
#
68,7 → 68,7
#
# CONFIG_FIREWALL is not set
# CONFIG_NET_ALIAS is not set
# CONFIG_INET is not set
CONFIG_INET=y
# CONFIG_IP_FORWARD is not set
# CONFIG_IP_MULTICAST is not set
# CONFIG_SYN_COOKIES is not set
97,7 → 97,7
#
# Network device support
#
# CONFIG_NETDEVICES is not set
CONFIG_NETDEVICES=y
# CONFIG_DUMMY is not set
# CONFIG_SLIP is not set
# CONFIG_SLIP_COMPRESSED is not set
113,6 → 113,7
# CONFIG_UCCS8900_HW_SWAP is not set
# CONFIG_SMC9194 is not set
# CONFIG_NE2000 is not set
CONFIG_OETH=y
 
#
# Filesystems
140,6 → 141,7
#
CONFIG_SERIAL=y
# CONFIG_WATCHDOG is not set
# CONFIG_KEYBOARD is not set
 
#
# Kernel hacking
/trunk/uclinux/uClinux-2.0.x/arch/or32/board/initrd Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/uclinux/uClinux-2.0.x/arch/or32/board/rom.ld
1,7 → 1,7
MEMORY
{
romvec : ORIGIN = 0x04000000, LENGTH = 0x2000
flash : ORIGIN = 0x04002000, LENGTH = 0x00200000 - 0x2000
flash : ORIGIN = 0x04002000, LENGTH = 0x00400000 - 0x2000
eflash : ORIGIN = 0x04200000, LENGTH = 0
ramvec : ORIGIN = 0x00000000, LENGTH = 0x00002000
ram : ORIGIN = 0x00002000, LENGTH = 0x00800000 - 0x2000
15,6 → 15,7
__romvec = . ;
*(.romvec)
} > romvec
 
.text :
{
___rom_start = . ;
22,6 → 23,7
*(.text)
__etext = . ;
} > flash
 
.initrd :
{
__initrd_start = . ;
29,10 → 31,12
__initrd_end = . ;
___data_rom_start = . ;
} > flash
 
.eflash :
{
__flashend = . ;
} > eflash
 
.data :
AT ( ADDR (.initrd) + SIZEOF (.initrd))
{
45,6 → 49,7
__data_end = . ;
edata = ALIGN( 0x10 ) ;
} > ram
 
.bss :
{
__sbss = ALIGN( 0x10 ) ;
56,6 → 61,7
end = ALIGN( 0x10 ) ;
__end = ALIGN( 0x10 ) ;
} > ram
 
.ramvec :
AT ( ADDR (.initrd) + SIZEOF (.initrd) + SIZEOF (.data))
{
63,6 → 69,7
*(.ramvec)
__ramvec_end = . ;
} > ramvec
 
.eram :
{
__ramend = . ;
/trunk/uclinux/uClinux-2.0.x/arch/or32/config.in
122,12 → 122,7
comment 'CCP compressors for PPP are only built as modules.'
fi
tristate 'EQL (serial line load balancing) support' CONFIG_EQUALIZER
bool 'Cirrus Logic cs8900 ethernet' CONFIG_UCCS8900
if [ "$CONFIG_UCCS8900" != "n" ]; then
bool 'Hardware byte-swapping support for cs8900 ethernet' CONFIG_UCCS8900_HW_SWAP
fi
bool 'SMC 9194 ethernet' CONFIG_SMC9194
bool 'NE2000/NE1000 ISA ethernet' CONFIG_NE2000
bool 'Open ethernet core' CONFIG_OETH
 
fi
endmenu
/trunk/uclinux/uClinux-2.0.x/drivers/net/Space.c
100,6 → 100,7
extern int shaper_probe(struct device *);
/* Red Creek PCI hook */
extern int rcpci_probe(struct device *);
extern int oeth_probe(struct device *);
 
static int
ethif_probe(struct device *dev)
275,6 → 276,9
#ifdef CONFIG_LANCE
&& lance_probe(dev)
#endif
#ifdef CONFIG_OETH
&& oeth_probe(dev)
#endif
&& 1 ) {
return 1; /* -ENODEV or -EAGAIN would be more accurate. */
}
/trunk/uclinux/uClinux-2.0.x/drivers/net/Makefile
689,6 → 689,16
endif
endif
 
ifeq ($(CONFIG_OETH),y)
L_OBJS += open_eth.o
CONFIG_OETH_BUILTIN = y
else
ifeq ($(CONFIG_OETH),m)
CONFIG_OETH_MODULE = y
M_OBJS += open_eth.o
endif
endif
 
include $(TOPDIR)/Rules.make
 
clean:
763,3 → 773,9
$(CC) $(CPPFLAGS) $(CFLAGS) -c $<
tulip.o: tulip.c CONFIG
$(CC) $(CPPFLAGS) $(CFLAGS) $(TULIP_OPTS) -c $<
 
open_eth.o: open_eth.c CONFIG
$(CC) $(CPPFLAGS) $(CFLAGS) $(OETH_OPTS) -c $<
 
 
 
/trunk/uclinux/uClinux-2.0.x/drivers/net/open_eth.c
0,0 → 1,839
/*
* Ethernet driver for Open Ethernet Controller (www.opencores.org).
* Copyright (c) 2002 Simon Srot (simons@opencores.org)
*
* Based on:
*
* Ethernet driver for Motorola MPC8xx.
* Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
*
* mcen302.c: A Linux network driver for Mototrola 68EN302 MCU
*
* Copyright (C) 1999 Aplio S.A. Written by Vadim Lebedev
*
* Rigt now XXBUFF_PREALLOC must be used, bacause MAC does not
* handle unaligned buffers yet. Also the cache inhibit calls
* should be used some day.
*
*/
 
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/string.h>
#include <linux/ptrace.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/inet.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
 
#include <asm/irq.h>
#include <asm/pgtable.h>
#include <asm/bitops.h>
 
 
#include "open_eth.h"
 
#define net_device device
#define __pa(x) (x)
#define __va(x) (x)
#define __clear_user(add,len) memset((add),0,(len))
 
#define DEBUG 1
 
#define RXBUFF_PREALLOC 1
#define TXBUFF_PREALLOC 1
 
/* The transmitter timeout
*/
#define TX_TIMEOUT (2*HZ)
 
/* Buffer number (must be 2^n)
*/
#define OETH_RXBD_NUM 8
#define OETH_TXBD_NUM 8
#define OETH_RXBD_NUM_MASK (OETH_RXBD_NUM-1)
#define OETH_TXBD_NUM_MASK (OETH_TXBD_NUM-1)
 
/* Buffer size
*/
#define OETH_RX_BUFF_SIZE 2048
#define OETH_TX_BUFF_SIZE 2048
 
/* How many buffers per page
*/
#define OETH_RX_BUFF_PPGAE (PAGE_SIZE/OETH_RX_BUFF_SIZE)
#define OETH_TX_BUFF_PPGAE (PAGE_SIZE/OETH_TX_BUFF_SIZE)
 
/* How many pages is needed for buffers
*/
#define OETH_RX_BUFF_PAGE_NUM (OETH_RXBD_NUM/OETH_RX_BUFF_PPGAE)
#define OETH_TX_BUFF_PAGE_NUM (OETH_TXBD_NUM/OETH_TX_BUFF_PPGAE)
 
/* Buffer size (if not XXBUF_PREALLOC
*/
#define MAX_FRAME_SIZE 1518
 
/* The buffer descriptors track the ring buffers.
*/
struct oeth_private {
struct sk_buff* rx_skbuff[OETH_RXBD_NUM];
struct sk_buff* tx_skbuff[OETH_TXBD_NUM];
 
ushort tx_next; /* Next buffer to be sent */
ushort tx_last; /* Next buffer to be checked if packet sent */
ushort tx_full; /* Buffer ring fuul indicator */
ushort rx_cur; /* Next buffer to be checked if packet received */
 
oeth_regs *regs; /* Address of controller registers. */
oeth_bd *rx_bd_base; /* Address of Rx BDs. */
oeth_bd *tx_bd_base; /* Address of Tx BDs. */
 
struct enet_statistics stats;
};
 
static int oeth_open(struct net_device *dev);
static int oeth_start_xmit(struct sk_buff *skb, struct net_device *dev);
static void oeth_rx(struct net_device *dev);
static void oeth_tx(struct net_device *dev);
static void oeth_interrupt(int irq, void *dev_id, struct pt_regs *regs);
static int oeth_close(struct net_device *dev);
static struct enet_statistics *oeth_get_stats(struct net_device *dev);
static void oeth_set_multicast_list(struct net_device *dev);
static void oeth_set_mac_add(struct device *dev, void *addr);
static int calc_crc(char *mac_addr);
 
#if DEBUG
static void
oeth_print_packet(unsigned long add, int len)
{
int i;
 
_print("ipacket: add = %x len = %d\n", add, len);
for(i = 0; i < len; i++) {
if(!(i % 16))
_print("\n");
_print(" %.2x", *(((unsigned char *)add) + i));
}
_print("\n");
}
#endif
 
static int
oeth_open(struct net_device *dev)
{
 
oeth_regs *regs = (oeth_regs *)dev->base_addr;
 
#ifndef RXBUFF_PREALLOC
struct oeth_private *cep = (struct oeth_private *)dev->priv;
struct sk_buff *skb;
volatile oeth_bd *rx_bd;
int i;
 
rx_bd = cep->rx_bd_base;
 
for(i = 0; i < OETH_RXBD_NUM; i++) {
 
skb = dev_alloc_skb(MAX_FRAME_SIZE);
 
if (skb == NULL)
rx_bd[i].status = OETH_RX_BD_IRQ;
else
rx_bd[i].status = OETH_RX_BD_EMPTY | OETH_RX_BD_IRQ;
 
cep->rx_skbuff[i] = skb;
 
rx_bd[i].len = 0;
rx_bd[i].addr = (unsigned long)skb->tail;
}
rx_bd[OETH_RXBD_NUM - 1].status |= OETH_RX_BD_WRAP;
#endif
 
/* Install our interrupt handler.
*/
request_irq(IRQ_ETH_0, oeth_interrupt, 0, "eth", (void *)dev);
 
/* Enable receiver and transmiter
*/
regs->moder |= OETH_MODER_RXEN | OETH_MODER_TXEN;
 
return 0;
}
 
static int
oeth_close(struct net_device *dev)
{
struct oeth_private *cep = (struct oeth_private *)dev->priv;
oeth_regs *regs = (oeth_regs *)dev->base_addr;
volatile oeth_bd *bdp;
int i;
 
/* Free interrupt hadler
*/
free_irq(IRQ_ETH_0, (void *)dev);
 
/* Disable receiver and transmitesr
*/
regs->moder &= ~(OETH_MODER_RXEN | OETH_MODER_TXEN);
 
bdp = cep->rx_bd_base;
for (i = 0; i < OETH_RXBD_NUM; i++) {
bdp->status &= ~(OETH_TX_BD_STATS | OETH_TX_BD_READY);
bdp++;
}
 
bdp = cep->tx_bd_base;
for (i = 0; i < OETH_TXBD_NUM; i++) {
bdp->status &= ~(OETH_RX_BD_STATS | OETH_RX_BD_EMPTY);
bdp++;
}
 
#ifndef RXBUFF_PREALLOC
 
/* Free all alocated rx buffers
*/
for (i = 0; i < OETH_RXBD_NUM; i++) {
if (cep->rx_skbuff[i] != NULL)
dev_kfree_skb(cep->rx_skbuff[i], FREE_READ);
}
#endif
#ifndef TXBUFF_PREALLOC
 
/* Free all alocated tx buffers
*/
for (i = 0; i < OETH_TXBD_NUM; i++) {
if (cep->tx_skbuff[i] != NULL)
dev_kfree_skb(cep->tx_skbuff[i], FREE_WRITE);
}
#endif
 
return 0;
}
 
static int
oeth_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
struct oeth_private *cep = (struct oeth_private *)dev->priv;
volatile oeth_bd *bdp;
unsigned long flags;
 
/* Fill in a Tx ring entry
*/
bdp = cep->tx_bd_base + cep->tx_next;
 
if (cep->tx_full) {
 
/* All transmit buffers are full. Bail out.
*/
printk("%s: tx queue full!.\n", dev->name);
return 1;
}
 
/* Clear all of the status flags.
*/
bdp->status &= ~OETH_TX_BD_STATS;
 
/* If the frame is short, tell CPM to pad it.
*/
if (skb->len <= ETH_ZLEN)
bdp->status |= OETH_TX_BD_PAD;
else
bdp->status &= ~OETH_TX_BD_PAD;
 
#if DEBUG
_print("TX\n");
oeth_print_packet(skb->data, skb->len);
#endif
 
#ifdef TXBUFF_PREALLOC
 
/* Copy data in preallocated buffer */
if (skb->len > OETH_TX_BUFF_SIZE) {
printk("%s: tx frame too long!.\n", dev->name);
return 1;
}
else
memcpy((unsigned char *)bdp->addr, skb->data, skb->len);
 
bdp->len = skb->len;
 
dev_kfree_skb(skb, FREE_WRITE);
#else
/* Set buffer length and buffer pointer.
*/
bdp->len = skb->len;
bdp->addr = (uint)__pa(skb->data);
 
/* Save skb pointer.
*/
cep->tx_skbuff[cep->tx_next] = skb;
#endif
 
cep->tx_next = (cep->tx_next + 1) & OETH_TXBD_NUM_MASK;
save_flags(flags); cli();
 
if (cep->tx_next == cep->tx_last)
cep->tx_full = 1;
 
/* Send it on its way. Tell controller its ready, interrupt when done,
* and to put the CRC on the end.
*/
bdp->status |= (OETH_TX_BD_READY | OETH_TX_BD_IRQ | OETH_TX_BD_CRC);
 
dev->trans_start = jiffies;
 
restore_flags(flags);
 
return 0;
}
 
/* The interrupt handler.
*/
static void
oeth_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
struct net_device *dev = dev_id;
volatile struct oeth_private *cep;
uint int_events;
 
cep = (struct oeth_private *)dev->priv;
 
/* Get the interrupt events that caused us to be here.
*/
int_events = cep->regs->int_src;
cep->regs->int_src = int_events;
 
/* Handle receive event in its own function.
*/
if (int_events & (OETH_INT_RXF | OETH_INT_RXE))
oeth_rx(dev_id);
 
/* Handle transmit event in its own function.
*/
if (int_events & (OETH_INT_TXB | OETH_INT_TXE)) {
oeth_tx(dev_id);
mark_bh(NET_BH);
}
 
/* Check for receive busy, i.e. packets coming but no place to
* put them.
*/
if (int_events & OETH_INT_BUSY) {
if (!(int_events & (OETH_INT_RXF | OETH_INT_RXE)))
oeth_rx(dev_id);
}
 
return;
}
 
 
static void
oeth_tx(struct net_device *dev)
{
struct oeth_private *cep;
volatile oeth_bd *bdp;
 
#ifndef TXBUFF_PREALLOC
struct sk_buff *skb;
#endif
 
cep = (struct oeth_private *)dev->priv;
 
for (;; cep->tx_last = (cep->tx_last + 1) & OETH_TXBD_NUM_MASK) {
 
bdp = cep->tx_bd_base + cep->tx_last;
 
if ((bdp->status & OETH_TX_BD_READY) ||
((cep->tx_last == cep->tx_next) && !cep->tx_full))
break;
 
/* Check status for errors
*/
if (bdp->status & OETH_TX_BD_LATECOL)
cep->stats.tx_window_errors++;
if (bdp->status & OETH_TX_BD_RETLIM)
cep->stats.tx_aborted_errors++;
if (bdp->status & OETH_TX_BD_UNDERRUN)
cep->stats.tx_fifo_errors++;
if (bdp->status & OETH_TX_BD_CARRIER)
cep->stats.tx_carrier_errors++;
if (bdp->status & (OETH_TX_BD_LATECOL | OETH_TX_BD_RETLIM | OETH_TX_BD_UNDERRUN))
cep->stats.tx_errors++;
 
cep->stats.tx_packets++;
cep->stats.collisions += (bdp->status >> 4) & 0x000f;
 
#ifndef TXBUFF_PREALLOC
skb = cep->tx_skbuff[cep->tx_last];
 
/* Free the sk buffer associated with this last transmit.
*/
dev_kfree_skb(skb, FREE_WRITE);
#endif
 
if (cep->tx_full)
cep->tx_full = 0;
}
}
 
static void
oeth_rx(struct net_device *dev)
{
struct oeth_private *cep;
volatile oeth_bd *bdp;
struct sk_buff *skb;
int pkt_len;
int bad = 0;
#ifndef RXBUFF_PREALLOC
struct sk_buff *small_skb;
#endif
 
cep = (struct oeth_private *)dev->priv;
 
/* First, grab all of the stats for the incoming packet.
* These get messed up if we get called due to a busy condition.
*/
for (;;cep->rx_cur = (cep->rx_cur + 1) & OETH_RXBD_NUM_MASK) {
 
bdp = cep->rx_bd_base + cep->rx_cur;
 
#ifndef RXBUFF_PREALLOC
skb = cep->rx_skbuff[cep->rx_cur];
 
if (skb == NULL) {
 
skb = dev_alloc_skb(MAX_FRAME_SIZE);
 
if (skb != NULL)
{
bdp->addr = (unsigned long) skb->tail;
bdp->status |= OETH_RX_BD_EMPTY;
}
 
continue;
}
#endif
if (bdp->status & OETH_RX_BD_EMPTY)
break;
/* Check status for errors.
*/
if (bdp->status & (OETH_RX_BD_TOOLONG | OETH_RX_BD_SHORT)) {
cep->stats.rx_length_errors++;
bad = 1;
}
if (bdp->status & OETH_RX_BD_DRIBBLE) {
cep->stats.rx_frame_errors++;
bad = 1;
}
if (bdp->status & OETH_RX_BD_CRCERR) {
cep->stats.rx_crc_errors++;
bad = 1;
}
if (bdp->status & OETH_RX_BD_OVERRUN) {
cep->stats.rx_crc_errors++;
bad = 1;
}
if (bdp->status & OETH_RX_BD_MISS) {
 
}
if (bdp->status & OETH_RX_BD_LATECOL) {
cep->stats.rx_frame_errors++;
bad = 1;
}
if (bad) {
 
bdp->status &= ~OETH_RX_BD_STATS;
bdp->status |= OETH_RX_BD_EMPTY;
 
continue;
}
 
/* Process the incoming frame.
*/
pkt_len = bdp->len;
#ifdef RXBUFF_PREALLOC
skb = dev_alloc_skb(pkt_len);
if (skb == NULL) {
printk("%s: Memory squeeze, dropping packet.\n", dev->name);
cep->stats.rx_dropped++;
}
else {
skb->dev = dev;
#if DEBUG
_print("RX\n");
oeth_print_packet(bdp->addr, pkt_len);
#endif
memcpy(skb_put(skb, pkt_len), (unsigned char *)__va(bdp->addr), pkt_len);
skb->protocol = eth_type_trans(skb,dev);
netif_rx(skb);
cep->stats.rx_packets++;
}
 
bdp->status &= ~OETH_RX_BD_STATS;
bdp->status |= OETH_RX_BD_EMPTY;
#else
 
if (pkt_len < 128) {
 
small_skb = dev_alloc_skb(pkt_len);
 
if (small_skb) {
small_skb->dev = dev;
#if DEBUG
_print("RX short\n");
oeth_print_packet(bdp->addr, bdp->len);
#endif
memcpy(skb_put(small_skb, pkt_len), (unsigned char *)__va(bdp->addr), pkt_len);
small_skb->protocol = eth_type_trans(small_skb,dev);
netif_rx(small_skb);
cep->stats.rx_packets++;
}
else {
printk("%s: Memory squeeze, dropping packet.\n", dev->name);
cep->stats.rx_dropped++;
}
 
bdp->status &= ~OETH_RX_BD_STATS;
bdp->status |= OETH_RX_BD_EMPTY;
}
else {
skb->dev = dev;
skb_put(skb, bdp->len);
skb->protocol = eth_type_trans(skb,dev);
netif_rx(skb);
cep->stats.rx_packets++;
#if DEBUG
_print("RX long\n");
oeth_print_packet(bdp->addr, bdp->len);
#endif
skb = dev_alloc_skb(MAX_FRAME_SIZE);
 
bdp->status &= ~OETH_RX_BD_STATS;
if (skb) {
cep->rx_skbuff[cep->rx_cur] = skb;
 
bdp->addr = (unsigned long)skb->tail;
bdp->status |= OETH_RX_BD_EMPTY;
}
else {
cep->rx_skbuff[cep->rx_cur] = NULL;
}
}
#endif
}
}
 
static int calc_crc(char *mac_addr)
{
int result = 0;
return (result & 0x3f);
}
 
static struct enet_statistics *oeth_get_stats(struct net_device *dev)
{
struct oeth_private *cep = (struct oeth_private *)dev->priv;
return &cep->stats;
}
 
static void oeth_set_multicast_list(struct net_device *dev)
{
struct oeth_private *cep;
struct dev_mc_list *dmi;
volatile oeth_regs *regs;
int i;
 
cep = (struct oeth_private *)dev->priv;
 
/* Get pointer of controller registers.
*/
regs = (oeth_regs *)dev->base_addr;
 
if (dev->flags & IFF_PROMISC) {
/* Log any net taps.
*/
printk("%s: Promiscuous mode enabled.\n", dev->name);
regs->moder |= OETH_MODER_PRO;
} else {
 
regs->moder &= ~OETH_MODER_PRO;
 
if (dev->flags & IFF_ALLMULTI) {
 
/* Catch all multicast addresses, so set the
* filter to all 1's.
*/
regs->hash_addr0 = 0xffffffff;
regs->hash_addr1 = 0xffffffff;
}
else if (dev->mc_count) {
 
/* Clear filter and add the addresses in the list.
*/
regs->hash_addr0 = 0x00000000;
regs->hash_addr0 = 0x00000000;
 
dmi = dev->mc_list;
 
for (i = 0; i < dev->mc_count; i++) {
int hash_b;
 
/* Only support group multicast for now.
*/
if (!(dmi->dmi_addr[0] & 1))
continue;
 
hash_b = calc_crc(dmi->dmi_addr);
if(hash_b >= 32)
regs->hash_addr1 |= 1 << (hash_b - 32);
else
regs->hash_addr0 |= 1 << hash_b;
}
}
}
}
 
static void oeth_set_mac_add(struct net_device *dev, void *p)
{
struct sockaddr *addr=p;
volatile oeth_regs *regs;
 
memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
 
regs = (oeth_regs *)dev->base_addr;
 
regs->mac_addr1 = addr->sa_data[0] << 8 |
addr->sa_data[1];
regs->mac_addr0 = addr->sa_data[2] << 24 |
addr->sa_data[3] << 16 |
addr->sa_data[4] << 8 |
addr->sa_data[5];
}
 
/* Initialize the Open Ethernet MAC.
*/
int oeth_probe(struct net_device *dev)
{
struct oeth_private *cep;
volatile oeth_regs *regs;
volatile oeth_bd *tx_bd, *rx_bd;
int i, j, k;
 
cep = (struct oeth_private *)dev->priv;
 
/* Allocate a new 'dev' if needed.
*/
if (dev == NULL) {
/*
* Don't allocate the private data here, it is done later
* This makes it easier to free the memory when this driver
* is used as a module.
*/
dev = init_etherdev(0, 0);
if (dev == NULL)
return -ENOMEM;
}
 
/* Initialize the device structure.
*/
if (dev->priv == NULL) {
cep = (struct oeth_private *)kmalloc(sizeof(*cep), GFP_KERNEL);
dev->priv = cep;
if (dev->priv == NULL)
return -ENOMEM;
}
 
__clear_user(cep,sizeof(*cep));
 
/* Get pointer ethernet controller configuration registers.
*/
cep->regs = (oeth_regs *)(OETH_REG_BASE);
regs = (oeth_regs *)(OETH_REG_BASE);
 
/* Reset the controller.
*/
regs->moder = OETH_MODER_RST; /* Reset ON */
regs->moder &= OETH_MODER_RST; /* Reset OFF */
 
/* Setting TXBD base to OETH_TXBD_NUM.
*/
regs->tx_bd_num = OETH_TXBD_NUM << 1;
/* Initialize TXBD pointer
*/
cep->tx_bd_base = (oeth_bd *)OETH_BD_BASE;
tx_bd = (volatile oeth_bd *)OETH_BD_BASE;
 
/* Initialize RXBD pointer
*/
cep->rx_bd_base = ((oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
rx_bd = ((volatile oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
 
/* Initialize transmit pointers.
*/
cep->rx_cur = 0;
cep->tx_next = 0;
cep->tx_last = 0;
cep->tx_full = 0;
 
/* Set min/max packet length
*/
regs->packet_len = 0x003c0600;
 
/* Set IPGT register to recomended value
*/
regs->ipgt = 0x00000012;
 
/* Set IPGR1 register to recomended value
*/
regs->ipgr1 = 0x0000000c;
 
/* Set IPGR2 register to recomended value
*/
regs->ipgr2 = 0x00000012;
 
/* Set COLLCONF register to recomended value
*/
regs->collconf = 0x000f003f;
 
/* Set control module mode
*/
#if 0
regs->ctrlmoder = OETH_CTRLMODER_TXFLOW | OETH_CTRLMODER_RXFLOW;
#else
regs->ctrlmoder = 0;
#endif
 
#ifdef TXBUFF_PREALLOC
 
/* Initialize TXBDs.
*/
for(i = 0, k = 0; i < OETH_TX_BUFF_PAGE_NUM; i++) {
 
unsigned long mem_addr = __get_free_page(GFP_KERNEL);
 
for(j = 0; j < OETH_TX_BUFF_PPGAE; j++, k++) {
tx_bd[k].status = OETH_TX_BD_PAD | OETH_TX_BD_CRC | OETH_RX_BD_IRQ;
tx_bd[k].addr = __pa(mem_addr);
mem_addr += OETH_TX_BUFF_SIZE;
}
}
tx_bd[OETH_TXBD_NUM - 1].status |= OETH_TX_BD_WRAP;
#else
 
/* Initialize TXBDs.
*/
for(i = 0; i < OETH_TXBD_NUM; i++) {
 
cep->tx_skbuff[i] = NULL;
 
tx_bd[i].len = 0;
tx_bd[i].status = OETH_TX_BD_PAD | OETH_TX_BD_CRC | OETH_RX_BD_IRQ;
tx_bd[i].addr = 0;
}
tx_bd[OETH_TXBD_NUM - 1].status |= OETH_TX_BD_WRAP;
#endif
 
#ifdef RXBUFF_PREALLOC
 
/* Initialize RXBDs.
*/
for(i = 0, k = 0; i < OETH_RX_BUFF_PAGE_NUM; i++) {
 
unsigned long mem_addr = __get_free_page(GFP_KERNEL);
 
for(j = 0; j < OETH_RX_BUFF_PPGAE; j++, k++) {
rx_bd[k].status = OETH_RX_BD_EMPTY | OETH_RX_BD_IRQ;
rx_bd[k].addr = __pa(mem_addr);
mem_addr += OETH_RX_BUFF_SIZE;
}
}
rx_bd[OETH_RXBD_NUM - 1].status |= OETH_RX_BD_WRAP;
 
#else
/* Initialize RXBDs.
*/
for(i = 0; i < OETH_RXBD_NUM; i++) {
 
 
rx_bd[i].status = OETH_RX_BD_IRQ;
 
cep->rx_skbuff[i] = NULL;
 
rx_bd[i].len = 0;
rx_bd[i].addr = 0;
}
rx_bd[OETH_RXBD_NUM - 1].status |= OETH_RX_BD_WRAP;
 
#endif
 
/* Set default ethernet station address.
*/
dev->dev_addr[0] = MACADDR0;
dev->dev_addr[1] = MACADDR1;
dev->dev_addr[2] = MACADDR2;
dev->dev_addr[3] = MACADDR3;
dev->dev_addr[4] = MACADDR4;
dev->dev_addr[5] = MACADDR5;
 
regs->mac_addr1 = MACADDR0 << 8 | MACADDR1;
regs->mac_addr0 = MACADDR2 << 24 | MACADDR3 << 16 | MACADDR4 << 8 | MACADDR5;
/* Clear all pending interrupts
*/
regs->int_src = 0xffffffff;
 
/* Promisc, IFG, CRCEn
*/
regs->moder |= OETH_MODER_PAD | OETH_MODER_IFG | OETH_MODER_CRCEN;
 
/* Enable interrupt sources.
*/
regs->int_mask = OETH_INT_MASK_TXB |
OETH_INT_MASK_TXE |
OETH_INT_MASK_RXF |
OETH_INT_MASK_RXE |
OETH_INT_MASK_BUSY |
OETH_INT_MASK_TXC |
OETH_INT_MASK_RXC;
 
/* Fill in the fields of the device structure with ethernet values.
*/
ether_setup(dev);
 
dev->base_addr = (unsigned long)OETH_REG_BASE;
 
/* The Open Ethernet specific entries in the device structure.
*/
dev->open = oeth_open;
dev->hard_start_xmit = oeth_start_xmit;
dev->stop = oeth_close;
dev->get_stats = oeth_get_stats;
dev->set_multicast_list = oeth_set_multicast_list;
dev->set_mac_address = oeth_set_mac_add;
 
printk("%s: Open Ethernet Core Version 1.0\n", dev->name);
 
return 0;
}
 
 
/trunk/uclinux/uClinux-2.0.x/drivers/net/open_eth.h
0,0 → 1,140
 
/* Ethernet configuration registers */
typedef struct _oeth_regs {
uint moder; /* Mode Register */
uint int_src; /* Interrupt Source Register */
uint int_mask; /* Interrupt Mask Register */
uint ipgt; /* Back to Bak Inter Packet Gap Register */
uint ipgr1; /* Non Back to Back Inter Packet Gap Register 1 */
uint ipgr2; /* Non Back to Back Inter Packet Gap Register 2 */
uint packet_len; /* Packet Length Register (min. and max.) */
uint collconf; /* Collision and Retry Configuration Register */
uint tx_bd_num; /* Transmit Buffer Descriptor Number Register */
uint ctrlmoder; /* Control Module Mode Register */
uint miimoder; /* MII Mode Register */
uint miicommand; /* MII Command Register */
uint miiaddress; /* MII Address Register */
uint miitx_data; /* MII Transmit Data Register */
uint miirx_data; /* MII Receive Data Register */
uint miistatus; /* MII Status Register */
uint mac_addr0; /* MAC Individual Address Register 0 */
uint mac_addr1; /* MAC Individual Address Register 1 */
uint hash_addr0; /* Hash Register 0 */
uint hash_addr1; /* Hash Register 1 */
} oeth_regs;
 
/* Ethernet buffer descriptor */
typedef struct _oeth_bd {
ushort len; /* Buffer length */
ushort status; /* Buffer status */
uint addr; /* Buffer address */
} oeth_bd;
 
#define OETH_REG_BASE ETH_BASE_ADD
#define OETH_BD_BASE (ETH_BASE_ADD + 0x400)
#define OETH_TOTAL_BD 128
#define OETH_MAXBUF_LEN 0x600
/* Tx BD */
#define OETH_TX_BD_READY 0x8000 /* Tx BD Ready */
#define OETH_TX_BD_IRQ 0x4000 /* Tx BD IRQ Enable */
#define OETH_TX_BD_WRAP 0x2000 /* Tx BD Wrap (last BD) */
#define OETH_TX_BD_PAD 0x1000 /* Tx BD Pad Enable */
#define OETH_TX_BD_CRC 0x0800 /* Tx BD CRC Enable */
#define OETH_TX_BD_UNDERRUN 0x0100 /* Tx BD Underrun Status */
#define OETH_TX_BD_RETRY 0x00F0 /* Tx BD Retry Status */
#define OETH_TX_BD_RETLIM 0x0008 /* Tx BD Retransmission Limit Status */
#define OETH_TX_BD_LATECOL 0x0004 /* Tx BD Late Collision Status */
#define OETH_TX_BD_DEFER 0x0002 /* Tx BD Defer Status */
#define OETH_TX_BD_CARRIER 0x0001 /* Tx BD Carrier Sense Lost Status */
#define OETH_TX_BD_STATS (OETH_TX_BD_UNDERRUN | \
OETH_TX_BD_RETRY | \
OETH_TX_BD_RETLIM | \
OETH_TX_BD_LATECOL | \
OETH_TX_BD_DEFER | \
OETH_TX_BD_CARRIER)
/* Rx BD */
#define OETH_RX_BD_EMPTY 0x8000 /* Rx BD Empty */
#define OETH_RX_BD_IRQ 0x4000 /* Rx BD IRQ Enable */
#define OETH_RX_BD_WRAP 0x2000 /* Rx BD Wrap (last BD) */
#define OETH_RX_BD_MISS 0x0080 /* Rx BD Miss Status */
#define OETH_RX_BD_OVERRUN 0x0040 /* Rx BD Overrun Status */
#define OETH_RX_BD_INVSIMB 0x0020 /* Rx BD Invalid Symbol Status */
#define OETH_RX_BD_DRIBBLE 0x0010 /* Rx BD Dribble Nibble Status */
#define OETH_RX_BD_TOOLONG 0x0008 /* Rx BD Too Long Status */
#define OETH_RX_BD_SHORT 0x0004 /* Rx BD Too Short Frame Status */
#define OETH_RX_BD_CRCERR 0x0002 /* Rx BD CRC Error Status */
#define OETH_RX_BD_LATECOL 0x0001 /* Rx BD Late Collision Status */
#define OETH_RX_BD_STATS (OETH_RX_BD_MISS | \
OETH_RX_BD_OVERRUN | \
OETH_RX_BD_INVSIMB | \
OETH_RX_BD_DRIBBLE | \
OETH_RX_BD_TOOLONG | \
OETH_RX_BD_SHORT | \
OETH_RX_BD_CRCERR | \
OETH_RX_BD_LATECOL)
 
/* MODER Register */
#define OETH_MODER_RXEN 0x00000001 /* Receive Enable */
#define OETH_MODER_TXEN 0x00000002 /* Transmit Enable */
#define OETH_MODER_NOPRE 0x00000004 /* No Preamble */
#define OETH_MODER_BRO 0x00000008 /* Reject Broadcast */
#define OETH_MODER_IAM 0x00000010 /* Use Individual Hash */
#define OETH_MODER_PRO 0x00000020 /* Promiscuous (receive all) */
#define OETH_MODER_IFG 0x00000040 /* Min. IFG not required */
#define OETH_MODER_LOOPBCK 0x00000080 /* Loop Back */
#define OETH_MODER_NOBCKOF 0x00000100 /* No Backoff */
#define OETH_MODER_EXDFREN 0x00000200 /* Excess Defer */
#define OETH_MODER_FULLD 0x00000400 /* Full Duplex */
#define OETH_MODER_RST 0x00000800 /* Reset MAC */
#define OETH_MODER_DLYCRCEN 0x00001000 /* Delayed CRC Enable */
#define OETH_MODER_CRCEN 0x00002000 /* CRC Enable */
#define OETH_MODER_HUGEN 0x00004000 /* Huge Enable */
#define OETH_MODER_PAD 0x00008000 /* Pad Enable */
#define OETH_MODER_RECSMALL 0x00010000 /* Receive Small */
/* Interrupt Source Register */
#define OETH_INT_TXB 0x00000001 /* Transmit Buffer IRQ */
#define OETH_INT_TXE 0x00000002 /* Transmit Error IRQ */
#define OETH_INT_RXF 0x00000004 /* Receive Frame IRQ */
#define OETH_INT_RXE 0x00000008 /* Receive Error IRQ */
#define OETH_INT_BUSY 0x00000010 /* Busy IRQ */
#define OETH_INT_TXC 0x00000020 /* Transmit Control Frame IRQ */
#define OETH_INT_RXC 0x00000040 /* Received Control Frame IRQ */
 
/* Interrupt Mask Register */
#define OETH_INT_MASK_TXB 0x00000001 /* Transmit Buffer IRQ Mask */
#define OETH_INT_MASK_TXE 0x00000002 /* Transmit Error IRQ Mask */
#define OETH_INT_MASK_RXF 0x00000004 /* Receive Frame IRQ Mask */
#define OETH_INT_MASK_RXE 0x00000008 /* Receive Error IRQ Mask */
#define OETH_INT_MASK_BUSY 0x00000010 /* Busy IRQ Mask */
#define OETH_INT_MASK_TXC 0x00000020 /* Transmit Control Frame IRQ Mask */
#define OETH_INT_MASK_RXC 0x00000040 /* Received Control Frame IRQ Mask */
/* Control Module Mode Register */
#define OETH_CTRLMODER_PASSALL 0x00000001 /* Pass Control Frames */
#define OETH_CTRLMODER_RXFLOW 0x00000002 /* Receive Control Flow Enable */
#define OETH_CTRLMODER_TXFLOW 0x00000004 /* Transmit Control Flow Enable */
/* MII Mode Register */
#define OETH_MIIMODER_CLKDIV 0x000000FF /* Clock Divider */
#define OETH_MIIMODER_NOPRE 0x00000100 /* No Preamble */
#define OETH_MIIMODER_RST 0x00000200 /* MIIM Reset */
/* MII Command Register */
#define OETH_MIICOMMAND_SCANSTAT 0x00000001 /* Scan Status */
#define OETH_MIICOMMAND_RSTAT 0x00000002 /* Read Status */
#define OETH_MIICOMMAND_WCTRLDATA 0x00000004 /* Write Control Data */
/* MII Address Register */
#define OETH_MIIADDRESS_FIAD 0x0000001F /* PHY Address */
#define OETH_MIIADDRESS_RGAD 0x00001F00 /* RGAD Address */
/* MII Status Register */
#define OETH_MIISTATUS_LINKFAIL 0x00000001 /* Link Fail */
#define OETH_MIISTATUS_BUSY 0x00000002 /* MII Busy */
#define OETH_MIISTATUS_NVALID 0x00000004 /* Data in MII Status Register is invalid */
 
/trunk/uclinux/uClinux-2.0.x/drivers/net/CONFIG
99,3 → 99,4
DEFXX_OPTS =
ELP_OPTS =
TULIP_OPTS =
OETH_OPTS =
/trunk/uclinux/uClinux-2.0.x/drivers/block/rd.c
99,7 → 99,7
* architecture-specific setup routine (from the stored bootsector
* information).
*/
int rd_size = 1024; /* Size of the ramdisks */
int rd_size = 2048; /* Size of the ramdisks */
 
#ifndef MODULE
int rd_doload = 0; /* 1 = load ramdisk, 0 = don't load */

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