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URL https://opencores.org/ocsvn/or1k/or1k/trunk

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 743 to Rev 744
    ↔ Reverse comparison
  •

Rev 743 → Rev 744

/trunk/or1ksim/peripheral/eth.c
148,6 → 148,7
/* stay in this state if (TXEN && !READY) */
break;
case ETH_TXSTATE_READFIFO:
#if 1
if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
read_word = eval_mem32(eth->tx.bytes_sent + eth->tx.bd_addr, &breakpoint);
eth->tx_buff[eth->tx.bytes_sent] = (unsigned char)(read_word >> 24);
156,6 → 157,12
eth->tx_buff[eth->tx.bytes_sent+3] = (unsigned char)(read_word);
eth->tx.bytes_sent += 4;
}
#else
if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
eth->tx_buff[eth->tx.bytes_sent] = eval_mem8(eth->tx.bytes_sent + eth->tx.bd_addr, &breakpoint);
eth->tx.bytes_sent += 1;
}
#endif
else {
debug (3, "TX - entering state TRANSMIT\n");
eth->tx.state = ETH_TXSTATE_TRANSMIT;
276,7 → 283,7
eth->rx.state = ETH_RXSTATE_IDLE;
}
else {
nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, MSG_PEEK | MSG_DONTWAIT);
nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, /*MSG_PEEK | */MSG_DONTWAIT);
if (nread > 0) {
SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, BUSY);
if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, BUSY_M) )
319,8 → 326,11
case ETH_RTX_SOCK:
nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, MSG_DONTWAIT);
if (nread < 0) {
if ( errno != EAGAIN ) {
 
if (nread == 0)
break;
else if (nread < 0) {
if ( errno != EAGAIN ) {
debug (3, "recv() FAILED!\n");
break;
}
327,7 → 337,23
else {
break;
}
}
}
/* If not promiscouos mode, check the destination address */
if (!TEST_FLAG(eth->regs.moder, ETH_MODER, PRO)) {
if (TEST_FLAG(eth->regs.moder, ETH_MODER, IAM) && (eth->rx_buff[0] & 1)) {
/* Nothing for now */
}
 
if (eth->mac_address[5] != eth->rx_buff[0] ||
eth->mac_address[4] != eth->rx_buff[1] ||
eth->mac_address[3] != eth->rx_buff[2] ||
eth->mac_address[2] != eth->rx_buff[3] ||
eth->mac_address[1] != eth->rx_buff[4] ||
eth->mac_address[0] != eth->rx_buff[5])
break;
}
eth->rx.packet_length = nread;
eth->rx.bytes_left = nread;
eth->rx.bytes_read = 0;
339,16 → 365,22
break;
case ETH_RXSTATE_WRITEFIFO:
#if 1
send_word = ((unsigned long)eth->rx_buff[eth->rx.bytes_read] << 24) |
((unsigned long)eth->rx_buff[eth->rx.bytes_read+1] << 16) |
((unsigned long)eth->rx_buff[eth->rx.bytes_read+2] << 8) |
((unsigned long)eth->rx_buff[eth->rx.bytes_read+3] );
set_mem32( eth->rx.bd_addr + eth->rx.bytes_read, send_word, &breakpoint);
/* update counters */
debug (3, "Write %d, left %d - %08lXd\n", eth->rx.bytes_read, eth->rx.bytes_left, send_word);
eth->rx.bytes_left -= 4;
eth->rx.bytes_read += 4;
#else
set_mem8( eth->rx.bd_addr + eth->rx.bytes_read, eth->rx_buff[eth->rx.bytes_read], &breakpoint);
eth->rx.bytes_left -= 1;
eth->rx.bytes_read += 1;
#endif
if ( eth->rx.bytes_left <= 0 ) {
/* Write result to bd */
SET_FIELD( eth->rx.bd, ETH_RX_BD, LENGTH, eth->rx.packet_length );
356,9 → 388,9
SET_FLAG( eth->regs.int_source, ETH_INT_SOURCE, RXB);
if ( eth->rx.packet_length < GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MINFL ) )
SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOSHORT);
if ( eth->rx.packet_length > GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MAXFL ) )
SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOBIG);
if ( eth->rx.packet_length > GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MAXFL ) )
SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOSHORT);
eth->regs.bd_ram[eth->rx.bd_index] = eth->rx.bd;
600,6 → 632,8
printf( "MAC Address : %02X:%02X:%02X:%02X:%02X:%02X\n",
eth->mac_address[0], eth->mac_address[1], eth->mac_address[2],
eth->mac_address[3], eth->mac_address[4], eth->mac_address[5] );
printf( "HASH0 : 0x%08lX\n", eth->regs.hash0 );
printf( "HASH1 : 0x%08lX\n", eth->regs.hash1 );
}
}
/* ========================================================================= */
654,6 → 688,8
(unsigned long)eth->mac_address[0];
case ETH_MAC_ADDR1: return (((unsigned long)eth->mac_address[5]) << 8) |
(unsigned long)eth->mac_address[4];
case ETH_HASH0: return eth->regs.hash0;
case ETH_HASH1: return eth->regs.hash1;
/*case ETH_DMA_RX_TX: return eth_rx( eth );*/
}
 
680,7 → 716,7
switch( addr ) {
case ETH_MODER: eth->regs.moder = value; return;
case ETH_INT_SOURCE: eth->regs.int_source = value; return;
case ETH_INT_SOURCE: eth->regs.int_source &= ~value; return;
case ETH_INT_MASK: eth->regs.int_mask = value; return;
case ETH_IPGT: eth->regs.ipgt = value; return;
case ETH_IPGR1: eth->regs.ipgr1 = value; return;
705,6 → 741,8
eth->mac_address[4] = value & 0xFF;
eth->mac_address[5] = (value >> 8) & 0xFF;
return;
case ETH_HASH0: eth->regs.hash0 = value; return;
case ETH_HASH1: eth->regs.hash1 = value; return;
/*case ETH_DMA_RX_TX: eth_tx( eth, value ); return;*/
}
/trunk/or1ksim/peripheral/ethernet.h
49,6 → 49,8
#define ETH_MIISTATUS (4 * 0x0F)
#define ETH_MAC_ADDR0 (4 * 0x10)
#define ETH_MAC_ADDR1 (4 * 0x11)
#define ETH_HASH0 (4 * 0x12)
#define ETH_HASH1 (4 * 0x13)
 
/* Where BD's are stored */
#define ETH_BD_BASE 0x400
/trunk/or1ksim/peripheral/ethernet_i.h
178,6 → 178,8
unsigned long miitx_data;
unsigned long miirx_data;
unsigned long miistatus;
unsigned long hash0;
unsigned long hash1;
/* Buffer descriptors */
unsigned long bd_ram[ETH_BD_SPACE / 4];

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