URL
https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk
Subversion Repositories dbg_interface
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 75 to Rev 76
- ↔ Reverse comparison
Rev 75 → Rev 76
/tags/rel_10/bench/verilog/timescale.v
0,0 → 1,?rev2len?
`timescale 1ns/10ps |
tags/rel_10/bench/verilog/timescale.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/rel_10/bench/verilog/dbg_tb.v
===================================================================
--- tags/rel_10/bench/verilog/dbg_tb.v (nonexistent)
+++ tags/rel_10/bench/verilog/dbg_tb.v (revision 76)
@@ -0,0 +1,1032 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// dbg_tb.v ////
+//// ////
+//// ////
+//// This file is part of the SoC/OpenRISC Development Interface ////
+//// http://www.opencores.org/projects/DebugInterface/ ////
+//// ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor ////
+//// igorm@opencores.org ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000,2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.13 2003/08/28 13:54:33 simons
+// Three more chains added for cpu debug access.
+//
+// Revision 1.12 2002/05/07 14:44:52 mohor
+// mon_cntl_o signals that controls monitor mux added.
+//
+// Revision 1.11 2002/03/12 14:32:26 mohor
+// Few outputs for boundary scan chain added.
+//
+// Revision 1.10 2002/03/08 15:27:08 mohor
+// Structure changed. Hooks for jtag chain added.
+//
+// Revision 1.9 2001/10/19 11:39:20 mohor
+// dbg_timescale.v changed to timescale.v This is done for the simulation of
+// few different cores in a single project.
+//
+// Revision 1.8 2001/10/17 10:39:17 mohor
+// bs_chain_o added.
+//
+// Revision 1.7 2001/10/16 10:10:18 mohor
+// Signal names changed to lowercase.
+//
+// Revision 1.6 2001/10/15 09:52:50 mohor
+// Wishbone interface added, few fixes for better performance,
+// hooks for boundary scan testing added.
+//
+// Revision 1.5 2001/09/24 14:06:12 mohor
+// Changes connected to the OpenRISC access (SPR read, SPR write).
+//
+// Revision 1.4 2001/09/20 10:10:29 mohor
+// Working version. Few bugs fixed, comments added.
+//
+// Revision 1.3 2001/09/19 11:54:03 mohor
+// Minor changes for simulation.
+//
+// Revision 1.2 2001/09/18 14:12:43 mohor
+// Trace fixed. Some registers changed, trace simplified.
+//
+// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
+// Initial official release.
+//
+// Revision 1.3 2001/06/01 22:23:40 mohor
+// This is a backup. It is not a fully working version. Not for use, yet.
+//
+// Revision 1.2 2001/05/18 13:10:05 mohor
+// Headers changed. All additional information is now avaliable in the README.txt file.
+//
+// Revision 1.1.1.1 2001/05/18 06:35:15 mohor
+// Initial release
+//
+//
+
+
+`include "timescale.v"
+`include "dbg_defines.v"
+`include "dbg_tb_defines.v"
+
+// Test bench
+module dbg_tb;
+
+parameter Tp = 1;
+parameter Tclk = 50; // Clock half period (Clok period = 100 ns => 10 MHz)
+
+
+reg P_TMS, P_TCK;
+reg P_TRST, P_TDI;
+reg wb_rst_i;
+reg Mclk;
+
+reg [10:0] Wp;
+reg Bp;
+reg [3:0] LsStatus;
+reg [1:0] IStatus;
+reg BS_CHAIN_I;
+reg MBIST_I;
+
+wire P_TDO;
+wire [31:0] ADDR_CPU;
+wire [31:0] DATAIN_CPU; // DATAIN_CPU is connect to DATAOUT
+
+wire [31:0] DATAOUT_CPU; // DATAOUT_CPU is connect to DATAIN
+
+wire [`OPSELECTWIDTH-1:0] OpSelect;
+
+wire [31:0] wb_adr_i;
+wire [31:0] wb_dat_i;
+reg [31:0] wb_dat_o;
+wire wb_cyc_i;
+wire wb_stb_i;
+wire [3:0] wb_sel_i;
+wire wb_we_i;
+reg wb_ack_o;
+wire wb_cab_i;
+reg wb_err_o;
+
+wire ShiftDR;
+wire Exit1DR;
+wire UpdateDR;
+wire UpdateDR_q;
+wire CaptureDR;
+wire SelectDRScan;
+wire IDCODESelected;
+wire CHAIN_SELECTSelected;
+wire DEBUGSelected;
+wire TDOData_dbg;
+wire BypassRegister;
+wire EXTESTSelected;
+wire MBISTSelected;
+wire [3:0] mon_cntl_o;
+wire CpuDebugScanChain0;
+wire CpuDebugScanChain1;
+wire CpuDebugScanChain2;
+wire CpuDebugScanChain3;
+
+
+// Connecting TAP module
+tap_top i_tap_top
+ (.tms_pad_i(P_TMS), .tck_pad_i(P_TCK), .trst_pad_i(P_TRST), .tdi_pad_i(P_TDI),
+ .tdo_pad_o(P_TDO), .tdo_padoe_o(tdo_padoe_o),
+
+ // TAP states
+ .ShiftDR(ShiftDR), .Exit1DR(Exit1DR), .UpdateDR(UpdateDR), .UpdateDR_q(UpdateDR_q),
+ .CaptureDR(CaptureDR), .SelectDRScan(SelectDRScan),
+
+ // Instructions
+ .IDCODESelected(IDCODESelected), .CHAIN_SELECTSelected(CHAIN_SELECTSelected),
+ .DEBUGSelected(DEBUGSelected), .EXTESTSelected(EXTESTSelected),
+ .MBISTSelected(MBISTSelected),
+
+ // TDO from dbg module
+ .TDOData_dbg(TDOData_dbg), .BypassRegister(BypassRegister),
+
+ // Boundary Scan Chain
+ .bs_chain_i(BS_CHAIN_I),
+
+ // From Mbist Chain
+ .mbist_so_i(MBIST_I),
+
+ // Selected chains
+ .RegisterScanChain(RegisterScanChain),
+ .CpuDebugScanChain0(CpuDebugScanChain0),
+ .CpuDebugScanChain1(CpuDebugScanChain1),
+ .CpuDebugScanChain2(CpuDebugScanChain2),
+ .CpuDebugScanChain3(CpuDebugScanChain3),
+ .WishboneScanChain(WishboneScanChain)
+
+ );
+
+
+
+dbg_top i_dbg_top
+ (
+ .cpu_clk_i(Mclk), .cpu_addr_o(ADDR_CPU), .cpu_data_i(DATAOUT_CPU),
+ .cpu_data_o(DATAIN_CPU), .wp_i(Wp), .bp_i(Bp), .opselect_o(OpSelect),
+ .lsstatus_i(LsStatus), .istatus_i(IStatus), .cpu_stall_o(),
+ .cpu_stall_all_o(), .cpu_sel_o(), .reset_o(),
+
+ .wb_rst_i(wb_rst_i), .wb_clk_i(Mclk),
+
+ .wb_adr_o(wb_adr_i), .wb_dat_o(wb_dat_i), .wb_dat_i(wb_dat_o),
+ .wb_cyc_o(wb_cyc_i), .wb_stb_o(wb_stb_i), .wb_sel_o(wb_sel_i),
+ .wb_we_o(wb_we_i), .wb_ack_i(wb_ack_o), .wb_cab_o(wb_cab_i),
+ .wb_err_i(wb_err_o),
+
+ // TAP states
+ .ShiftDR(ShiftDR), .Exit1DR(Exit1DR), .UpdateDR(UpdateDR), .UpdateDR_q(UpdateDR_q),
+ .SelectDRScan(SelectDRScan),
+
+ // Instructions
+ .IDCODESelected(IDCODESelected), .CHAIN_SELECTSelected(CHAIN_SELECTSelected),
+ .DEBUGSelected(DEBUGSelected),
+
+ // TAP signals
+ .trst_in(P_TRST), .tck(P_TCK), .tdi(P_TDI), .TDOData(TDOData_dbg),
+
+ .BypassRegister(BypassRegister),
+
+
+ .mon_cntl_o(mon_cntl_o),
+
+ // Selected chains
+ .RegisterScanChain(RegisterScanChain),
+ .CpuDebugScanChain0(CpuDebugScanChain0),
+ .CpuDebugScanChain1(CpuDebugScanChain1),
+ .CpuDebugScanChain2(CpuDebugScanChain2),
+ .CpuDebugScanChain3(CpuDebugScanChain3),
+ .WishboneScanChain(WishboneScanChain)
+
+ );
+
+reg TestEnabled;
+
+
+
+initial
+begin
+ TestEnabled<=#Tp 0;
+ P_TMS<=#Tp 'hz;
+ P_TCK<=#Tp 'hz;
+ P_TDI<=#Tp 'hz;
+ BS_CHAIN_I = 0;
+ MBIST_I = 0;
+
+ Wp<=#Tp 0;
+ Bp<=#Tp 0;
+ LsStatus<=#Tp 0;
+ IStatus<=#Tp 0;
+
+ wb_dat_o<=#Tp 32'h0;
+ wb_ack_o<=#Tp 1'h0;
+ wb_err_o<=#Tp 1'h0;
+
+
+
+ wb_rst_i<=#Tp 0;
+ P_TRST<=#Tp 0;
+ #100 wb_rst_i<=#Tp 1;
+ P_TRST<=#Tp 1;
+ #100 wb_rst_i<=#Tp 0;
+ P_TRST<=#Tp 0;
+ #Tp TestEnabled<=#Tp 1;
+end
+
+
+// Generating master clock (cpu clock) 200 MHz
+initial
+begin
+ Mclk<=#Tp 0;
+ #1 forever #`CPU_CLOCK Mclk<=~Mclk;
+end
+
+
+// Generating random number for use in DATAOUT_CPU[31:0]
+reg [31:0] RandNumb;
+always @ (posedge Mclk or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ RandNumb[31:0]<=#Tp 0;
+ else
+ RandNumb[31:0]<=#Tp RandNumb[31:0] + 1;
+end
+
+
+assign DATAOUT_CPU[31:0] = RandNumb[31:0];
+
+
+always @ (posedge TestEnabled)
+begin
+
+ $display("//////////////////////////////////////////////////////////////////////////////////////");
+ $display("// //");
+ $display("// (%0t) dbg_tb starting //", $time);
+ $display("// //");
+ $display("//////////////////////////////////////////////////////////////////////////////////////");
+
+ fork
+
+
+ begin
+ EnableWishboneSlave; // enabling WISHBONE slave
+ end
+
+
+ begin
+ ResetTAP;
+ GotoRunTestIdle;
+
+ // Testing read and write to WISHBONE (WB and CPU chain are the same)
+ SetInstruction(`CHAIN_SELECT);
+ ChainSelect(`WISHBONE_SCAN_CHAIN, 8'h36); // {chain, crc}
+ SetInstruction(`DEBUG);
+ WriteCPURegister(32'h18273645, 32'hbeefbeef, 8'haa); // {data, addr, crc}
+
+ #10000;
+ ReadCPURegister(32'h87654321, 8'hfd); // {addr, crc} // Wishbone and CPU accesses are similar
+ ReadCPURegister(32'h87654321, 8'hfd); // {addr, crc} // Wishbone and CPU accesses are similar
+
+ // Testing read and write to CPU0 registers
+ #10000;
+ SetInstruction(`CHAIN_SELECT);
+ ChainSelect(`CPU_DEBUG_CHAIN_0, 8'h12); // {chain, crc}
+ SetInstruction(`DEBUG);
+ WriteCPURegister(32'h11001100, 32'h00110011, 8'h86); // {data, addr, crc}
+
+ ReadCPURegister(32'h11001100, 8'hdb); // {addr, crc}
+ ReadCPURegister(32'h11001100, 8'hdb); // {addr, crc}
+
+ // Testing read and write to CPU1 registers
+ #10000;
+ SetInstruction(`CHAIN_SELECT);
+ ChainSelect(`CPU_DEBUG_CHAIN_1, 8'h2a); // {chain, crc}
+ SetInstruction(`DEBUG);
+ WriteCPURegister(32'h22002200, 32'h00220022, 8'h10); // {data, addr, crc}
+
+ ReadCPURegister(32'h22002200, 8'hee); // {addr, crc}
+ ReadCPURegister(32'h22002200, 8'hee); // {addr, crc}
+
+ // Testing read and write to CPU2 registers
+ #10000;
+ SetInstruction(`CHAIN_SELECT);
+ ChainSelect(`CPU_DEBUG_CHAIN_2, 8'h38); // {chain, crc}
+ SetInstruction(`DEBUG);
+ WriteCPURegister(32'h33003300, 32'h00330033, 8'hf4); // {data, addr, crc}
+
+ ReadCPURegister(32'h33003300, 8'h35); // {addr, crc}
+ ReadCPURegister(32'h33003300, 8'h35); // {addr, crc}
+
+ // Testing read and write to CPU3 registers
+ #10000;
+ SetInstruction(`CHAIN_SELECT);
+ ChainSelect(`CPU_DEBUG_CHAIN_3, 8'h07); // {chain, crc}
+ SetInstruction(`DEBUG);
+ WriteCPURegister(32'h44004400, 32'h00440044, 8'h5b); // {data, addr, crc}
+
+ ReadCPURegister(32'h44004400, 8'h77); // {addr, crc}
+ ReadCPURegister(32'h44004400, 8'h77); // {addr, crc}
+
+ // Testing read and write to internal registers
+ #10000;
+ SetInstruction(`IDCODE);
+ ReadIDCode;
+
+ SetInstruction(`CHAIN_SELECT);
+ ChainSelect(`REGISTER_SCAN_CHAIN, 8'h0e); // {chain, crc}
+ SetInstruction(`DEBUG);
+
+
+ // Testing internal registers
+ WriteRegister(32'h00000001, `CPUOP_ADR, 8'h4a); // {data, addr, crc}
+ WriteRegister(32'h00000002, `CPUOP_ADR, 8'he0); // {data, addr, crc}
+ WriteRegister(32'h00000004, `CPUOP_ADR, 8'hb5); // {data, addr, crc}
+ WriteRegister(32'h00000000, `CPUSEL_ADR, 8'h1f); // {data, addr, crc}
+ WriteRegister(32'h00000001, `CPUSEL_ADR, 8'h2e); // {data, addr, crc}
+ WriteRegister(32'h00000002, `CPUSEL_ADR, 8'h84); // {data, addr, crc}
+
+ ReadRegister(`CPUOP_ADR, 8'h19); // {addr, crc}
+ ReadRegister(`CPUOP_ADR, 8'h19); // {addr, crc}
+ ReadRegister(`CPUSEL_ADR, 8'h7d); // {addr, crc}
+ ReadRegister(`CPUSEL_ADR, 8'h7d); // {addr, crc}
+
+ //ReadRegister(`MODER_ADR, 8'h00); // {addr, crc}
+ //ReadRegister(`TSEL_ADR, 8'h64); // {addr, crc}
+ //ReadRegister(`QSEL_ADR, 8'h32); // {addr, crc}
+ //ReadRegister(`SSEL_ADR, 8'h56); // {addr, crc}
+ //ReadRegister(`RECSEL_ADR, 8'hc4); // {addr, crc}
+ //ReadRegister(`MON_CNTL_ADR, 8'ha0); // {addr, crc}
+ //ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
+ //ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
+
+ //WriteRegister(32'h00000001, `MODER_ADR, 8'h53); // {data, addr, crc}
+ //WriteRegister(32'h00000020, `TSEL_ADR, 8'h5e); // {data, addr, crc}
+ //WriteRegister(32'h00000300, `QSEL_ADR, 8'hdd); // {data, addr, crc}
+ //WriteRegister(32'h00004000, `SSEL_ADR, 8'he2); // {data, addr, crc}
+ //WriteRegister(32'h0000dead, `RECSEL_ADR, 8'hfb); // {data, addr, crc}
+ //WriteRegister(32'h0000000d, `MON_CNTL_ADR, 8'h5a); // {data, addr, crc}
+
+
+ // testing trigger and qualifier
+ `ifdef TRACE_ENABLED
+ // Anything starts trigger and qualifier
+ #1000 WriteRegister(32'h00000000, `QSEL_ADR, 8'h50); // Any qualifier
+ #1000 WriteRegister(32'h00000000, `TSEL_ADR, 8'h06); // Any trigger
+ #1000 WriteRegister(32'h00000003, `RECSEL_ADR, 8'h0c); // Two samples are selected for recording (RECPC and RECLSEA)
+ #100 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
+ #1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
+ // End: Anything starts trigger and qualifier //
+
+ /* Anything starts trigger, breakpoint starts qualifier
+ // Uncomment this part when you want to test it.
+ #1000 WriteRegister(`QUALIFOP_OR | `BPQUALIFVALID | `BPQUALIF, `QSEL_ADR, 8'had); // Any qualifier
+ #1000 WriteRegister(32'h00000000, `TSEL_ADR, 8'h06); // Any trigger
+ #1000 WriteRegister(32'h0000000c, `RECSEL_ADR, 8'h0f); // Two samples are selected for recording (RECSDATA and RECLDATA)
+ #1000 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
+ #1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
+ wait(dbg_tb.i_dbg_top.TraceEnable)
+ @ (posedge Mclk);
+ #1 Bp = 1; // Set breakpoint
+ repeat(8) @(posedge Mclk);
+ wait(dbg_tb.i_dbg_top.dbgTrace1.CpuStall)
+ #1 Bp = 0; // Clear breakpoint
+ // End: Anything starts trigger, breakpoint starts qualifier */
+
+ /* Anything starts qualifier, breakpoint starts trigger
+ // Uncomment this part when you want to test it.
+ #1000 WriteRegister(32'h00000000, `QSEL_ADR, 8'h50); // Any qualifier
+ #1000 WriteRegister(`LSSTRIG_0 | `LSSTRIG_2 | `LSSTRIGVALID | `WPTRIG_4 | `WPTRIGVALID | `TRIGOP_AND, `TSEL_ADR, 8'had); // Trigger is AND of Watchpoint4 and LSSTRIG[0] and LSSTRIG[2]
+ #1000 WriteRegister(32'h00000003, `RECSEL_ADR, 8'h0c); // Two samples are selected for recording (RECPC and RECLSEA)
+ #1000 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
+ #1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
+ wait(dbg_tb.i_dbg_top.TraceEnable)
+ @ (posedge Mclk)
+ Wp[4] = 1; // Set watchpoint[4]
+ LsStatus = 4'h5; // LsStatus[0] and LsStatus[2] are active
+ @ (posedge Mclk)
+ Wp[4] = 0; // Clear watchpoint[4]
+ LsStatus = 4'h0; // LsStatus[0] and LsStatus[2] are cleared
+ // End: Anything starts trigger and qualifier */
+
+ // Reading data from the trace buffer
+ SetInstruction(`CHAIN_SELECT);
+ ChainSelect(`TRACE_TEST_CHAIN, 8'h24); // {chain, crc}
+ SetInstruction(`DEBUG);
+ ReadTraceBuffer;
+ ReadTraceBuffer;
+ ReadTraceBuffer;
+ ReadTraceBuffer;
+ ReadTraceBuffer;
+ ReadTraceBuffer;
+ ReadTraceBuffer;
+ ReadTraceBuffer;
+ ReadTraceBuffer;
+ ReadTraceBuffer;
+ ReadTraceBuffer;
+ ReadTraceBuffer;
+ `endif // TRACE_ENABLED
+
+
+
+
+ #5000 GenClk(1); // One extra TCLK for debugging purposes
+ #1000 $stop;
+
+ end
+ join
+end
+
+// Generation of the TCLK signal
+task GenClk;
+ input [7:0] Number;
+ integer i;
+ begin
+ for(i=0; i
tags/rel_10/sim/rtl_sim/log/dir_keeper
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/rel_10/sim/rtl_sim/run/clean
===================================================================
--- tags/rel_10/sim/rtl_sim/run/clean (nonexistent)
+++ tags/rel_10/sim/rtl_sim/run/clean (revision 76)
@@ -0,0 +1,4 @@
+rm ../bin/INCA_libs/worklib/*
+rm ../bin/INCA_libs/worklib/.*
+rm ../log/*.log
+rm -rf ../out/*.shm
tags/rel_10/sim/rtl_sim/run/clean
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/rel_10/sim/rtl_sim/run/run_sim.scr
===================================================================
--- tags/rel_10/sim/rtl_sim/run/run_sim.scr (nonexistent)
+++ tags/rel_10/sim/rtl_sim/run/run_sim.scr (revision 76)
@@ -0,0 +1,72 @@
+#!/bin/csh -f
+
+if ( $# < 1 ) then
+ echo "First argument must be a top level module name!"
+ exit
+else
+ set SIM_TOP = $1
+endif
+
+set current_par = 1
+set output_waveform = 0
+while ( $current_par < $# )
+ @ current_par = $current_par + 1
+ case wave:
+ @ output_waveform = 1
+ breaksw
+ default:
+ echo 'Unknown option "'$argv[$current_par]'"!'
+ exit
+ breaksw
+ endsw
+end
+
+echo "-CDSLIB ../bin/cds.lib" > ncvlog.args
+echo "-HDLVAR ../bin/hdl.var" >> ncvlog.args
+echo "-MESSAGES" >> ncvlog.args
+echo "-INCDIR ../../../bench/verilog" >> ncvlog.args
+echo "-INCDIR ../../../rtl/verilog" >> ncvlog.args
+echo "-NOCOPYRIGHT" >> ncvlog.args
+echo "-LOGFILE ../log/ncvlog.log" >> ncvlog.args
+
+foreach filename ( `cat ../bin/rtl_file_list` )
+ echo "../../../rtl/verilog/"$filename >> ncvlog.args
+end
+
+foreach filename ( `cat ../bin/sim_file_list` )
+ echo "../../../bench/verilog/"$filename >> ncvlog.args
+end
+
+ncvlog -f ncvlog.args
+
+echo "-MESSAGES" > ncelab.args
+echo "-NOCOPYRIGHT" >> ncelab.args
+echo "-CDSLIB ../bin/cds.lib" >> ncelab.args
+echo "-HDLVAR ../bin/hdl.var" >> ncelab.args
+echo "-LOGFILE ../log/ncelab.log" >> ncelab.args
+echo "-SNAPSHOT worklib.bench:rtl" >> ncelab.args
+echo "-NO_TCHK_MSG" >> ncelab.args
+echo "-ACCESS +RWC" >> ncelab.args
+echo worklib.$SIM_TOP >> ncelab.args
+
+ncelab -f ncelab.args
+
+echo "-MESSAGES" > ncsim.args
+echo "-NOCOPYRIGHT" >> ncsim.args
+echo "-CDSLIB ../bin/cds.lib" >> ncsim.args
+echo "-HDLVAR ../bin/hdl.var" >> ncsim.args
+echo "-INPUT ncsim.tcl" >> ncsim.args
+echo "-LOGFILE ../log/ncsim.log" >> ncsim.args
+echo "worklib.bench:rtl" >> ncsim.args
+
+if ( $output_waveform ) then
+ echo "database -open waves -shm -into ../out/waves.shm" > ./ncsim.tcl
+ echo "probe -create -database waves $SIM_TOP -shm -all -depth all" >> ./ncsim.tcl
+ echo "run" >> ./ncsim.tcl
+else
+ echo "run" > ./ncsim.tcl
+endif
+
+echo "quit" >> ncsim.tcl
+
+ncsim -LICQUEUE -f ./ncsim.args
tags/rel_10/sim/rtl_sim/run/run_sim.scr
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/rel_10/sim/rtl_sim/run/wave.do
===================================================================
--- tags/rel_10/sim/rtl_sim/run/wave.do (nonexistent)
+++ tags/rel_10/sim/rtl_sim/run/wave.do (revision 76)
@@ -0,0 +1,308 @@
+// Signalscan Version 6.7p1
+
+
+define noactivityindicator
+define analog waveform lines
+define add variable default overlay off
+define waveform window analogheight 1
+define terminal automatic
+define buttons control \
+ 1 opensimmulationfile \
+ 2 executedofile \
+ 3 designbrowser \
+ 4 waveform \
+ 5 source \
+ 6 breakpoints \
+ 7 definesourcessearchpath \
+ 8 exit \
+ 9 createbreakpoint \
+ 10 creategroup \
+ 11 createmarker \
+ 12 closesimmulationfile \
+ 13 renamesimmulationfile \
+ 14 replacesimulationfiledata \
+ 15 listopensimmulationfiles \
+ 16 savedofile
+define buttons waveform \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 zoomin \
+ 7 zoomout \
+ 8 zoomoutfull \
+ 9 expand \
+ 10 createmarker \
+ 11 designbrowser:1 \
+ 12 variableradixbinary \
+ 13 variableradixoctal \
+ 14 variableradixdecimal \
+ 15 variableradixhexadecimal \
+ 16 variableradixascii
+define buttons designbrowser \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 cdupscope \
+ 7 getallvariables \
+ 8 getdeepallvariables \
+ 9 addvariables \
+ 10 addvarsandclosewindow \
+ 11 closewindow \
+ 12 scopefiltermodule \
+ 13 scopefiltertask \
+ 14 scopefilterfunction \
+ 15 scopefilterblock \
+ 16 scopefilterprimitive
+define buttons event \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 move \
+ 7 closewindow \
+ 8 duplicate \
+ 9 defineasrisingedge \
+ 10 defineasfallingedge \
+ 11 defineasanyedge \
+ 12 variableradixbinary \
+ 13 variableradixoctal \
+ 14 variableradixdecimal \
+ 15 variableradixhexadecimal \
+ 16 variableradixascii
+define buttons source \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 createbreakpoint \
+ 7 creategroup \
+ 8 createmarker \
+ 9 createevent \
+ 10 createregisterpage \
+ 11 closewindow \
+ 12 opensimmulationfile \
+ 13 closesimmulationfile \
+ 14 renamesimmulationfile \
+ 15 replacesimulationfiledata \
+ 16 listopensimmulationfiles
+define buttons register \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 createregisterpage \
+ 7 closewindow \
+ 8 continuefor \
+ 9 continueuntil \
+ 10 continueforever \
+ 11 stop \
+ 12 previous \
+ 13 next \
+ 14 variableradixbinary \
+ 15 variableradixhexadecimal \
+ 16 variableradixascii
+define show related transactions
+define exit prompt
+define event search direction forward
+define variable nofullhierarchy
+define variable nofilenames
+define variable nofullpathfilenames
+include bookmark with filenames
+include scope history without filenames
+define waveform window listpane 13.22
+define waveform window namepane 20.97
+define multivalueindication
+define pattern curpos dot
+define pattern cursor1 dot
+define pattern cursor2 dot
+define pattern marker dot
+define print designer "Igor Mohor"
+define print border
+define print color blackonwhite
+define print command "/usr/ucb/lpr -P%P"
+define print printer lp
+define print range visible
+define print variable visible
+define rise fall time low threshold percentage 10
+define rise fall time high threshold percentage 90
+define rise fall time low value 0
+define rise fall time high value 3.3
+define sendmail command "/usr/lib/sendmail"
+define sequence time width 30.00
+define snap
+
+define source noprompt
+define time units default
+define userdefinedbussymbol
+define user guide directory "/usr/local/designacc/signalscan-6.7p1/doc/html"
+define waveform window grid off
+define waveform window waveheight 14
+define waveform window wavespace 6
+define web browser command netscape
+define zoom outfull on initial add off
+add group \
+ tap_top \
+ dbg_tb.i_tap_top.tck_pad_i \
+ dbg_tb.i_tap_top.tdi_pad_i \
+ dbg_tb.i_tap_top.tdo_pad_o \
+ dbg_tb.i_tap_top.tdo_padoe_o \
+ dbg_tb.i_tap_top.tms_pad_i \
+ dbg_tb.i_tap_top.trst_pad_i \
+ dbg_tb.i_tap_top.TestLogicReset \
+ dbg_tb.i_tap_top.RunTestIdle \
+ dbg_tb.i_tap_top.SelectDRScan \
+ dbg_tb.i_tap_top.CaptureDR \
+ dbg_tb.i_tap_top.SelectIRScan \
+ dbg_tb.i_tap_top.CaptureIR \
+ dbg_tb.i_tap_top.PauseDR \
+ dbg_tb.i_tap_top.ShiftDR \
+ dbg_tb.i_tap_top.ShiftIR \
+ dbg_tb.i_tap_top.PauseIR \
+ dbg_tb.i_tap_top.UpdateDR \
+ dbg_tb.i_tap_top.UpdateIR \
+ dbg_tb.i_tap_top.UpdateDR_q \
+ dbg_tb.i_tap_top.Exit1DR \
+ dbg_tb.i_tap_top.Exit1IR \
+ dbg_tb.i_dbg_top.CrcMatch \
+ dbg_tb.i_dbg_top.crc_cnt[3:0]'h \
+ dbg_tb.i_dbg_top.crc_bypassed \
+ dbg_tb.i_dbg_top.CalculatedCrcIn[7:0]'h \
+ dbg_tb.i_dbg_top.CalculatedCrcOut[7:0]'h \
+ dbg_tb.i_dbg_top.BitCounter[7:0]'h \
+ dbg_tb.i_dbg_top.CalculatedCrcOut[7:0]'h \
+ dbg_tb.i_dbg_top.BitCounter[7:0]'h \
+ dbg_tb.i_dbg_top.TDOData \
+ dbg_tb.i_dbg_top.crc_cnt[3:0]'h \
+ dbg_tb.i_tap_top.JTAG_IR[3:0]'h \
+ dbg_tb.i_tap_top.LatchedJTAG_IR[3:0]'h \
+ dbg_tb.i_tap_top.BypassRegister \
+ dbg_tb.i_tap_top.CHAIN_SELECTSelected \
+ dbg_tb.i_tap_top.DEBUGSelected \
+ dbg_tb.i_tap_top.EXTESTSelected \
+ dbg_tb.i_tap_top.IDCODESelected \
+ dbg_tb.i_tap_top.MBISTSelected \
+ dbg_tb.i_tap_top.CpuDebugScanChain0 \
+ dbg_tb.i_tap_top.CpuDebugScanChain1 \
+ dbg_tb.i_tap_top.CpuDebugScanChain2 \
+ dbg_tb.i_tap_top.CpuDebugScanChain3 \
+ dbg_tb.i_tap_top.RegisterScanChain \
+ dbg_tb.i_tap_top.WishboneScanChain \
+ dbg_tb.i_tap_top.TDOData_dbg \
+ dbg_tb.i_tap_top.bs_chain_i \
+ dbg_tb.i_tap_top.mbist_so_i \
+
+add group \
+ dbg_registers \
+ dbg_tb.i_dbg_top.dbgregs.CPUOPOut[2:1]'h \
+ dbg_tb.i_dbg_top.dbgregs.CPUOP_Acc \
+ dbg_tb.i_dbg_top.dbgregs.CPUOP_Rd \
+ dbg_tb.i_dbg_top.dbgregs.CPUOP_Wr \
+ dbg_tb.i_dbg_top.dbgregs.CPUSELOut[1:0]'h \
+ dbg_tb.i_dbg_top.dbgregs.CPUSEL_Acc \
+ dbg_tb.i_dbg_top.dbgregs.CPUSEL_Rd \
+ dbg_tb.i_dbg_top.dbgregs.CPUSEL_Wr \
+ dbg_tb.i_dbg_top.dbgregs.CpuStallBp \
+ dbg_tb.i_dbg_top.dbgregs.MODEROut[31:0]'h \
+ dbg_tb.i_dbg_top.dbgregs.MODER_Acc \
+ dbg_tb.i_dbg_top.dbgregs.MODER_Rd \
+ dbg_tb.i_dbg_top.dbgregs.MODER_Wr \
+ dbg_tb.i_dbg_top.dbgregs.MONCNTLOut[3:0]'h \
+ dbg_tb.i_dbg_top.dbgregs.MON_CNTL_Acc \
+ dbg_tb.i_dbg_top.dbgregs.MON_CNTL_Rd \
+ dbg_tb.i_dbg_top.dbgregs.MON_CNTL_Wr \
+ dbg_tb.i_dbg_top.dbgregs.WB_CNTLOut[1:0]'h \
+ dbg_tb.i_dbg_top.dbgregs.WB_CNTL_Acc \
+ dbg_tb.i_dbg_top.dbgregs.WB_CNTL_Rd \
+ dbg_tb.i_dbg_top.dbgregs.WB_CNTL_Wr \
+ dbg_tb.i_dbg_top.dbgregs.access \
+ dbg_tb.i_dbg_top.dbgregs.address[4:0]'h \
+ dbg_tb.i_dbg_top.dbgregs.bp \
+ dbg_tb.i_dbg_top.dbgregs.clk \
+ dbg_tb.i_dbg_top.dbgregs.cpu_reset \
+ dbg_tb.i_dbg_top.dbgregs.cpu_stall \
+ dbg_tb.i_dbg_top.dbgregs.cpu_stall_all \
+ dbg_tb.i_dbg_top.dbgregs.cpu_sel[1:0]'h \
+ dbg_tb.i_dbg_top.dbgregs.data_in[31:0]'h \
+ dbg_tb.i_dbg_top.dbgregs.data_out[31:0]'h \
+ dbg_tb.i_dbg_top.dbgregs.mon_cntl_o[3:0]'h \
+ dbg_tb.i_dbg_top.dbgregs.reset \
+ dbg_tb.i_dbg_top.dbgregs.rw \
+ dbg_tb.i_dbg_top.dbgregs.wb_cntl_o[1:0]'h \
+
+add group \
+ dbg_top \
+ dbg_tb.i_dbg_top.BypassRegister \
+ dbg_tb.i_dbg_top.CHAIN_SELECTSelected \
+ dbg_tb.i_dbg_top.RegisterScanChain \
+ dbg_tb.i_dbg_top.CpuDebugScanChain0 \
+ dbg_tb.i_dbg_top.CpuDebugScanChain1 \
+ dbg_tb.i_dbg_top.CpuDebugScanChain2 \
+ dbg_tb.i_dbg_top.CpuDebugScanChain3 \
+ dbg_tb.i_dbg_top.cpu_addr_o[31:0]'h \
+ dbg_tb.i_dbg_top.cpu_data_i[31:0]'h \
+ dbg_tb.i_dbg_top.cpu_data_o[31:0]'h \
+ dbg_tb.i_dbg_top.opselect_o[2:0]'h \
+ dbg_tb.i_dbg_top.cpu_sel_o[1:0]'h \
+ dbg_tb.i_dbg_top.cpu_stall_all_o \
+ dbg_tb.i_dbg_top.cpu_stall_o \
+ dbg_tb.i_dbg_top.CpuStall_access \
+ dbg_tb.i_dbg_top.CpuStall_read_access_0 \
+ dbg_tb.i_dbg_top.CpuStall_read_access_1 \
+ dbg_tb.i_dbg_top.CpuStall_read_access_2 \
+ dbg_tb.i_dbg_top.CpuStall_read_access_3 \
+ dbg_tb.i_dbg_top.CpuStall_write_access_0 \
+ dbg_tb.i_dbg_top.CpuStall_write_access_1 \
+ dbg_tb.i_dbg_top.CpuStall_write_access_2 \
+ dbg_tb.i_dbg_top.CpuStall_write_access_3 \
+ dbg_tb.i_dbg_top.cpu_clk_i \
+ dbg_tb.i_dbg_top.DEBUGSelected \
+ dbg_tb.i_dbg_top.Exit1DR \
+ dbg_tb.i_dbg_top.IDCODESelected \
+ dbg_tb.i_dbg_top.ShiftDR \
+ dbg_tb.i_dbg_top.TDOData \
+ dbg_tb.i_dbg_top.UpdateDR \
+ dbg_tb.i_dbg_top.UpdateDR_q \
+ dbg_tb.i_dbg_top.WishboneScanChain \
+ dbg_tb.i_dbg_top.bp_i \
+ dbg_tb.i_dbg_top.cpu_addr_o[31:0]'h \
+ dbg_tb.i_dbg_top.cpu_clk_i \
+ dbg_tb.i_dbg_top.cpu_data_i[31:0]'h \
+ dbg_tb.i_dbg_top.cpu_data_o[31:0]'h \
+ dbg_tb.i_dbg_top.cpu_sel_o[1:0]'h \
+ dbg_tb.i_dbg_top.cpu_stall_all_o \
+ dbg_tb.i_dbg_top.cpu_stall_o \
+ dbg_tb.i_dbg_top.istatus_i[1:0]'h \
+ dbg_tb.i_dbg_top.lsstatus_i[3:0]'h \
+ dbg_tb.i_dbg_top.mon_cntl_o[3:0]'h \
+ dbg_tb.i_dbg_top.opselect_o[2:0]'h \
+ dbg_tb.i_dbg_top.reset_o \
+ dbg_tb.i_dbg_top.tck \
+ dbg_tb.i_dbg_top.tdi \
+ dbg_tb.i_dbg_top.trst_in \
+ dbg_tb.i_dbg_top.wb_ack_i \
+ dbg_tb.i_dbg_top.wb_adr_o[31:0]'h \
+ dbg_tb.i_dbg_top.wb_cab_o \
+ dbg_tb.i_dbg_top.wb_clk_i \
+ dbg_tb.i_dbg_top.wb_cyc_o \
+ dbg_tb.i_dbg_top.wb_dat_i[31:0]'h \
+ dbg_tb.i_dbg_top.wb_dat_o[31:0]'h \
+ dbg_tb.i_dbg_top.wb_err_i \
+ dbg_tb.i_dbg_top.wb_rst_i \
+ dbg_tb.i_dbg_top.wb_sel_o[3:0]'h \
+ dbg_tb.i_dbg_top.wb_stb_o \
+ dbg_tb.i_dbg_top.wb_we_o \
+ dbg_tb.i_dbg_top.wp_i[10:0]'h \
+ dbg_tb.i_dbg_top.RW \
+
+
+deselect all
+open window designbrowser 1 geometry 64 125 855 550
+open window waveform 1 geometry 14 67 1024 662
+zoom at 168762.05(0)ns 0.00005926 0.00000000
tags/rel_10/sim/rtl_sim/run/wave.do
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/rel_10/sim/rtl_sim/out/dir_keeper
===================================================================
--- tags/rel_10/sim/rtl_sim/out/dir_keeper (nonexistent)
+++ tags/rel_10/sim/rtl_sim/out/dir_keeper (revision 76)
@@ -0,0 +1 @@
+Only keeper of empty directories
tags/rel_10/sim/rtl_sim/out/dir_keeper
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/rel_10/sim/rtl_sim/bin/sim_file_list
===================================================================
--- tags/rel_10/sim/rtl_sim/bin/sim_file_list (nonexistent)
+++ tags/rel_10/sim/rtl_sim/bin/sim_file_list (revision 76)
@@ -0,0 +1,4 @@
+timescale.v
+dbg_tb_defines.v
+dbg_tb.v
+
tags/rel_10/sim/rtl_sim/bin/sim_file_list
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/rel_10/sim/rtl_sim/bin/INCA_libs/worklib/dir_keeper
===================================================================
Index: tags/rel_10/sim/rtl_sim/bin/rtl_file_list
===================================================================
--- tags/rel_10/sim/rtl_sim/bin/rtl_file_list (nonexistent)
+++ tags/rel_10/sim/rtl_sim/bin/rtl_file_list (revision 76)
@@ -0,0 +1,11 @@
+dbg_defines.v
+dbg_register.v
+dbg_top.v
+jtag_chain.v
+timescale.v
+dbg_crc8_d1.v
+dbg_registers.v
+dbg_sync_clk1_clk2.v
+dbg_trace.v
+tap_top.v
+
tags/rel_10/sim/rtl_sim/bin/rtl_file_list
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/rel_10/sim/rtl_sim/bin/cds.lib
===================================================================
--- tags/rel_10/sim/rtl_sim/bin/cds.lib (nonexistent)
+++ tags/rel_10/sim/rtl_sim/bin/cds.lib (revision 76)
@@ -0,0 +1,6 @@
+#
+# cds.lib: Defines the locations of compiled libraries.
+# Created by ncprep on Tue Jul 3 11:40:44 2001
+#
+
+define worklib ./INCA_libs/worklib
tags/rel_10/sim/rtl_sim/bin/cds.lib
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/rel_10/sim/rtl_sim/bin/hdl.var
===================================================================
--- tags/rel_10/sim/rtl_sim/bin/hdl.var (nonexistent)
+++ tags/rel_10/sim/rtl_sim/bin/hdl.var (revision 76)
@@ -0,0 +1,9 @@
+#
+# hdl.var: Defines variables used by the INCA tools.
+# Created by ncprep on Tue Jul 3 11:40:44 2001
+#
+
+softinclude $CDS_INST_DIR/tools/inca/files/hdl.var
+
+define LIB_MAP ( $LIB_MAP, + => worklib )
+define VIEW_MAP ( $VIEW_MAP, .v => v)
tags/rel_10/sim/rtl_sim/bin/hdl.var
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/rel_10/rtl/verilog/dbg_top.v
===================================================================
--- tags/rel_10/rtl/verilog/dbg_top.v (nonexistent)
+++ tags/rel_10/rtl/verilog/dbg_top.v (revision 76)
@@ -0,0 +1,1239 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// dbg_top.v ////
+//// ////
+//// ////
+//// This file is part of the SoC/OpenRISC Development Interface ////
+//// http://www.opencores.org/projects/DebugInterface/ ////
+//// ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor ////
+//// igorm@opencores.org ////
+//// ////
+//// ////
+//// All additional information is available in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000,2001, 2002 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.32 2003/09/18 14:00:47 simons
+// Lower two address lines must be always zero.
+//
+// Revision 1.31 2003/09/17 14:38:57 simons
+// WB_CNTL register added, some syncronization fixes.
+//
+// Revision 1.30 2003/08/28 13:55:22 simons
+// Three more chains added for cpu debug access.
+//
+// Revision 1.29 2003/07/31 12:19:49 simons
+// Multiple cpu support added.
+//
+// Revision 1.28 2002/11/06 14:22:41 mohor
+// Trst signal is not inverted here any more. Inverted on higher layer !!!.
+//
+// Revision 1.27 2002/10/10 02:42:55 mohor
+// WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added).
+// Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value,
+// wb_cyc_o is negated.
+//
+// Revision 1.26 2002/05/07 14:43:59 mohor
+// mon_cntl_o signals that controls monitor mux added.
+//
+// Revision 1.25 2002/04/22 12:54:11 mohor
+// Signal names changed to lower case.
+//
+// Revision 1.24 2002/04/17 13:17:01 mohor
+// Intentional error removed.
+//
+// Revision 1.23 2002/04/17 11:16:33 mohor
+// A block for checking possible simulation/synthesis missmatch added.
+//
+// Revision 1.22 2002/03/12 10:31:53 mohor
+// tap_top and dbg_top modules are put into two separate modules. tap_top
+// contains only tap state machine and related logic. dbg_top contains all
+// logic necessery for debugging.
+//
+// Revision 1.21 2002/03/08 15:28:16 mohor
+// Structure changed. Hooks for jtag chain added.
+//
+// Revision 1.20 2002/02/06 12:23:09 mohor
+// LatchedJTAG_IR used when muxing TDO instead of JTAG_IR.
+//
+// Revision 1.19 2002/02/05 13:34:51 mohor
+// Stupid bug that was entered by previous update fixed.
+//
+// Revision 1.18 2002/02/05 12:41:01 mohor
+// trst synchronization is not needed and was removed.
+//
+// Revision 1.17 2002/01/25 07:58:35 mohor
+// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
+// not filled-in. Tested in hw.
+//
+// Revision 1.16 2001/12/20 11:17:26 mohor
+// TDO and TDO Enable signal are separated into two signals.
+//
+// Revision 1.15 2001/12/05 13:28:21 mohor
+// trst signal is synchronized to wb_clk_i.
+//
+// Revision 1.14 2001/11/28 09:36:15 mohor
+// Register length fixed.
+//
+// Revision 1.13 2001/11/27 13:37:43 mohor
+// CRC is returned when chain selection data is transmitted.
+//
+// Revision 1.12 2001/11/26 10:47:09 mohor
+// Crc generation is different for read or write commands. Small synthesys fixes.
+//
+// Revision 1.11 2001/11/14 10:10:41 mohor
+// Wishbone data latched on wb_clk_i instead of risc_clk.
+//
+// Revision 1.10 2001/11/12 01:11:27 mohor
+// Reset signals are not combined any more.
+//
+// Revision 1.9 2001/10/19 11:40:01 mohor
+// dbg_timescale.v changed to timescale.v This is done for the simulation of
+// few different cores in a single project.
+//
+// Revision 1.8 2001/10/17 10:39:03 mohor
+// bs_chain_o added.
+//
+// Revision 1.7 2001/10/16 10:09:56 mohor
+// Signal names changed to lowercase.
+//
+//
+// Revision 1.6 2001/10/15 09:55:47 mohor
+// Wishbone interface added, few fixes for better performance,
+// hooks for boundary scan testing added.
+//
+// Revision 1.5 2001/09/24 14:06:42 mohor
+// Changes connected to the OpenRISC access (SPR read, SPR write).
+//
+// Revision 1.4 2001/09/20 10:11:25 mohor
+// Working version. Few bugs fixed, comments added.
+//
+// Revision 1.3 2001/09/19 11:55:13 mohor
+// Asynchronous set/reset not used in trace any more.
+//
+// Revision 1.2 2001/09/18 14:13:47 mohor
+// Trace fixed. Some registers changed, trace simplified.
+//
+// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
+// Initial official release.
+//
+// Revision 1.3 2001/06/01 22:22:35 mohor
+// This is a backup. It is not a fully working version. Not for use, yet.
+//
+// Revision 1.2 2001/05/18 13:10:00 mohor
+// Headers changed. All additional information is now avaliable in the README.txt file.
+//
+// Revision 1.1.1.1 2001/05/18 06:35:02 mohor
+// Initial release
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "dbg_defines.v"
+
+// Top module
+module dbg_top(
+
+ // CPU signals
+ cpu_clk_i, cpu_addr_o, cpu_data_i, cpu_data_o, wp_i,
+ bp_i, opselect_o, lsstatus_i, istatus_i,
+ cpu_stall_o, cpu_stall_all_o, cpu_sel_o, reset_o,
+
+ // WISHBONE common signals
+ wb_rst_i, wb_clk_i,
+
+ // WISHBONE master interface
+ wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
+ wb_we_o, wb_ack_i, wb_cab_o, wb_err_i,
+
+ // TAP states
+ ShiftDR, Exit1DR, UpdateDR, UpdateDR_q, SelectDRScan,
+
+ // Instructions
+ IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected,
+
+ // TAP signals
+ trst_in, tck, tdi, TDOData,
+
+ BypassRegister,
+
+ // Monitor mux control
+ mon_cntl_o,
+
+ // Selected chains
+ RegisterScanChain,
+ CpuDebugScanChain0,
+ CpuDebugScanChain1,
+ CpuDebugScanChain2,
+ CpuDebugScanChain3,
+ WishboneScanChain
+
+
+
+ );
+
+parameter Tp = 1;
+
+
+// CPU signals
+input cpu_clk_i; // Master clock (CPU clock)
+input [31:0] cpu_data_i; // CPU data inputs (data that is written to the CPU registers)
+input [10:0] wp_i; // Watchpoint inputs
+input bp_i; // Breakpoint input
+input [3:0] lsstatus_i; // Load/store status inputs
+input [1:0] istatus_i; // Instruction status inputs
+output [31:0] cpu_addr_o; // CPU address output (for adressing registers within CPU)
+output [31:0] cpu_data_o; // CPU data output (data read from cpu registers)
+output [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the cpu_data_i)
+output cpu_stall_o; // Stalls the selected CPU
+output cpu_stall_all_o; // Stalls all the rest CPUs
+output [`CPU_NUM-1:0] cpu_sel_o; // Stalls all the rest CPUs
+output reset_o; // Resets the CPU
+
+
+// WISHBONE common signals
+input wb_rst_i; // WISHBONE reset
+input wb_clk_i; // WISHBONE clock
+
+// WISHBONE master interface
+output [31:0] wb_adr_o;
+output [31:0] wb_dat_o;
+input [31:0] wb_dat_i;
+output wb_cyc_o;
+output wb_stb_o;
+output [3:0] wb_sel_o;
+output wb_we_o;
+input wb_ack_i;
+output wb_cab_o;
+input wb_err_i;
+
+// TAP states
+input ShiftDR;
+input Exit1DR;
+input UpdateDR;
+input UpdateDR_q;
+input SelectDRScan;
+
+input trst_in;
+input tck;
+input tdi;
+
+input BypassRegister;
+
+output TDOData;
+output [3:0] mon_cntl_o;
+
+// Defining which instruction is selected
+input IDCODESelected;
+input CHAIN_SELECTSelected;
+input DEBUGSelected;
+
+// Selected chains
+output RegisterScanChain;
+output CpuDebugScanChain0;
+output CpuDebugScanChain1;
+output CpuDebugScanChain2;
+output CpuDebugScanChain3;
+output WishboneScanChain;
+
+reg wb_cyc_o;
+
+reg [31:0] ADDR;
+reg [31:0] DataOut;
+
+reg [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the cpu_data_i)
+
+reg [`CHAIN_ID_LENGTH-1:0] Chain; // Selected chain
+reg [31:0] DataReadLatch; // Data when reading register or CPU is latched one cpu_clk_i clock after the data is read.
+reg RegAccessTck; // Indicates access to the registers (read or write)
+reg CPUAccessTck0; // Indicates access to the CPU (read or write)
+reg CPUAccessTck1; // Indicates access to the CPU (read or write)
+reg CPUAccessTck2; // Indicates access to the CPU (read or write)
+reg CPUAccessTck3; // Indicates access to the CPU (read or write)
+reg [7:0] BitCounter; // Counting bits in the ShiftDR and Exit1DR stages
+reg RW; // Read/Write bit
+reg CrcMatch; // The crc that is shifted in and the internaly calculated crc are equal
+reg CrcMatch_q;
+
+reg RegAccess_q; // Delayed signals used for accessing the registers
+reg RegAccess_q2; // Delayed signals used for accessing the registers
+reg CPUAccess_q; // Delayed signals used for accessing the CPU
+reg CPUAccess_q2; // Delayed signals used for accessing the CPU
+reg CPUAccess_q3; // Delayed signals used for accessing the CPU
+
+reg wb_AccessTck; // Indicates access to the WISHBONE
+reg [31:0] WBReadLatch; // Data latched during WISHBONE read
+reg WBErrorLatch; // Error latched during WISHBONE read
+reg WBInProgress; // WISHBONE access is in progress
+reg [7:0] WBAccessCounter; // Counting access cycles. WBInProgress is cleared to 0 after counter exceeds 0xff
+wire WBAccessCounterExceed; // Marks when the WBAccessCounter exceeds max value (oxff)
+reg WBInProgress_sync1; // Synchronizing WBInProgress
+reg WBInProgress_tck; // Synchronizing WBInProgress to tck clock signal
+
+wire trst;
+
+
+wire [31:0] RegDataIn; // Data from registers (read data)
+wire [`CRC_LENGTH-1:0] CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.
+
+wire CpuStall_reg; // CPU is stalled by setting the register bit
+wire CpuReset_reg; // CPU is reset by setting the register bit
+wire CpuStall_trace; // CPU is stalled by trace module
+
+
+wire CpuStall_read_access_0; // Stalling Cpu because of the read access (SPR read)
+wire CpuStall_read_access_1; // Stalling Cpu because of the read access (SPR read)
+wire CpuStall_read_access_2; // Stalling Cpu because of the read access (SPR read)
+wire CpuStall_read_access_3; // Stalling Cpu because of the read access (SPR read)
+wire CpuStall_write_access_0; // Stalling Cpu because of the write access (SPR write)
+wire CpuStall_write_access_1; // Stalling Cpu because of the write access (SPR write)
+wire CpuStall_write_access_2; // Stalling Cpu because of the write access (SPR write)
+wire CpuStall_write_access_3; // Stalling Cpu because of the write access (SPR write)
+wire CpuStall_access; // Stalling Cpu because of the read or write access
+
+wire BitCounter_Lt4;
+wire BitCounter_Eq5;
+wire BitCounter_Eq32;
+wire BitCounter_Lt38;
+wire BitCounter_Lt65;
+
+
+
+// This signals are used only when TRACE is used in the design
+`ifdef TRACE_ENABLED
+ wire [39:0] TraceChain; // Chain that comes from trace module
+ reg ReadBuffer_Tck; // Command for incrementing the trace read pointer (synchr with tck)
+ wire ReadTraceBuffer; // Command for incrementing the trace read pointer (synchr with MClk)
+ reg ReadTraceBuffer_q; // Delayed command for incrementing the trace read pointer (synchr with MClk)
+ wire ReadTraceBufferPulse; // Pulse for reading the trace buffer (valid for only one Mclk command)
+
+ // Outputs from registers
+ wire ContinMode; // Trace working in continous mode
+ wire TraceEnable; // Trace enabled
+
+ wire [10:0] WpTrigger; // Watchpoint starts trigger
+ wire BpTrigger; // Breakpoint starts trigger
+ wire [3:0] LSSTrigger; // Load/store status starts trigger
+ wire [1:0] ITrigger; // Instruction status starts trigger
+ wire [1:0] TriggerOper; // Trigger operation
+
+ wire WpTriggerValid; // Watchpoint trigger is valid
+ wire BpTriggerValid; // Breakpoint trigger is valid
+ wire LSSTriggerValid; // Load/store status trigger is valid
+ wire ITriggerValid; // Instruction status trigger is valid
+
+ wire [10:0] WpQualif; // Watchpoint starts qualifier
+ wire BpQualif; // Breakpoint starts qualifier
+ wire [3:0] LSSQualif; // Load/store status starts qualifier
+ wire [1:0] IQualif; // Instruction status starts qualifier
+ wire [1:0] QualifOper; // Qualifier operation
+
+ wire WpQualifValid; // Watchpoint qualifier is valid
+ wire BpQualifValid; // Breakpoint qualifier is valid
+ wire LSSQualifValid; // Load/store status qualifier is valid
+ wire IQualifValid; // Instruction status qualifier is valid
+
+ wire [10:0] WpStop; // Watchpoint stops recording of the trace
+ wire BpStop; // Breakpoint stops recording of the trace
+ wire [3:0] LSSStop; // Load/store status stops recording of the trace
+ wire [1:0] IStop; // Instruction status stops recording of the trace
+ wire [1:0] StopOper; // Stop operation
+
+ wire WpStopValid; // Watchpoint stop is valid
+ wire BpStopValid; // Breakpoint stop is valid
+ wire LSSStopValid; // Load/store status stop is valid
+ wire IStopValid; // Instruction status stop is valid
+
+ wire RecordPC; // Recording program counter
+ wire RecordLSEA; // Recording load/store effective address
+ wire RecordLDATA; // Recording load data
+ wire RecordSDATA; // Recording store data
+ wire RecordReadSPR; // Recording read SPR
+ wire RecordWriteSPR; // Recording write SPR
+ wire RecordINSTR; // Recording instruction
+
+ // End: Outputs from registers
+
+ wire TraceTestScanChain; // Trace Test Scan chain selected
+ wire [47:0] Trace_Data; // Trace data
+
+ wire [`OPSELECTWIDTH-1:0]opselect_trace;// Operation selection (trace selecting what kind of
+ // data is set to the cpu_data_i)
+ wire BitCounter_Lt40;
+
+`endif
+
+
+assign trst = trst_in; // trst_pad_i is active high !!! Inverted on higher layer.
+
+
+/**********************************************************************************
+* *
+* JTAG_DR: JTAG Data Register *
+* *
+**********************************************************************************/
+reg [`DR_LENGTH-1:0]JTAG_DR_IN; // Data register
+reg TDOData;
+
+
+always @ (posedge tck or posedge trst)
+begin
+ if(trst)
+ JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
+ else
+ if(IDCODESelected) // To save space JTAG_DR_IN is also used for shifting out IDCODE
+ begin
+ if(ShiftDR)
+ JTAG_DR_IN[31:0] <= #Tp {tdi, JTAG_DR_IN[31:1]};
+ else
+ JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
+ end
+ else
+ if(CHAIN_SELECTSelected & ShiftDR)
+ JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};
+ else
+ if(DEBUGSelected & ShiftDR)
+ begin
+ if(CpuDebugScanChain0 | CpuDebugScanChain1 |
+ CpuDebugScanChain2 | CpuDebugScanChain3 | WishboneScanChain)
+ JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};
+ else
+ if(RegisterScanChain)
+ JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};
+ end
+end
+
+wire [73:0] CPU_Data;
+wire [46:0] Register_Data;
+wire [73:0] WISHBONE_Data;
+wire [12:0] chain_sel_data;
+wire wb_Access_wbClk;
+wire [1:0] wb_cntl_o;
+
+
+reg crc_bypassed;
+always @ (posedge tck or posedge trst)
+begin
+ if(trst)
+ crc_bypassed <= 0;
+ else if (CHAIN_SELECTSelected)
+ crc_bypassed <=#Tp 1;
+ else if(
+ RegisterScanChain & BitCounter_Eq5 |
+ CpuDebugScanChain0 & BitCounter_Eq32 |
+ CpuDebugScanChain1 & BitCounter_Eq32 |
+ CpuDebugScanChain2 & BitCounter_Eq32 |
+ CpuDebugScanChain3 & BitCounter_Eq32 |
+ WishboneScanChain & BitCounter_Eq32 )
+ crc_bypassed <=#Tp tdi; // when write is performed.
+end
+
+reg [7:0] send_crc;
+wire [7:0] CalculatedCrcIn; // crc calculated from the input data (shifted in)
+
+// Calculated CRC is returned when read operation is performed, else received crc is returned (loopback).
+always @ (crc_bypassed or CrcMatch or CrcMatch_q or BypassRegister or CalculatedCrcOut)
+ begin
+ if (crc_bypassed)
+ begin
+ if (CrcMatch | CrcMatch_q) // When crc is looped back, first bit is not inverted
+ send_crc = {8{BypassRegister}}; // since it caused the error. By inverting it we would
+ else // get ok crc.
+ send_crc = {8{~BypassRegister}};
+ end
+ else
+ begin
+ if (CrcMatch)
+ send_crc = {8{CalculatedCrcOut}};
+ else
+ send_crc = {8{~CalculatedCrcOut}};
+ end
+ end
+
+assign CPU_Data = {send_crc, DataReadLatch, 33'h0, 1'b0};
+assign Register_Data = {send_crc, DataReadLatch, 6'h0, 1'b0};
+assign WISHBONE_Data = {send_crc, WBReadLatch, 31'h0, WBInProgress, WBErrorLatch, 1'b0};
+assign chain_sel_data = {send_crc, 4'h0, 1'b0};
+
+
+`ifdef TRACE_ENABLED
+ assign Trace_Data = {CalculatedCrcOut, TraceChain};
+`endif
+
+//TDO is changing on the falling edge of tck
+always @ (negedge tck or posedge trst)
+begin
+ if(trst)
+ begin
+ TDOData <= #Tp 0;
+ `ifdef TRACE_ENABLED
+ ReadBuffer_Tck<=#Tp 0;
+ `endif
+ end
+ else
+ if(UpdateDR)
+ begin
+ TDOData <= #Tp CrcMatch;
+ `ifdef TRACE_ENABLED
+ if(DEBUGSelected & TraceTestScanChain & TraceChain[0]) // Sample in the trace buffer is valid
+ ReadBuffer_Tck<=#Tp 1; // Increment read pointer
+ `endif
+ end
+ else
+ begin
+ if(ShiftDR)
+ begin
+ if(IDCODESelected)
+ TDOData <= #Tp JTAG_DR_IN[0]; // IDCODE is shifted out 32-bits, then tdi is bypassed
+ else
+ if(CHAIN_SELECTSelected)
+ TDOData <= #Tp chain_sel_data[BitCounter]; // Received crc is sent back
+ else
+ if(DEBUGSelected)
+ begin
+ if(CpuDebugScanChain0 | CpuDebugScanChain1 | CpuDebugScanChain2 | CpuDebugScanChain3)
+ TDOData <= #Tp CPU_Data[BitCounter]; // Data read from CPU in the previous cycle is shifted out
+ else
+ if(RegisterScanChain)
+ TDOData <= #Tp Register_Data[BitCounter]; // Data read from register in the previous cycle is shifted out
+ else
+ if(WishboneScanChain)
+ TDOData <= #Tp WISHBONE_Data[BitCounter]; // Data read from the WISHBONE slave
+ `ifdef TRACE_ENABLED
+ else
+ if(TraceTestScanChain)
+ TDOData <= #Tp Trace_Data[BitCounter]; // Data from the trace buffer is shifted out
+ `endif
+ end
+ end
+ else
+ begin
+ TDOData <= #Tp 0;
+ `ifdef TRACE_ENABLED
+ ReadBuffer_Tck<=#Tp 0;
+ `endif
+ end
+ end
+end
+
+
+//synopsys translate_off
+always @ (posedge tck)
+begin
+ if(ShiftDR & CHAIN_SELECTSelected & BitCounter > 12)
+ begin
+ $display("\n%m Error: BitCounter is bigger then chain_sel_data bits width[12:0]. BitCounter=%d\n",BitCounter);
+ $stop;
+ end
+ else
+ if(ShiftDR & DEBUGSelected)
+ begin
+ if((CpuDebugScanChain0 | CpuDebugScanChain1 | CpuDebugScanChain2 | CpuDebugScanChain3) & BitCounter > 73)
+ begin
+ $display("\n%m Error: BitCounter is bigger then CPU_Data bits width[73:0]. BitCounter=%d\n",BitCounter);
+ $stop;
+ end
+ else
+ if(RegisterScanChain & BitCounter > 46)
+ begin
+ $display("\n%m Error: BitCounter is bigger then Register_Data bits width[46:0]. BitCounter=%d\n",BitCounter);
+ $stop;
+ end
+ else
+ if(WishboneScanChain & BitCounter > 73)
+ begin
+ $display("\n%m Error: BitCounter is bigger then WISHBONE_Data bits width[73:0]. BitCounter=%d\n",BitCounter);
+ $stop;
+ end
+ `ifdef TRACE_ENABLED
+ else
+ if(TraceTestScanChain & BitCounter > 47)
+ begin
+ $display("\n%m Error: BitCounter is bigger then Trace_Data bits width[47:0]. BitCounter=%d\n",BitCounter);
+ $stop;
+ end
+ `endif
+ end
+end
+// synopsys translate_on
+
+
+
+
+
+
+
+
+/**********************************************************************************
+* *
+* End: JTAG_DR *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* CHAIN_SELECT logic *
+* *
+**********************************************************************************/
+always @ (posedge tck or posedge trst)
+begin
+ if(trst)
+ Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp `GLOBAL_BS_CHAIN; // Global BS chain is selected after reset
+ else
+ if(UpdateDR & CHAIN_SELECTSelected & CrcMatch)
+ Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp JTAG_DR_IN[3:0]; // New chain is selected
+end
+
+
+
+/**********************************************************************************
+* *
+* Register read/write logic *
+* CPU registers read/write logic *
+* *
+**********************************************************************************/
+always @ (posedge tck or posedge trst)
+begin
+ if(trst)
+ begin
+ ADDR[31:0] <=#Tp 32'h0;
+ DataOut[31:0] <=#Tp 32'h0;
+ RW <=#Tp 1'b0;
+ RegAccessTck <=#Tp 1'b0;
+ CPUAccessTck0 <=#Tp 1'b0;
+ CPUAccessTck1 <=#Tp 1'b0;
+ CPUAccessTck2 <=#Tp 1'b0;
+ CPUAccessTck3 <=#Tp 1'b0;
+ wb_AccessTck <=#Tp 1'h0;
+ end
+ else
+ if(UpdateDR & DEBUGSelected & CrcMatch)
+ begin
+ if(RegisterScanChain)
+ begin
+ ADDR[4:0] <=#Tp JTAG_DR_IN[4:0]; // Latching address for register access
+ RW <=#Tp JTAG_DR_IN[5]; // latch R/W bit
+ DataOut[31:0] <=#Tp JTAG_DR_IN[37:6]; // latch data for write
+ RegAccessTck <=#Tp 1'b1;
+ end
+ else
+ if(WishboneScanChain & (!WBInProgress_tck))
+ begin
+ ADDR <=#Tp JTAG_DR_IN[31:0]; // Latching address for WISHBONE slave access
+ RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
+ DataOut <=#Tp JTAG_DR_IN[64:33]; // latch data for write
+ wb_AccessTck <=#Tp 1'b1; //
+ end
+ else
+ if(CpuDebugScanChain0)
+ begin
+ ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for CPU register access
+ RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
+ DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
+ CPUAccessTck0 <=#Tp 1'b1;
+ end
+ else
+ if(CpuDebugScanChain1)
+ begin
+ ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for CPU register access
+ RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
+ DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
+ CPUAccessTck1 <=#Tp 1'b1;
+ end
+ else
+ if(CpuDebugScanChain2)
+ begin
+ ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for CPU register access
+ RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
+ DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
+ CPUAccessTck2 <=#Tp 1'b1;
+ end
+ else
+ if(CpuDebugScanChain3)
+ begin
+ ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for CPU register access
+ RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
+ DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
+ CPUAccessTck3 <=#Tp 1'b1;
+ end
+ end
+ else
+ begin
+ RegAccessTck <=#Tp 1'b0; // This signals are valid for one tck clock period only
+ wb_AccessTck <=#Tp 1'b0;
+ CPUAccessTck0 <=#Tp 1'b0;
+ CPUAccessTck1 <=#Tp 1'b0;
+ CPUAccessTck2 <=#Tp 1'b0;
+ CPUAccessTck3 <=#Tp 1'b0;
+ end
+end
+
+
+assign wb_adr_o = {ADDR[31:2] & {30{wb_cyc_o}}, 2'b0};
+assign wb_we_o = RW & wb_cyc_o;
+assign wb_cab_o = 1'b0;
+
+reg [31:0] wb_dat_o;
+always @(wb_sel_o or wb_cyc_o or DataOut)
+begin
+ if(wb_cyc_o)
+ case (wb_sel_o)
+ 4'b0001: wb_dat_o = {24'hx, DataOut[7:0]};
+ 4'b0010: wb_dat_o = {16'hx, DataOut[7:0], 8'hx};
+ 4'b0100: wb_dat_o = {8'hx, DataOut[7:0], 16'hx};
+ 4'b1000: wb_dat_o = {DataOut[7:0], 24'hx};
+ 4'b0011: wb_dat_o = {16'hx, DataOut[15:0]};
+ 4'b1100: wb_dat_o = {DataOut[15:0], 16'hx};
+ default: wb_dat_o = DataOut;
+ endcase
+ else
+ wb_dat_o = 32'hx;
+end
+
+reg [3:0] wb_sel_o;
+always @(ADDR[1:0] or wb_cntl_o or wb_cyc_o)
+begin
+ if(wb_cyc_o)
+ case (wb_cntl_o)
+ 2'b00: wb_sel_o = 4'hf;
+ 2'b01: wb_sel_o = ADDR[1] ? 4'h3 : 4'hc;
+ 2'b10: wb_sel_o = ADDR[1] ? (ADDR[0] ? 4'h1 : 4'h2) : (ADDR[0] ? 4'h4 : 4'h8);
+ default: wb_sel_o = 4'hx;
+ endcase
+ else
+ wb_sel_o = 4'hx;
+end
+
+// Synchronizing the RegAccess signal to cpu_clk_i clock
+dbg_sync_clk1_clk2 syn1 (.clk1(cpu_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
+ .set2(RegAccessTck), .sync_out(RegAccess)
+ );
+
+// Synchronizing the wb_Access signal to wishbone clock
+dbg_sync_clk1_clk2 syn2 (.clk1(wb_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
+ .set2(wb_AccessTck), .sync_out(wb_Access_wbClk)
+ );
+
+// Synchronizing the CPUAccess0 signal to cpu_clk_i clock
+dbg_sync_clk1_clk2 syn3 (.clk1(cpu_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
+ .set2(CPUAccessTck0), .sync_out(CPUAccess0)
+ );
+
+// Synchronizing the CPUAccess1 signal to cpu_clk_i clock
+dbg_sync_clk1_clk2 syn4 (.clk1(cpu_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
+ .set2(CPUAccessTck1), .sync_out(CPUAccess1)
+ );
+
+// Synchronizing the CPUAccess2 signal to cpu_clk_i clock
+dbg_sync_clk1_clk2 syn5 (.clk1(cpu_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
+ .set2(CPUAccessTck2), .sync_out(CPUAccess2)
+ );
+
+// Synchronizing the CPUAccess3 signal to cpu_clk_i clock
+dbg_sync_clk1_clk2 syn6 (.clk1(cpu_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
+ .set2(CPUAccessTck3), .sync_out(CPUAccess3)
+ );
+
+
+
+
+
+// Delayed signals used for accessing registers and CPU
+always @ (posedge cpu_clk_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ begin
+ RegAccess_q <=#Tp 1'b0;
+ RegAccess_q2 <=#Tp 1'b0;
+ CPUAccess_q <=#Tp 1'b0;
+ CPUAccess_q2 <=#Tp 1'b0;
+ CPUAccess_q3 <=#Tp 1'b0;
+ end
+ else
+ begin
+ RegAccess_q <=#Tp RegAccess;
+ RegAccess_q2 <=#Tp RegAccess_q;
+ CPUAccess_q <=#Tp CPUAccess0 | CPUAccess1 | CPUAccess2 | CPUAccess3;
+ CPUAccess_q2 <=#Tp CPUAccess_q;
+ CPUAccess_q3 <=#Tp CPUAccess_q2;
+ end
+end
+
+// Chip select and read/write signals for accessing CPU
+assign CpuStall_write_access_0 = CPUAccess0 & ~CPUAccess_q2 & RW;
+assign CpuStall_read_access_0 = CPUAccess0 & ~CPUAccess_q2 & ~RW;
+assign CpuStall_write_access_1 = CPUAccess1 & ~CPUAccess_q2 & RW;
+assign CpuStall_read_access_1 = CPUAccess1 & ~CPUAccess_q2 & ~RW;
+assign CpuStall_write_access_2 = CPUAccess2 & ~CPUAccess_q2 & RW;
+assign CpuStall_read_access_2 = CPUAccess2 & ~CPUAccess_q2 & ~RW;
+assign CpuStall_write_access_3 = CPUAccess3 & ~CPUAccess_q2 & RW;
+assign CpuStall_read_access_3 = CPUAccess3 & ~CPUAccess_q2 & ~RW;
+assign CpuStall_access = (CPUAccess0 | CPUAccess1 | CPUAccess2 | CPUAccess3) & ~CPUAccess_q3;
+
+
+reg wb_Access_wbClk_q;
+// Delayed signals used for accessing WISHBONE
+always @ (posedge wb_clk_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ wb_Access_wbClk_q <=#Tp 1'b0;
+ else
+ wb_Access_wbClk_q <=#Tp wb_Access_wbClk;
+end
+
+always @ (posedge wb_clk_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ wb_cyc_o <=#Tp 1'b0;
+ else
+ if(wb_Access_wbClk & ~wb_Access_wbClk_q)
+ wb_cyc_o <=#Tp 1'b1;
+ else
+ if(wb_ack_i | wb_err_i | WBAccessCounterExceed)
+ wb_cyc_o <=#Tp 1'b0;
+end
+
+assign wb_stb_o = wb_cyc_o;
+
+
+// Latching data read from registers
+always @ (posedge wb_clk_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ WBReadLatch[31:0]<=#Tp 32'h0;
+ else
+ if(wb_ack_i)
+ case (wb_sel_o)
+ 4'b0001: WBReadLatch[31:0]<=#Tp {24'h0, wb_dat_i[7:0]};
+ 4'b0010: WBReadLatch[31:0]<=#Tp {24'h0, wb_dat_i[15:8]};
+ 4'b0100: WBReadLatch[31:0]<=#Tp {24'h0, wb_dat_i[23:16]};
+ 4'b1000: WBReadLatch[31:0]<=#Tp {24'h0, wb_dat_i[31:24]};
+ 4'b0011: WBReadLatch[31:0]<=#Tp {16'h0, wb_dat_i[15:0]};
+ 4'b1100: WBReadLatch[31:0]<=#Tp {16'h0, wb_dat_i[31:16]};
+ default: WBReadLatch[31:0]<=#Tp wb_dat_i[31:0];
+ endcase
+end
+
+// Latching WISHBONE error cycle
+always @ (posedge wb_clk_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ WBErrorLatch<=#Tp 1'b0;
+ else
+ if(wb_err_i)
+ WBErrorLatch<=#Tp 1'b1; // Latching wb_err_i while performing WISHBONE access
+ else
+ if(wb_ack_i)
+ WBErrorLatch<=#Tp 1'b0; // Clearing status
+end
+
+
+// WBInProgress is set at the beginning of the access and cleared when wb_ack_i or wb_err_i is set
+always @ (posedge wb_clk_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ WBInProgress<=#Tp 1'b0;
+ else
+ if(wb_Access_wbClk & ~wb_Access_wbClk_q)
+ WBInProgress<=#Tp 1'b1;
+ else
+ if(wb_ack_i | wb_err_i | WBAccessCounterExceed)
+ WBInProgress<=#Tp 1'b0;
+end
+
+
+// Synchronizing WBInProgress
+always @ (posedge wb_clk_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ WBAccessCounter<=#Tp 8'h0;
+ else
+ if(wb_ack_i | wb_err_i | WBAccessCounterExceed)
+ WBAccessCounter<=#Tp 8'h0;
+ else
+ if(wb_cyc_o)
+ WBAccessCounter<=#Tp WBAccessCounter + 1'b1;
+end
+
+assign WBAccessCounterExceed = WBAccessCounter==8'hff;
+
+
+// Synchronizing WBInProgress
+always @ (posedge tck)
+begin
+ WBInProgress_sync1<=#Tp WBInProgress;
+ WBInProgress_tck<=#Tp WBInProgress_sync1;
+end
+
+
+// Whan enabled, TRACE stalls CPU while saving data to the trace buffer.
+`ifdef TRACE_ENABLED
+ assign cpu_stall_o = CpuStall_access | CpuStall_reg | CpuStall_trace ;
+`else
+ assign cpu_stall_o = CpuStall_access | CpuStall_reg;
+`endif
+
+assign reset_o = CpuReset_reg;
+
+
+`ifdef TRACE_ENABLED
+always @ (CpuStall_write_access_0 or CpuStall_write_access_1 or
+ CpuStall_write_access_2 or CpuStall_write_access_2 or
+ CpuStall_read_access_0 or CpuStall_read_access_1 or
+ CpuStall_read_access_2 or CpuStall_read_access_3 or opselect_trace)
+`else
+always @ (CpuStall_write_access_0 or CpuStall_write_access_1 or
+ CpuStall_write_access_2 or CpuStall_write_access_3 or
+ CpuStall_read_access_0 or CpuStall_read_access_1 or
+ CpuStall_read_access_2 or CpuStall_read_access_3)
+`endif
+begin
+ if(CpuStall_write_access_0)
+ opselect_o = `DEBUG_WRITE_0;
+ else
+ if(CpuStall_read_access_0)
+ opselect_o = `DEBUG_READ_0;
+ else
+ if(CpuStall_write_access_1)
+ opselect_o = `DEBUG_WRITE_1;
+ else
+ if(CpuStall_read_access_1)
+ opselect_o = `DEBUG_READ_1;
+ else
+ if(CpuStall_write_access_2)
+ opselect_o = `DEBUG_WRITE_2;
+ else
+ if(CpuStall_read_access_2)
+ opselect_o = `DEBUG_READ_2;
+ else
+ if(CpuStall_write_access_3)
+ opselect_o = `DEBUG_WRITE_3;
+ else
+ if(CpuStall_read_access_3)
+ opselect_o = `DEBUG_READ_3;
+ else
+`ifdef TRACE_ENABLED
+ opselect_o = opselect_trace;
+`else
+ opselect_o = 3'h0;
+`endif
+end
+
+
+// Latching data read from CPU or registers
+always @ (posedge cpu_clk_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ DataReadLatch[31:0]<=#Tp 0;
+ else
+ if(CPUAccess_q & ~CPUAccess_q2)
+ DataReadLatch[31:0]<=#Tp cpu_data_i[31:0];
+ else
+ if(RegAccess_q & ~RegAccess_q2)
+ DataReadLatch[31:0]<=#Tp RegDataIn[31:0];
+end
+
+assign cpu_addr_o = ADDR;
+assign cpu_data_o = DataOut;
+
+
+
+/**********************************************************************************
+* *
+* Read Trace buffer logic *
+* *
+**********************************************************************************/
+`ifdef TRACE_ENABLED
+
+
+// Synchronizing the trace read buffer signal to cpu_clk_i clock
+dbg_sync_clk1_clk2 syn4 (.clk1(cpu_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
+ .set2(ReadBuffer_Tck), .sync_out(ReadTraceBuffer)
+ );
+
+
+
+ always @(posedge cpu_clk_i or posedge wb_rst_i)
+ begin
+ if(wb_rst_i)
+ ReadTraceBuffer_q <=#Tp 0;
+ else
+ ReadTraceBuffer_q <=#Tp ReadTraceBuffer;
+ end
+
+ assign ReadTraceBufferPulse = ReadTraceBuffer & ~ReadTraceBuffer_q;
+
+`endif
+
+/**********************************************************************************
+* *
+* End: Read Trace buffer logic *
+* *
+**********************************************************************************/
+
+
+
+
+
+/**********************************************************************************
+* *
+* Bit counter *
+* *
+**********************************************************************************/
+
+
+always @ (posedge tck or posedge trst)
+begin
+ if(trst)
+ BitCounter[7:0]<=#Tp 0;
+ else
+ if(ShiftDR)
+ BitCounter[7:0]<=#Tp BitCounter[7:0]+1;
+ else
+ if(UpdateDR)
+ BitCounter[7:0]<=#Tp 0;
+end
+
+
+
+/**********************************************************************************
+* *
+* End: Bit counter *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* Connecting Registers *
+* *
+**********************************************************************************/
+dbg_registers dbgregs(.data_in(DataOut[31:0]), .data_out(RegDataIn[31:0]),
+ .address(ADDR[4:0]), .rw(RW), .access(RegAccess & ~RegAccess_q), .clk(cpu_clk_i),
+ .bp(bp_i), .reset(wb_rst_i),
+ `ifdef TRACE_ENABLED
+ .ContinMode(ContinMode), .TraceEnable(TraceEnable),
+ .WpTrigger(WpTrigger), .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger),
+ .ITrigger(ITrigger), .TriggerOper(TriggerOper), .WpQualif(WpQualif),
+ .BpQualif(BpQualif), .LSSQualif(LSSQualif), .IQualif(IQualif),
+ .QualifOper(QualifOper), .RecordPC(RecordPC),
+ .RecordLSEA(RecordLSEA), .RecordLDATA(RecordLDATA),
+ .RecordSDATA(RecordSDATA), .RecordReadSPR(RecordReadSPR),
+ .RecordWriteSPR(RecordWriteSPR), .RecordINSTR(RecordINSTR),
+ .WpTriggerValid(WpTriggerValid),
+ .BpTriggerValid(BpTriggerValid), .LSSTriggerValid(LSSTriggerValid),
+ .ITriggerValid(ITriggerValid), .WpQualifValid(WpQualifValid),
+ .BpQualifValid(BpQualifValid), .LSSQualifValid(LSSQualifValid),
+ .IQualifValid(IQualifValid),
+ .WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
+ .StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
+ .LSSStopValid(LSSStopValid), .IStopValid(IStopValid),
+ `endif
+ .cpu_stall(CpuStall_reg), .cpu_stall_all(cpu_stall_all_o), .cpu_sel(cpu_sel_o),
+ .cpu_reset(CpuReset_reg), .mon_cntl_o(mon_cntl_o), .wb_cntl_o(wb_cntl_o)
+
+ );
+
+/**********************************************************************************
+* *
+* End: Connecting Registers *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* Connecting CRC module *
+* *
+**********************************************************************************/
+wire AsyncResetCrc = trst;
+wire SyncResetCrc = UpdateDR_q;
+
+assign BitCounter_Lt4 = BitCounter<4;
+assign BitCounter_Eq5 = BitCounter==5;
+assign BitCounter_Eq32 = BitCounter==32;
+assign BitCounter_Lt38 = BitCounter<38;
+assign BitCounter_Lt65 = BitCounter<65;
+
+`ifdef TRACE_ENABLED
+ assign BitCounter_Lt40 = BitCounter<40;
+`endif
+
+
+// wire EnableCrcIn = ShiftDR &
+// ( (CHAIN_SELECTSelected & BitCounter_Lt4) |
+// ((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
+// ((DEBUGSelected & CpuDebugScanChain0) & BitCounter_Lt65)|
+// ((DEBUGSelected & CpuDebugScanChain1) & BitCounter_Lt65)|
+// ((DEBUGSelected & CpuDebugScanChain2) & BitCounter_Lt65)|
+// ((DEBUGSelected & CpuDebugScanChain3) & BitCounter_Lt65)|
+// ((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
+// );
+
+wire EnableCrc = ShiftDR &
+ ( (CHAIN_SELECTSelected & BitCounter_Lt4) |
+ ((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
+ ((DEBUGSelected & CpuDebugScanChain0) & BitCounter_Lt65)|
+ ((DEBUGSelected & CpuDebugScanChain1) & BitCounter_Lt65)|
+ ((DEBUGSelected & CpuDebugScanChain2) & BitCounter_Lt65)|
+ ((DEBUGSelected & CpuDebugScanChain3) & BitCounter_Lt65)|
+ ((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
+ `ifdef TRACE_ENABLED
+ |
+ ((DEBUGSelected & TraceTestScanChain) & BitCounter_Lt40)
+ `endif
+ );
+
+// wire EnableCrcOut= ShiftDR &
+// (
+// ((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
+// ((DEBUGSelected & CpuDebugScanChain0) & BitCounter_Lt65)|
+// ((DEBUGSelected & CpuDebugScanChain1) & BitCounter_Lt65)|
+// ((DEBUGSelected & CpuDebugScanChain2) & BitCounter_Lt65)|
+// ((DEBUGSelected & CpuDebugScanChain3) & BitCounter_Lt65)|
+// ((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
+// `ifdef TRACE_ENABLED
+// |
+// ((DEBUGSelected & TraceTestScanChain) & BitCounter_Lt40)
+// `endif
+// );
+
+// Calculating crc for input data
+//dbg_crc8_d1 crc1 (.data(tdi), .enable_crc(EnableCrcIn), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
+dbg_crc8_d1 crc1 (.data(tdi), .enable_crc(EnableCrc), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
+ .crc_out(CalculatedCrcIn), .clk(tck));
+
+// Calculating crc for output data
+//dbg_crc8_d1 crc2 (.data(TDOData), .enable_crc(EnableCrcOut), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
+dbg_crc8_d1 crc2 (.data(TDOData), .enable_crc(EnableCrc), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
+ .crc_out(CalculatedCrcOut), .clk(tck));
+
+
+reg [3:0] crc_cnt;
+always @ (posedge tck or posedge trst)
+begin
+ if (trst)
+ crc_cnt <= 0;
+ else if (Exit1DR)
+ crc_cnt <=#Tp 0;
+// else if ((~EnableCrcIn) & ShiftDR)
+ else if ((~EnableCrc) & ShiftDR)
+ crc_cnt <=#Tp crc_cnt + 1'b1;
+end
+
+
+// Generating CrcMatch signal.
+always @ (posedge tck or posedge trst)
+begin
+ if(trst)
+ CrcMatch <=#Tp 1'b1;
+ else if (SelectDRScan)
+ CrcMatch <=#Tp 1'b1;
+// else if ((~EnableCrcIn) & ShiftDR)
+ else if ((~EnableCrc) & ShiftDR)
+ begin
+ if (tdi != CalculatedCrcIn[crc_cnt])
+ CrcMatch <=#Tp 1'b0;
+ end
+end
+
+
+// Generating CrcMatch_q signal.
+always @ (posedge tck or posedge trst)
+begin
+ CrcMatch_q <=#Tp CrcMatch;
+end
+
+
+// Active chain
+assign RegisterScanChain = Chain == `REGISTER_SCAN_CHAIN;
+assign CpuDebugScanChain0 = Chain == `CPU_DEBUG_CHAIN_0;
+assign CpuDebugScanChain1 = Chain == `CPU_DEBUG_CHAIN_1;
+assign CpuDebugScanChain2 = Chain == `CPU_DEBUG_CHAIN_2;
+assign CpuDebugScanChain3 = Chain == `CPU_DEBUG_CHAIN_3;
+assign WishboneScanChain = Chain == `WISHBONE_SCAN_CHAIN;
+
+`ifdef TRACE_ENABLED
+ assign TraceTestScanChain = Chain == `TRACE_TEST_CHAIN;
+`endif
+
+/**********************************************************************************
+* *
+* End: Connecting CRC module *
+* *
+**********************************************************************************/
+
+/**********************************************************************************
+* *
+* Connecting trace module *
+* *
+**********************************************************************************/
+`ifdef TRACE_ENABLED
+ dbg_trace dbgTrace1(.Wp(wp_i), .Bp(bp_i), .DataIn(cpu_data_i), .OpSelect(opselect_trace),
+ .LsStatus(lsstatus_i), .IStatus(istatus_i), .CpuStall_O(CpuStall_trace),
+ .Mclk(cpu_clk_i), .Reset(wb_rst_i), .TraceChain(TraceChain),
+ .ContinMode(ContinMode), .TraceEnable_reg(TraceEnable),
+ .WpTrigger(WpTrigger),
+ .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger), .ITrigger(ITrigger),
+ .TriggerOper(TriggerOper), .WpQualif(WpQualif), .BpQualif(BpQualif),
+ .LSSQualif(LSSQualif), .IQualif(IQualif), .QualifOper(QualifOper),
+ .RecordPC(RecordPC), .RecordLSEA(RecordLSEA),
+ .RecordLDATA(RecordLDATA), .RecordSDATA(RecordSDATA),
+ .RecordReadSPR(RecordReadSPR), .RecordWriteSPR(RecordWriteSPR),
+ .RecordINSTR(RecordINSTR),
+ .WpTriggerValid(WpTriggerValid), .BpTriggerValid(BpTriggerValid),
+ .LSSTriggerValid(LSSTriggerValid), .ITriggerValid(ITriggerValid),
+ .WpQualifValid(WpQualifValid), .BpQualifValid(BpQualifValid),
+ .LSSQualifValid(LSSQualifValid), .IQualifValid(IQualifValid),
+ .ReadBuffer(ReadTraceBufferPulse),
+ .WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
+ .StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
+ .LSSStopValid(LSSStopValid), .IStopValid(IStopValid)
+ );
+`endif
+/**********************************************************************************
+* *
+* End: Connecting trace module *
+* *
+**********************************************************************************/
+
+
+
+endmodule
Index: tags/rel_10/rtl/verilog/dbg_registers.v
===================================================================
--- tags/rel_10/rtl/verilog/dbg_registers.v (nonexistent)
+++ tags/rel_10/rtl/verilog/dbg_registers.v (revision 76)
@@ -0,0 +1,347 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// dbg_registers.v ////
+//// ////
+//// ////
+//// This file is part of the SoC/OpenRISC Development Interface ////
+//// http://www.opencores.org/cores/DebugInterface/ ////
+//// ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor ////
+//// igorm@opencores.org ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000,2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.12 2003/09/17 14:38:57 simons
+// WB_CNTL register added, some syncronization fixes.
+//
+// Revision 1.11 2003/07/31 14:01:53 simons
+// Lapsus fixed.
+//
+// Revision 1.9 2003/07/31 12:19:49 simons
+// Multiple cpu support added.
+//
+// Revision 1.8 2002/10/10 02:42:55 mohor
+// WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.
+//
+// Revision 1.7 2002/05/07 14:43:59 mohor
+// mon_cntl_o signals that controls monitor mux added.
+//
+// Revision 1.6 2002/04/22 12:54:11 mohor
+// Signal names changed to lower case.
+//
+// Revision 1.5 2001/11/26 10:47:09 mohor
+// Crc generation is different for read or write commands. Small synthesys fixes.
+//
+// Revision 1.4 2001/10/19 11:40:02 mohor
+// dbg_timescale.v changed to timescale.v This is done for the simulation of
+// few different cores in a single project.
+//
+// Revision 1.3 2001/10/15 09:55:47 mohor
+// Wishbone interface added, few fixes for better performance,
+// hooks for boundary scan testing added.
+//
+// Revision 1.2 2001/09/18 14:13:47 mohor
+// Trace fixed. Some registers changed, trace simplified.
+//
+// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
+// Initial official release.
+//
+// Revision 1.3 2001/06/01 22:22:35 mohor
+// This is a backup. It is not a fully working version. Not for use, yet.
+//
+// Revision 1.2 2001/05/18 13:10:00 mohor
+// Headers changed. All additional information is now avaliable in the README.txt file.
+//
+// Revision 1.1.1.1 2001/05/18 06:35:10 mohor
+// Initial release
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "dbg_defines.v"
+
+module dbg_registers(data_in, data_out, address, rw, access, clk, bp, reset,
+ `ifdef TRACE_ENABLED
+ ContinMode,
+ TraceEnable, WpTrigger, BpTrigger, LSSTrigger,
+ ITrigger, TriggerOper, WpQualif, BpQualif, LSSQualif, IQualif,
+ QualifOper, RecordPC, RecordLSEA, RecordLDATA,
+ RecordSDATA, RecordReadSPR, RecordWriteSPR, RecordINSTR,
+ WpTriggerValid, BpTriggerValid, LSSTriggerValid, ITriggerValid,
+ WpQualifValid, BpQualifValid, LSSQualifValid, IQualifValid,
+ WpStop, BpStop, LSSStop, IStop, StopOper, WpStopValid, BpStopValid,
+ LSSStopValid, IStopValid,
+ `endif
+ cpu_stall, cpu_stall_all, cpu_sel, cpu_reset, mon_cntl_o, wb_cntl_o
+ );
+
+parameter Tp = 1;
+
+input [31:0] data_in;
+input [4:0] address;
+
+input rw;
+input access;
+input clk;
+input bp;
+input reset;
+
+output [31:0] data_out;
+reg [31:0] data_out;
+
+`ifdef TRACE_ENABLED
+ output ContinMode;
+ output TraceEnable;
+
+ output [10:0] WpTrigger;
+ output BpTrigger;
+ output [3:0] LSSTrigger;
+ output [1:0] ITrigger;
+ output [1:0] TriggerOper;
+
+ output WpTriggerValid;
+ output BpTriggerValid;
+ output LSSTriggerValid;
+ output ITriggerValid;
+
+ output [10:0] WpQualif;
+ output BpQualif;
+ output [3:0] LSSQualif;
+ output [1:0] IQualif;
+ output [1:0] QualifOper;
+
+ output WpQualifValid;
+ output BpQualifValid;
+ output LSSQualifValid;
+ output IQualifValid;
+
+ output [10:0] WpStop;
+ output BpStop;
+ output [3:0] LSSStop;
+ output [1:0] IStop;
+ output [1:0] StopOper;
+
+ output WpStopValid;
+ output BpStopValid;
+ output LSSStopValid;
+ output IStopValid;
+
+ output RecordPC;
+ output RecordLSEA;
+ output RecordLDATA;
+ output RecordSDATA;
+ output RecordReadSPR;
+ output RecordWriteSPR;
+ output RecordINSTR;
+`endif
+
+ output cpu_stall;
+ output cpu_stall_all;
+ output [`CPU_NUM-1:0] cpu_sel;
+ output cpu_reset;
+ output [3:0] mon_cntl_o;
+ output [1:0] wb_cntl_o;
+
+ wire MODER_Acc = (address == `MODER_ADR) & access;
+ wire CPUOP_Acc = (address == `CPUOP_ADR) & access;
+ wire CPUSEL_Acc = (address == `CPUSEL_ADR) & access;
+ wire MON_CNTL_Acc = (address == `MON_CNTL_ADR) & access;
+ wire WB_CNTL_Acc = (address == `WB_CNTL_ADR) & access;
+`ifdef TRACE_ENABLED
+ wire TSEL_Acc = (address == `TSEL_ADR) & access;
+ wire QSEL_Acc = (address == `QSEL_ADR) & access;
+ wire SSEL_Acc = (address == `SSEL_ADR) & access;
+ wire RECSEL_Acc = (address == `RECSEL_ADR) & access;
+`endif
+
+
+ wire MODER_Wr = MODER_Acc & rw;
+ wire CPUOP_Wr = CPUOP_Acc & rw;
+ wire CPUSEL_Wr = CPUSEL_Acc & rw;
+ wire MON_CNTL_Wr = MON_CNTL_Acc & rw;
+ wire WB_CNTL_Wr = WB_CNTL_Acc & rw;
+`ifdef TRACE_ENABLED
+ wire TSEL_Wr = TSEL_Acc & rw;
+ wire QSEL_Wr = QSEL_Acc & rw;
+ wire SSEL_Wr = SSEL_Acc & rw;
+ wire RECSEL_Wr = RECSEL_Acc & rw;
+`endif
+
+
+
+ wire MODER_Rd = MODER_Acc & ~rw;
+ wire CPUOP_Rd = CPUOP_Acc & ~rw;
+ wire CPUSEL_Rd = CPUSEL_Acc & ~rw;
+ wire MON_CNTL_Rd = MON_CNTL_Acc & ~rw;
+ wire WB_CNTL_Rd = WB_CNTL_Acc & ~rw;
+`ifdef TRACE_ENABLED
+ wire TSEL_Rd = TSEL_Acc & ~rw;
+ wire QSEL_Rd = QSEL_Acc & ~rw;
+ wire SSEL_Rd = SSEL_Acc & ~rw;
+ wire RECSEL_Rd = RECSEL_Acc & ~rw;
+`endif
+
+
+ wire [31:0] MODEROut;
+ wire [2:1] CPUOPOut;
+ wire [`CPU_NUM-1:0] CPUSELOut;
+ wire [3:0] MONCNTLOut;
+ wire [1:0] WB_CNTLOut;
+
+`ifdef TRACE_ENABLED
+ wire [31:0] TSELOut;
+ wire [31:0] QSELOut;
+ wire [31:0] SSELOut;
+ wire [6:0] RECSELOut;
+`endif
+
+
+`ifdef TRACE_ENABLED
+ assign MODEROut[15:0] = 16'h0001;
+ assign MODEROut[31:18] = 14'h0;
+`else
+ assign MODEROut[31:0] = 32'h0000;
+`endif
+
+
+ reg CpuStallBp;
+ always @(posedge clk or posedge reset)
+ begin
+ if(reset)
+ CpuStallBp <= 1'b0;
+ else
+ if(bp) // Breakpoint sets bit
+ CpuStallBp <= 1'b1;
+ else
+ if(CPUOP_Wr) // Register access can set or clear bit
+ CpuStallBp <= data_in[0];
+ end
+
+ dbg_register #(2, 0) CPUOP (.data_in(data_in[2:1]), .data_out(CPUOPOut[2:1]), .write(CPUOP_Wr), .clk(clk), .reset(reset));
+ dbg_register #(`CPU_NUM, 1) CPUSEL (.data_in(data_in[`CPU_NUM-1:0]), .data_out(CPUSELOut), .write(CPUSEL_Wr), .clk(clk), .reset(reset));
+ dbg_register #(4, `MON_CNTL_DEF) MONCNTL (.data_in(data_in[3:0]), .data_out(MONCNTLOut[3:0]), .write(MON_CNTL_Wr), .clk(clk), .reset(reset));
+ dbg_register #(2, 0) WBCNTL (.data_in(data_in[1:0]), .data_out(WB_CNTLOut[1:0]), .write(WB_CNTL_Wr), .clk(clk), .reset(reset));
+
+
+`ifdef TRACE_ENABLED
+ dbg_register #(2, `MODER_DEF) MODER (.data_in(data_in[17:16]), .data_out(MODEROut[17:16]), .write(MODER_Wr), .clk(clk), .reset(reset));
+ dbg_register #(32, `TSEL_DEF) TSEL (.data_in(data_in), .data_out(TSELOut), .write(TSEL_Wr), .clk(clk), .reset(reset));
+ dbg_register #(32, `QSEL_DEF) QSEL (.data_in(data_in), .data_out(QSELOut), .write(QSEL_Wr), .clk(clk), .reset(reset));
+ dbg_register #(32, `SSEL_DEF) SSEL (.data_in(data_in), .data_out(SSELOut), .write(SSEL_Wr), .clk(clk), .reset(reset));
+ dbg_register #(7, `RECSEL_DEF) RECSEL (.data_in(data_in[6:0]), .data_out(RECSELOut), .write(RECSEL_Wr), .clk(clk), .reset(reset));
+`endif
+
+
+
+always @ (posedge clk)
+begin
+ if(MODER_Rd) data_out<= #Tp MODEROut;
+ else
+ if(CPUOP_Rd) data_out<= #Tp {29'h0, CPUOPOut[2:1], cpu_stall};
+ else
+ if(CPUSEL_Rd) data_out<= #Tp {{(32-`CPU_NUM){1'b0}}, CPUSELOut};
+ else
+ if(MON_CNTL_Rd) data_out<= #Tp {28'h0, MONCNTLOut};
+ else
+ if(WB_CNTL_Rd) data_out<= #Tp {30'h0, WB_CNTLOut};
+`ifdef TRACE_ENABLED
+ else
+ if(TSEL_Rd) data_out<= #Tp TSELOut;
+ else
+ if(QSEL_Rd) data_out<= #Tp QSELOut;
+ else
+ if(SSEL_Rd) data_out<= #Tp SSELOut;
+ else
+ if(RECSEL_Rd) data_out<= #Tp {25'h0, RECSELOut};
+`endif
+ else data_out<= #Tp 'h0;
+end
+
+`ifdef TRACE_ENABLED
+ assign TraceEnable = MODEROut[16];
+ assign ContinMode = MODEROut[17];
+
+ assign WpTrigger[10:0] = TSELOut[10:0];
+ assign WpTriggerValid = TSELOut[11];
+ assign BpTrigger = TSELOut[12];
+ assign BpTriggerValid = TSELOut[13];
+ assign LSSTrigger[3:0] = TSELOut[19:16];
+ assign LSSTriggerValid = TSELOut[20];
+ assign ITrigger[1:0] = TSELOut[22:21];
+ assign ITriggerValid = TSELOut[23];
+ assign TriggerOper[1:0] = TSELOut[31:30];
+
+ assign WpQualif[10:0] = QSELOut[10:0];
+ assign WpQualifValid = QSELOut[11];
+ assign BpQualif = QSELOut[12];
+ assign BpQualifValid = QSELOut[13];
+ assign LSSQualif[3:0] = QSELOut[19:16];
+ assign LSSQualifValid = QSELOut[20];
+ assign IQualif[1:0] = QSELOut[22:21];
+ assign IQualifValid = QSELOut[23];
+ assign QualifOper[1:0] = QSELOut[31:30];
+
+ assign WpStop[10:0] = SSELOut[10:0];
+ assign WpStopValid = SSELOut[11];
+ assign BpStop = SSELOut[12];
+ assign BpStopValid = SSELOut[13];
+ assign LSSStop[3:0] = SSELOut[19:16];
+ assign LSSStopValid = SSELOut[20];
+ assign IStop[1:0] = SSELOut[22:21];
+ assign IStopValid = SSELOut[23];
+ assign StopOper[1:0] = SSELOut[31:30];
+
+
+ assign RecordPC = RECSELOut[0];
+ assign RecordLSEA = RECSELOut[1];
+ assign RecordLDATA = RECSELOut[2];
+ assign RecordSDATA = RECSELOut[3];
+ assign RecordReadSPR = RECSELOut[4];
+ assign RecordWriteSPR = RECSELOut[5];
+ assign RecordINSTR = RECSELOut[6];
+`endif
+
+ assign cpu_stall = bp | CpuStallBp; // bp asynchronously sets the cpu_stall, then CpuStallBp (from register) holds it active
+ assign cpu_stall_all = CPUOPOut[2]; // this signal is used to stall all the cpus except the one that is selected in cpusel register
+ assign cpu_sel = CPUSELOut;
+ assign cpu_reset = CPUOPOut[1];
+ assign mon_cntl_o = MONCNTLOut;
+ assign wb_cntl_o = WB_CNTLOut;
+
+endmodule
Index: tags/rel_10/rtl/verilog/tap_top.v
===================================================================
--- tags/rel_10/rtl/verilog/tap_top.v (nonexistent)
+++ tags/rel_10/rtl/verilog/tap_top.v (revision 76)
@@ -0,0 +1,629 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// tap_top.v ////
+//// ////
+//// ////
+//// This file is part of the SoC/OpenRISC Development Interface ////
+//// http://www.opencores.org/projects/DebugInterface/ ////
+//// ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor ////
+//// igorm@opencores.org ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000, 2001, 2002 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.8 2003/10/21 09:48:31 simons
+// Mbist support added.
+//
+// Revision 1.7 2002/11/06 14:30:10 mohor
+// Trst active high. Inverted on higher layer.
+//
+// Revision 1.6 2002/04/22 12:55:56 mohor
+// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
+//
+// Revision 1.5 2002/03/26 14:23:38 mohor
+// Signal tdo_padoe_o changed back to tdo_padoen_o.
+//
+// Revision 1.4 2002/03/25 13:16:15 mohor
+// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
+// not named correctly.
+//
+// Revision 1.3 2002/03/12 14:30:05 mohor
+// Few outputs for boundary scan chain added.
+//
+// Revision 1.2 2002/03/12 10:31:53 mohor
+// tap_top and dbg_top modules are put into two separate modules. tap_top
+// contains only tap state machine and related logic. dbg_top contains all
+// logic necessery for debugging.
+//
+// Revision 1.1 2002/03/08 15:28:16 mohor
+// Structure changed. Hooks for jtag chain added.
+//
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "dbg_defines.v"
+
+// Top module
+module tap_top(
+ // JTAG pins
+ tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o, tdo_padoe_o,
+
+ // TAP states
+ ShiftDR, Exit1DR, UpdateDR, UpdateDR_q, CaptureDR, SelectDRScan,
+
+ // Instructions
+ IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected, EXTESTSelected, MBISTSelected,
+
+ // TDO from dbg module
+ TDOData_dbg, BypassRegister,
+
+ // From Boundary Scan Chain
+ bs_chain_i,
+
+ // From Mbist Chain
+ mbist_so_i,
+
+ // Selected chains
+ RegisterScanChain,
+ CpuDebugScanChain0,
+ CpuDebugScanChain1,
+ CpuDebugScanChain2,
+ CpuDebugScanChain3,
+ WishboneScanChain
+
+
+
+ );
+
+parameter Tp = 1;
+
+// JTAG pins
+input tms_pad_i; // JTAG test mode select pad
+input tck_pad_i; // JTAG test clock pad
+input trst_pad_i; // JTAG test reset pad
+input tdi_pad_i; // JTAG test data input pad
+output tdo_pad_o; // JTAG test data output pad
+output tdo_padoe_o; // Output enable for JTAG test data output pad
+
+// TAP states
+output ShiftDR;
+output Exit1DR;
+output UpdateDR;
+output UpdateDR_q;
+output CaptureDR;
+output SelectDRScan;
+
+// Instructions
+output IDCODESelected;
+output CHAIN_SELECTSelected;
+output DEBUGSelected;
+output EXTESTSelected;
+output MBISTSelected;
+
+input TDOData_dbg;
+output BypassRegister;
+
+// From Boundary Scan Chain
+input bs_chain_i;
+
+// From Mbist Chain
+input mbist_so_i;
+
+// Selected chains
+input RegisterScanChain;
+input CpuDebugScanChain0;
+input CpuDebugScanChain1;
+input CpuDebugScanChain2;
+input CpuDebugScanChain3;
+input WishboneScanChain;
+
+
+reg tdo_pad_o;
+
+// TAP states
+reg TestLogicReset;
+reg RunTestIdle;
+reg SelectDRScan;
+reg CaptureDR;
+reg ShiftDR;
+reg Exit1DR;
+reg PauseDR;
+reg Exit2DR;
+reg UpdateDR;
+
+reg SelectIRScan;
+reg CaptureIR;
+reg ShiftIR;
+reg Exit1IR;
+reg PauseIR;
+reg Exit2IR;
+reg UpdateIR;
+
+
+// Defining which instruction is selected
+reg EXTESTSelected;
+reg SAMPLE_PRELOADSelected;
+reg IDCODESelected;
+reg CHAIN_SELECTSelected;
+reg MBISTSelected;
+reg CLAMPSelected;
+reg CLAMPZSelected;
+reg HIGHZSelected;
+reg DEBUGSelected;
+reg BYPASSSelected;
+
+reg BypassRegister; // Bypass register
+
+wire trst;
+wire tck;
+wire TMS;
+wire tdi;
+
+
+assign trst = trst_pad_i; // trst_pad_i is active high !!! Inverted on higher layer
+assign tck = tck_pad_i;
+assign TMS = tms_pad_i;
+assign tdi = tdi_pad_i;
+
+
+/**********************************************************************************
+* *
+* TAP State Machine: Fully JTAG compliant *
+* *
+**********************************************************************************/
+
+// TestLogicReset state
+always @ (posedge tck or posedge trst)
+begin
+ if(trst)
+ TestLogicReset<=#Tp 1;
+ else
+ begin
+ if(TMS & (TestLogicReset | SelectIRScan))
+ TestLogicReset<=#Tp 1;
+ else
+ TestLogicReset<=#Tp 0;
+ end
+end
+
+// RunTestIdle state
+always @ (posedge tck or posedge trst)
+begin
+ if(trst)
+ RunTestIdle<=#Tp 0;
+ else
+ if(~TMS & (TestLogicReset | RunTestIdle | UpdateDR | UpdateIR))
+ RunTestIdle<=#Tp 1;
+ else
+ RunTestIdle<=#Tp 0;
+end
+
+// SelectDRScan state
+always @ (posedge tck or posedge trst)
+begin
+ if(trst)
+ SelectDRScan<=#Tp 0;
+ else
+ if(TMS & (RunTestIdle | UpdateDR | UpdateIR))
+ SelectDRScan<=#Tp 1;
+ else
+ SelectDRScan<=#Tp 0;
+end
+
+// CaptureDR state
+always @ (posedge tck or posedge trst)
+begin
+ if(trst)
+ CaptureDR<=#Tp 0;
+ else
+ if(~TMS & SelectDRScan)
+ CaptureDR<=#Tp 1;
+ else
+ CaptureDR<=#Tp 0;
+end
+
+// ShiftDR state
+always @ (posedge tck or posedge trst)
+begin
+ if(trst)
+ ShiftDR<=#Tp 0;
+ else
+ if(~TMS & (CaptureDR | ShiftDR | Exit2DR))
+ ShiftDR<=#Tp 1;
+ else
+ ShiftDR<=#Tp 0;
+end
+
+// Exit1DR state
+always @ (posedge tck or posedge trst)
+begin
+ if(trst)
+ Exit1DR<=#Tp 0;
+ else
+ if(TMS & (CaptureDR | ShiftDR))
+ Exit1DR<=#Tp 1;
+ else
+ Exit1DR<=#Tp 0;
+end
+
+// PauseDR state
+always @ (posedge tck or posedge trst)
+begin
+ if(trst)
+ PauseDR<=#Tp 0;
+ else
+ if(~TMS & (Exit1DR | PauseDR))
+ PauseDR<=#Tp 1;
+ else
+ PauseDR<=#Tp 0;
+end
+
+// Exit2DR state
+always @ (posedge tck or posedge trst)
+begin
+ if(trst)
+ Exit2DR<=#Tp 0;
+ else
+ if(TMS & PauseDR)
+ Exit2DR<=#Tp 1;
+ else
+ Exit2DR<=#Tp 0;
+end
+
+// UpdateDR state
+always @ (posedge tck or posedge trst)
+begin
+ if(trst)
+ UpdateDR<=#Tp 0;
+ else
+ if(TMS & (Exit1DR | Exit2DR))
+ UpdateDR<=#Tp 1;
+ else
+ UpdateDR<=#Tp 0;
+end
+
+// Delayed UpdateDR state
+reg UpdateDR_q;
+always @ (posedge tck)
+begin
+ UpdateDR_q<=#Tp UpdateDR;
+end
+
+// SelectIRScan state
+always @ (posedge tck or posedge trst)
+begin
+ if(trst)
+ SelectIRScan<=#Tp 0;
+ else
+ if(TMS & SelectDRScan)
+ SelectIRScan<=#Tp 1;
+ else
+ SelectIRScan<=#Tp 0;
+end
+
+// CaptureIR state
+always @ (posedge tck or posedge trst)
+begin
+ if(trst)
+ CaptureIR<=#Tp 0;
+ else
+ if(~TMS & SelectIRScan)
+ CaptureIR<=#Tp 1;
+ else
+ CaptureIR<=#Tp 0;
+end
+
+// ShiftIR state
+always @ (posedge tck or posedge trst)
+begin
+ if(trst)
+ ShiftIR<=#Tp 0;
+ else
+ if(~TMS & (CaptureIR | ShiftIR | Exit2IR))
+ ShiftIR<=#Tp 1;
+ else
+ ShiftIR<=#Tp 0;
+end
+
+// Exit1IR state
+always @ (posedge tck or posedge trst)
+begin
+ if(trst)
+ Exit1IR<=#Tp 0;
+ else
+ if(TMS & (CaptureIR | ShiftIR))
+ Exit1IR<=#Tp 1;
+ else
+ Exit1IR<=#Tp 0;
+end
+
+// PauseIR state
+always @ (posedge tck or posedge trst)
+begin
+ if(trst)
+ PauseIR<=#Tp 0;
+ else
+ if(~TMS & (Exit1IR | PauseIR))
+ PauseIR<=#Tp 1;
+ else
+ PauseIR<=#Tp 0;
+end
+
+// Exit2IR state
+always @ (posedge tck or posedge trst)
+begin
+ if(trst)
+ Exit2IR<=#Tp 0;
+ else
+ if(TMS & PauseIR)
+ Exit2IR<=#Tp 1;
+ else
+ Exit2IR<=#Tp 0;
+end
+
+// UpdateIR state
+always @ (posedge tck or posedge trst)
+begin
+ if(trst)
+ UpdateIR<=#Tp 0;
+ else
+ if(TMS & (Exit1IR | Exit2IR))
+ UpdateIR<=#Tp 1;
+ else
+ UpdateIR<=#Tp 0;
+end
+
+/**********************************************************************************
+* *
+* End: TAP State Machine *
+* *
+**********************************************************************************/
+
+
+
+/**********************************************************************************
+* *
+* JTAG_IR: JTAG Instruction Register *
+* *
+**********************************************************************************/
+wire [1:0]Status = 2'b10; // Holds current chip status. Core should return this status. For now a constant is used.
+
+reg [`IR_LENGTH-1:0]JTAG_IR; // Instruction register
+reg [`IR_LENGTH-1:0]LatchedJTAG_IR;
+
+reg TDOInstruction;
+
+always @ (posedge tck or posedge trst)
+begin
+ if(trst)
+ JTAG_IR[`IR_LENGTH-1:0] <= #Tp 0;
+ else
+ if(CaptureIR)
+ begin
+ JTAG_IR[1:0] <= #Tp 2'b01; // This value is fixed for easier fault detection
+ JTAG_IR[3:2] <= #Tp Status[1:0]; // Current status of chip
+ end
+ else
+ if(ShiftIR)
+ JTAG_IR[`IR_LENGTH-1:0] <= #Tp {tdi, JTAG_IR[`IR_LENGTH-1:1]};
+end
+
+
+//TDO is changing on the falling edge of tck
+always @ (negedge tck or posedge trst)
+begin
+ if (trst)
+ TDOInstruction <= #Tp 1'b0;
+ else if(ShiftIR)
+ TDOInstruction <= #Tp JTAG_IR[0];
+end
+
+/**********************************************************************************
+* *
+* End: JTAG_IR *
+* *
+**********************************************************************************/
+
+
+/**********************************************************************************
+* *
+* JTAG_DR: JTAG Data Register *
+* *
+**********************************************************************************/
+reg [`DR_LENGTH-1:0]JTAG_DR_IN; // Data register
+
+
+always @ (posedge tck or posedge trst)
+begin
+ if(trst)
+ JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
+ else
+ if(IDCODESelected) // To save space JTAG_DR_IN is also used for shifting out IDCODE
+ begin
+ if(ShiftDR)
+ JTAG_DR_IN[31:0] <= #Tp {tdi, JTAG_DR_IN[31:1]};
+ else
+ JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
+ end
+ else
+ if(CHAIN_SELECTSelected & ShiftDR)
+ JTAG_DR_IN[11:0] <= #Tp {tdi, JTAG_DR_IN[11:1]};
+ else
+ if(DEBUGSelected & ShiftDR)
+ begin
+ if(CpuDebugScanChain0 | CpuDebugScanChain1 | CpuDebugScanChain2 | CpuDebugScanChain3 | WishboneScanChain)
+ JTAG_DR_IN[72:0] <= #Tp {tdi, JTAG_DR_IN[72:1]};
+ else
+ if(RegisterScanChain)
+ JTAG_DR_IN[45:0] <= #Tp {tdi, JTAG_DR_IN[45:1]};
+ end
+end
+
+
+
+/**********************************************************************************
+* *
+* End: JTAG_DR *
+* *
+**********************************************************************************/
+
+
+
+
+
+/**********************************************************************************
+* *
+* Bypass logic *
+* *
+**********************************************************************************/
+reg TDOBypassed;
+
+always @ (posedge tck or posedge trst)
+begin
+ if (trst)
+ BypassRegister<=#Tp 1'b0;
+ else if(ShiftDR)
+ BypassRegister<=#Tp tdi;
+end
+
+always @ (negedge tck)
+begin
+ TDOBypassed<=#Tp BypassRegister;
+end
+/**********************************************************************************
+* *
+* End: Bypass logic *
+* *
+**********************************************************************************/
+
+
+
+
+
+/**********************************************************************************
+* *
+* Activating Instructions *
+* *
+**********************************************************************************/
+
+// Updating JTAG_IR (Instruction Register)
+always @ (posedge tck or posedge trst)
+begin
+ if(trst)
+ LatchedJTAG_IR <=#Tp `IDCODE; // IDCODE selected after reset
+ else
+ if(UpdateIR)
+ LatchedJTAG_IR <=#Tp JTAG_IR;
+end
+
+/**********************************************************************************
+* *
+* End: Activating Instructions *
+* *
+**********************************************************************************/
+
+
+// Updating JTAG_IR (Instruction Register)
+always @ (LatchedJTAG_IR)
+begin
+ EXTESTSelected = 0;
+ SAMPLE_PRELOADSelected = 0;
+ IDCODESelected = 0;
+ CHAIN_SELECTSelected = 0;
+ MBISTSelected = 0;
+ CLAMPSelected = 0;
+ CLAMPZSelected = 0;
+ HIGHZSelected = 0;
+ DEBUGSelected = 0;
+ BYPASSSelected = 0;
+
+ case(LatchedJTAG_IR)
+ `EXTEST: EXTESTSelected = 1; // External test
+ `SAMPLE_PRELOAD: SAMPLE_PRELOADSelected = 1; // Sample preload
+ `IDCODE: IDCODESelected = 1; // ID Code
+ `CHAIN_SELECT: CHAIN_SELECTSelected = 1; // Chain select
+ `MBIST: MBISTSelected = 1; // Mbist test
+ `CLAMP: CLAMPSelected = 1; // Clamp
+ `CLAMPZ: CLAMPZSelected = 1; // ClampZ
+ `HIGHZ: HIGHZSelected = 1; // High Z
+ `DEBUG: DEBUGSelected = 1; // Debug
+ `BYPASS: BYPASSSelected = 1; // BYPASS
+ default: BYPASSSelected = 1; // BYPASS
+ endcase
+end
+
+
+
+/**********************************************************************************
+* *
+* Multiplexing TDO data *
+* *
+**********************************************************************************/
+
+// This multiplexer can be expanded with number of user registers
+always @ (LatchedJTAG_IR or TDOInstruction or TDOData_dbg or TDOBypassed or bs_chain_i or mbist_so_i or ShiftIR or Exit1IR)
+begin
+ if(ShiftIR | Exit1IR)
+ tdo_pad_o <=#Tp TDOInstruction;
+ else
+ begin
+ case(LatchedJTAG_IR)
+ `IDCODE: tdo_pad_o <=#Tp TDOData_dbg; // Reading ID code
+ `CHAIN_SELECT: tdo_pad_o <=#Tp TDOData_dbg; // Selecting the chain
+ `DEBUG: tdo_pad_o <=#Tp TDOData_dbg; // Debug
+ `SAMPLE_PRELOAD: tdo_pad_o <=#Tp bs_chain_i; // Sampling/Preloading
+ `EXTEST: tdo_pad_o <=#Tp bs_chain_i; // External test
+ `INTEST: tdo_pad_o <=#Tp mbist_so_i; // External test
+ default: tdo_pad_o <=#Tp TDOBypassed; // BYPASS instruction
+ endcase
+ end
+end
+
+// Tristate control for tdo_pad_o pin
+assign tdo_padoe_o = ShiftIR | ShiftDR | Exit1IR | Exit1DR | UpdateDR;
+
+/**********************************************************************************
+* *
+* End: Multiplexing TDO data *
+* *
+**********************************************************************************/
+
+endmodule
Index: tags/rel_10/rtl/verilog/dbg_defines.v
===================================================================
--- tags/rel_10/rtl/verilog/dbg_defines.v (nonexistent)
+++ tags/rel_10/rtl/verilog/dbg_defines.v (revision 76)
@@ -0,0 +1,190 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// dbg_defines.v ////
+//// ////
+//// ////
+//// This file is part of the SoC/OpenRISC Development Interface ////
+//// http://www.opencores.org/cores/DebugInterface/ ////
+//// ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor ////
+//// igorm@opencores.org ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000,2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.13 2003/10/21 09:48:31 simons
+// Mbist support added.
+//
+// Revision 1.12 2003/09/17 14:38:57 simons
+// WB_CNTL register added, some syncronization fixes.
+//
+// Revision 1.11 2003/08/28 13:55:21 simons
+// Three more chains added for cpu debug access.
+//
+// Revision 1.10 2003/07/31 12:19:49 simons
+// Multiple cpu support added.
+//
+// Revision 1.9 2002/05/07 14:43:59 mohor
+// mon_cntl_o signals that controls monitor mux added.
+//
+// Revision 1.8 2002/01/25 07:58:34 mohor
+// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
+// not filled-in. Tested in hw.
+//
+// Revision 1.7 2001/12/06 10:08:06 mohor
+// Warnings from synthesys tools fixed.
+//
+// Revision 1.6 2001/11/28 09:38:30 mohor
+// Trace disabled by default.
+//
+// Revision 1.5 2001/10/15 09:55:47 mohor
+// Wishbone interface added, few fixes for better performance,
+// hooks for boundary scan testing added.
+//
+// Revision 1.4 2001/09/24 14:06:42 mohor
+// Changes connected to the OpenRISC access (SPR read, SPR write).
+//
+// Revision 1.3 2001/09/20 10:11:25 mohor
+// Working version. Few bugs fixed, comments added.
+//
+// Revision 1.2 2001/09/18 14:13:47 mohor
+// Trace fixed. Some registers changed, trace simplified.
+//
+// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
+// Initial official release.
+//
+// Revision 1.3 2001/06/01 22:22:35 mohor
+// This is a backup. It is not a fully working version. Not for use, yet.
+//
+// Revision 1.2 2001/05/18 13:10:00 mohor
+// Headers changed. All additional information is now avaliable in the README.txt file.
+//
+// Revision 1.1.1.1 2001/05/18 06:35:08 mohor
+// Initial release
+//
+//
+
+
+
+// Enable TRACE
+//`define TRACE_ENABLED // Uncomment this define to activate the trace
+
+// Define number of cpus supported by the dbg interface
+`define CPU_NUM 2
+
+// Define IDCODE Value
+`define IDCODE_VALUE 32'h14951185
+
+// Define master clock (CPU clock)
+//`define CPU_CLOCK 50 // Half period = 50 ns => MCLK = 10 Mhz
+`define CPU_CLOCK 2.5 // Half period = 5 ns => MCLK = 200 Mhz
+
+// Length of the Instruction register
+`define IR_LENGTH 4
+
+// Length of the Data register (must be equal to the longest scan chain for shifting the data in)
+`define DR_LENGTH 74
+
+// Length of the CHAIN ID register
+`define CHAIN_ID_LENGTH 4
+
+// Length of the CRC
+`define CRC_LENGTH 8
+
+// Trace buffer size and counter and write/read pointer width. This can be expanded when more RAM is avaliable
+`define TRACECOUNTERWIDTH 5
+`define TRACEBUFFERLENGTH 32 // 2^5
+
+`define TRACESAMPLEWIDTH 36
+
+// OpSelect width
+`define OPSELECTWIDTH 3
+`define OPSELECTIONCOUNTER 8 //2^3
+
+// OpSelect (dbg_op_i) signal meaning
+`define DEBUG_READ_0 0
+`define DEBUG_WRITE_0 1
+`define DEBUG_READ_1 2
+`define DEBUG_WRITE_1 3
+`define DEBUG_READ_2 4
+`define DEBUG_WRITE_2 5
+`define DEBUG_READ_3 6
+`define DEBUG_WRITE_3 7
+
+// Supported Instructions
+`define EXTEST 4'b0000
+`define SAMPLE_PRELOAD 4'b0001
+`define IDCODE 4'b0010
+`define CHAIN_SELECT 4'b0011
+`define INTEST 4'b0100
+`define CLAMP 4'b0101
+`define CLAMPZ 4'b0110
+`define HIGHZ 4'b0111
+`define DEBUG 4'b1000
+`define MBIST 4'b1001
+`define BYPASS 4'b1111
+
+// Chains
+`define GLOBAL_BS_CHAIN 4'b0000
+`define CPU_DEBUG_CHAIN_2 4'b0001
+`define CPU_TEST_CHAIN 4'b0010
+`define TRACE_TEST_CHAIN 4'b0011
+`define REGISTER_SCAN_CHAIN 4'b0100
+`define WISHBONE_SCAN_CHAIN 4'b0101
+`define CPU_DEBUG_CHAIN_0 4'b0110
+`define CPU_DEBUG_CHAIN_1 4'b0111
+`define CPU_DEBUG_CHAIN_3 4'b1000
+
+// Registers addresses
+`define MODER_ADR 5'h00
+`define TSEL_ADR 5'h01
+`define QSEL_ADR 5'h02
+`define SSEL_ADR 5'h03
+`define CPUOP_ADR 5'h04
+`define CPUSEL_ADR 5'h05
+`define RECSEL_ADR 5'h10
+`define MON_CNTL_ADR 5'h11
+`define WB_CNTL_ADR 5'h12
+
+
+// Registers default values (after reset)
+`define MODER_DEF 2'h0
+`define TSEL_DEF 32'h00000000
+`define QSEL_DEF 32'h00000000
+`define SSEL_DEF 32'h00000000
+`define CPUOP_DEF 2'h0
+`define RECSEL_DEF 7'h0
+`define MON_CNTL_DEF 4'h0
Index: tags/rel_10/rtl/verilog/dbg_trace.v
===================================================================
--- tags/rel_10/rtl/verilog/dbg_trace.v (nonexistent)
+++ tags/rel_10/rtl/verilog/dbg_trace.v (revision 76)
@@ -0,0 +1,473 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// dbg_trace.v ////
+//// ////
+//// ////
+//// This file is part of the SoC/OpenRISC Development Interface ////
+//// http://www.opencores.org/cores/DebugInterface/ ////
+//// ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor ////
+//// igorm@opencores.org ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000,2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.6 2001/11/26 10:47:09 mohor
+// Crc generation is different for read or write commands. Small synthesys fixes.
+//
+// Revision 1.5 2001/10/19 11:40:01 mohor
+// dbg_timescale.v changed to timescale.v This is done for the simulation of
+// few different cores in a single project.
+//
+// Revision 1.4 2001/09/20 10:11:25 mohor
+// Working version. Few bugs fixed, comments added.
+//
+// Revision 1.3 2001/09/19 11:55:13 mohor
+// Asynchronous set/reset not used in trace any more.
+//
+// Revision 1.2 2001/09/18 14:13:47 mohor
+// Trace fixed. Some registers changed, trace simplified.
+//
+// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
+// Initial official release.
+//
+// Revision 1.3 2001/06/01 22:22:35 mohor
+// This is a backup. It is not a fully working version. Not for use, yet.
+//
+// Revision 1.2 2001/05/18 13:10:00 mohor
+// Headers changed. All additional information is now avaliable in the README.txt file.
+//
+// Revision 1.1.1.1 2001/05/18 06:35:06 mohor
+// Initial release
+//
+//
+
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "dbg_defines.v"
+
+// module Trace
+module dbg_trace (Wp, Bp, DataIn, OpSelect, LsStatus, IStatus, CpuStall_O,
+ Mclk, Reset, TraceChain, ContinMode, TraceEnable_reg,
+ WpTrigger, BpTrigger, LSSTrigger, ITrigger, TriggerOper, WpQualif,
+ BpQualif, LSSQualif, IQualif, QualifOper, RecordPC, RecordLSEA,
+ RecordLDATA, RecordSDATA, RecordReadSPR, RecordWriteSPR,
+ RecordINSTR,
+ WpTriggerValid, BpTriggerValid, LSSTriggerValid, ITriggerValid,
+ WpQualifValid, BpQualifValid, LSSQualifValid, IQualifValid, ReadBuffer,
+ WpStop, BpStop, LSSStop, IStop, StopOper, WpStopValid, BpStopValid,
+ LSSStopValid, IStopValid
+ );
+
+parameter Tp = 1;
+
+
+input [10:0] Wp; // Watchpoints
+input Bp; // Breakpoint
+input [31:0] DataIn; // Data from the RISC
+input [3:0] LsStatus; // Load/Store status
+input [1:0] IStatus; // Instruction status
+
+input Mclk; // Master clock (RISC clock)
+input Reset; // Reset
+input ReadBuffer; // Instruction for reading a sample from the Buffer
+
+// from registers
+input ContinMode; // Continous mode of the trace
+input TraceEnable_reg; // Trace is enabled (enabled by writing a bit in the register)
+
+input [10:0] WpTrigger; // Signals that come from registers to set the trigger
+input BpTrigger; // Signals that come from registers to set the trigger
+input [3:0] LSSTrigger; // Signals that come from registers to set the trigger
+input [1:0] ITrigger; // Signals that come from registers to set the trigger
+input [1:0] TriggerOper; // Signals that come from registers to set the trigger
+
+input [10:0] WpQualif; // Signals that come from registers to set the qualifier
+input BpQualif; // Signals that come from registers to set the qualifier
+input [3:0] LSSQualif; // Signals that come from registers to set the qualifier
+input [1:0] IQualif; // Signals that come from registers to set the qualifier
+input [1:0] QualifOper; // Signals that come from registers to set the qualifier
+
+input [10:0] WpStop; // Signals that come from registers to set the stop condition
+input BpStop; // Signals that come from registers to set the stop condition
+input [3:0] LSSStop; // Signals that come from registers to set the stop condition
+input [1:0] IStop; // Signals that come from registers to set the stop condition
+input [1:0] StopOper; // Signals that come from registers to set the stop condition
+
+input RecordPC; // Signals that come from registers for defining the sample for recording
+input RecordLSEA; // Signals that come from registers for defining the sample for recording
+input RecordLDATA; // Signals that come from registers for defining the sample for recording
+input RecordSDATA; // Signals that come from registers for defining the sample for recording
+input RecordReadSPR; // Signals that come from registers for defining the sample for recording
+input RecordWriteSPR; // Signals that come from registers for defining the sample for recording
+input RecordINSTR; // Signals that come from registers for defining the sample for recording
+
+input WpTriggerValid; // Signals that come from registers and indicate which trigger conditions are valid
+input BpTriggerValid; // Signals that come from registers and indicate which trigger conditions are valid
+input LSSTriggerValid; // Signals that come from registers and indicate which trigger conditions are valid
+input ITriggerValid; // Signals that come from registers and indicate which trigger conditions are valid
+
+input WpQualifValid; // Signals that come from registers and indicate which qualifier conditions are valid
+input BpQualifValid; // Signals that come from registers and indicate which qualifier conditions are valid
+input LSSQualifValid; // Signals that come from registers and indicate which qualifier conditions are valid
+input IQualifValid; // Signals that come from registers and indicate which qualifier conditions are valid
+
+input WpStopValid; // Signals that come from registers and indicate which stop conditions are valid
+input BpStopValid; // Signals that come from registers and indicate which stop conditions are valid
+input LSSStopValid; // Signals that come from registers and indicate which stop conditions are valid
+input IStopValid; // Signals that come from registers and indicate which stop conditions are valid
+// end: from registers
+
+
+output [`OPSELECTWIDTH-1:0] OpSelect; // Operation select (what kind of information is avaliable on the DataIn)
+output CpuStall_O; // CPU stall (stalls the RISC)
+output [39:0] TraceChain; // Scan shain from the trace module
+
+reg TraceEnable_d;
+reg TraceEnable;
+
+
+
+reg [`TRACECOUNTERWIDTH:0] Counter;
+reg [`TRACECOUNTERWIDTH-1:0] WritePointer;
+reg [`TRACECOUNTERWIDTH-1:0] ReadPointer;
+reg CpuStall;
+reg CpuStall_q;
+reg [`OPSELECTWIDTH-1:0] StallCounter;
+
+reg [`TRACESAMPLEWIDTH-1:0] Buffer[0:`TRACEBUFFERLENGTH-1];
+
+reg TriggerLatch;
+
+
+/**********************************************************************************
+* *
+* Generation of the trigger *
+* *
+**********************************************************************************/
+wire TempWpTrigger = |(Wp[10:0] & WpTrigger[10:0]);
+wire TempBpTrigger = Bp & BpTrigger;
+wire TempLSSTrigger = LsStatus[3:0] == LSSTrigger[3:0];
+wire TempITrigger = IStatus[1:0] == ITrigger[1:0];
+
+wire TempTriggerAND = ( (TempWpTrigger | ~WpTriggerValid)
+ & (TempBpTrigger | ~BpTriggerValid)
+ & (TempLSSTrigger | ~LSSTriggerValid)
+ & (TempITrigger | ~ITriggerValid)
+ )
+ & (WpTriggerValid | BpTriggerValid | LSSTriggerValid | ITriggerValid);
+
+wire TempTriggerOR = ( (TempWpTrigger & WpTriggerValid)
+ | (TempBpTrigger & BpTriggerValid)
+ | (TempLSSTrigger & LSSTriggerValid)
+ | (TempITrigger & ITriggerValid)
+ );
+
+wire Trigger = TraceEnable & (~TriggerOper[1]? 1 : // any
+ TriggerOper[0]? TempTriggerAND : TempTriggerOR // AND : OR
+ );
+
+/**********************************************************************************
+* *
+* Generation of the qualifier *
+* *
+**********************************************************************************/
+wire TempWpQualifier = |(Wp[10:0] & WpQualif[10:0]);
+wire TempBpQualifier = Bp & BpQualif;
+wire TempLSSQualifier = LsStatus[3:0] == LSSQualif[3:0];
+wire TempIQualifier = IStatus[1:0] == IQualif[1:0];
+
+wire TempQualifierAND = ( (TempWpQualifier | ~WpQualifValid)
+ & (TempBpQualifier | ~BpQualifValid)
+ & (TempLSSQualifier | ~LSSQualifValid)
+ & (TempIQualifier | ~IQualifValid)
+ )
+ & (WpQualifValid | BpQualifValid | LSSQualifValid | IQualifValid);
+
+wire TempQualifierOR = ( (TempWpQualifier & WpQualifValid)
+ | (TempBpQualifier & BpQualifValid)
+ | (TempLSSQualifier & LSSQualifValid)
+ | (TempIQualifier & IQualifValid)
+ );
+
+
+wire Stop;
+wire Qualifier = TraceEnable & ~Stop & (~QualifOper[1]? 1 : // any
+ QualifOper[0]? TempQualifierAND : TempQualifierOR // AND : OR
+ );
+
+/**********************************************************************************
+* *
+* Generation of the stop signal *
+* *
+**********************************************************************************/
+wire TempWpStop = |(Wp[10:0] & WpStop[10:0]);
+wire TempBpStop = Bp & BpStop;
+wire TempLSSStop = LsStatus[3:0] == LSSStop[3:0];
+wire TempIStop = IStatus[1:0] == IStop[1:0];
+
+wire TempStopAND = ( (TempWpStop | ~WpStopValid)
+ & (TempBpStop | ~BpStopValid)
+ & (TempLSSStop | ~LSSStopValid)
+ & (TempIStop | ~IStopValid)
+ )
+ & (WpStopValid | BpStopValid | LSSStopValid | IStopValid);
+
+wire TempStopOR = ( (TempWpStop & WpStopValid)
+ | (TempBpStop & BpStopValid)
+ | (TempLSSStop & LSSStopValid)
+ | (TempIStop & IStopValid)
+ );
+
+
+assign Stop = TraceEnable & (~StopOper[1]? 0 : // nothing
+ StopOper[0]? TempStopAND : TempStopOR // AND : OR
+ );
+
+
+
+/**********************************************************************************
+* *
+* Generation of the TriggerLatch *
+* *
+**********************************************************************************/
+always @(posedge Mclk or posedge Reset)
+begin
+ if(Reset)
+ TriggerLatch<=#Tp 0;
+ else
+ if(TriggerLatch & ~TraceEnable)
+ TriggerLatch<=#Tp 0;
+ else
+ if(Trigger)
+ TriggerLatch<=#Tp 1;
+end
+
+
+
+
+/**********************************************************************************
+* *
+* TraceEnable Synchronization *
+* *
+**********************************************************************************/
+always @(posedge Mclk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ TraceEnable_d<=#Tp 0;
+ TraceEnable<=#Tp 0;
+ end
+ else
+ begin
+ TraceEnable_d<=#Tp TraceEnable_reg;
+ TraceEnable<=#Tp TraceEnable_d;
+ end
+end
+
+
+
+
+/**********************************************************************************
+* *
+* CpuStall, counter and pointers generation *
+* *
+**********************************************************************************/
+reg BufferFullDetected;
+wire [`OPSELECTIONCOUNTER-1:0] RecEnable;
+
+wire BufferFull = Counter[`TRACECOUNTERWIDTH:0]==`TRACEBUFFERLENGTH;
+wire BufferEmpty = Counter[`TRACECOUNTERWIDTH:0]==0;
+wire IncrementCounter = CpuStall_q & ~(BufferFull | BufferFullDetected) & Qualifier & RecEnable[StallCounter];
+wire IncrementPointer = CpuStall_q & (~BufferFull | ContinMode) & Qualifier & RecEnable[StallCounter];
+
+wire WriteSample = IncrementPointer;
+
+wire Decrement = ReadBuffer & ~BufferEmpty & (~ContinMode | ContinMode & ~TraceEnable);
+wire CounterEn = IncrementCounter ^ Decrement;
+
+wire SyncResetCpuStall;
+wire ResetStallCounter;
+reg BufferFull_q;
+reg BufferFull_2q;
+
+reg Qualifier_mclk;
+
+always @(posedge Mclk)
+begin
+ Qualifier_mclk<=#Tp Qualifier;
+ BufferFull_q<=#Tp BufferFull;
+ BufferFull_2q<=#Tp BufferFull_q;
+ CpuStall_q <=#Tp CpuStall_O;
+end
+
+
+wire FirstCpuStall = Qualifier & ~Qualifier_mclk & TriggerLatch |
+ Qualifier_mclk & Trigger & ~TriggerLatch |
+ Qualifier & Trigger & ~Qualifier_mclk & ~TriggerLatch ;
+
+
+//wire SyncSetCpuStall = Qualifier_mclk & TriggerLatch &
+
+wire SyncSetCpuStall = CpuStall_O & ~CpuStall_q |
+ Qualifier_mclk & TriggerLatch &
+ (
+ (~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) |
+ (~ContinMode & ~BufferFull_q & BufferFull_2q & StallCounter==0) |
+ ( ContinMode & StallCounter==`OPSELECTIONCOUNTER-1)
+ );
+
+assign SyncResetCpuStall = (
+ (~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-2) |
+ (~ContinMode & ~BufferFull & BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) |
+ ( ContinMode & StallCounter==`OPSELECTIONCOUNTER-2)
+ );
+
+assign CpuStall_O = FirstCpuStall | CpuStall;
+
+
+always @(posedge Mclk or posedge Reset)
+begin
+ if(Reset)
+ Counter<=#Tp 0;
+ else
+ if(CounterEn)
+ if(IncrementCounter)
+ Counter[`TRACECOUNTERWIDTH:0]<=#Tp Counter[`TRACECOUNTERWIDTH:0] + 1;
+ else
+ Counter[`TRACECOUNTERWIDTH:0]<=#Tp Counter[`TRACECOUNTERWIDTH:0] - 1;
+end
+
+
+always @(posedge Mclk or posedge Reset)
+begin
+ if(Reset)
+ WritePointer<=#Tp 0;
+ else
+ if(IncrementPointer)
+ WritePointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
+end
+
+always @(posedge Mclk or posedge Reset)
+begin
+ if(Reset)
+ ReadPointer<=#Tp 0;
+ else
+ if(Decrement & ~ContinMode | Decrement & ContinMode & ~TraceEnable)
+ ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp ReadPointer[`TRACECOUNTERWIDTH-1:0] + 1;
+ else
+ if(ContinMode & IncrementPointer & (BufferFull | BufferFullDetected))
+ ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
+end
+
+always @(posedge Mclk)
+begin
+ if(~TraceEnable)
+ BufferFullDetected<=#Tp 0;
+ else
+ if(ContinMode & BufferFull)
+ BufferFullDetected<=#Tp 1;
+end
+
+
+always @(posedge Mclk or posedge Reset)
+begin
+ if(Reset)
+ CpuStall<=#Tp 0;
+ else
+ if(SyncResetCpuStall)
+ CpuStall<=#Tp 0;
+ else
+ if(SyncSetCpuStall)
+ CpuStall<=#Tp 1;
+end
+
+
+always @(posedge Mclk)
+begin
+ if(ResetStallCounter)
+ StallCounter<=#Tp 0;
+ else
+ if(CpuStall_q & (~BufferFull | ContinMode))
+ StallCounter<=#Tp StallCounter+1;
+end
+
+assign ResetStallCounter = StallCounter==(`OPSELECTIONCOUNTER-1) & ~BufferFull | Reset;
+
+
+/**********************************************************************************
+* *
+* Valid status *
+* *
+**********************************************************************************/
+wire Valid = ~BufferEmpty;
+
+
+/**********************************************************************************
+* *
+* Writing and reading the sample to/from the buffer *
+* *
+**********************************************************************************/
+always @ (posedge Mclk)
+begin
+ if(WriteSample)
+ Buffer[WritePointer[`TRACECOUNTERWIDTH-1:0]]<={DataIn, 1'b0, OpSelect[`OPSELECTWIDTH-1:0]};
+end
+
+assign TraceChain = {Buffer[ReadPointer], 3'h0, Valid};
+
+
+
+/**********************************************************************************
+* *
+* Operation select (to select which kind of data appears on the DATAIN lines) *
+* *
+**********************************************************************************/
+assign OpSelect[`OPSELECTWIDTH-1:0] = StallCounter[`OPSELECTWIDTH-1:0];
+
+
+
+/**********************************************************************************
+* *
+* Selecting which parts are going to be recorded as part of the sample *
+* *
+**********************************************************************************/
+assign RecEnable = {1'b0, RecordINSTR, RecordWriteSPR, RecordReadSPR, RecordSDATA, RecordLDATA, RecordLSEA, RecordPC};
+
+
+endmodule
Index: tags/rel_10/rtl/verilog/dbg_register.v
===================================================================
--- tags/rel_10/rtl/verilog/dbg_register.v (nonexistent)
+++ tags/rel_10/rtl/verilog/dbg_register.v (revision 76)
@@ -0,0 +1,101 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// dbg_register.v ////
+//// ////
+//// ////
+//// This file is part of the SoC/OpenRISC Development Interface ////
+//// http://www.opencores.org/cores/DebugInterface/ ////
+//// ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor ////
+//// igorm@opencores.org ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000,2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.5 2002/04/29 08:41:02 mohor
+// Asynchronous reset used instead of synchronous.
+//
+// Revision 1.4 2002/04/22 12:54:11 mohor
+// Signal names changed to lower case.
+//
+// Revision 1.3 2001/11/26 10:47:09 mohor
+// Crc generation is different for read or write commands. Small synthesys fixes.
+//
+// Revision 1.2 2001/10/19 11:40:02 mohor
+// dbg_timescale.v changed to timescale.v This is done for the simulation of
+// few different cores in a single project.
+//
+// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
+// Initial official release.
+//
+//
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+
+module dbg_register(data_in, data_out, write, clk, reset);
+
+parameter WIDTH = 8; // default parameter of the register width
+parameter RESET_VALUE = 0;
+
+input [WIDTH-1:0] data_in;
+
+input write;
+input clk;
+input reset;
+
+output [WIDTH-1:0] data_out;
+reg [WIDTH-1:0] data_out;
+
+always @ (posedge clk or posedge reset)
+//always @ (posedge clk)
+begin
+ if(reset)
+ data_out[WIDTH-1:0]<=#1 RESET_VALUE;
+ else
+ begin
+ if(write) // write
+ data_out[WIDTH-1:0]<=#1 data_in[WIDTH-1:0];
+ end
+end
+
+
+endmodule // Register
+
Index: tags/rel_10/rtl/verilog/dbg_crc8_d1.v
===================================================================
--- tags/rel_10/rtl/verilog/dbg_crc8_d1.v (nonexistent)
+++ tags/rel_10/rtl/verilog/dbg_crc8_d1.v (revision 76)
@@ -0,0 +1,147 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// dbg_crc8_d1 crc1.v ////
+//// ////
+//// ////
+//// This file is part of the SoC/OpenRISC Development Interface ////
+//// http://www.opencores.org/cores/DebugInterface/ ////
+//// ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor ////
+//// igorm@opencores.org ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000,2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.6 2002/04/09 14:19:22 mohor
+// Function changed to logic because of some synthesis warnings.
+//
+// Revision 1.5 2001/12/06 10:01:57 mohor
+// Warnings from synthesys tools fixed.
+//
+// Revision 1.4 2001/11/26 10:47:09 mohor
+// Crc generation is different for read or write commands. Small synthesys fixes.
+//
+// Revision 1.3 2001/10/19 11:40:02 mohor
+// dbg_timescale.v changed to timescale.v This is done for the simulation of
+// few different cores in a single project.
+//
+// Revision 1.2 2001/09/20 10:11:25 mohor
+// Working version. Few bugs fixed, comments added.
+//
+// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
+// Initial official release.
+//
+// Revision 1.3 2001/06/01 22:22:36 mohor
+// This is a backup. It is not a fully working version. Not for use, yet.
+//
+// Revision 1.2 2001/05/18 13:10:00 mohor
+// Headers changed. All additional information is now avaliable in the README.txt file.
+//
+// Revision 1.1.1.1 2001/05/18 06:35:03 mohor
+// Initial release
+//
+//
+///////////////////////////////////////////////////////////////////////
+// File: CRC8_D1.v
+// Date: Fri Apr 27 20:56:55 2001
+//
+// Copyright (C) 1999 Easics NV.
+// This source file may be used and distributed without restriction
+// provided that this copyright statement is not removed from the file
+// and that any derivative work contains the original copyright notice
+// and the associated disclaimer.
+//
+// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
+// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+// Purpose: Verilog module containing a synthesizable CRC function
+// * polynomial: (0 1 2 8)
+// * data width: 1
+//
+// Info: jand@easics.be (Jan Decaluwe)
+// http://www.easics.com
+///////////////////////////////////////////////////////////////////////
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "dbg_defines.v"
+
+
+module dbg_crc8_d1 (data, enable_crc, reset, sync_rst_crc, crc_out, clk);
+
+parameter Tp = 1;
+
+
+input data;
+input enable_crc;
+input reset;
+input sync_rst_crc;
+input clk;
+
+
+output [7:0] crc_out;
+reg [7:0] crc_out;
+
+wire [7:0] NewCRC;
+
+assign NewCRC[0] = data ^ crc_out[7];
+assign NewCRC[1] = data ^ crc_out[0] ^ crc_out[7];
+assign NewCRC[2] = data ^ crc_out[1] ^ crc_out[7];
+assign NewCRC[3] = crc_out[2];
+assign NewCRC[4] = crc_out[3];
+assign NewCRC[5] = crc_out[4];
+assign NewCRC[6] = crc_out[5];
+assign NewCRC[7] = crc_out[6];
+
+
+
+always @ (posedge clk or posedge reset)
+begin
+ if(reset)
+ crc_out[7:0] <= #Tp 0;
+ else
+ if(sync_rst_crc)
+ crc_out[7:0] <= #Tp 0;
+ else
+ if(enable_crc)
+ crc_out[7:0] <= #Tp NewCRC;
+end
+
+
+
+endmodule
Index: tags/rel_10/rtl/verilog/jtag_chain.v
===================================================================
--- tags/rel_10/rtl/verilog/jtag_chain.v (nonexistent)
+++ tags/rel_10/rtl/verilog/jtag_chain.v (revision 76)
@@ -0,0 +1,75 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// jtag_chain.v ////
+//// ////
+//// ////
+//// This file is part of the SoC/OpenRISC Development Interface ////
+//// http://www.opencores.org/projects/DebugInterface/ ////
+//// ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor ////
+//// igorm@opencores.org ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000, 2001, 2002 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "dbg_defines.v"
+
+// Top module
+module jtag_chain ( capture_dr_i, shift_dr_i, update_dr_i, extest_selected_i,
+ bs_chain_i, bs_chain_o
+ );
+
+parameter Tp = 1;
+
+
+input capture_dr_i;
+input shift_dr_i;
+input update_dr_i;
+input extest_selected_i;
+input bs_chain_i;
+
+output bs_chain_o;
+
+assign bs_chain_o = 0;
+
+endmodule
Index: tags/rel_10/rtl/verilog/dbg_sync_clk1_clk2.v
===================================================================
--- tags/rel_10/rtl/verilog/dbg_sync_clk1_clk2.v (nonexistent)
+++ tags/rel_10/rtl/verilog/dbg_sync_clk1_clk2.v (revision 76)
@@ -0,0 +1,151 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// dbg_sync_clk1_clk2.v ////
+//// ////
+//// This file is part of the SoC/OpenRISC Development Interface ////
+//// http://www.opencores.org/cores/DebugInterface/ ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.2 2001/10/19 11:40:01 mohor
+// dbg_timescale.v changed to timescale.v This is done for the simulation of
+// few different cores in a single project.
+//
+// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
+// Initial official release.
+//
+//
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+
+// FF in clock domain 1 is being set by a signal from the clock domain 2
+module dbg_sync_clk1_clk2 (clk1, clk2, reset1, reset2, set2, sync_out);
+
+parameter Tp = 1;
+
+input clk1;
+input clk2;
+input reset1;
+input reset2;
+input set2;
+
+output sync_out;
+
+reg set2_q;
+reg set2_q2;
+reg set1_q;
+reg set1_q2;
+reg clear2_q;
+reg clear2_q2;
+reg sync_out;
+
+wire z;
+
+assign z = set2 | set2_q & ~clear2_q2;
+
+
+// Latching and synchronizing "set" to clk2
+always @ (posedge clk2 or posedge reset2)
+begin
+ if(reset2)
+ set2_q <=#Tp 1'b0;
+ else
+ set2_q <=#Tp z;
+end
+
+
+always @ (posedge clk2 or posedge reset2)
+begin
+ if(reset2)
+ set2_q2 <=#Tp 1'b0;
+ else
+ set2_q2 <=#Tp set2_q;
+end
+
+
+// Synchronizing "set" to clk1
+always @ (posedge clk1 or posedge reset1)
+begin
+ if(reset1)
+ set1_q <=#Tp 1'b0;
+ else
+ set1_q <=#Tp set2_q2;
+end
+
+
+always @ (posedge clk1 or posedge reset1)
+begin
+ if(reset1)
+ set1_q2 <=#Tp 1'b0;
+ else
+ set1_q2 <=#Tp set1_q;
+end
+
+
+// Synchronizing "clear" to clk2
+always @ (posedge clk2 or posedge reset2)
+begin
+ if(reset2)
+ clear2_q <=#Tp 1'b0;
+ else
+ clear2_q <=#Tp set1_q2;
+end
+
+
+always @ (posedge clk2 or posedge reset2)
+begin
+ if(reset2)
+ clear2_q2 <=#Tp 1'b0;
+ else
+ clear2_q2 <=#Tp clear2_q;
+end
+
+
+always @ (posedge clk1 or posedge reset1)
+begin
+ if(reset1)
+ sync_out <=#Tp 1'b0;
+ else
+ sync_out <=#Tp set1_q2;
+end
+
+endmodule
Index: tags/rel_10/rtl/verilog/timescale.v
===================================================================
--- tags/rel_10/rtl/verilog/timescale.v (nonexistent)
+++ tags/rel_10/rtl/verilog/timescale.v (revision 76)
@@ -0,0 +1,57 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// timescale.v ////
+//// ////
+//// ////
+//// This file is part of the SoC/OpenRISC Development Interface ////
+//// http://www.opencores.org/cores/DebugInterface/ ////
+//// ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor ////
+//// igorm@opencores.org ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000,2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
+// Initial official release.
+//
+//
+//
+//
+//
+
+
+`timescale 1ns / 1ns
Index: tags/rel_10/rtl/README.txt
===================================================================
--- tags/rel_10/rtl/README.txt (nonexistent)
+++ tags/rel_10/rtl/README.txt (revision 76)
@@ -0,0 +1,114 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// README.txt ////
+//// ////
+//// ////
+//// This file is part of the SoC/OpenRISC Development Interface ////
+//// http://www.opencores.org/cores/DebugInterface/ ////
+//// ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor ////
+//// igorm@opencores.org ////
+//// ////
+//// ////
+//// All additional information is avaliable in this README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000,2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
+// Initial official release.
+//
+// Revision 1.2 2001/06/01 22:22:35 mohor
+// This is a backup. It is not a fully working version. Not for use, yet.
+//
+// Revision 1.1 2001/05/18 13:12:09 mohor
+// Header changed. All additional information is now avaliable in this README.txt file.
+//
+//
+
+
+
+PROJECT:
+SoC/OpenRISC Development (debug) Interface
+
+
+PROJECT AND DOCUMENTATION ON THE WEB:
+
+The project that this files are part of is avaliable on the opencores
+web page:
+
+http://www.opencores.org/cores/DebugInterface/
+
+Documentation can also be found there. For direct download of the
+documentation go to:
+
+http://www.opencores.org/cgi-bin/cvsget.cgi/dbg_interface/doc/DbgSupp.pdf
+
+
+
+
+OVERVIEW (main Features):
+
+Development Interface is used for development purposes
+(Boundary Scan testing and debugging). It is an interface
+between the RISC, peripheral cores and any commercial
+debugger/emulator or BS testing device. The external
+debugger or BS tester connects to the core via JTAG port.
+The Development Port also contains a trace and support for
+tracing the program flow, execution coverage and profiling
+the code.
+
+dbg_tb.v is a testbench file.
+file_communication.v is used for simulating the whole design together with the
+ debugger through two files that make a JTAG interface
+dbg_top.v is top level module of the development interface design
+
+
+
+COMPATIBILITY:
+
+- WISHBONE rev B.1
+- IEEE 1149.1 (JTAG)
+
+
+
+KNOWN PROBLEMS (limits):
+- RISC changes Watchpoints and breakpoints on rising edge of the
+Mclk clock signal. Simulation should do the same.
+
+
+
+TO DO:
+- Add a WISHBONE master support if needed
+- Add support for boundary scan (This is already done, but not yet incorporated in the design)
+
Index: tags/rel_10/doc/DbgSupp.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/rel_10/doc/DbgSupp.pdf
===================================================================
--- tags/rel_10/doc/DbgSupp.pdf (nonexistent)
+++ tags/rel_10/doc/DbgSupp.pdf (revision 76)
tags/rel_10/doc/DbgSupp.pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: tags/rel_10/doc/src/DbgSupp.doc
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/rel_10/doc/src/DbgSupp.doc
===================================================================
--- tags/rel_10/doc/src/DbgSupp.doc (nonexistent)
+++ tags/rel_10/doc/src/DbgSupp.doc (revision 76)
tags/rel_10/doc/src/DbgSupp.doc
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: tags/rel_10/doc/src/Debug Support Datasheet (prl.).doc
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/rel_10/doc/src/Debug Support Datasheet (prl.).doc
===================================================================
--- tags/rel_10/doc/src/Debug Support Datasheet (prl.).doc (nonexistent)
+++ tags/rel_10/doc/src/Debug Support Datasheet (prl.).doc (revision 76)
tags/rel_10/doc/src/Debug Support Datasheet (prl.).doc
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: tags/rel_10/doc/src/DbgSupp_PB.doc
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/rel_10/doc/src/DbgSupp_PB.doc
===================================================================
--- tags/rel_10/doc/src/DbgSupp_PB.doc (nonexistent)
+++ tags/rel_10/doc/src/DbgSupp_PB.doc (revision 76)
tags/rel_10/doc/src/DbgSupp_PB.doc
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: tags/rel_10/doc/Debug Support Datasheet (prl.).pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/rel_10/doc/Debug Support Datasheet (prl.).pdf
===================================================================
--- tags/rel_10/doc/Debug Support Datasheet (prl.).pdf (nonexistent)
+++ tags/rel_10/doc/Debug Support Datasheet (prl.).pdf (revision 76)
tags/rel_10/doc/Debug Support Datasheet (prl.).pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: tags/rel_10/doc/DbgSupp_PB.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/rel_10/doc/DbgSupp_PB.pdf
===================================================================
--- tags/rel_10/doc/DbgSupp_PB.pdf (nonexistent)
+++ tags/rel_10/doc/DbgSupp_PB.pdf (revision 76)
tags/rel_10/doc/DbgSupp_PB.pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property