OpenCores
URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /
    from Rev 75 to Rev 76
    Reverse comparison

Rev 75 → Rev 76

/xulalx25soc/trunk/sw/zipdbg.cpp
1,18 → 1,19
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
// Filename: zipdbg.cpp
// Filename: zipdbg.cpp
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
// Project: XuLA2-LX25 SoC based upon the ZipCPU
//
// Purpose:
// Purpose: Provide a debugger to step through the ZipCPU assembler,
// evaluate the ZipCPU's current state, modify registers as(if)
// needed, etc. All of this through the JTAG port of the XuLA2 board.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
24,20 → 25,23
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
//
// BUGS:
// - No ability to verify CPU functionality (3rd party simulator)
// - No ability to set/clear breakpoints
//
//
//
#include <stdlib.h>
#include <signal.h>
#include <time.h>
154,6 → 158,18
for(int i=1; i<5; i++)
m_state.m_smem[i].m_a = m_state.m_smem[i-1].m_a+1;
for(int i=0; i<5; i++) {
m_state.m_smem[i].m_valid = true;
if (m_state.m_smem[i].m_a < 0x2000)
m_state.m_smem[i].m_valid = false;
else if (m_state.m_smem[i].m_a < 0x4000)
m_state.m_smem[i].m_valid = false;
else if (m_state.m_smem[i].m_a < 0x800000)
m_state.m_smem[i].m_valid = false;
else if (m_state.m_smem[i].m_a < 0x1000000)
m_state.m_smem[i].m_valid = true;
else
m_state.m_smem[i].m_valid = false;
if (m_state.m_smem[i].m_valid)
try {
m_state.m_smem[i].m_d = readio(m_state.m_smem[i].m_a);
m_state.m_smem[i].m_valid = true;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.