URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
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- This comparison shows the changes necessary to convert path
/
- from Rev 752 to Rev 753
- ↔ Reverse comparison
Rev 752 → Rev 753
/trunk/uclinux/uClinux-2.0.x/include/asm-or32/irq.h
14,9 → 14,10
* "Generic" interrupt sources |
*/ |
|
#define IRQ_UART_0 (19) /* interrupt source for UART dvice 0 */ |
#define IRQ_ETH_0 (15) /* interrupt source for Ethernet dvice 0 */ |
#define IRQ_PS2_0 (12) /* interrupt source for ps2 dvice 0 */ |
#define IRQ_SCHED_TIMER (0) /* interrupt source for scheduling timer */ |
#define IRQ_UART_0 (15) /* interrupt source for UART dvice 0 */ |
#define IRQ_ETH_0 (16) /* interrupt source for Ethernet dvice 0 */ |
|
/* |
* various flags for request_irq() |
/trunk/uclinux/uClinux-2.0.x/include/asm-or32/board.h
7,11 → 7,12
#define FLASH_BASE_ADD 0x04000000 |
|
/* Devices base address */ |
#define UART_BASE_ADD 0x9c000000 |
#define MC_BASE_ADD 0xa0000000 |
#define CRT_BASE_ADD 0xb0000000 |
#define KBD_BASE_ADD 0xb1000000 |
#define ETH_BASE_ADD 0xb2000000 |
#define UART_BASE_ADD 0x90000000 |
#define MC_BASE_ADD 0x60000000 |
#define CRT_BASE_ADD 0xc0000000 |
#define FBMEM_BASE_ADD 0xa8000000 |
#define ETH_BASE_ADD 0xd0000000 |
#define KBD_BASE_ADD 0x98000000 |
|
/* Define this if you want to use I and/or D cache */ |
#define ICACHE 0 |
37,8 → 38,16
|
|
/* Define this if you are using MC */ |
#define MC_INIT 0 |
#define MC_INIT 1 |
|
/* Memory controller initialize values */ |
#define MC_CSR_VAL 0x0B000300 |
#define MC_MASK_VAL 0x000000e0 |
#define FLASH_BASE_ADD 0x04000000 |
#define FLASH_TMS_VAL 0x00102102 |
#define SDRAM_BASE_ADD 0x00000000 |
#define SDRAM_TMS_VAL 0x07248230 |
|
/* Define ethernet MAC address */ |
#define MACADDR0 0x00 |
#define MACADDR1 0x01 |
/trunk/uclinux/uClinux-2.0.x/sim.cfg
102,12 → 102,12
pattern = 0x00 |
type = unknown /* Fastest */ |
|
nmemories = 2 |
nmemories = 3 |
device 0 |
name = "FLASH" |
ce = 0 |
baseaddr = 0x04000000 |
size = 0x00400000 |
size = 0x00800000 |
delayr = 10 |
delayw = -1 |
/* log = "flash.log"*/ |
122,6 → 122,15
delayw = 2 |
/* log = "ram.log"*/ |
enddevice |
device 2 |
name = "SRAM" |
ce = 2 |
baseaddr = 0x08000000 |
size = 0x00400000 |
delayr = 1 |
delayw = 2 |
/* log = "ram.log"*/ |
enddevice |
end |
|
/* IMMU SECTION |
410,7 → 419,7
|
section mc |
enabled = 1 |
baseaddr = 0xa0000000 |
baseaddr = 0x60000000 |
POC = 0x00000008 /* Power on configuration register */ |
end |
|
454,8 → 463,8
nuarts = 1 |
|
device 0 |
baseaddr = 0x9c000000 |
irq = 15 |
baseaddr = 0x90000000 |
irq = 19 |
rxfile = "uart0.rx" |
txfile = "uart0.tx" |
jitter = -1 /* async behaviour */ |
491,7 → 500,7
ndmas = 1 |
|
device 0 |
baseaddr = 0x90000000 |
baseaddr = 0xa0000000 |
irq = 4 |
enddevice |
end |
535,14 → 544,14
nethernets = 1 |
|
device 0 |
baseaddr = 0xb2000000 |
baseaddr = 0xd0000000 |
dma = 0 |
irq = 16 |
rtx_type = 1 |
irq = 15 |
rtx_type = 0 |
tx_channel = 0 |
rx_channel = 1 |
rxfile = "/tmp/eth0.rx" |
txfile = "/tmp/eth0.tx" |
rxfile = "eth0.rx" |
txfile = "eth0.tx" |
sockif = "eth0" |
enddevice |
end |
565,7 → 574,7
|
section fb |
enabled = 1 |
baseaddr = 0xb0000000 |
baseaddr = 0xc0000000 |
refresh_rate = 1000000 |
filename = "primary" |
end |
586,8 → 595,8
|
section kbd |
enabled = 1 |
irq = 21 |
baseaddr = 0xb1000000 |
irq = 12 |
baseaddr = 0x98000000 |
rxfile = "kbd.rx" |
end |
|
/trunk/uclinux/uClinux-2.0.x/arch/or32/kernel/head.S
5,8 → 5,6
#include <linux/errno.h> |
|
#define RAM 0 |
#undef MC_INIT |
#define MC_INIT 1 |
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.global __text_start |
.global __main |
216,7 → 214,14
.section .romvec |
.org 0x100 |
|
l.nop |
l.movhi r3,hi(__start) |
l.movhi r3,hi(MC_BASE_ADD) |
l.ori r3,r3,MC_BA_MASK |
l.addi r5,r0,0x00 |
l.sw 0(r3),r5 |
|
l.movhi r3,hi(__start) |
l.ori r3,r3,lo(__start) |
l.jr r3 |
l.nop |
370,37 → 375,53
__flsh_start: |
|
#if MC_INIT |
/* Init memory controller */ |
l.movhi r3,hi(MC_BASE_ADD) |
l.ori r3,r3,lo(MC_BASE_ADD) |
|
|
l.addi r4,r3,MC_CSC(0) |
l.movhi r5,hi(FLASH_BASE_ADD) |
l.srai r5,r5,5 |
l.ori r5,r5,0x0005 |
l.ori r5,r5,0x0025 |
l.sw 0(r4),r5 |
|
|
l.addi r4,r3,MC_TMS(0) |
l.movhi r5,0xffff |
l.ori r5,r5,0xffff |
l.sw 0(r4),r5 |
|
l.movhi r5,hi(FLASH_TMS_VAL) |
l.ori r5,r5,lo(FLASH_TMS_VAL) |
l.sw 0(r4),r5 |
|
l.addi r4,r3,MC_BA_MASK |
l.addi r5,r0,0xfc |
l.addi r5,r0,MC_MASK_VAL |
l.sw 0(r4),r5 |
|
|
l.addi r4,r3,MC_CSR |
l.movhi r5,hi(MC_CSR_VAL) |
l.ori r5,r5,lo(MC_CSR_VAL) |
l.sw 0(r4),r5 |
|
l.addi r4,r3,MC_TMS(1) |
l.movhi r5,hi(SDRAM_TMS_VAL) |
l.ori r5,r5,lo(SDRAM_TMS_VAL) |
l.sw 0(r4),r5 |
|
l.addi r4,r3,MC_CSC(1) |
l.movhi r5,hi(SRAM_BASE_ADD) |
l.movhi r5,hi(SDRAM_BASE_ADD) |
l.srai r5,r5,5 |
l.ori r5,r5,0x0025 |
l.ori r5,r5,0x0411 |
l.sw 0(r4),r5 |
#ifdef FBMEM_BASE_ADD |
l.addi r4,r3,MC_CSC(2) |
l.movhi r5,hi(FBMEM_BASE_ADD) |
l.srai r5,r5,5 |
l.ori r5,r5,0x0005 |
l.sw 0(r4),r5 |
|
l.addi r4,r3,MC_TMS(1) |
l.addi r4,r3,MC_TMS(2) |
l.movhi r5,0xffff |
l.ori r5,r5,0xffff |
l.sw 0(r4),r5 |
#endif |
#endif |
#endif |
|
#if ICACHE |
l.jal _ic_enable |
/trunk/uclinux/uClinux-2.0.x/arch/or32/board/rom.ld
1,8 → 1,8
MEMORY |
{ |
romvec : ORIGIN = 0x04000000, LENGTH = 0x2000 |
flash : ORIGIN = 0x04002000, LENGTH = 0x00400000 - 0x2000 |
eflash : ORIGIN = 0x04200000, LENGTH = 0 |
flash : ORIGIN = 0x04002000, LENGTH = 0x00800000 - 0x2000 |
eflash : ORIGIN = 0x04800000, LENGTH = 0 |
ramvec : ORIGIN = 0x00000000, LENGTH = 0x00002000 |
ram : ORIGIN = 0x00002000, LENGTH = 0x00800000 - 0x2000 |
eram : ORIGIN = 0x00800000, LENGTH = 0 |
/trunk/uclinux/uClinux-2.0.x/drivers/char/keyboard.c
17,7 → 17,7
* |
*/ |
|
#define KEYBOARD_IRQ 21 |
#define KEYBOARD_IRQ IRQ_PS2_0 |
#define DISABLE_KBD_DURING_INTERRUPTS 0 |
|
#include <linux/sched.h> |
32,6 → 32,9
#include <linux/random.h> |
|
#include <asm/bitops.h> |
#ifdef CONFIG_OR32 |
#include <asm/irq.h> |
#endif |
|
#include "kbd_kern.h" |
#include "diacr.h" |