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URL https://opencores.org/ocsvn/or1k/or1k/trunk

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    from Rev 755 to Rev 756
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Rev 755 → Rev 756

/trunk/orp/orp_soc/sw/orp_mon/sim
638,7 → 638,7
-`뢐&UWV1S h}t& t[u [^_]É'Ft{t%$exCD$CSHD$M빍v$qxCD$5롐v'U]]uu $\$t$ D$wx\$t$$>u u]]]:UEE8uEЍE(UUSR[vvo]$Revision: 1.1.1.1 $qthelpdedmrunprpmpcresetbreakhiststatsstallinfordvset%sOpenRISC 1000 (OR32) Architectural Simulator, %s +`뢐&UWV1S h}t& t[u [^_]É'Ft{t%$exCD$CSHD$M빍v$qxCD$5롐v'U]]uu $\$t$ D$wx\$t$$>u u]]]:UEE8uEЍE(UUSR[vvo]$Revision: 1.2 $qthelpdedmrunprpmpcresetbreakhiststatsstallinfordvset%sOpenRISC 1000 (OR32) Architectural Simulator, %s Copyright (C) 1999 Damjan Lampret, lampret@opencores.orgCopyright (C) 2000 Damjan Lampret, lampret@opencores.org Jimmy Chen-Min Chen, jimmy@ee.nctu.edu.tw Johan Rydberg, johan.rydberg@insight.se Marko Mlinar, markom@opencores.orgCopyright (C) 2001 Simon Srot, simons@opencores.orgVisit http://www.opencores.org for more information about OpenRISC 1000 and other open source cores. This software comes with ABSOLUTELY NO WARRANTY; for details see COPYING.
/trunk/orp/orp_soc/sw/orp_mon/board.h
16,7 → 16,7
#define SDRAM_TMS_VAL 0x07248230
 
#ifdef XESS
#define IN_CLK 12500000
#define IN_CLK 10000000
#else
#define IN_CLK 25000000
#endif

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