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URL https://opencores.org/ocsvn/or1k/or1k/trunk

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    from Rev 772 to Rev 773
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Rev 772 → Rev 773

/trunk/xess/xsv_fpga/README
26,12 → 26,12
Directory Structure
+++++++++++++++++++
 
bench: test bench (for simulation verification)
doc: Some of the documentation (more on the OpenCores web)
rtl: Verilog sources of the XSV FPGA SoC
sim: For running simulation
sw: Software example (OR1K GNU toolchain is available from OpenCores web)
syn: Synthesis scripts/constraints for FPGA and ASIC
orp_soc/bench: test bench (for simulation verification)
orp_soc/doc: Some of the documentation (more on the OpenCores web)
orp_soc/rtl: Verilog sources of the XSV FPGA SoC
orp_soc/sim: For running simulation
orp_soc/sw: Software example (OR1K GNU toolchain is available from OpenCores web)
orp_soc/syn: Synthesis scripts/constraints for FPGA and ASIC
exo: Download files for XSV800
 
Simulation
98,5 → 98,8
--
Damjan Lampret, Mar/2002
$Log: not supported by cvs2svn $
Revision 1.2 2002/03/21 22:14:46 lampret
Explained 10MHz. Fixed directory name.
 
Revision 1.1.1.1 2002/03/21 20:47:47 lampret
First import of the "new" XESS XSV environment.

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