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Rev 774 → Rev 775

/trunk/or1200/rtl/verilog/or1200_dc_fsm.v
44,6 → 44,13
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2002/03/21 16:55:45 lampret
// First import of the "new" XESS XSV environment.
//
//
// Revision 1.5 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.4 2002/02/01 19:56:54 lampret
// Fixed combinational loops.
//
210,7 → 217,6
cache_inhibit <= #1 1'b0;
end
else begin // idle
state <= #1 `OR1200_DCFSM_IDLE;
hitmiss_eval <= #1 1'b0;
store <= #1 1'b0;
load <= #1 1'b0;
221,26 → 227,14
cache_inhibit <= #1 1'b1;
if (hitmiss_eval)
saved_addr_r[31:13] <= #1 start_addr[31:13];
if (!dc_en)
if ((hitmiss_eval & !dcdmmu_cycstb_i) || // load aborted (usually caused by DMMU)
(biudata_error) || // load terminated with an error
((cache_inhibit | dcdmmu_ci_i) & biudata_valid)) begin // load from cache-inhibited area
state <= #1 `OR1200_DCFSM_IDLE;
else if (hitmiss_eval & !dcdmmu_cycstb_i) begin // load aborted (usually caused by DMMU)
state <= #1 `OR1200_DCFSM_IDLE;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
else if (biudata_error) begin // load terminated with an error
state <= #1 `OR1200_DCFSM_IDLE;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
else if ((cache_inhibit | dcdmmu_ci_i) & biudata_valid) begin // load from cache-inhibited area
state <= #1 `OR1200_DCFSM_IDLE;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
else if (tagcomp_miss & biudata_valid) begin // load missed, finish current external load and refill
state <= #1 `OR1200_DCFSM_LREFILL3;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
258,9 → 252,7
hitmiss_eval <= #1 1'b0;
end
`OR1200_DCFSM_LREFILL3 : begin
if (!dc_en)
state <= #1 `OR1200_DCFSM_IDLE;
else if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
cnt <= #1 cnt - 'd1;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
end
274,26 → 266,14
cache_inhibit <= #1 1'b1;
if (hitmiss_eval)
saved_addr_r[31:13] <= #1 start_addr[31:13];
if (!dc_en)
if ((hitmiss_eval & !dcdmmu_cycstb_i) || // store aborted (usually caused by DMMU)
(biudata_error) || // store terminated with an error
((cache_inhibit | dcdmmu_ci_i) & biudata_valid)) begin // store to cache-inhibited area
state <= #1 `OR1200_DCFSM_IDLE;
else if (hitmiss_eval & !dcdmmu_cycstb_i) begin // store aborted (usually caused by DMMU)
state <= #1 `OR1200_DCFSM_IDLE;
hitmiss_eval <= #1 1'b0;
store <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
else if (biudata_error) begin // store terminated with an error
state <= #1 `OR1200_DCFSM_IDLE;
hitmiss_eval <= #1 1'b0;
store <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
else if ((cache_inhibit | dcdmmu_ci_i) & biudata_valid) begin // store to cache-inhibited area
state <= #1 `OR1200_DCFSM_IDLE;
hitmiss_eval <= #1 1'b0;
store <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
`ifdef OR1200_DC_STORE_REFILL
else if (tagcomp_miss & biudata_valid) begin // store missed, finish write-through and do load refill
state <= #1 `OR1200_DCFSM_SREFILL4;
315,9 → 295,7
end
`ifdef OR1200_DC_STORE_REFILL
`OR1200_DCFSM_SREFILL4 : begin
if (!dc_en)
state <= #1 `OR1200_DCFSM_IDLE;
else if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
cnt <= #1 cnt - 'd1;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
end
/trunk/or1200/rtl/verilog/or1200_ic_fsm.v
44,6 → 44,13
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2002/03/21 16:55:45 lampret
// First import of the "new" XESS XSV environment.
//
//
// Revision 1.5 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.4 2002/02/01 19:56:54 lampret
// Fixed combinational loops.
//
185,7 → 192,6
cache_inhibit <= #1 1'b0;
end
else begin // idle
state <= #1 `OR1200_ICFSM_IDLE;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
195,26 → 201,15
cache_inhibit <= #1 1'b1;
if (hitmiss_eval)
saved_addr_r[31:13] <= #1 start_addr[31:13];
if (!ic_en)
if ((!ic_en) ||
(hitmiss_eval & !icimmu_cycstb_i) || // fetch aborted (usually caused by IMMU)
(biudata_error) || // fetch terminated with an error
(cache_inhibit & biudata_valid)) begin // fetch from cache-inhibited page
state <= #1 `OR1200_ICFSM_IDLE;
else if (hitmiss_eval & !icimmu_cycstb_i) begin // fetch aborted (usually caused by IMMU)
state <= #1 `OR1200_ICFSM_IDLE;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
else if (biudata_error) begin // fetch terminated with an error
state <= #1 `OR1200_ICFSM_IDLE;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
else if (cache_inhibit & biudata_valid) begin // fetch from cache-inhibited page
state <= #1 `OR1200_ICFSM_IDLE;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
else if (tagcomp_miss & biudata_valid) begin // fetch missed, finish current external fetch and refill
state <= #1 `OR1200_ICFSM_LREFILL3;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
223,10 → 218,7
cache_inhibit <= #1 1'b0;
end
else if (!tagcomp_miss & !icimmu_ci_i) begin // fetch hit, finish immediately
state <= #1 `OR1200_ICFSM_CFETCH;
saved_addr_r <= #1 start_addr;
hitmiss_eval <= #1 1'b1;
load <= #1 1'b1;
cache_inhibit <= #1 1'b0;
end
else if (!icimmu_cycstb_i) begin // fetch aborted (usually caused by exception)
239,9 → 231,7
hitmiss_eval <= #1 1'b0;
end
`OR1200_ICFSM_LREFILL3 : begin
if (!ic_en)
state <= #1 `OR1200_ICFSM_IDLE;
else if (biudata_valid && (|cnt)) begin // refill ack, more fetchs to come
if (biudata_valid && (|cnt)) begin // refill ack, more fetchs to come
cnt <= #1 cnt - 'd1;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
end

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