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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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Rev 78 → Rev 79

/t6507lp/trunk/rtl/verilog/T6507LP_ALU.v
74,19 → 74,59
X <= 0;
Y <= 0;
end
else begin
alu_status <= STATUS;
else if ( alu_enable == 1 ) begin
alu_result <= result;
A <= A;
X <= X;
Y <= Y;
case (alu_opcode)
ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY, AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY, ASL_ACC, EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC, SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY :
ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY,
AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY,
ASL_ACC,
EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY,
LSR_ACC,
ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY,
ROL_ACC, ROR_ACC,
SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY :
begin
A <= result;
alu_status <= STATUS;
end
LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY,
PLA_IMP :
begin
A <= alu_a;
alu_status <= STATUS;
end
LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY :
begin
X <= alu_a;
alu_status <= STATUS;
end
LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX :
begin
Y <= alu_a;
alu_status <= STATUS;
end
LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX,
ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX,
ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX,
BIT_ZPG, BIT_ABS,
BRK_IMP,
CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP,
CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY,
CPX_IMM, CPX_ZPG, CPX_ABS,
CPY_IMM, CPY_ZPG, CPY_ABS,
SEC_IMP, SED_IMP, SEI_IMP,
TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP :
begin
alu_status <= STATUS;
end
PLP_IMP :
begin
alu_status <= alu_a;
end
 
endcase
end
end
/t6507lp/trunk/sim/T6507LP_ULA/T6507LP_ALU_TestBench.v
0,0 → 1,46
`timescale 1ns / 1ps
module T6507LP_ALU_TestBench(input dummy,output error);
 
`include "T6507LP_Package.v"
 
reg clk_i;
reg n_rst_i;
reg alu_enable;
wire [7:0] alu_result;
wire [7:0] alu_status;
reg [7:0] alu_opcode;
reg [7:0] alu_a;
 
//`include "T6507LP_Package.v"
 
T6507LP_ALU DUT (
.clk_i (clk_i),
.n_rst_i (n_rst_i),
.alu_enable (alu_enable),
.alu_result (alu_result),
.alu_status (alu_status),
.alu_opcode (alu_opcode),
.alu_a (alu_a)
);
 
localparam period = 10;
 
always begin
#(period/2) clk_i = ~clk_i;
end
 
 
initial
begin
clk_i = 0;
n_rst_i = 1;
@(negedge clk_i);
alu_opcode = ADC_IMM;
alu_a = 1;
while (1) begin
$display("op1 = %h op2 = %d c = %h d = %h n = %h v = %h ", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V]);
end
$finish;
end
endmodule
 

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