URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 783 to Rev 784
- ↔ Reverse comparison
Rev 783 → Rev 784
/trunk/orp/orp_soc/doc/ORP.txt
0,0 → 1,59
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OpenRISC Reference Platform (ORP) |
|
Address Space |
|
0xf000_0000 - 0xffff_ffff Cached 256MB ROM |
0xc000_0000 - 0xefff_ffff Cached 768MB Reserved |
0xb800_0000 - 0xbfff_ffff Uncached 128MB Reserved for custom devices |
0xa600_0000 - 0xb7ff_ffff Uncached 288MB Reserved |
0xa500_0000 - 0xa5ff_ffff Uncached 16MB Debug 0-15 |
0xa400_0000 - 0xa4ff_ffff Uncached 16MB Digital Camera Controller 0-15 |
0xa300_0000 - 0xa3ff_ffff Uncached 16MB I2C Controller 0-15 |
0xa200_0000 - 0xa2ff_ffff Uncached 16MB TDM Controller 0-15 |
0xa100_0000 - 0xa1ff_ffff Uncached 16MB HDLC Controller 0-15 |
0xa000_0000 - 0xa0ff_ffff Uncached 16MB Real-Time Clock 0-15 |
0x9f00_0000 - 0x9fff_ffff Uncached 16MB Firewire Controller 0-15 |
0x9e00_0000 - 0x9eff_ffff Uncached 16MB IDE Controller 0-15 |
0x9d00_0000 - 0x9dff_ffff Uncached 16MB Audio Controller 0-15 |
0x9c00_0000 - 0x9cff_ffff Uncached 16MB USB Host Controller 0-15 |
0x9b00_0000 - 0x9bff_ffff Uncached 16MB USB Func Controller 0-15 |
0x9a00_0000 - 0x9aff_ffff Uncached 16MB General-Purpose DMA 0-15 |
0x9900_0000 - 0x99ff_ffff Uncached 16MB PCI Controller 0-15 |
0x9800_0000 - 0x98ff_ffff Uncached 16MB IrDA Controller 0-15 |
0x9700_0000 - 0x97ff_ffff Uncached 16MB Graphics Controller 0-15 |
0x9600_0000 - 0x96ff_ffff Uncached 16MB PWM/Timer/Counter Controller 0-15 |
0x9500_0000 - 0x95ff_ffff Uncached 16MB Traffic COP 0-15 |
0x9400_0000 - 0x94ff_ffff Uncached 16MB PS/2 Controller 0-15 |
0x9300_0000 - 0x93ff_ffff Uncached 16MB Memory Controller 0-15 |
0x9200_0000 - 0x92ff_ffff Uncached 16MB Ethernet Controller 0-15 |
0x9100_0000 - 0x91ff_ffff Uncached 16MB General-Purpose I/O 0-15 |
0x9000_0000 - 0x90ff_ffff Uncached 16MB UART16550 Controller 0-15 |
0x8000_0000 - 0x8fff_ffff Uncached 256MB PCI I/O |
0x4000_0000 - 0x7fff_ffff Uncached 1GB Reserved |
0x0000_0000 - 0x3fff_ffff Cached 1GB RAM |
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Interrupts |
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0 Reserved |
1 Reserved |
2 UART16550 Controller 0 |
3 General-Purpose I/O 0 |
4 Ethernet Controller 0 |
5 PS/2 Controller 0 |
6 Traffic COP 0, Real-Time Clock 0 |
7 PWM/Timer/Counter Controller 0 |
8 Graphics Controller 0 |
9 IrDA Controller 0 |
10 PCI Controller 0 |
11 General-Purpose DMA 0 |
12 USB Func Controller 0 |
13 USB Host Controller 0 |
14 Audio Controller 0 |
15 IDE Controller 0 |
16 Firewire Controller 0 |
17 HDLC Controller 0 |
18 TDM Controller 0 |
19 I2C Controller 0, Digital Camera Controller 0 |
|
|
trunk/orp/orp_soc/doc/ORP.txt
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_MUX_BUS_V3_0.v
===================================================================
--- trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_MUX_BUS_V3_0.v (nonexistent)
+++ trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_MUX_BUS_V3_0.v (revision 784)
@@ -0,0 +1,408 @@
+/* $Id: C_MUX_BUS_V3_0.v,v 1.1 2002-03-28 20:50:04 lampret Exp $
+--
+-- Filename - C_MUX_BUS_V3_0.v
+-- Author - Xilinx
+-- Creation - 4 Feb 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_BUS_V3_0 module
+*/
+
+`ifdef C_MUX_BUS_V3_0_DEF
+`else
+`define C_MUX_BUS_V3_0_DEF
+
+`ifdef C_REG_FD_V3_0_DEF
+`else
+`include "XilinxCoreLib/C_REG_FD_V3_0.v"
+`include "XilinxCoreLib/C_SHIFT_RAM_V3_0.v"
+`endif
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_lut_based 0
+`define c_buft_based 1
+
+
+
+`define allmyXs {C_WIDTH{1'bx}}
+`define allmyZs {C_WIDTH{1'bz}}
+
+module C_MUX_BUS_V3_0 (MA, MB, MC, MD, ME, MF, MG, MH,
+ MAA, MAB, MAC, MAD, MAE, MAF, MAG, MAH,
+ MBA, MBB, MBC, MBD, MBE, MBF, MBG, MBH,
+ MCA, MCB, MCC, MCD, MCE, MCF, MCG, MCH,
+ S, CLK, CE, EN, ACLR, ASET, AINIT,
+ SCLR, SSET, SINIT, O, Q);
+
+ parameter C_AINIT_VAL = "";
+ parameter C_ENABLE_RLOCS = 1;
+ parameter C_HAS_ACLR = 0;
+ parameter C_HAS_AINIT = 0;
+ parameter C_HAS_ASET = 0;
+ parameter C_HAS_CE = 0;
+ parameter C_HAS_EN = 0;
+ parameter C_HAS_O = 0;
+ parameter C_HAS_Q = 1;
+ parameter C_HAS_SCLR = 1;
+ parameter C_HAS_SINIT = 0;
+ parameter C_HAS_SSET = 1;
+ parameter C_INPUTS = 2;
+ parameter C_LATENCY = 1;
+ parameter C_MUX_TYPE = `c_lut_based;
+ parameter C_SEL_WIDTH = 1;
+ parameter C_SINIT_VAL = "";
+ parameter C_SYNC_ENABLE = `c_override;
+ parameter C_SYNC_PRIORITY = `c_clear;
+ parameter C_WIDTH = 2;
+
+ // Parameters, used to drive additional register, for pipelining.
+ parameter PIPE_HAS_ACLR = (C_LATENCY == 1 ? C_HAS_ACLR : 1'b0);
+ parameter PIPE_HAS_AINIT = (C_LATENCY == 1 ? C_HAS_AINIT : 1'b0);
+ parameter PIPE_HAS_ASET = (C_LATENCY == 1 ? C_HAS_ASET : 1'b0);
+ parameter PIPE_HAS_SSET = (C_LATENCY == 1 ? C_HAS_SSET : 1'b0);
+ parameter PIPE_HAS_SINIT = (C_LATENCY == 1 ? C_HAS_SINIT : 1'b0);
+
+
+ input [C_WIDTH-1 : 0] MA;
+ input [C_WIDTH-1 : 0] MB;
+ input [C_WIDTH-1 : 0] MC;
+ input [C_WIDTH-1 : 0] MD;
+ input [C_WIDTH-1 : 0] ME;
+ input [C_WIDTH-1 : 0] MF;
+ input [C_WIDTH-1 : 0] MG;
+ input [C_WIDTH-1 : 0] MH;
+ input [C_WIDTH-1 : 0] MAA;
+ input [C_WIDTH-1 : 0] MAB;
+ input [C_WIDTH-1 : 0] MAC;
+ input [C_WIDTH-1 : 0] MAD;
+ input [C_WIDTH-1 : 0] MAE;
+ input [C_WIDTH-1 : 0] MAF;
+ input [C_WIDTH-1 : 0] MAG;
+ input [C_WIDTH-1 : 0] MAH;
+ input [C_WIDTH-1 : 0] MBA;
+ input [C_WIDTH-1 : 0] MBB;
+ input [C_WIDTH-1 : 0] MBC;
+ input [C_WIDTH-1 : 0] MBD;
+ input [C_WIDTH-1 : 0] MBE;
+ input [C_WIDTH-1 : 0] MBF;
+ input [C_WIDTH-1 : 0] MBG;
+ input [C_WIDTH-1 : 0] MBH;
+ input [C_WIDTH-1 : 0] MCA;
+ input [C_WIDTH-1 : 0] MCB;
+ input [C_WIDTH-1 : 0] MCC;
+ input [C_WIDTH-1 : 0] MCD;
+ input [C_WIDTH-1 : 0] MCE;
+ input [C_WIDTH-1 : 0] MCF;
+ input [C_WIDTH-1 : 0] MCG;
+ input [C_WIDTH-1 : 0] MCH;
+ input [C_SEL_WIDTH-1 : 0] S;
+ input CLK;
+ input CE;
+ input EN;
+ input ACLR;
+ input ASET;
+ input AINIT;
+ input SCLR;
+ input SSET;
+ input SINIT;
+ output [C_WIDTH-1 : 0] O;
+ output [C_WIDTH-1 : 0] Q;
+
+ // Internal values to drive signals when input is missing
+ wire [C_WIDTH-1 : 0] intMA = MA;
+ wire [C_WIDTH-1 : 0] intMB = MB;
+ wire [C_WIDTH-1 : 0] intMC = (C_INPUTS > 2 ? MC : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMD = (C_INPUTS > 3 ? MD : `allmyXs);
+ wire [C_WIDTH-1 : 0] intME = (C_INPUTS > 4 ? ME : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMF = (C_INPUTS > 5 ? MF : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMG = (C_INPUTS > 6 ? MG : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMH = (C_INPUTS > 7 ? MH : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMAA = (C_INPUTS > 8 ? MAA : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMAB = (C_INPUTS > 9 ? MAB : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMAC = (C_INPUTS > 10 ? MAC : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMAD = (C_INPUTS > 11 ? MAD : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMAE = (C_INPUTS > 12 ? MAE : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMAF = (C_INPUTS > 13 ? MAF : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMAG = (C_INPUTS > 14 ? MAG : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMAH = (C_INPUTS > 15 ? MAH : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMBA = (C_INPUTS > 16 ? MBA : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMBB = (C_INPUTS > 17 ? MBB : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMBC = (C_INPUTS > 18 ? MBC : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMBD = (C_INPUTS > 19 ? MBD : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMBE = (C_INPUTS > 20 ? MBE : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMBF = (C_INPUTS > 21 ? MBF : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMBG = (C_INPUTS > 22 ? MBG : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMBH = (C_INPUTS > 23 ? MBH : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMCA = (C_INPUTS > 24 ? MCA : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMCB = (C_INPUTS > 25 ? MCB : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMCC = (C_INPUTS > 26 ? MCC : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMCD = (C_INPUTS > 27 ? MCD : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMCE = (C_INPUTS > 28 ? MCE : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMCF = (C_INPUTS > 29 ? MCF : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMCG = (C_INPUTS > 30 ? MCG : `allmyXs);
+ wire [C_WIDTH-1 : 0] intMCH = (C_INPUTS > 31 ? MCH : `allmyXs);
+
+ reg [C_WIDTH-1 : 0] intO;
+ reg [C_WIDTH-1 : 0] intQ;
+
+ wire [C_WIDTH-1 : 0] STAGE1;
+ wire [C_WIDTH-1 : 0] STAGE2;
+ wire [C_SEL_WIDTH-1 : 0] intS = S;
+ wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : `allmyXs);
+ wire [C_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : `allmyXs);
+ wire intEN;
+
+
+ assign intEN = defval(EN, C_HAS_EN, 1);
+
+
+ integer j, k, j1, k1;
+ integer m, unknown, m1, unknown1;
+
+ // Register on output by default
+
+ C_REG_FD_V3_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, PIPE_HAS_ACLR, PIPE_HAS_AINIT, PIPE_HAS_ASET,
+ C_HAS_CE, C_HAS_SCLR, PIPE_HAS_SINIT, PIPE_HAS_SSET,
+ C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH)
+ REG1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+ .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+ .Q(STAGE1));
+
+
+ C_REG_FD_V3_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+ C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+ C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH)
+ REG2 (.D(STAGE1), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+ .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+ .Q(STAGE2));
+
+
+ initial
+ begin
+
+ #1;
+ k = 1;
+ m = 1;
+ unknown = 0;
+ for(j = 0; j < C_SEL_WIDTH; j = j + 1)
+ begin
+ if(intS[j] === 1)
+ k = k + m;
+ else if(intS[j] === 1'bz || intS[j] === 1'bx)
+ unknown = 1;
+ m = m * 2;
+ end
+
+ if(intEN === 1'b0)
+ intO <= #1 `allmyZs;
+ else if(intEN === 1'bx)
+ intO <= #1 `allmyXs;
+ else if(unknown == 1)
+ intO <= #1 `allmyXs;
+ else if (k == 1)
+ intO <= #1 intMA;
+ else if (k == 2)
+ intO <= #1 intMB;
+ else if (k == 3)
+ intO <= #1 intMC;
+ else if (k == 4)
+ intO <= #1 intMD;
+ else if (k == 5)
+ intO <= #1 intME;
+ else if (k == 6)
+ intO <= #1 intMF;
+ else if (k == 7)
+ intO <= #1 intMG;
+ else if (k == 8)
+ intO <= #1 intMH;
+ else if (k == 9)
+ intO <= #1 intMAA;
+ else if (k == 10)
+ intO <= #1 intMAB;
+ else if (k == 11)
+ intO <= #1 intMAC;
+ else if (k == 12)
+ intO <= #1 intMAD;
+ else if (k == 13)
+ intO <= #1 intMAE;
+ else if (k == 14)
+ intO <= #1 intMAF;
+ else if (k == 15)
+ intO <= #1 intMAG;
+ else if (k == 16)
+ intO <= #1 intMAH;
+ else if (k == 17)
+ intO <= #1 intMBA;
+ else if (k == 18)
+ intO <= #1 intMBB;
+ else if (k == 19)
+ intO <= #1 intMBC;
+ else if (k == 20)
+ intO <= #1 intMBD;
+ else if (k == 21)
+ intO <= #1 intMBE;
+ else if (k == 22)
+ intO <= #1 intMBF;
+ else if (k == 23)
+ intO <= #1 intMBG;
+ else if (k == 24)
+ intO <= #1 intMBH;
+ else if (k == 25)
+ intO <= #1 intMCA;
+ else if (k == 26)
+ intO <= #1 intMCB;
+ else if (k == 27)
+ intO <= #1 intMCC;
+ else if (k == 28)
+ intO <= #1 intMCD;
+ else if (k == 29)
+ intO <= #1 intMCE;
+ else if (k == 30)
+ intO <= #1 intMCF;
+ else if (k == 31)
+ intO <= #1 intMCG;
+ else if (k == 32)
+ intO <= #1 intMCH;
+ else
+ intO <= #1 `allmyXs;
+
+ end
+
+ always@(intMA or intMB or intMC or intMD or intME or intMF or intMG or intMH or
+ intMAA or intMAB or intMAC or intMAD or intMAE or intMAF or intMAG or intMAH or
+ intMBA or intMBB or intMBC or intMBD or intMBE or intMBF or intMBG or intMBH or
+ intMCA or intMCB or intMCC or intMCD or intMCE or intMCF or intMCG or intMCH or
+ intEN or intS)
+ begin
+
+ k1 = 1;
+ m1 = 1;
+ unknown1 = 0;
+ for(j1 = 0; j1 < C_SEL_WIDTH; j1 = j1 + 1)
+ begin
+ if(intS[j1] === 1)
+ k1 = k1 + m1;
+ else if(intS[j1] === 1'bz || intS[j1] === 1'bx)
+ unknown1 = 1;
+ m1 = m1 * 2;
+ end
+
+
+ if(intEN === 1'b0)
+ intO = #1 `allmyZs;
+ else if(intEN === 1'bx)
+ intO = #1 `allmyXs;
+ else if(unknown1 == 1)
+ intO <= #1 `allmyXs;
+ else if (k1 == 1)
+ intO <= #1 intMA;
+ else if (k1 == 2)
+ intO <= #1 intMB;
+ else if (k1 == 3)
+ intO <= #1 intMC;
+ else if (k1 == 4)
+ intO <= #1 intMD;
+ else if (k1 == 5)
+ intO <= #1 intME;
+ else if (k1 == 6)
+ intO <= #1 intMF;
+ else if (k1 == 7)
+ intO <= #1 intMG;
+ else if (k1 == 8)
+ intO <= #1 intMH;
+ else if (k1 == 9)
+ intO <= #1 intMAA;
+ else if (k1 == 10)
+ intO <= #1 intMAB;
+ else if (k1 == 11)
+ intO <= #1 intMAC;
+ else if (k1 == 12)
+ intO <= #1 intMAD;
+ else if (k1 == 13)
+ intO <= #1 intMAE;
+ else if (k1 == 14)
+ intO <= #1 intMAF;
+ else if (k1 == 15)
+ intO <= #1 intMAG;
+ else if (k1 == 16)
+ intO <= #1 intMAH;
+ else if (k1 == 17)
+ intO <= #1 intMBA;
+ else if (k1 == 18)
+ intO <= #1 intMBB;
+ else if (k1 == 19)
+ intO <= #1 intMBC;
+ else if (k1 == 20)
+ intO <= #1 intMBD;
+ else if (k1 == 21)
+ intO <= #1 intMBE;
+ else if (k1 == 22)
+ intO <= #1 intMBF;
+ else if (k1 == 23)
+ intO <= #1 intMBG;
+ else if (k1 == 24)
+ intO <= #1 intMBH;
+ else if (k1 == 25)
+ intO <= #1 intMCA;
+ else if (k1 == 26)
+ intO <= #1 intMCB;
+ else if (k1 == 27)
+ intO <= #1 intMCC;
+ else if (k1 == 28)
+ intO <= #1 intMCD;
+ else if (k1 == 29)
+ intO <= #1 intMCE;
+ else if (k1 == 30)
+ intO <= #1 intMCF;
+ else if (k1 == 31)
+ intO <= #1 intMCG;
+ else if (k1 == 32)
+ intO <= #1 intMCH;
+ else
+ intO <= #1 `allmyXs;
+
+ end
+
+// Register output settings
+always
+begin
+ //------------------------------
+ //-- REGISTER CLOCKED OUTPUTS --
+ //------------------------------
+ if (C_LATENCY === 1)
+ intQ = STAGE1;
+ else
+ intQ = STAGE2;
+ @(STAGE1 or STAGE2);
+end
+
+
+ function defval;
+ input i;
+ input hassig;
+ input val;
+ begin
+ if(hassig == 1)
+ defval = i;
+ else
+ defval = val;
+ end
+ endfunction
+
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_lut_based
+`undef c_buft_based
+
+`undef allmyXs
+`undef allmyZs
+
+`endif
+
+
trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_MUX_BUS_V3_0.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_ADDSUB_V3_0.v
===================================================================
--- trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_ADDSUB_V3_0.v (nonexistent)
+++ trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_ADDSUB_V3_0.v (revision 784)
@@ -0,0 +1,665 @@
+/* $Id: C_ADDSUB_V3_0.v,v 1.1 2002-03-28 20:50:04 lampret Exp $
+--
+-- Filename - C_ADDSUB_V3_0.v
+-- Author - Xilinx
+-- Creation - 22 Mar 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_ADDSUB_V3_0 module
+*/
+
+`ifdef C_ADDSUB_V3_0_DEF
+`else
+`define C_ADDSUB_V3_0_DEF
+
+`ifdef C_REG_FD_V3_0_DEF
+`else
+`include "XilinxCoreLib/C_REG_FD_V3_0.v"
+`define C_REG_FD_V3_0_DEF
+`endif
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_add 0
+`define c_sub 1
+`define c_add_sub 2
+`define c_signed 0
+`define c_unsigned 1
+`define c_pin 2
+`define allUKs {(C_HIGH_BIT-C_LOW_BIT)+1{1'bx}}
+
+module C_ADDSUB_V3_0 (A, B, CLK, ADD, C_IN, B_IN, CE, BYPASS, ACLR, ASET, AINIT,
+ SCLR, SSET, SINIT, A_SIGNED, B_SIGNED, OVFL, C_OUT, B_OUT,
+ Q_OVFL, Q_C_OUT, Q_B_OUT, S, Q);
+
+ parameter C_ADD_MODE = `c_add;
+ parameter C_AINIT_VAL = "";
+ parameter C_A_TYPE = `c_unsigned;
+ parameter C_A_WIDTH = 16;
+ parameter C_BYPASS_ENABLE = `c_override;
+ parameter C_BYPASS_LOW = 0;
+ parameter C_B_CONSTANT = 0;
+ parameter C_B_TYPE = `c_unsigned;
+ parameter C_B_VALUE = "";
+ parameter C_B_WIDTH = 16;
+ parameter C_ENABLE_RLOCS = 1;
+ parameter C_HAS_ACLR = 0;
+ parameter C_HAS_ADD = 0;
+ parameter C_HAS_AINIT = 0;
+ parameter C_HAS_ASET = 0;
+ parameter C_HAS_A_SIGNED = 0;
+ parameter C_HAS_BYPASS = 0;
+ parameter C_HAS_B_IN = 1;
+ parameter C_HAS_B_OUT = 0;
+ parameter C_HAS_B_SIGNED = 0;
+ parameter C_HAS_CE = 0;
+ parameter C_HAS_C_IN = 1;
+ parameter C_HAS_C_OUT = 0;
+ parameter C_HAS_OVFL = 0;
+ parameter C_HAS_Q = 1;
+ parameter C_HAS_Q_B_OUT = 0;
+ parameter C_HAS_Q_C_OUT = 0;
+ parameter C_HAS_Q_OVFL = 0;
+ parameter C_HAS_S = 0;
+ parameter C_HAS_SCLR = 0;
+ parameter C_HAS_SINIT = 0;
+ parameter C_HAS_SSET = 0;
+ parameter C_HIGH_BIT = 15;
+ parameter C_LATENCY = 1;
+ parameter C_LOW_BIT = 0;
+ parameter C_OUT_WIDTH = 16;
+ parameter C_PIPE_STAGES = 1;
+ parameter C_SINIT_VAL = "";
+ parameter C_SYNC_ENABLE = `c_override;
+ parameter C_SYNC_PRIORITY = `c_clear;
+
+ // internal parameters (not to be set from instanciation)
+ parameter tmpWidth = (C_A_WIDTH > C_B_WIDTH) ? C_A_WIDTH + 2 : C_B_WIDTH + 2;
+ parameter output_reg_width = C_HIGH_BIT-C_LOW_BIT+1;
+
+ input [C_A_WIDTH-1 : 0] A;
+ input [C_B_WIDTH-1 : 0] B;
+ input CLK;
+ input ADD;
+ input C_IN;
+ input B_IN;
+ input CE;
+ input BYPASS;
+ input ACLR;
+ input ASET;
+ input AINIT;
+ input SCLR;
+ input SSET;
+ input SINIT;
+ input A_SIGNED;
+ input B_SIGNED;
+ output OVFL;
+ output C_OUT;
+ output B_OUT;
+ output Q_OVFL;
+ output Q_C_OUT;
+ output Q_B_OUT;
+ output [C_HIGH_BIT : C_LOW_BIT] S;
+ output [C_HIGH_BIT : C_LOW_BIT] Q;
+
+
+ // Internal values to drive signals when input is missing
+ wire [C_B_WIDTH-1 : 0] intBconst;
+ wire [C_B_WIDTH-1 : 0] intB;
+ wire intADD;
+ wire intBYPASS;
+ wire intC_IN;
+ wire intB_IN;
+ wire intCE;
+ wire intQCE;
+ wire intA_SIGNED;
+ wire intB_SIGNED;
+ reg intC_OUT;
+ reg intB_OUT;
+ reg intOVFL;
+ wire intQ_C_OUT;
+ wire intQ_B_OUT;
+ wire intQ_OVFL;
+ reg [C_HIGH_BIT : C_LOW_BIT ] intS;
+ wire [C_HIGH_BIT : C_LOW_BIT ] intQ;
+ wire intACLR;
+ wire intASET;
+ wire intAINIT;
+ wire intSCLR;
+ wire intSSET;
+ wire intSINIT;
+ wire intACLR_INIT;
+ wire intSCLR_INIT;
+ reg lastCLK;
+ reg lastADD;
+
+ reg [C_HIGH_BIT : C_LOW_BIT] intQpipe [C_LATENCY+2 : 0];
+ reg [C_LATENCY+2 : 0] intQ_C_OUTpipe;
+ reg [C_LATENCY+2 : 0] intQ_B_OUTpipe;
+ reg [C_LATENCY : 0] intQ_OVFLpipe;
+
+ reg [C_HIGH_BIT : C_LOW_BIT] intQpipeend;
+ reg intQ_C_OUTpipeend;
+ reg intQ_B_OUTpipeend;
+ reg intQ_OVFLpipeend;
+ reg [C_HIGH_BIT : C_LOW_BIT] tmp_pipe1;
+ reg [C_HIGH_BIT : C_LOW_BIT] tmp_pipe2;
+
+
+ wire [C_HIGH_BIT : C_LOW_BIT] Q = (C_HAS_Q == 1 ? intQ : `allUKs);
+ wire Q_C_OUT = (C_HAS_Q_C_OUT == 1 ? intQ_C_OUT : 1'bx);
+ wire Q_B_OUT = (C_HAS_Q_B_OUT == 1 ? intQ_B_OUT : 1'bx);
+ wire Q_OVFL = (C_HAS_Q_OVFL == 1 ? intQ_OVFL : 1'bx);
+ wire [C_HIGH_BIT : C_LOW_BIT] S = (C_HAS_S == 1 ? intS : `allUKs);
+ wire C_OUT = (C_HAS_C_OUT == 1 ? intC_OUT : 1'bx);
+ wire B_OUT = (C_HAS_B_OUT == 1 ? intB_OUT : 1'bx);
+ wire OVFL = (C_HAS_OVFL == 1 ? intOVFL : 1'bx);
+
+ // Sort out default values for missing ports
+
+ assign intCE = defval(CE, C_HAS_CE, 1);
+ assign intACLR = defval(ACLR, C_HAS_ACLR, 0);
+ assign intASET = defval(ASET, C_HAS_ASET, 0);
+ assign intAINIT = defval(AINIT, C_HAS_AINIT, 0);
+ assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);
+ assign intSSET = defval(SSET, C_HAS_SSET, 0);
+ assign intSINIT = defval(SINIT, C_HAS_SINIT, 0);
+ assign intACLR_INIT = (intACLR || intAINIT);
+ assign intSCLR_INIT = (intSCLR || intSINIT);
+
+ assign intBconst = (C_B_CONSTANT === 1) ? to_bitsB(C_B_VALUE) : B;
+ assign intADD = (C_HAS_ADD === 1) ? ADD : ((C_ADD_MODE === `c_add) ? 1 : ((C_ADD_MODE === `c_sub) ? 0 : 3)); // 3 is an illegal value since this is an illegal option!
+ assign intBYPASS = (C_HAS_BYPASS === 1) ? ((C_BYPASS_LOW === 1) ? !BYPASS : BYPASS) : 0;
+ assign intC_IN = ((C_HAS_C_IN === 1) ? C_IN : ((C_HAS_ADD === 1) ? ~intADD : 0));
+ assign intB_IN = defval(B_IN, C_HAS_B_IN, 1);
+ assign intA_SIGNED = defval(A_SIGNED, C_HAS_A_SIGNED, 0);
+ //assign intB_SIGNED = defval(B_SIGNED, C_HAS_B_SIGNED, 0);
+ assign intB_SIGNED = ((C_HAS_B_SIGNED === 0) ? 0 : (((C_HAS_B_SIGNED === 1) && ~((C_B_CONSTANT === 1) && (C_HAS_BYPASS === 0) && (C_B_VALUE[((C_B_WIDTH*8)-1):((C_B_WIDTH-1)*8)] === "0")) ? B_SIGNED : 0))) ;
+ assign intB = (intBYPASS === 0 ? intBconst : B);
+ assign intQCE = (C_HAS_CE === 1 ? (C_HAS_BYPASS === 1 ? (C_BYPASS_ENABLE === `c_override ? CE || intBYPASS : CE) : CE) : 1'b1);
+
+ integer j, k;
+ integer pipe, pipe1;
+ integer i;
+
+ reg [tmpWidth-1 : 0] tmpA;
+ reg [tmpWidth-1 : 0] tmpB;
+ reg [tmpWidth-1 : 0] tmpC;
+ reg [tmpWidth-1 : 0] tmpBC;
+ reg [tmpWidth-1 : 0] tmpABC;
+ reg [tmpWidth-2 : 0] tmpD;
+ reg [tmpWidth-2 : 0] tmpE;
+ reg [tmpWidth-2 : 0] tmpF;
+
+ // Registers on outputs by default
+ C_REG_FD_V3_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+ C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+ C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, output_reg_width)
+ regq (.D(intQpipeend), .CLK(CLK), .CE(intQCE), .ACLR(ACLR), .ASET(ASET),
+ .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+ .Q(intQ));
+
+ C_REG_FD_V3_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+ C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+ "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+ regcout (.D(intQ_C_OUTpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT),
+ .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET),
+ .Q(intQ_C_OUT));
+
+ C_REG_FD_V3_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+ C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+ "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+ regbout (.D(intQ_B_OUTpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT),
+ .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET),
+ .Q(intQ_B_OUT));
+
+ C_REG_FD_V3_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+ C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+ "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+ regovfl (.D(intQ_OVFLpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT),
+ .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET),
+ .Q(intQ_OVFL));
+
+ initial
+ begin
+ #1;
+ for(i = 0; i <= C_LATENCY+2; i = i + 1)
+ begin
+ intQpipe[i] = 'bx;
+ intQ_C_OUTpipe[i] = 1'bx;
+ intQ_B_OUTpipe[i] = 1'bx;
+ intQ_OVFLpipe[i] = 1'bx;
+ end
+ intQpipeend = `allUKs;
+ intQ_C_OUTpipeend = 0;
+ intQ_B_OUTpipeend = 0;
+ intQ_OVFLpipeend = 0;
+ intS = `allUKs;
+ intC_OUT = 0;
+ intB_OUT = 0;
+ intOVFL = 0;
+ end
+
+ always@(A or intB or intADD or intBYPASS or intC_IN or intB_IN or intA_SIGNED or intB_SIGNED)
+ begin
+ tmpC = 0;
+ if(intC_IN !== 1'b0)
+ begin
+ if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add)
+ begin
+ tmpC = intC_IN;
+ end
+ end
+ else if(intC_IN !== 1'b1 && C_ADD_MODE == `c_add_sub && intADD === 1'b0)
+ begin
+ tmpC[0] = ~intC_IN;
+ end
+ else if(intB_IN !== 1'b1 && C_ADD_MODE == `c_sub)
+ begin
+ tmpC[0] = ~intB_IN;
+ end
+
+ if(C_A_TYPE == `c_signed || (C_A_TYPE == `c_pin && intA_SIGNED === 1))
+ begin
+ for(j = tmpWidth-1; j >= C_A_WIDTH; j = j - 1)
+ begin
+ tmpA[j] = A[C_A_WIDTH-1];
+ end
+ end
+ else if(C_A_TYPE == `c_unsigned || (C_A_TYPE == `c_pin && intA_SIGNED === 0))
+ begin
+ for(j = tmpWidth-1; j >= C_A_WIDTH; j = j - 1)
+ begin
+ tmpA[j] = 0;
+ end
+ end
+
+ tmpA[C_A_WIDTH-1 : 0] = A;
+
+ if(C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED === 1))
+ begin
+ for(j = tmpWidth-1; j >= C_B_WIDTH; j = j - 1)
+ begin
+ tmpB[j] = intB[C_B_WIDTH-1];
+ end
+ end
+ else if(C_B_TYPE == `c_unsigned || (C_B_TYPE == `c_pin && intB_SIGNED === 0))
+ begin
+ for(j = tmpWidth-1; j >= C_B_WIDTH; j = j - 1)
+ begin
+ tmpB[j] = 0;
+ end
+ end
+
+ tmpB[C_B_WIDTH-1 : 0] = intB;
+
+ if(intBYPASS == 1)
+ begin
+ intS <= #1 tmpB[C_HIGH_BIT : C_LOW_BIT];
+ if (is_X(tmpB) && C_LATENCY >1)
+ begin
+ intC_OUT <= #1 1'bx;
+ intB_OUT <= #1 1'bx;
+ intOVFL <= #1 1'bx;
+ end
+ else
+ begin
+ intC_OUT <= #1 1'b0;
+ intB_OUT <= #1 1'b0;
+ intOVFL <= #1 1'b0;
+ end
+ end
+ else if(is_X(tmpA) || is_X(tmpB) || is_X(tmpC) || intBYPASS === 1'bx || intADD === 1'bx)
+ begin
+ intS <= #1 {C_HIGH_BIT-C_LOW_BIT+1{1'bx}};
+ intC_OUT <= #1 1'bx;
+ intB_OUT <= #1 1'bx;
+ intOVFL <= #1 1'bx;
+ end
+ else
+ begin
+ if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add)
+ begin
+ tmpBC = add(tmpB, tmpC);
+ end
+ else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub)
+ begin
+ tmpBC = add(tmpB, tmpC);
+ end
+
+ if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add)
+ begin
+ tmpABC = add(tmpA, tmpBC);
+ end
+ else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub)
+ begin
+ tmpABC = sub(tmpA, tmpBC);
+ end
+
+ intS <= #1 tmpABC[C_HIGH_BIT : C_LOW_BIT];
+
+ if(C_HAS_C_OUT == 1 || C_HAS_Q_C_OUT == 1)
+ begin
+ if((C_ADD_MODE == `c_add_sub && intADD === 1'b1) || C_ADD_MODE == `c_add)
+ intC_OUT <= #1 tmpABC[tmpWidth-2];
+ else if(C_ADD_MODE == `c_add_sub && intADD === 1'b0)
+ intC_OUT <= #1 ~tmpABC[tmpWidth-2];
+ end
+
+ if(C_HAS_B_OUT == 1 || C_HAS_Q_B_OUT == 1)
+ begin
+ intB_OUT <= #1 !tmpABC[tmpWidth-2];
+ end
+
+ if(C_HAS_OVFL == 1 || C_HAS_Q_OVFL == 1)
+ begin
+ tmpD[tmpWidth-3 : 0] = tmpA[tmpWidth-3 : 0];
+ if(C_A_TYPE == `c_signed || (C_A_TYPE == `c_pin && intA_SIGNED == 1))
+ tmpD[tmpWidth-2] = tmpA[tmpWidth-1];
+ else
+ tmpD[tmpWidth-2] = 1'b0;
+ tmpE[tmpWidth-3 : 0] = tmpBC[tmpWidth-3 : 0];
+ if(C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED == 1))
+ tmpE[tmpWidth-2] = tmpBC[tmpWidth-1];
+ else
+ tmpE[tmpWidth-2] = 1'b0;
+ if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add)
+ begin
+ tmpF = sm_add(tmpD, tmpE);
+ end
+ else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub)
+ begin
+ tmpF = sm_sub(tmpD, tmpE);
+ end
+
+ intOVFL <= #1 tmpF[tmpWidth-3] ^ tmpABC[tmpWidth-2];
+ end
+ end
+ end
+
+ always@(posedge CLK)
+ lastADD <= intADD;
+
+ always@(posedge CLK)
+ begin
+ if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines!
+ begin
+ if (lastADD === intADD) // is pipeline data valid?
+ begin
+ for(pipe = 2; pipe <= C_LATENCY-1; pipe = pipe + 1)
+ begin
+ intQpipe[pipe] <= intQpipe[pipe+1];
+ intQ_C_OUTpipe[pipe] <= intQ_C_OUTpipe[pipe+1];
+ intQ_B_OUTpipe[pipe] <= intQ_B_OUTpipe[pipe+1];
+ intQ_OVFLpipe[pipe] <= intQ_OVFLpipe[pipe+1];
+ end
+ end
+ else
+ begin
+ for(pipe = 2; pipe <= C_LATENCY-1; pipe = pipe + 1)
+ begin
+ intQpipe[pipe] <= 'bx;
+ intQ_C_OUTpipe[pipe] <= 1'bx;
+ intQ_B_OUTpipe[pipe] <= 1'bx;
+ intQ_OVFLpipe[pipe] <= 1'bx;
+ end
+ end
+ intQpipe[C_LATENCY] <= intS;
+ intQ_C_OUTpipe[C_LATENCY] <= intC_OUT;
+ intQ_B_OUTpipe[C_LATENCY] <= intB_OUT;
+ intQ_OVFLpipe[C_LATENCY] <= intOVFL;
+ end
+ else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines!
+ begin
+ for(pipe = 2; pipe <= C_LATENCY-1; pipe = pipe + 1)
+ begin
+ if(intQ_C_OUTpipe[pipe] !== intQ_C_OUTpipe[pipe+1])
+ intQ_C_OUTpipe[pipe] <= 1'bx;
+ if(intQ_B_OUTpipe[pipe] !== intQ_B_OUTpipe[pipe+1])
+ intQ_B_OUTpipe[pipe] <= 1'bx;
+ if(intQ_OVFLpipe[pipe] !== intQ_OVFLpipe[pipe+1])
+ intQ_OVFLpipe[pipe] <= 1'bx;
+ tmp_pipe1 = intQpipe[pipe];
+ tmp_pipe2 = intQpipe[pipe+1];
+ for(pipe1 = C_LOW_BIT; pipe1 < C_HIGH_BIT+1; pipe1 = pipe1 + 1)
+ begin
+ if(tmp_pipe1[pipe1] !== tmp_pipe2[pipe1])
+ tmp_pipe1[pipe1] = 1'bx;
+ end
+ intQpipe[pipe] <= tmp_pipe1;
+ end
+ if(intQ_C_OUTpipe[C_LATENCY] !== intC_OUT)
+ intQ_C_OUTpipe[C_LATENCY] <= 1'bx;
+ if(intQ_B_OUTpipe[C_LATENCY] !== intB_OUT)
+ intQ_B_OUTpipe[C_LATENCY] <= 1'bx;
+ if(intQ_OVFLpipe[C_LATENCY] !== intOVFL)
+ intQ_OVFLpipe[C_LATENCY] <= 1'bx;
+ for(pipe1 = C_LOW_BIT; pipe1 < C_HIGH_BIT+1; pipe1 = pipe1 + 1)
+ begin
+ if(tmp_pipe1[pipe1] !== intS[pipe1])
+ tmp_pipe1[pipe1] = 1'bx;
+ end
+ intQpipe[C_LATENCY] <= tmp_pipe1;
+ end
+ end
+
+ always@(intS or intQpipe[2] or intADD or lastADD)
+ begin
+ if(C_LATENCY < 2) // No pipeline
+ intQpipeend <= intS;
+ else if (lastADD === intADD)
+ // Pipeline stages required
+ intQpipeend <= intQpipe[2];
+ else
+ // pipeline data invalid
+ intQpipeend <= 'bx;
+ end
+
+ always@(intC_OUT or intQ_C_OUTpipe[2] or intADD or lastADD)
+ begin
+ if(C_LATENCY < 2) // No pipeline
+ intQ_C_OUTpipeend <= intC_OUT;
+ else if (lastADD === intADD)
+ // Pipeline stages required
+ intQ_C_OUTpipeend <= intQ_C_OUTpipe[2];
+ else
+ // Pipeline data invalid
+ intQ_C_OUTpipeend <= 1'bx;
+ end
+
+ always@(intB_OUT or intQ_B_OUTpipe[2] or intADD or lastADD)
+ begin
+ if(C_LATENCY < 2) // No pipeline
+ intQ_B_OUTpipeend <= intB_OUT;
+ else if (lastADD === intADD)
+ // Pipeline stages required
+ intQ_B_OUTpipeend <= intQ_B_OUTpipe[2];
+ else
+ intQ_B_OUTpipeend <= 1'bx;
+ end
+
+ always@(intOVFL or intQ_OVFLpipe[2] or intADD or lastADD)
+ begin
+ if(C_LATENCY < 2) // No pipeline
+ intQ_OVFLpipeend <= intOVFL;
+ else if (lastADD === intADD)
+ // Pipeline stages required
+ intQ_OVFLpipeend <= intQ_OVFLpipe[2];
+ else
+ intQ_OVFLpipeend <= 1'bx;
+ end
+
+ always@(CLK)
+ lastCLK <= CLK;
+
+/* helper functions */
+
+ function defval;
+ input i;
+ input hassig;
+ input val;
+ begin
+ if(hassig == 1)
+ defval = i;
+ else
+ defval = val;
+ end
+ endfunction
+
+ function [C_B_WIDTH - 1 : 0] to_bitsB;
+ input [C_B_WIDTH*8 : 1] instring;
+ integer i;
+ integer non_null_string;
+ begin
+ non_null_string = 0;
+ for(i = C_B_WIDTH; i > 0; i = i - 1)
+ begin // Is the string empty?
+ if(instring[(i*8)] == 0 &&
+ instring[(i*8)-1] == 0 &&
+ instring[(i*8)-2] == 0 &&
+ instring[(i*8)-3] == 0 &&
+ instring[(i*8)-4] == 0 &&
+ instring[(i*8)-5] == 0 &&
+ instring[(i*8)-6] == 0 &&
+ instring[(i*8)-7] == 0 &&
+ non_null_string == 0)
+ non_null_string = 0; // Use the return value to flag a non-empty string
+ else
+ non_null_string = 1; // Non-null character!
+ end
+ if(non_null_string == 0) // String IS empty! Just return the value to be all '0's
+ begin
+ for(i = C_B_WIDTH; i > 0; i = i - 1)
+ to_bitsB[i-1] = 0;
+ end
+ else
+ begin
+ for(i = C_B_WIDTH; i > 0; i = i - 1)
+ begin // Is this character a '0'? (ASCII = 48 = 00110000)
+ if(instring[(i*8)] == 0 &&
+ instring[(i*8)-1] == 0 &&
+ instring[(i*8)-2] == 1 &&
+ instring[(i*8)-3] == 1 &&
+ instring[(i*8)-4] == 0 &&
+ instring[(i*8)-5] == 0 &&
+ instring[(i*8)-6] == 0 &&
+ instring[(i*8)-7] == 0)
+ to_bitsB[i-1] = 0;
+ // Or is it a '1'?
+ else if(instring[(i*8)] == 0 &&
+ instring[(i*8)-1] == 0 &&
+ instring[(i*8)-2] == 1 &&
+ instring[(i*8)-3] == 1 &&
+ instring[(i*8)-4] == 0 &&
+ instring[(i*8)-5] == 0 &&
+ instring[(i*8)-6] == 0 &&
+ instring[(i*8)-7] == 1)
+ to_bitsB[i-1] = 1;
+ // Or is it a ' '? (a null char - in which case insert a '0')
+ else if(instring[(i*8)] == 0 &&
+ instring[(i*8)-1] == 0 &&
+ instring[(i*8)-2] == 0 &&
+ instring[(i*8)-3] == 0 &&
+ instring[(i*8)-4] == 0 &&
+ instring[(i*8)-5] == 0 &&
+ instring[(i*8)-6] == 0 &&
+ instring[(i*8)-7] == 0)
+ to_bitsB[i-1] = 0;
+ else
+ begin
+ $display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring);
+ $finish;
+ end
+ end
+ end
+ end
+ endfunction
+
+ function max;
+ input a;
+ input b;
+ begin
+ max = (a > b) ? a : b;
+ end
+ endfunction
+
+ function is_X;
+ input [tmpWidth-1 : 0] i;
+ begin
+ is_X = 1'b0;
+ for(j = 0; j < tmpWidth; j = j + 1)
+ begin
+ if(i[j] === 1'bx)
+ is_X = 1'b1;
+ end // loop
+ end
+ endfunction
+
+ function [tmpWidth-1 : 0] add;
+ input [tmpWidth-1 : 0] i1;
+ input [tmpWidth-1 : 0] i2;
+ integer bit;
+ integer carryin, carryout;
+ begin
+ carryin = 0;
+ carryout = 0;
+ for(bit=0; bit < tmpWidth; bit = bit + 1)
+ begin
+ add[bit] = i1[bit] ^ i2[bit] ^ carryin;
+ carryout = (i1[bit] && i2[bit]) || (carryin && (i1[bit] || i2[bit]));
+ carryin = carryout;
+ end
+ end
+ endfunction
+
+ function [tmpWidth-1 : 0] sub;
+ input [tmpWidth-1 : 0] i1;
+ input [tmpWidth-1 : 0] i2;
+ begin
+ i2 = add(~i2, 1);
+ sub = add(i1, i2);
+ end
+ endfunction
+
+ function [tmpWidth-2 : 0] sm_add;
+ input [tmpWidth-2 : 0] i1;
+ input [tmpWidth-2 : 0] i2;
+ integer bit;
+ integer carryin, carryout;
+ begin
+ carryin = 0;
+ carryout = 0;
+ for(bit=0; bit < tmpWidth-1; bit = bit + 1)
+ begin
+ sm_add[bit] = i1[bit] ^ i2[bit] ^ carryin;
+ carryout = (i1[bit] && i2[bit]) || (carryin && (i1[bit] || i2[bit]));
+ carryin = carryout;
+ end
+ end
+ endfunction
+
+ function [tmpWidth-2 : 0] sm_sub;
+ input [tmpWidth-2 : 0] i1;
+ input [tmpWidth-2 : 0] i2;
+ begin
+ i2 = sm_add(~i2, 1);
+ sm_sub = sm_add(i1, i2);
+ end
+ endfunction
+
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_add
+`undef c_sub
+`undef c_add_sub
+`undef c_signed
+`undef c_unsigned
+`undef c_pin
+`undef allUKs
+
+`endif
trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_ADDSUB_V3_0.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_COUNTER_BINARY_V3_0.v
===================================================================
--- trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_COUNTER_BINARY_V3_0.v (nonexistent)
+++ trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_COUNTER_BINARY_V3_0.v (revision 784)
@@ -0,0 +1,425 @@
+/* $Id: C_COUNTER_BINARY_V3_0.v,v 1.1 2002-03-28 20:50:04 lampret Exp $
+--
+-- Filename - C_COUNTER_BINARY_V3_0.v
+-- Author - Xilinx
+-- Creation -14 July 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_COUNTER_BINARY_V3_0 module
+*/
+
+`ifdef C_COUNTER_BINARY_V3_0_DEF
+`else
+`define C_COUNTER_BINARY_V3_0_DEF
+
+`ifdef C_ADDSUB_V3_0_DEF
+`else
+`include "XilinxCoreLib/C_ADDSUB_V3_0.v"
+`endif
+
+`ifdef C_COMPARE_V3_0_DEF
+`else
+`include "XilinxCoreLib/C_COMPARE_V3_0.v"
+`endif
+
+`ifdef C_MUX_BUS_V3_0_DEF
+`else
+`include "XilinxCoreLib/C_MUX_BUS_V3_0.v"
+`endif
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_signed 0
+`define c_unsigned 1
+`define c_pin 2
+`define c_up 0
+`define c_down 1
+`define c_updown 2
+`define allXs {C_WIDTH{1'bx}}
+
+module C_COUNTER_BINARY_V3_0 (CLK, UP, CE, LOAD, L, IV, ACLR, ASET, AINIT, SCLR, SSET, SINIT, THRESH0, Q_THRESH0, THRESH1, Q_THRESH1, Q);
+
+ parameter C_AINIT_VAL = "0";
+ parameter C_COUNT_BY = "";
+ parameter C_COUNT_MODE = `c_up;
+ parameter C_COUNT_TO = "1111111111111111";
+ parameter C_ENABLE_RLOCS = 1;
+ parameter C_HAS_ACLR = 0;
+ parameter C_HAS_AINIT = 0;
+ parameter C_HAS_ASET = 0;
+ parameter C_HAS_CE = 0;
+ parameter C_HAS_IV = 0;
+ parameter C_HAS_L = 0;
+ parameter C_HAS_LOAD = 0;
+ parameter C_HAS_Q_THRESH0 = 0;
+ parameter C_HAS_Q_THRESH1 = 0;
+ parameter C_HAS_SCLR = 0;
+ parameter C_HAS_SINIT = 0;
+ parameter C_HAS_SSET = 0;
+ parameter C_HAS_THRESH0 = 0;
+ parameter C_HAS_THRESH1 = 0;
+ parameter C_HAS_UP = 0;
+ parameter C_LOAD_ENABLE = `c_no_override;
+ parameter C_LOAD_LOW = 0;
+ parameter C_PIPE_STAGES = 0;
+ parameter C_RESTRICT_COUNT = 0;
+ parameter C_SINIT_VAL = "0";
+ parameter C_SYNC_ENABLE = `c_override;
+ parameter C_SYNC_PRIORITY = `c_clear;
+ parameter C_THRESH0_VALUE = "1111111111111111";
+ parameter C_THRESH1_VALUE = "1111111111111111";
+ parameter C_THRESH_EARLY = 1;
+ parameter C_WIDTH = 16;
+
+ parameter C_OUT_TYPE = `c_signed;
+ parameter adder_HAS_SCLR = ((C_RESTRICT_COUNT == 1) || (C_HAS_SCLR == 1) ? 1 : 0);
+
+ parameter iaxero = {62{"0"}};
+ parameter iextendC_THRESH0_VALUE = {iaxero,C_THRESH0_VALUE};
+ parameter iextendC_THRESH1_VALUE = {iaxero,C_THRESH1_VALUE};
+ parameter iazero = {64{"0"}};
+ parameter intC_HAS_SCLR0 = (iextendC_THRESH0_VALUE[0] == "0" ? (iextendC_THRESH0_VALUE[1] == "0" ?
+ (iextendC_THRESH0_VALUE[2] == "0" ? (iextendC_THRESH0_VALUE[3] == "0" ?
+ (iextendC_THRESH0_VALUE[4] == "0" ? (iextendC_THRESH0_VALUE[5] == "0" ?
+ (iextendC_THRESH0_VALUE[6] == "0" ? (iextendC_THRESH0_VALUE[7] == "0" ?
+ (iextendC_THRESH0_VALUE[8] == "0" ? (iextendC_THRESH0_VALUE[9] == "0" ?
+ (iextendC_THRESH0_VALUE[10] == "0" ? (iextendC_THRESH0_VALUE[11] == "0" ?
+ (iextendC_THRESH0_VALUE[12] == "0" ? (iextendC_THRESH0_VALUE[13] == "0" ?
+ (iextendC_THRESH0_VALUE[14] == "0" ? (iextendC_THRESH0_VALUE[15] == "0" ?
+ (iextendC_THRESH0_VALUE[16] == "0" ? (iextendC_THRESH0_VALUE[17] == "0" ?
+ (iextendC_THRESH0_VALUE[18] == "0" ? (iextendC_THRESH0_VALUE[19] == "0" ?
+ (iextendC_THRESH0_VALUE[20] == "0" ? (iextendC_THRESH0_VALUE[21] == "0" ?
+ (iextendC_THRESH0_VALUE[22] == "0" ? (iextendC_THRESH0_VALUE[23] == "0" ?
+ (iextendC_THRESH0_VALUE[24] == "0" ? (iextendC_THRESH0_VALUE[25] == "0" ?
+ (iextendC_THRESH0_VALUE[26] == "0" ? (iextendC_THRESH0_VALUE[27] == "0" ?
+ (iextendC_THRESH0_VALUE[28] == "0" ? (iextendC_THRESH0_VALUE[29] == "0" ?
+ (iextendC_THRESH0_VALUE[30] == "0" ? (iextendC_THRESH0_VALUE[31] == "0" ?
+ (iextendC_THRESH0_VALUE[32] == "0" ? (iextendC_THRESH0_VALUE[33] == "0" ?
+ (iextendC_THRESH0_VALUE[34] == "0" ? (iextendC_THRESH0_VALUE[35] == "0" ?
+ (iextendC_THRESH0_VALUE[36] == "0" ? (iextendC_THRESH0_VALUE[37] == "0" ?
+ (iextendC_THRESH0_VALUE[38] == "0" ? (iextendC_THRESH0_VALUE[39] == "0" ?
+ (iextendC_THRESH0_VALUE[40] == "0" ? (iextendC_THRESH0_VALUE[41] == "0" ?
+ (iextendC_THRESH0_VALUE[42] == "0" ? (iextendC_THRESH0_VALUE[43] == "0" ?
+ (iextendC_THRESH0_VALUE[44] == "0" ? (iextendC_THRESH0_VALUE[45] == "0" ?
+ (iextendC_THRESH0_VALUE[46] == "0" ? (iextendC_THRESH0_VALUE[47] == "0" ?
+ (iextendC_THRESH0_VALUE[48] == "0" ? (iextendC_THRESH0_VALUE[49] == "0" ?
+ (iextendC_THRESH0_VALUE[50] == "0" ? (iextendC_THRESH0_VALUE[51] == "0" ?
+ (iextendC_THRESH0_VALUE[52] == "0" ? (iextendC_THRESH0_VALUE[53] == "0" ?
+ (iextendC_THRESH0_VALUE[54] == "0" ? (iextendC_THRESH0_VALUE[55] == "0" ?
+ (iextendC_THRESH0_VALUE[56] == "0" ? (iextendC_THRESH0_VALUE[57] == "0" ?
+ (iextendC_THRESH0_VALUE[58] == "0" ? (iextendC_THRESH0_VALUE[59] == "0" ?
+ (iextendC_THRESH0_VALUE[60] == "0" ? (iextendC_THRESH0_VALUE[61] == "0" ?
+ (iextendC_THRESH0_VALUE[62] == "0" ? (iextendC_THRESH0_VALUE[63] == "0" ? 0
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0));
+ parameter intC_HAS_SCLR1 = (iextendC_THRESH1_VALUE[0] == "0" ? (iextendC_THRESH1_VALUE[1] == "0" ?
+ (iextendC_THRESH1_VALUE[2] == "0" ? (iextendC_THRESH1_VALUE[3] == "0" ?
+ (iextendC_THRESH1_VALUE[4] == "0" ? (iextendC_THRESH1_VALUE[5] == "0" ?
+ (iextendC_THRESH1_VALUE[6] == "0" ? (iextendC_THRESH1_VALUE[7] == "0" ?
+ (iextendC_THRESH1_VALUE[8] == "0" ? (iextendC_THRESH1_VALUE[9] == "0" ?
+ (iextendC_THRESH1_VALUE[10] == "0" ? (iextendC_THRESH1_VALUE[11] == "0" ?
+ (iextendC_THRESH1_VALUE[12] == "0" ? (iextendC_THRESH1_VALUE[13] == "0" ?
+ (iextendC_THRESH1_VALUE[14] == "0" ? (iextendC_THRESH1_VALUE[15] == "0" ?
+ (iextendC_THRESH1_VALUE[16] == "0" ? (iextendC_THRESH1_VALUE[17] == "0" ?
+ (iextendC_THRESH1_VALUE[18] == "0" ? (iextendC_THRESH1_VALUE[19] == "0" ?
+ (iextendC_THRESH1_VALUE[20] == "0" ? (iextendC_THRESH1_VALUE[21] == "0" ?
+ (iextendC_THRESH1_VALUE[22] == "0" ? (iextendC_THRESH1_VALUE[23] == "0" ?
+ (iextendC_THRESH1_VALUE[24] == "0" ? (iextendC_THRESH1_VALUE[25] == "0" ?
+ (iextendC_THRESH1_VALUE[26] == "0" ? (iextendC_THRESH1_VALUE[27] == "0" ?
+ (iextendC_THRESH1_VALUE[28] == "0" ? (iextendC_THRESH1_VALUE[29] == "0" ?
+ (iextendC_THRESH1_VALUE[30] == "0" ? (iextendC_THRESH1_VALUE[31] == "0" ?
+ (iextendC_THRESH1_VALUE[32] == "0" ? (iextendC_THRESH1_VALUE[33] == "0" ?
+ (iextendC_THRESH1_VALUE[34] == "0" ? (iextendC_THRESH1_VALUE[35] == "0" ?
+ (iextendC_THRESH1_VALUE[36] == "0" ? (iextendC_THRESH1_VALUE[37] == "0" ?
+ (iextendC_THRESH1_VALUE[38] == "0" ? (iextendC_THRESH1_VALUE[39] == "0" ?
+ (iextendC_THRESH1_VALUE[40] == "0" ? (iextendC_THRESH1_VALUE[41] == "0" ?
+ (iextendC_THRESH1_VALUE[42] == "0" ? (iextendC_THRESH1_VALUE[43] == "0" ?
+ (iextendC_THRESH1_VALUE[44] == "0" ? (iextendC_THRESH1_VALUE[45] == "0" ?
+ (iextendC_THRESH1_VALUE[46] == "0" ? (iextendC_THRESH1_VALUE[47] == "0" ?
+ (iextendC_THRESH1_VALUE[48] == "0" ? (iextendC_THRESH1_VALUE[49] == "0" ?
+ (iextendC_THRESH1_VALUE[50] == "0" ? (iextendC_THRESH1_VALUE[51] == "0" ?
+ (iextendC_THRESH1_VALUE[52] == "0" ? (iextendC_THRESH1_VALUE[53] == "0" ?
+ (iextendC_THRESH1_VALUE[54] == "0" ? (iextendC_THRESH1_VALUE[55] == "0" ?
+ (iextendC_THRESH1_VALUE[56] == "0" ? (iextendC_THRESH1_VALUE[57] == "0" ?
+ (iextendC_THRESH1_VALUE[58] == "0" ? (iextendC_THRESH1_VALUE[59] == "0" ?
+ (iextendC_THRESH1_VALUE[60] == "0" ? (iextendC_THRESH1_VALUE[61] == "0" ?
+ (iextendC_THRESH1_VALUE[62] == "0" ? (iextendC_THRESH1_VALUE[63] == "0" ? 0
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+ : (C_HAS_SCLR == 1 ? 1 : 0));
+
+
+
+
+
+ input CLK;
+ input UP;
+ input CE;
+ input LOAD;
+ input [C_WIDTH-1 : 0] L;
+ input [C_WIDTH-1 : 0] IV;
+ input ACLR;
+ input ASET;
+ input AINIT;
+ input SCLR;
+ input SSET;
+ input SINIT;
+ output THRESH0;
+ output Q_THRESH0;
+ output THRESH1;
+ output Q_THRESH1;
+ output [C_WIDTH-1 : 0] Q;
+
+ // Internal values to drive signals when input is missing
+ wire intUP;
+ wire intUPbar = ~intUP;
+ wire intCE;
+ wire intLOAD;
+ wire [C_WIDTH-1 : 0] intL;
+ wire [C_WIDTH-1 : 0] intB;
+ wire [C_WIDTH-1 : 0] all_zeros = {C_WIDTH{1'b0}};
+ wire intSCLR;
+ wire intCount_to_reached;
+ reg intTHRESH0;
+ reg intTHRESH1;
+ wire intQ_THRESH0;
+ wire intQ_THRESH1;
+ wire [C_WIDTH-1 : 0] intFBq;
+ wire [C_WIDTH-1 : 0] intFBs;
+ wire [C_WIDTH-1 : 0] intQ = intFBq;
+ wire [C_WIDTH-1 : 0] intFBq_or_zero;
+ wire [C_WIDTH-1 : 0] intFBs_or_q;
+ wire [C_WIDTH-1 : 0] intCount_by = to_bits(C_COUNT_BY);
+ wire [C_WIDTH-1 : 0] intB_or_load;
+ wire [C_WIDTH-1 : 0] tmpintB_or_load;
+
+ wire Q_THRESH0 = (C_HAS_Q_THRESH0 == 1 ? intQ_THRESH0 : 1'bx);
+ wire Q_THRESH1 = (C_HAS_Q_THRESH1 == 1 ? intQ_THRESH1 : 1'bx);
+ wire [C_WIDTH-1 : 0] Q = intQ;
+
+ wire [C_WIDTH-1 : 0] intXLOADMUX;
+ wire [C_WIDTH-1 : 0] intSINITVAL = to_bits(C_SINIT_VAL);
+ wire [C_WIDTH-1 : 0] intXL;
+ wire intXLOAD;
+ wire intXXLOAD;
+ wire #5 intSCLR_RESET = (intSCLR || (intCount_to_reached && intCE && C_RESTRICT_COUNT == 1)) && ~intXXLOAD;
+
+ // Sort out default values for missing ports
+
+ assign intUP = (C_HAS_UP == 1 ? UP : (C_COUNT_MODE == `c_up ? 1'b1 : 1'b0));
+ assign intCE = defval(CE, C_HAS_CE, 1);
+ assign intL = (C_HAS_L == 1 ? L : {C_WIDTH{1'b0}});
+ assign intB = (C_HAS_IV == 1 ? IV : intCount_by);
+ assign intXL = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? intXLOADMUX : intSINITVAL) : intL) : intL);
+ assign intLOAD = (C_LOAD_LOW == 1 ? ~LOAD : LOAD );
+ assign intXLOAD = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? (C_HAS_CE == 1 ? (C_SYNC_ENABLE != C_LOAD_ENABLE ? (C_SYNC_ENABLE == 0 ? (C_LOAD_LOW == 1 ? (((~SINIT) && (~CE)) || ((~SINIT) && LOAD && CE)) : (SINIT || (LOAD && CE))) : (C_LOAD_LOW == 1 ? ((LOAD && (~CE)) || ((~SINIT) && LOAD && CE)) : (LOAD || (SINIT && CE)))) : (C_LOAD_LOW == 1 ? LOAD && ~SINIT : LOAD || SINIT)) : (C_LOAD_LOW == 1 ? LOAD && ~SINIT : LOAD || SINIT)) : (C_LOAD_LOW ? ~SINIT : SINIT)) : (C_HAS_LOAD == 1 ? LOAD : 1'b0)) : (C_HAS_LOAD == 1 ? LOAD : 1'b0));
+ assign intXXLOAD = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? (C_LOAD_LOW == 1 ? ~intXLOAD : intXLOAD) : (C_LOAD_LOW == 1 ? ~intXLOAD : intXLOAD)) : (C_HAS_LOAD == 1 ? intLOAD : 1'b0)) : (C_HAS_LOAD == 1 ? intLOAD : 1'b0));
+ assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);
+ assign intB_or_load = (C_HAS_LOAD == 1 ? tmpintB_or_load : (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? tmpintB_or_load : intB) : intB));
+ assign intFBs_or_q = (C_THRESH_EARLY == 1 ? intFBs : intFBq);
+
+
+ // The addsub on which this is based...
+
+ C_ADDSUB_V3_0 #(C_COUNT_MODE,
+ C_AINIT_VAL,
+ C_OUT_TYPE,
+ C_WIDTH,
+ (((~(C_HAS_LOAD===1)) || C_LOAD_ENABLE) && (C_SYNC_ENABLE || ~(C_RESTRICT_COUNT && C_HAS_SINIT))),
+ C_LOAD_LOW, // DLUNN CHANGED FROM 0,
+ 0,
+ C_OUT_TYPE,
+ "",
+ C_WIDTH,
+ C_ENABLE_RLOCS,
+ C_HAS_ACLR,
+ C_HAS_UP,
+ C_HAS_AINIT,
+ C_HAS_ASET,
+ 0,
+ C_HAS_LOAD || (C_RESTRICT_COUNT == 1 && C_HAS_SINIT == 1), // DLUNN CHANGED FROM 1,
+ 0,
+ 0,
+ 0,
+ C_HAS_CE,
+ 1,
+ 0,
+ 0,
+ 1,
+ 0,
+ 0,
+ 0,
+ 1,
+ adder_HAS_SCLR,
+ C_HAS_SINIT && ~(C_RESTRICT_COUNT === 1),
+ C_HAS_SSET,
+ C_WIDTH-1,
+ 1,
+ 0,
+ C_WIDTH,
+ C_PIPE_STAGES,
+ C_SINIT_VAL,
+ C_SYNC_ENABLE,
+ C_SYNC_PRIORITY)
+ the_addsub (.A(intFBq_or_zero), .B(intB_or_load), .CLK(CLK), .ADD(intUP),
+ .CE(CE), .C_IN(intUPbar), .ACLR(ACLR), .ASET(ASET),
+ .AINIT(AINIT), .SCLR(intSCLR_RESET), .SSET(SSET),
+ .SINIT(SINIT), .BYPASS(intXLOAD), .S(intFBs), .Q(intFBq));
+
+ // The Restrict Count/Sinit LOAD mux
+
+ C_MUX_BUS_V3_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 2,
+ 0, 0, 1, "", 0, 0, C_WIDTH)
+ mxRCSL(.MA(intSINITVAL), .MB(intL), .S(intLOAD), .O(intXLOADMUX));
+
+ // The feedback mux
+
+ C_MUX_BUS_V3_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 2,
+ 0, 0, 1, "", 0, 0, C_WIDTH)
+ mxfb(.MA(intFBq), .MB(all_zeros), .S(intXXLOAD), .O(intFBq_or_zero));
+
+ // The LOAD mux
+
+ C_MUX_BUS_V3_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 2,
+ 0, 0, 1, "", 0, 0, C_WIDTH)
+ mx1(.MA(intB), .MB(intXL), .S(intXXLOAD), .O(tmpintB_or_load));
+
+ // The Threshhold comparators
+
+ C_COMPARE_V3_0 #("0", 1, C_THRESH0_VALUE, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0,
+ C_HAS_THRESH0, 0, 0, 0, 0, 0, C_HAS_CE, C_HAS_Q_THRESH0,
+ 0, 0, 0, 0, 0, intC_HAS_SCLR0, 0, 0, 0, 0, C_WIDTH)
+ th0(.A(intFBs_or_q), .CLK(CLK), .CE(CE), .ACLR(ACLR), .SCLR(intSCLR_RESET), .A_EQ_B(THRESH0), .QA_EQ_B(Q_THRESH0));
+
+ C_COMPARE_V3_0 #("0", 1, C_THRESH1_VALUE, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0,
+ C_HAS_THRESH1, 0, 0, 0, 0, 0, C_HAS_CE, C_HAS_Q_THRESH1,
+ 0, 0, 0, 0, 0, intC_HAS_SCLR1, 0, 0, 0, 0, C_WIDTH)
+ th1(.A(intFBs_or_q), .CLK(CLK), .CE(CE), .ACLR(ACLR), .SCLR(intSCLR_RESET), .A_EQ_B(THRESH1), .QA_EQ_B(Q_THRESH1));
+
+ C_COMPARE_V3_0 #("0", 1, C_COUNT_TO, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0,
+ 0, 0, 0, 0, 0, 0, C_HAS_CE, 1,
+ 0, 0, 0, 0, 0, C_HAS_SCLR, 0, 0, 0, 0, C_WIDTH)
+ th_to(.A(intFBs), .CLK(CLK), .CE(CE), .ACLR(ACLR), .SCLR(SCLR), .QA_EQ_B(intCount_to_reached));
+
+ initial
+ begin
+
+ #1;
+
+
+ end
+
+ function defval;
+ input i;
+ input hassig;
+ input val;
+ begin
+ if(hassig == 1)
+ defval = i;
+ else
+ defval = val;
+ end
+ endfunction
+
+ function [C_WIDTH - 1 : 0] to_bits;
+ input [C_WIDTH*8 : 1] instring;
+ integer i;
+ begin
+ for(i = C_WIDTH; i > 0; i = i - 1)
+ begin // Is this character a '0'? (ASCII = 48 = 00110000)
+ if(instring[(i*8)] == 0 &&
+ instring[(i*8)-1] == 0 &&
+ instring[(i*8)-2] == 1 &&
+ instring[(i*8)-3] == 1 &&
+ instring[(i*8)-4] == 0 &&
+ instring[(i*8)-5] == 0 &&
+ instring[(i*8)-6] == 0 &&
+ instring[(i*8)-7] == 0)
+ to_bits[i-1] = 0;
+ // Or is it a '1'?
+ else if(instring[(i*8)] == 0 &&
+ instring[(i*8)-1] == 0 &&
+ instring[(i*8)-2] == 1 &&
+ instring[(i*8)-3] == 1 &&
+ instring[(i*8)-4] == 0 &&
+ instring[(i*8)-5] == 0 &&
+ instring[(i*8)-6] == 0 &&
+ instring[(i*8)-7] == 1)
+
+ to_bits[i-1] = 1;
+ // Or is it a ' '? (a null char - in which case insert a '0')
+ else if(instring[(i*8)] == 0 &&
+ instring[(i*8)-1] == 0 &&
+ instring[(i*8)-2] == 0 &&
+ instring[(i*8)-3] == 0 &&
+ instring[(i*8)-4] == 0 &&
+ instring[(i*8)-5] == 0 &&
+ instring[(i*8)-6] == 0 &&
+ instring[(i*8)-7] == 0)
+ to_bits[i-1] = 0;
+ else
+ begin
+ $display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring);
+ $finish;
+ end
+ end
+ end
+ endfunction
+
+
+
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_signed
+`undef c_unsigned
+`undef c_pin
+`undef c_up
+`undef c_down
+`undef c_updown
+`undef allXs
+
+`endif
trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_COUNTER_BINARY_V3_0.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_COMPARE_V3_0.v
===================================================================
--- trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_COMPARE_V3_0.v (nonexistent)
+++ trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_COMPARE_V3_0.v (revision 784)
@@ -0,0 +1,1227 @@
+/* $Id: C_COMPARE_V3_0.v,v 1.1 2002-03-28 20:50:04 lampret Exp $
+--
+-- Filename - C_COMPARE_V3_0.v
+-- Author - Xilinx
+-- Creation - 28 Jan 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_COMPARE_V3_0 module
+*/
+
+`ifdef C_COMPARE_V3_0_DEF
+`else
+`define C_COMPARE_V3_0_DEF
+
+`ifdef C_REG_FD_V3_0_DEF
+`else
+`include "XilinxCoreLib/C_REG_FD_V3_0.v"
+`endif
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_signed 0
+`define c_unsigned 1
+
+module C_COMPARE_V3_0 (A, B, CLK, CE, ACLR, ASET, SCLR, SSET,
+ A_EQ_B, A_NE_B, A_LT_B, A_GT_B, A_LE_B, A_GE_B,
+ QA_EQ_B, QA_NE_B, QA_LT_B, QA_GT_B, QA_LE_B, QA_GE_B);
+
+ parameter C_AINIT_VAL = "";
+ parameter C_B_CONSTANT = 0;
+ parameter C_B_VALUE = "";
+ parameter C_DATA_TYPE = `c_unsigned;
+ parameter C_ENABLE_RLOCS = 1;
+ parameter C_HAS_ACLR = 0;
+ parameter C_HAS_ASET = 0;
+ parameter C_HAS_A_EQ_B = 1;
+ parameter C_HAS_A_GE_B = 0;
+ parameter C_HAS_A_GT_B = 0;
+ parameter C_HAS_A_LE_B = 0;
+ parameter C_HAS_A_LT_B = 0;
+ parameter C_HAS_A_NE_B = 0;
+ parameter C_HAS_CE = 0;
+ parameter C_HAS_QA_EQ_B = 0;
+ parameter C_HAS_QA_GE_B = 0;
+ parameter C_HAS_QA_GT_B = 0;
+ parameter C_HAS_QA_LE_B = 0;
+ parameter C_HAS_QA_LT_B = 0;
+ parameter C_HAS_QA_NE_B = 0;
+ parameter C_HAS_SCLR = 0;
+ parameter C_HAS_SSET = 0;
+ parameter C_PIPE_STAGES = 1;
+ parameter C_SYNC_ENABLE = `c_override;
+ parameter C_SYNC_PRIORITY = `c_clear;
+ parameter C_WIDTH = 16;
+
+
+ input [C_WIDTH-1 : 0] A;
+ input [C_WIDTH-1 : 0] B;
+ input CLK;
+ input CE;
+ input ACLR;
+ input ASET;
+ input SCLR;
+ input SSET;
+ output A_EQ_B;
+ output A_NE_B;
+ output A_LT_B;
+ output A_GT_B;
+ output A_LE_B;
+ output A_GE_B;
+ output QA_EQ_B;
+ output QA_NE_B;
+ output QA_LT_B;
+ output QA_GT_B;
+ output QA_LE_B;
+ output QA_GE_B;
+
+ // Internal values to drive signals when input is missing
+ reg [C_WIDTH-1 : 0] intB;
+ reg intCE;
+ reg intACLR;
+ reg intASET;
+ reg intSCLR;
+ reg intSSET;
+ reg intA_EQ_B;
+ reg intA_NE_B;
+ reg intA_LT_B;
+ reg intA_GT_B;
+ reg intA_LE_B;
+ reg intA_GE_B;
+ wire intQA_EQ_B;
+ wire intQA_NE_B;
+ wire intQA_LT_B;
+ wire intQA_GT_B;
+ wire intQA_LE_B;
+ wire intQA_GE_B;
+ reg lastCLK;
+
+ reg [C_PIPE_STAGES+2 : 0] intQA_EQ_Bpipe;
+ reg intQA_EQ_Bpipeend;
+ reg [C_PIPE_STAGES+2 : 0] intQA_NE_Bpipe;
+ reg intQA_NE_Bpipeend;
+ reg [C_PIPE_STAGES+2 : 0] intQA_LT_Bpipe;
+ reg intQA_LT_Bpipeend;
+ reg [C_PIPE_STAGES+2 : 0] intQA_GT_Bpipe;
+ reg intQA_GT_Bpipeend;
+ reg [C_PIPE_STAGES+2 : 0] intQA_LE_Bpipe;
+ reg intQA_LE_Bpipeend;
+ reg [C_PIPE_STAGES+2 : 0] intQA_GE_Bpipe;
+ reg intQA_GE_Bpipeend;
+
+ wire AINIT;
+ wire SINIT;
+
+ wire A_EQ_B = (C_HAS_A_EQ_B == 1 ? intA_EQ_B : 1'bx);
+ wire A_NE_B = (C_HAS_A_NE_B == 1 ? intA_NE_B : 1'bx);
+ wire A_LT_B = (C_HAS_A_LT_B == 1 ? intA_LT_B : 1'bx);
+ wire A_GT_B = (C_HAS_A_GT_B == 1 ? intA_GT_B : 1'bx);
+ wire A_LE_B = (C_HAS_A_LE_B == 1 ? intA_LE_B : 1'bx);
+ wire A_GE_B = (C_HAS_A_GE_B == 1 ? intA_GE_B : 1'bx);
+ wire QA_EQ_B = (C_HAS_QA_EQ_B == 1 ? intQA_EQ_B : 1'bx);
+ wire QA_NE_B = (C_HAS_QA_NE_B == 1 ? intQA_NE_B : 1'bx);
+ wire QA_LT_B = (C_HAS_QA_LT_B == 1 ? intQA_LT_B : 1'bx);
+ wire QA_GT_B = (C_HAS_QA_GT_B == 1 ? intQA_GT_B : 1'bx);
+ wire QA_LE_B = (C_HAS_QA_LE_B == 1 ? intQA_LE_B : 1'bx);
+ wire QA_GE_B = (C_HAS_QA_GE_B == 1 ? intQA_GE_B : 1'bx);
+
+ integer pipe, notdone, i;
+
+ reg aeqb, aneb, altb, agtb, aleb, ageb;
+ reg [C_WIDTH-1:0] a_low;
+ reg [C_WIDTH-1:0] a_high;
+ reg [C_WIDTH-1:0] b_low;
+ reg [C_WIDTH-1:0] b_high;
+
+ // Instance the required output regs
+ C_REG_FD_V3_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET,
+ C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET,
+ "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+ regaeqb (.D(intQA_EQ_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+ .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+ .Q(intQA_EQ_B));
+
+ C_REG_FD_V3_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET,
+ C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET,
+ "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+ reganeb (.D(intQA_NE_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+ .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+ .Q(intQA_NE_B));
+
+ C_REG_FD_V3_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET,
+ C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET,
+ "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+ regaltb (.D(intQA_LT_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+ .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+ .Q(intQA_LT_B));
+
+ C_REG_FD_V3_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET,
+ C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET,
+ "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+ regagtb (.D(intQA_GT_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+ .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+ .Q(intQA_GT_B));
+
+ C_REG_FD_V3_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET,
+ C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET,
+ "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+ regaleb (.D(intQA_LE_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+ .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+ .Q(intQA_LE_B));
+
+ C_REG_FD_V3_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET,
+ C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET,
+ "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+ regageb (.D(intQA_GE_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+ .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+ .Q(intQA_GE_B));
+
+ initial
+ begin
+ #1;
+ intCE = defval(CE, C_HAS_CE, 1);
+ intB = defvecval(B, (C_B_CONSTANT == 1) ? 0 : 1, to_bits(C_B_VALUE));
+
+ intQA_EQ_Bpipe = 'b0;
+ intQA_NE_Bpipe = 'b0;
+ intQA_LT_Bpipe = 'b0;
+ intQA_GT_Bpipe = 'b0;
+ intQA_LE_Bpipe = 'b0;
+ intQA_GE_Bpipe = 'b0;
+
+ if(is_X(A) == 1 || is_X(intB) == 1)
+ begin
+ notdone = 1;
+ if((is_X(A) && A === {C_WIDTH{1'bx}}) && (is_X(intB) && intB === {C_WIDTH{1'bx}}))
+ begin
+ aeqb <= 1'bx;
+ aneb <= 1'bx;
+ altb <= 1'bx;
+ agtb <= 1'bx;
+ aleb <= 1'bx;
+ ageb <= 1'bx;
+ notdone = 0;
+ end
+ else if(C_DATA_TYPE == `c_signed)
+ begin
+/* if(A[C_WIDTH-1] === 1'bx && intB[C_WIDTH-1] === 1'bx)
+ // Don't know the sign of EITHER data => ALL X's
+ begin
+ aeqb <= 1'bx;
+ aneb <= 1'bx;
+ altb <= 1'bx;
+ agtb <= 1'bx;
+ aleb <= 1'bx;
+ ageb <= 1'bx;
+ notdone = 0;
+ end
+ else if (A[C_WIDTH-1] !== 1'bx && intB[C_WIDTH-1] !== 1'bx)
+*/ if (A[C_WIDTH-1] !== 1'bx && intB[C_WIDTH-1] !== 1'bx)
+ begin
+ // The sign bits are both known
+ if (A[C_WIDTH-1] !== intB[C_WIDTH-1])
+ begin
+ // different signs!
+ if (A[C_WIDTH-1] === 1'b1)
+ begin
+ // A is negative and B is positive
+ aeqb <= 0;
+ aneb <= 1;
+ altb <= 1;
+ agtb <= 0;
+ aleb <= 1;
+ ageb <= 0;
+ notdone = 0;
+ end
+ else // A is +ve and B is -ve
+ begin
+ aeqb <= 0;
+ aneb <= 1;
+ altb <= 0;
+ agtb <= 1;
+ aleb <= 0;
+ ageb <= 1;
+ notdone = 0;
+ end
+ end
+ end
+ end
+ if (notdone == 1) // check further
+ begin
+ // Make copies of A and B with all X's substituted with 0's and 1's
+ a_low = A;
+ a_high = A;
+ b_low = intB;
+ b_high = intB;
+ for (i=C_WIDTH-2; i >= 0; i = i - 1)
+ begin
+ if (a_low[i] === 1'bx)
+ begin
+ a_low[i] = 0;
+ a_high[i] = 1;
+ end
+ if (b_low[i] === 1'bx)
+ begin
+ b_low[i] = 0;
+ b_high[i] = 1;
+ end
+ end
+ // we now (almost - need to check possible sign bits) have worst-case values which must agree on the comparison result
+ // if that result is not to be unknown...
+ if (C_DATA_TYPE == `c_signed)
+ begin
+ // Set the sign bits of the range values to 0 since
+ // the sign of the values will be treated separately
+ a_low[C_WIDTH-1] = 0;
+ a_high[C_WIDTH-1] = 0;
+ b_low[C_WIDTH-1] = 0;
+ b_high[C_WIDTH-1] = 0;
+
+ if((A[C_WIDTH-1] === 1'b1 && intB[C_WIDTH-1] === 1'bx)
+ || (intB[C_WIDTH-1] === 1'b0 && A[C_WIDTH-1] === 1'bx))
+ begin // Sign of A is -ve and sign of B is unknown OR
+ // sign of B is +ve and sign of A is unknown
+ // Is A always < B?
+ if (a_high < b_low)
+ begin
+ // A is definitely < than B
+ aeqb <= 0;
+ aneb <= 1;
+ altb <= 1;
+ agtb <= 0;
+ aleb <= 1;
+ ageb <= 0;
+ end
+ else if (a_high == b_low)
+ begin
+ // A is <= than B
+ aeqb <= 1'bx;
+ aneb <= 1'bx;
+ altb <= 1'bx;
+ agtb <= 0;
+ aleb <= 1;
+ ageb <= 1'bx;
+ end
+ else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}}))
+ begin // Definitely not equal!
+ aeqb <= 1'b0;
+ aneb <= 1'b1;
+ altb <= 1'bx;
+ agtb <= 1'bx;
+ aleb <= 1'bx;
+ ageb <= 1'bx;
+ end
+ else // There is > 1 overlap between the ranges so all X's
+ begin
+ aeqb <= 1'bx;
+ aneb <= 1'bx;
+ altb <= 1'bx;
+ agtb <= 1'bx;
+ aleb <= 1'bx;
+ ageb <= 1'bx;
+ end
+ end
+ else if((A[C_WIDTH-1] === 1'b0 && intB[C_WIDTH-1] === 1'bx)
+ || (intB[C_WIDTH-1] === 1'b1 && A[C_WIDTH-1] === 1'bx))
+ begin // Sign of A is +ve and sign of B is unknown OR
+ // sign of B is -ve and sign of A is unknown
+ // Is B always < A?
+ if (b_high < a_low)
+ begin
+ // B is definitely < than A
+ aeqb <= 0;
+ aneb <= 1;
+ altb <= 0;
+ agtb <= 1;
+ aleb <= 0;
+ ageb <= 1;
+ end
+ else if (b_high == a_low)
+ begin
+ // B is <= than A
+ aeqb <= 1'bx;
+ aneb <= 1'bx;
+ altb <= 0;
+ agtb <= 1'bx;
+ aleb <= 1'bx;
+ ageb <= 1;
+ end
+ else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}}))
+ begin // Definitely not equal!
+ aeqb <= 1'b0;
+ aneb <= 1'b1;
+ altb <= 1'bx;
+ agtb <= 1'bx;
+ aleb <= 1'bx;
+ ageb <= 1'bx;
+ end
+ else // There is > 1 overlap between the ranges so all X's
+ begin
+ aeqb <= 1'bx;
+ aneb <= 1'bx;
+ altb <= 1'bx;
+ agtb <= 1'bx;
+ aleb <= 1'bx;
+ ageb <= 1'bx;
+ end
+ end
+ else // Sign bits on A and B are identical and both are known
+ begin
+ if (a_high < b_low)
+ begin
+ // A is definitely < than B
+ aeqb <= 0;
+ aneb <= 1;
+ altb <= 1;
+ agtb <= 0;
+ aleb <= 1;
+ ageb <= 0;
+ end
+ else if (a_low > b_high)
+ begin
+ // A is definitely > than B
+ aeqb <= 0;
+ aneb <= 1;
+ altb <= 0;
+ agtb <= 1;
+ aleb <= 0;
+ ageb <= 1;
+ end
+ else if (a_high == b_low)
+ begin
+ // A is <= than B
+ aeqb <= 1'bx;
+ aneb <= 1'bx;
+ altb <= 1'bx;
+ agtb <= 0;
+ aleb <= 1;
+ ageb <= 1'bx;
+ end
+ else if (a_low == b_high)
+ begin
+ // A is >= than B
+ aeqb <= 1'bx;
+ aneb <= 1'bx;
+ altb <= 0;
+ agtb <= 1'bx;
+ aleb <= 1'bx;
+ ageb <= 1;
+ end
+ else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}}))
+ begin // Definitely not equal!
+ aeqb <= 1'b0;
+ aneb <= 1'b1;
+ altb <= 1'bx;
+ agtb <= 1'bx;
+ aleb <= 1'bx;
+ ageb <= 1'bx;
+ end
+ else // There is > 1 overlap between the ranges so all X's
+ begin
+ aeqb <= 1'bx;
+ aneb <= 1'bx;
+ altb <= 1'bx;
+ agtb <= 1'bx;
+ aleb <= 1'bx;
+ ageb <= 1'bx;
+ end
+ end
+ end
+ else // unsigned data
+ begin
+ if (a_low[C_WIDTH-1] === 1'bx)
+ begin
+ a_low[C_WIDTH-1] = 0;
+ a_high[C_WIDTH-1] = 1;
+ end
+ if (b_low[C_WIDTH-1] === 1'bx)
+ begin
+ b_low[C_WIDTH-1] = 0;
+ b_high[C_WIDTH-1] = 1;
+ end
+ if (a_high < b_low)
+ begin
+ // A is definitely < than B
+ aeqb <= 0;
+ aneb <= 1;
+ altb <= 1;
+ agtb <= 0;
+ aleb <= 1;
+ ageb <= 0;
+ end
+ else if (a_low > b_high)
+ begin
+ // A is definitely > than B
+ aeqb <= 0;
+ aneb <= 1;
+ altb <= 0;
+ agtb <= 1;
+ aleb <= 0;
+ ageb <= 1;
+ end
+ else if (a_high == b_low)
+ begin
+ // A is <= B
+ aeqb <= 1'bx;
+ aneb <= 1'bx;
+ altb <= 1'bx;
+ agtb <= 0;
+ aleb <= 1;
+ ageb <= 1'bx;
+ end
+ else if (a_low == b_high)
+ begin
+ // A is >= B
+ aeqb <= 1'bx;
+ aneb <= 1'bx;
+ altb <= 0;
+ agtb <= 1'bx;
+ aleb <= 1'bx;
+ ageb <= 1;
+ end
+ else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}}))
+ begin // Definitely not equal!
+ aeqb <= 1'b0;
+ aneb <= 1'b1;
+ altb <= 1'bx;
+ agtb <= 1'bx;
+ aleb <= 1'bx;
+ ageb <= 1'bx;
+ end
+ else // There is > 1 overlap between the ranges so all X's
+ begin
+ aeqb <= 1'bx;
+ aneb <= 1'bx;
+ altb <= 1'bx;
+ agtb <= 1'bx;
+ aleb <= 1'bx;
+ ageb <= 1'bx;
+ end
+ end
+ end
+ end
+ else if (C_DATA_TYPE == `c_signed)
+ begin
+ // Signed data so examine MSB and rest separately in some cases
+ if(A == intB)
+ begin
+ aeqb <= 1;
+ aneb <= 0;
+ altb <= 0;
+ agtb <= 0;
+ end
+ else if(A[C_WIDTH-1] == intB[C_WIDTH-1]) // Both numbers are -ve or both are +ve
+ begin
+ if(A < intB)
+ begin
+ aeqb <= 0;
+ aneb <= 1;
+ altb <= 1;
+ agtb <= 0;
+ end
+ if(A > intB)
+ begin
+ aeqb <= 0;
+ aneb <= 1;
+ altb <= 0;
+ agtb <= 1;
+ end
+ end
+ else if(A[C_WIDTH-1] == 1 && intB[C_WIDTH-1] == 0) // A is -ve, B is +ve
+ begin
+ aeqb <= 0;
+ aneb <= 1;
+ altb <= 1;
+ agtb <= 0;
+ end
+ else if(A[C_WIDTH-1] == 0 && intB[C_WIDTH-1] == 1) // A is +ve, B is -ve
+ begin
+ aeqb <= 0;
+ aneb <= 1;
+ altb <= 0;
+ agtb <= 1;
+ end
+ if(aeqb == 1 || altb == 1)
+ aleb <= 1;
+ else
+ aleb <= 0;
+ if(aeqb == 1 || agtb == 1)
+ ageb <= 1;
+ else
+ ageb <= 0;
+ end
+ else // Data is unsigned
+ begin
+ if(A == intB)
+ begin
+ aeqb <= 1;
+ aneb <= 0;
+ altb <= 0;
+ agtb <= 0;
+ end
+ if(A < intB)
+ begin
+ aeqb <= 0;
+ aneb <= 1;
+ altb <= 1;
+ agtb <= 0;
+ end
+ if(A > intB)
+ begin
+ aeqb <= 0;
+ aneb <= 1;
+ altb <= 0;
+ agtb <= 1;
+ end
+ if(aeqb == 1 || altb == 1)
+ aleb <= 1;
+ else
+ aleb <= 0;
+ if(aeqb == 1 || agtb == 1)
+ ageb <= 1;
+ else
+ ageb <= 0;
+ end
+
+ intA_EQ_B <= #1 aeqb;
+ intA_NE_B <= #1 aneb;
+ intA_LT_B <= #1 altb;
+ intA_GT_B <= #1 agtb;
+ intA_LE_B <= #1 aleb;
+ intA_GE_B <= #1 ageb;
+
+ end
+
+ always @(CLK)
+ lastCLK <= CLK;
+
+ always @(A or B or CE or ACLR or ASET or SCLR or SSET)
+ begin
+ intCE = defval(CE, C_HAS_CE, 1);
+ intB = defvecval(B, (C_B_CONSTANT == 1) ? 0 : 1, to_bits(C_B_VALUE));
+
+ if(is_X(A) == 1 || is_X(intB) == 1)
+ begin
+ notdone = 1;
+ if((is_X(A) && A === {C_WIDTH{1'bx}}) && (is_X(intB) && intB === {C_WIDTH{1'bx}}))
+ begin
+ aeqb = 1'bx;
+ aneb = 1'bx;
+ altb = 1'bx;
+ agtb = 1'bx;
+ aleb = 1'bx;
+ ageb = 1'bx;
+ notdone = 0;
+ end
+ else if(C_DATA_TYPE == `c_signed)
+ begin
+/* if(A[C_WIDTH-1] === 1'bx && intB[C_WIDTH-1] === 1'bx)
+ // Don't know the sign of EITHER data => ALL X's
+ begin
+ aeqb = 1'bx;
+ aneb = 1'bx;
+ altb = 1'bx;
+ agtb = 1'bx;
+ aleb = 1'bx;
+ ageb = 1'bx;
+ notdone = 0;
+ end
+ else if (A[C_WIDTH-1] !== 1'bx && intB[C_WIDTH-1] !== 1'bx)
+*/ if (A[C_WIDTH-1] !== 1'bx && intB[C_WIDTH-1] !== 1'bx)
+ begin
+ // The sign bits are both known
+ if (A[C_WIDTH-1] !== intB[C_WIDTH-1])
+ begin
+ // different signs!
+ if (A[C_WIDTH-1] === 1'b1)
+ begin
+ // A is negative and B is positive
+ aeqb = 0;
+ aneb = 1;
+ altb = 1;
+ agtb = 0;
+ aleb = 1;
+ ageb = 0;
+ notdone = 0;
+ end
+ else // A is +ve and B is -ve
+ begin
+ aeqb = 0;
+ aneb = 1;
+ altb = 0;
+ agtb = 1;
+ aleb = 0;
+ ageb = 1;
+ notdone = 0;
+ end
+ end
+ end
+ end
+ if (notdone == 1) // check further
+ begin
+ // Make copies of A and B with all X's substituted with 0's and 1's
+ a_low = A;
+ a_high = A;
+ b_low = intB;
+ b_high = intB;
+ for (i=C_WIDTH-2; i >= 0; i = i - 1)
+ begin
+ if (a_low[i] === 1'bx)
+ begin
+ a_low[i] = 0;
+ a_high[i] = 1;
+ end
+ if (b_low[i] === 1'bx)
+ begin
+ b_low[i] = 0;
+ b_high[i] = 1;
+ end
+ end
+ // we now (almost - need to check possible sign bits) have worst-case values which must agree on the comparison result
+ // if that result is not to be unknown...
+ if (C_DATA_TYPE == `c_signed)
+ begin
+ // Set the sign bits of the range values to 0 since
+ // the sign of the values will be treated separately
+ a_low[C_WIDTH-1] = 0;
+ a_high[C_WIDTH-1] = 0;
+ b_low[C_WIDTH-1] = 0;
+ b_high[C_WIDTH-1] = 0;
+
+ if((A[C_WIDTH-1] === 1'b1 && intB[C_WIDTH-1] === 1'bx)
+ || (intB[C_WIDTH-1] === 1'b0 && A[C_WIDTH-1] === 1'bx))
+ begin // Sign of A is -ve and sign of B is unknown OR
+ // sign of B is +ve and sign of A is unknown
+ // Is A always < B?
+ if (a_high < b_low)
+ begin
+ // A is definitely < than B
+ aeqb = 0;
+ aneb = 1;
+ altb = 1;
+ agtb = 0;
+ aleb = 1;
+ ageb = 0;
+ end
+ else if (a_high == b_low)
+ begin
+ // A is <= than B
+ aeqb = 1'bx;
+ aneb = 1'bx;
+ altb = 1'bx;
+ agtb = 0;
+ aleb = 1;
+ ageb = 1'bx;
+ end
+ else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}}))
+ begin // Definitely not equal!
+ aeqb = 1'b0;
+ aneb = 1'b1;
+ altb = 1'bx;
+ agtb = 1'bx;
+ aleb = 1'bx;
+ ageb = 1'bx;
+ end
+ else // There is > 1 overlap between the ranges so all X's
+ begin
+ aeqb = 1'bx;
+ aneb = 1'bx;
+ altb = 1'bx;
+ agtb = 1'bx;
+ aleb = 1'bx;
+ ageb = 1'bx;
+ end
+ end
+ else if((A[C_WIDTH-1] === 1'b0 && intB[C_WIDTH-1] === 1'bx)
+ || (intB[C_WIDTH-1] === 1'b1 && A[C_WIDTH-1] === 1'bx))
+ begin // Sign of A is +ve and sign of B is unknown OR
+ // sign of B is -ve and sign of A is unknown
+ // Is B always < A?
+ if (b_high < a_low)
+ begin
+ // B is definitely < than A
+ aeqb = 0;
+ aneb = 1;
+ altb = 0;
+ agtb = 1;
+ aleb = 0;
+ ageb = 1;
+ end
+ else if (b_high == a_low)
+ begin
+ // B is <= than A
+ aeqb = 1'bx;
+ aneb = 1'bx;
+ altb = 0;
+ agtb = 1'bx;
+ aleb = 1'bx;
+ ageb = 1;
+ end
+ else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}}))
+ begin // Definitely not equal!
+ aeqb = 1'b0;
+ aneb = 1'b1;
+ altb = 1'bx;
+ agtb = 1'bx;
+ aleb = 1'bx;
+ ageb = 1'bx;
+ end
+ else // There is > 1 overlap between the ranges so all X's
+ begin
+ aeqb = 1'bx;
+ aneb = 1'bx;
+ altb = 1'bx;
+ agtb = 1'bx;
+ aleb = 1'bx;
+ ageb = 1'bx;
+ end
+ end
+ else // Sign bits on A and B are identical and both are known
+ begin
+ if (a_high < b_low)
+ begin
+ // A is definitely < than B
+ aeqb = 0;
+ aneb = 1;
+ altb = 1;
+ agtb = 0;
+ aleb = 1;
+ ageb = 0;
+ end
+ else if (a_low > b_high)
+ begin
+ // A is definitely > than B
+ aeqb = 0;
+ aneb = 1;
+ altb = 0;
+ agtb = 1;
+ aleb = 0;
+ ageb = 1;
+ end
+ else if (a_high == b_low)
+ begin
+ // A is <= than B
+ aeqb = 1'bx;
+ aneb = 1'bx;
+ altb = 1'bx;
+ agtb = 0;
+ aleb = 1;
+ ageb = 1'bx;
+ end
+ else if (a_low == b_high)
+ begin
+ // A is >= than B
+ aeqb = 1'bx;
+ aneb = 1'bx;
+ altb = 0;
+ agtb = 1'bx;
+ aleb = 1'bx;
+ ageb = 1;
+ end
+ else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}}))
+ begin // Definitely not equal!
+ aeqb = 1'b0;
+ aneb = 1'b1;
+ altb = 1'bx;
+ agtb = 1'bx;
+ aleb = 1'bx;
+ ageb = 1'bx;
+ end
+ else // There is > 1 overlap between the ranges so all X's
+ begin
+ aeqb = 1'bx;
+ aneb = 1'bx;
+ altb = 1'bx;
+ agtb = 1'bx;
+ aleb = 1'bx;
+ ageb = 1'bx;
+ end
+ end
+ end
+ else // unsigned data
+ begin
+ if (a_low[C_WIDTH-1] === 1'bx)
+ begin
+ a_low[C_WIDTH-1] = 0;
+ a_high[C_WIDTH-1] = 1;
+ end
+ if (b_low[C_WIDTH-1] === 1'bx)
+ begin
+ b_low[C_WIDTH-1] = 0;
+ b_high[C_WIDTH-1] = 1;
+ end
+ if (a_high < b_low)
+ begin
+ // A is definitely < than B
+ aeqb = 0;
+ aneb = 1;
+ altb = 1;
+ agtb = 0;
+ aleb = 1;
+ ageb = 0;
+ end
+ else if (a_low > b_high)
+ begin
+ // A is definitely > than B
+ aeqb = 0;
+ aneb = 1;
+ altb = 0;
+ agtb = 1;
+ aleb = 0;
+ ageb = 1;
+ end
+ else if (a_high == b_low)
+ begin
+ // A is <= B
+ aeqb = 1'bx;
+ aneb = 1'bx;
+ altb = 1'bx;
+ agtb = 0;
+ aleb = 1;
+ ageb = 1'bx;
+ end
+ else if (a_low == b_high)
+ begin
+ // A is >= B
+ aeqb = 1'bx;
+ aneb = 1'bx;
+ altb = 0;
+ agtb = 1'bx;
+ aleb = 1'bx;
+ ageb = 1;
+ end
+ else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}}))
+ begin // Definitely not equal!
+ aeqb = 1'b0;
+ aneb = 1'b1;
+ altb = 1'bx;
+ agtb = 1'bx;
+ aleb = 1'bx;
+ ageb = 1'bx;
+ end
+ else // There is > 1 overlap between the ranges so all X's
+ begin
+ aeqb = 1'bx;
+ aneb = 1'bx;
+ altb = 1'bx;
+ agtb = 1'bx;
+ aleb = 1'bx;
+ ageb = 1'bx;
+ end
+ end
+ end
+ end
+ else if (C_DATA_TYPE == `c_signed)
+ begin
+ // Signed data so examine MSB and rest separately in some cases
+ if(A == intB)
+ begin
+ aeqb = 1;
+ aneb = 0;
+ altb = 0;
+ agtb = 0;
+ end
+ else if(A[C_WIDTH-1] == intB[C_WIDTH-1]) // Both numbers are -ve or both are +ve
+ begin
+ if(A < intB)
+ begin
+ aeqb = 0;
+ aneb = 1;
+ altb = 1;
+ agtb = 0;
+ end
+ if(A > intB)
+ begin
+ aeqb = 0;
+ aneb = 1;
+ altb = 0;
+ agtb = 1;
+ end
+ end
+ else if(A[C_WIDTH-1] == 1 && intB[C_WIDTH-1] == 0) // A is -ve, B is +ve
+ begin
+ aeqb = 0;
+ aneb = 1;
+ altb = 1;
+ agtb = 0;
+ end
+ else if(A[C_WIDTH-1] == 0 && intB[C_WIDTH-1] == 1) // A is +ve, B is -ve
+ begin
+ aeqb = 0;
+ aneb = 1;
+ altb = 0;
+ agtb = 1;
+ end
+ if(aeqb == 1 || altb == 1)
+ aleb = 1;
+ else
+ aleb = 0;
+ if(aeqb == 1 || agtb == 1)
+ ageb = 1;
+ else
+ ageb = 0;
+ end
+ else // Data is unsigned
+ begin
+ if(A == intB)
+ begin
+ aeqb = 1;
+ aneb = 0;
+ altb = 0;
+ agtb = 0;
+ end
+ if(A < intB)
+ begin
+ aeqb = 0;
+ aneb = 1;
+ altb = 1;
+ agtb = 0;
+ end
+ if(A > intB)
+ begin
+ aeqb = 0;
+ aneb = 1;
+ altb = 0;
+ agtb = 1;
+ end
+ if(aeqb == 1 || altb == 1)
+ aleb = 1;
+ else
+ aleb = 0;
+ if(aeqb == 1 || agtb == 1)
+ ageb = 1;
+ else
+ ageb = 0;
+ end
+
+ intA_EQ_B <= #1 aeqb;
+ intA_NE_B <= #1 aneb;
+ intA_LT_B <= #1 altb;
+ intA_GT_B <= #1 agtb;
+ intA_LE_B <= #1 aleb;
+ intA_GE_B <= #1 ageb;
+ end
+
+ always@(posedge CLK)
+ begin
+ if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines!
+ begin
+ for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1)
+ begin
+ intQA_EQ_Bpipe[pipe] <= intQA_EQ_Bpipe[pipe+1];
+ intQA_NE_Bpipe[pipe] <= intQA_NE_Bpipe[pipe+1];
+ intQA_LT_Bpipe[pipe] <= intQA_LT_Bpipe[pipe+1];
+ intQA_GT_Bpipe[pipe] <= intQA_GT_Bpipe[pipe+1];
+ intQA_LE_Bpipe[pipe] <= intQA_LE_Bpipe[pipe+1];
+ intQA_GE_Bpipe[pipe] <= intQA_GE_Bpipe[pipe+1];
+ end
+ intQA_EQ_Bpipe[C_PIPE_STAGES] <= intA_EQ_B;
+ intQA_NE_Bpipe[C_PIPE_STAGES] <= intA_NE_B;
+ intQA_LT_Bpipe[C_PIPE_STAGES] <= intA_LT_B;
+ intQA_GT_Bpipe[C_PIPE_STAGES] <= intA_GT_B;
+ intQA_LE_Bpipe[C_PIPE_STAGES] <= intA_LE_B;
+ intQA_GE_Bpipe[C_PIPE_STAGES] <= intA_GE_B;
+ end
+ else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines!
+ begin
+ for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1)
+ begin
+ if(intQA_EQ_Bpipe[pipe] !== intQA_EQ_Bpipe[pipe+1])
+ intQA_EQ_Bpipe[pipe] <= 1'bx;
+ if(intQA_NE_Bpipe[pipe] !== intQA_NE_Bpipe[pipe+1])
+ intQA_NE_Bpipe[pipe] <= 1'bx;
+ if(intQA_LT_Bpipe[pipe] !== intQA_LT_Bpipe[pipe+1])
+ intQA_LT_Bpipe[pipe] <= 1'bx;
+ if(intQA_GT_Bpipe[pipe] !== intQA_GT_Bpipe[pipe+1])
+ intQA_GT_Bpipe[pipe] <= 1'bx;
+ if(intQA_LE_Bpipe[pipe] !== intQA_LE_Bpipe[pipe+1])
+ intQA_LE_Bpipe[pipe] <= 1'bx;
+ if(intQA_GE_Bpipe[pipe] !== intQA_GE_Bpipe[pipe+1])
+ intQA_GE_Bpipe[pipe] <= 1'bx;
+ end
+ if(intQA_EQ_Bpipe[C_PIPE_STAGES] !== intA_EQ_B)
+ intQA_EQ_Bpipe[C_PIPE_STAGES] <= 1'bx;
+ if(intQA_NE_Bpipe[C_PIPE_STAGES] !== intA_NE_B)
+ intQA_NE_Bpipe[C_PIPE_STAGES] <= 1'bx;
+ if(intQA_LT_Bpipe[C_PIPE_STAGES] !== intA_LT_B)
+ intQA_LT_Bpipe[C_PIPE_STAGES] <= 1'bx;
+ if(intQA_GT_Bpipe[C_PIPE_STAGES] !== intA_GT_B)
+ intQA_GT_Bpipe[C_PIPE_STAGES] <= 1'bx;
+ if(intQA_LE_Bpipe[C_PIPE_STAGES] !== intA_LE_B)
+ intQA_LE_Bpipe[C_PIPE_STAGES] <= 1'bx;
+ if(intQA_GE_Bpipe[C_PIPE_STAGES] !== intA_GE_B)
+ intQA_GE_Bpipe[C_PIPE_STAGES] <= 1'bx;
+ end
+ end
+
+ always@(intA_EQ_B or intQA_EQ_Bpipe[2])
+ begin
+ if(C_PIPE_STAGES < 2) // No pipeline
+ intQA_EQ_Bpipeend <= intA_EQ_B;
+ else // Pipeline stages required
+ begin
+ intQA_EQ_Bpipeend <= intQA_EQ_Bpipe[2];
+ end
+ end
+ always@(intA_NE_B or intQA_NE_Bpipe[2])
+ begin
+ if(C_PIPE_STAGES < 2) // No pipeline
+ intQA_NE_Bpipeend <= intA_NE_B;
+ else // Pipeline stages required
+ begin
+ intQA_NE_Bpipeend <= intQA_NE_Bpipe[2];
+ end
+ end
+ always@(intA_LT_B or intQA_LT_Bpipe[2])
+ begin
+ if(C_PIPE_STAGES < 2) // No pipeline
+ intQA_LT_Bpipeend <= intA_LT_B;
+ else // Pipeline stages required
+ begin
+ intQA_LT_Bpipeend <= intQA_LT_Bpipe[2];
+ end
+ end
+ always@(intA_GT_B or intQA_GT_Bpipe[2])
+ begin
+ if(C_PIPE_STAGES < 2) // No pipeline
+ intQA_GT_Bpipeend <= intA_GT_B;
+ else // Pipeline stages required
+ begin
+ intQA_GT_Bpipeend <= intQA_GT_Bpipe[2];
+ end
+ end
+ always@(intA_LE_B or intQA_LE_Bpipe[2])
+ begin
+ if(C_PIPE_STAGES < 2) // No pipeline
+ intQA_LE_Bpipeend <= intA_LE_B;
+ else // Pipeline stages required
+ begin
+ intQA_LE_Bpipeend <= intQA_LE_Bpipe[2];
+ end
+ end
+ always@(intA_GE_B or intQA_GE_Bpipe[2])
+ begin
+ if(C_PIPE_STAGES < 2) // No pipeline
+ intQA_GE_Bpipeend <= intA_GE_B;
+ else // Pipeline stages required
+ begin
+ intQA_GE_Bpipeend <= intQA_GE_Bpipe[2];
+ end
+ end
+
+ function is_X;
+ input [C_WIDTH-1 : 0] i;
+ integer j;
+ begin
+ is_X = 0;
+ for(j = 0; j < C_WIDTH; j = j + 1)
+ if(i[j] === 1'bx)
+ is_X = 1;
+ end
+ endfunction
+
+ function defval;
+ input i;
+ input hassig;
+ input val;
+ begin
+ if(hassig == 1)
+ defval = i;
+ else
+ defval = val;
+ end
+ endfunction
+
+ function [C_WIDTH - 1 : 0] defvecval;
+ input [C_WIDTH-1 : 0] i;
+ input hassig;
+ input [C_WIDTH-1 : 0] val;
+ begin
+ if(hassig == 1)
+ defvecval = i;
+ else
+ defvecval = val;
+ end
+ endfunction
+
+ function [C_WIDTH - 1 : 0] to_bits;
+ input [C_WIDTH*8 : 1] instring;
+ integer i;
+ integer non_null_string;
+ begin
+ non_null_string = 0;
+ for(i = C_WIDTH; i > 0; i = i - 1)
+ begin // Is the string empty?
+ if(instring[(i*8)] == 0 &&
+ instring[(i*8)-1] == 0 &&
+ instring[(i*8)-2] == 0 &&
+ instring[(i*8)-3] == 0 &&
+ instring[(i*8)-4] == 0 &&
+ instring[(i*8)-5] == 0 &&
+ instring[(i*8)-6] == 0 &&
+ instring[(i*8)-7] == 0 &&
+ non_null_string == 0)
+ non_null_string = 0; // Use the return value to flag a non-empty string
+ else
+ non_null_string = 1; // Non-null character!
+ end
+ if(non_null_string == 0) // String IS empty! Just return the value to be all '0's
+ begin
+ for(i = C_WIDTH; i > 0; i = i - 1)
+ to_bits[i-1] = 0;
+ end
+ else
+ begin
+ for(i = C_WIDTH; i > 0; i = i - 1)
+ begin // Is this character a '0'? (ASCII = 48 = 00110000)
+ if(instring[(i*8)] == 0 &&
+ instring[(i*8)-1] == 0 &&
+ instring[(i*8)-2] == 1 &&
+ instring[(i*8)-3] == 1 &&
+ instring[(i*8)-4] == 0 &&
+ instring[(i*8)-5] == 0 &&
+ instring[(i*8)-6] == 0 &&
+ instring[(i*8)-7] == 0)
+ to_bits[i-1] = 0;
+ // Or is it a '1'?
+ else if(instring[(i*8)] == 0 &&
+ instring[(i*8)-1] == 0 &&
+ instring[(i*8)-2] == 1 &&
+ instring[(i*8)-3] == 1 &&
+ instring[(i*8)-4] == 0 &&
+ instring[(i*8)-5] == 0 &&
+ instring[(i*8)-6] == 0 &&
+ instring[(i*8)-7] == 1)
+ to_bits[i-1] = 1;
+ // Or is it a ' '? (a null char - in which case insert a '0')
+ else if(instring[(i*8)] == 0 &&
+ instring[(i*8)-1] == 0 &&
+ instring[(i*8)-2] == 0 &&
+ instring[(i*8)-3] == 0 &&
+ instring[(i*8)-4] == 0 &&
+ instring[(i*8)-5] == 0 &&
+ instring[(i*8)-6] == 0 &&
+ instring[(i*8)-7] == 0)
+ to_bits[i-1] = 0;
+ else
+ begin
+ $display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring);
+ $finish;
+ end
+ end
+ end
+ end
+ endfunction
+
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_signed
+`undef c_unsigned
+
+`endif
+
trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_COMPARE_V3_0.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_REG_FD_V3_0.v
===================================================================
--- trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_REG_FD_V3_0.v (nonexistent)
+++ trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_REG_FD_V3_0.v (revision 784)
@@ -0,0 +1,333 @@
+/* $Id: C_REG_FD_V3_0.v,v 1.1 2002-03-28 20:50:04 lampret Exp $
+--
+-- Filename - C_REG_FD_V3_0.v
+-- Author - Xilinx
+-- Creation - 21 Oct 1998
+--
+-- Description - This file contains the Verilog behavior for the baseblocks C_REG_FD_V3_0 module
+*/
+
+`ifdef C_REG_FD_V3_0_DEF
+`else
+`define C_REG_FD_V3_0_DEF
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+
+`define all1s {C_WIDTH{1'b1}}
+`define all0s 'b0
+`define allXs {C_WIDTH{1'bx}}
+
+module C_REG_FD_V3_0 (D, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, Q);
+
+ parameter C_AINIT_VAL = "";
+ parameter C_ENABLE_RLOCS = 1;
+ parameter C_HAS_ACLR = 0;
+ parameter C_HAS_AINIT = 0;
+ parameter C_HAS_ASET = 0;
+ parameter C_HAS_CE = 0;
+ parameter C_HAS_SCLR = 0;
+ parameter C_HAS_SINIT = 0;
+ parameter C_HAS_SSET = 0;
+ parameter C_SINIT_VAL = "";
+ parameter C_SYNC_ENABLE = `c_override;
+ parameter C_SYNC_PRIORITY = `c_clear;
+ parameter C_WIDTH = 16;
+
+
+ input [C_WIDTH-1 : 0] D;
+ input CLK;
+ input CE;
+ input ACLR;
+ input ASET;
+ input AINIT;
+ input SCLR;
+ input SSET;
+ input SINIT;
+ output [C_WIDTH-1 : 0] Q;
+
+ reg [C_WIDTH-1 : 0] data;
+ reg [C_WIDTH-1 : 0] datatmp;
+ // Internal values to drive signals when input is missing
+ wire intCE;
+ wire intACLR;
+ wire intASET;
+ wire intAINIT;
+ wire intSCLR;
+ wire intSSET;
+ wire intSINIT;
+ wire intCLK;
+
+ wire [C_WIDTH-1 : 0] #1 Q = data;
+
+ // Sort out default values for missing ports
+
+ assign intCLK = CLK;
+ assign intACLR = defval(ACLR, C_HAS_ACLR, 0);
+ assign intASET = defval(ASET, C_HAS_ASET, 0);
+ assign intAINIT = defval(AINIT, C_HAS_AINIT, 0);
+ assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);
+ assign intSSET = defval(SSET, C_HAS_SSET, 0);
+ assign intSINIT = defval(SINIT, C_HAS_SINIT, 0);
+ assign intCE = ((((C_HAS_ACLR == 1 || C_HAS_ASET == 1 || C_HAS_AINIT == 1) &&
+ (C_HAS_SCLR == 1 || C_HAS_SSET == 1 || C_HAS_SINIT == 1)) ||
+ (C_HAS_SCLR == 1 && C_HAS_SSET == 1 && C_SYNC_PRIORITY == `c_set)) &&
+ (C_HAS_CE == 1) && (C_SYNC_ENABLE == `c_override) ?
+ (CE | intSCLR | intSSET | intSINIT) : ((C_HAS_CE == 1) ? CE : 1'b1));
+
+ reg lastCLK;
+ reg lastintACLR;
+ reg lastintASET;
+
+ reg [C_WIDTH-1 : 0] AIV;
+ reg [C_WIDTH-1 : 0] SIV;
+
+
+ integer i;
+ integer ASYNC_CTRL;
+
+ initial
+ begin
+ ASYNC_CTRL <= 1;
+ lastCLK = #1 1'b0;
+ lastintACLR <= 1'b0;
+ lastintASET <= 1'b0;
+ AIV = to_bits(C_AINIT_VAL);
+ SIV = to_bits(C_SINIT_VAL);
+ if(C_HAS_ACLR === 1)
+ data <= #1 `all0s;
+ else if(C_HAS_ASET === 1)
+ data <= #1 `all1s;
+ else if(C_HAS_AINIT === 1)
+ data <= #1 AIV;
+ else if(C_HAS_SCLR === 1)
+ data <= #1 `all0s;
+ else if(C_HAS_SSET === 1)
+ data <= #1 `all1s;
+ else if(C_HAS_SINIT === 1)
+ data <= #1 SIV;
+ else
+ data <= #1 AIV;
+ end
+
+ always@(posedge intCLK or intCE or intACLR or intASET or intAINIT)
+ begin
+ datatmp = data;
+
+ for(i = 0; i < C_WIDTH; i = i + 1)
+ begin
+ if(intACLR === 1'b1)
+ datatmp[i] = 1'b0;
+ else if(intACLR === 1'b0 && intASET === 1'b1)
+ datatmp[i] = 1'b1;
+ else if(intAINIT === 1'b1)
+ datatmp[i] = AIV[i];
+ else if(intACLR === 1'bx && intASET !== 1'b0)
+ datatmp[i] = 1'bx;
+ else if(intACLR != lastintACLR && lastintASET != intASET
+ && lastintACLR === 1'b1 && lastintASET === 1'b1
+ && intACLR === 1'b0 && intASET === 1'b0)
+ datatmp[i] = 1'bx;
+ else
+ begin
+ ASYNC_CTRL = 0;
+ if(lastCLK !== intCLK && lastCLK === 1'b0 && intCLK === 1'b1)
+ begin
+ if((intCE !== 1'b0 || C_SYNC_ENABLE === 0) &&
+ (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0))
+ begin
+ datatmp[i] = 1'bx;
+ ASYNC_CTRL = 1;
+ end
+ if((intCE !== 1'b0 || C_SYNC_ENABLE === 0) &&
+ (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx))
+ begin
+ datatmp[i] = 1'bx;
+ ASYNC_CTRL = 1;
+ end
+ if(intCE === 1'b1 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0)
+ datatmp[i] = D[i];
+ else if(intCE === 1'bx && datatmp[i] !== D[i] && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0)
+ datatmp[i] = 1'bx;
+
+ if(intSINIT === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && ASYNC_CTRL == 0)
+ datatmp[i] = SIV[i];
+ else if(intSINIT === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== SIV[i])
+ datatmp[i] = 1'bx;
+ else if(intSINIT === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i])
+ datatmp[i] = 1'bx;
+
+ if(intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && ASYNC_CTRL == 0)
+ datatmp[i] = 1'b0;
+ else if(intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0))
+ datatmp[i] = 1'bx;
+ else if(intSCLR === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0))
+ datatmp[i] = 1'bx;
+
+ if(intSSET === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && ASYNC_CTRL == 0)
+ datatmp[i] = 1'b1;
+ else if(intSSET === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0))
+ datatmp[i] = 1'bx;
+ else if(intSSET === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0))
+ datatmp[i] = 1'bx;
+ end
+ else if(lastCLK !== intCLK && ((lastCLK === 1'b0 && intCLK === 1'bx)
+ || (lastCLK === 1'bx && intCLK === 1'b1)))
+ begin
+ if((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0))
+ datatmp[i] = 1'bx;
+ else if((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx))
+ datatmp[i] = 1'bx;
+
+ if(intCE !== 1'b0 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && datatmp[i] !== D[i])
+ datatmp[i] = 1'bx;
+
+ if(intSINIT !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i])
+ datatmp[i] = 1'bx;
+
+ if(intSCLR !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && datatmp[i] !== 1'b0)
+ datatmp[i] = 1'bx;
+
+ if(intSSET !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && datatmp[i] !== 1'b1)
+ datatmp[i] = 1'bx;
+ end
+
+ if(intACLR === 1'b0 && intASET === 1'bx)
+ begin
+ if(datatmp[i] !== 1'b1)
+ begin
+ datatmp[i] = 1'bx;
+ ASYNC_CTRL = 1;
+ end
+ end
+ else if(intACLR === 1'bx && intASET === 1'b0)
+ begin
+ if(datatmp[i] !== 1'b0)
+ begin
+ datatmp[i] = 1'bx;
+ ASYNC_CTRL = 1;
+ end
+ end
+ else if(intAINIT === 1'bx)
+ begin
+ if(datatmp[i] !== AIV[i])
+ begin
+ datatmp[i] = 1'bx;
+ ASYNC_CTRL = 1;
+ end
+ end
+ end
+ end
+
+ data <= datatmp;
+ end
+
+
+ always@(intACLR or intASET)
+ begin
+ lastintACLR <= intACLR;
+ lastintASET <= intASET;
+ if($time != 0)
+ if(intACLR === 1'b0 && intASET === 1'b0 && lastintACLR !== 1'b0 && lastintASET !== 1'b0) // RACE
+ data <= `allXs;
+ end
+
+ always@(intCLK)
+ lastCLK <= intCLK;
+
+
+ function defval;
+ input i;
+ input hassig;
+ input val;
+ begin
+ if(hassig == 1)
+ defval = i;
+ else
+ defval = val;
+ end
+ endfunction
+
+ function [C_WIDTH - 1 : 0] to_bits;
+ input [C_WIDTH*8 : 1] instring;
+ integer i;
+ integer non_null_string;
+ begin
+ non_null_string = 0;
+ for(i = C_WIDTH; i > 0; i = i - 1)
+ begin // Is the string empty?
+ if(instring[(i*8)] == 0 &&
+ instring[(i*8)-1] == 0 &&
+ instring[(i*8)-2] == 0 &&
+ instring[(i*8)-3] == 0 &&
+ instring[(i*8)-4] == 0 &&
+ instring[(i*8)-5] == 0 &&
+ instring[(i*8)-6] == 0 &&
+ instring[(i*8)-7] == 0 &&
+ non_null_string == 0)
+ non_null_string = 0; // Use the return value to flag a non-empty string
+ else
+ non_null_string = 1; // Non-null character!
+ end
+ if(non_null_string == 0) // String IS empty! Just return the value to be all '0's
+ begin
+ for(i = C_WIDTH; i > 0; i = i - 1)
+ to_bits[i-1] = 0;
+ end
+ else
+ begin
+ for(i = C_WIDTH; i > 0; i = i - 1)
+ begin // Is this character a '0'? (ASCII = 48 = 00110000)
+ if(instring[(i*8)] == 0 &&
+ instring[(i*8)-1] == 0 &&
+ instring[(i*8)-2] == 1 &&
+ instring[(i*8)-3] == 1 &&
+ instring[(i*8)-4] == 0 &&
+ instring[(i*8)-5] == 0 &&
+ instring[(i*8)-6] == 0 &&
+ instring[(i*8)-7] == 0)
+ to_bits[i-1] = 0;
+ // Or is it a '1'?
+ else if(instring[(i*8)] == 0 &&
+ instring[(i*8)-1] == 0 &&
+ instring[(i*8)-2] == 1 &&
+ instring[(i*8)-3] == 1 &&
+ instring[(i*8)-4] == 0 &&
+ instring[(i*8)-5] == 0 &&
+ instring[(i*8)-6] == 0 &&
+ instring[(i*8)-7] == 1)
+ to_bits[i-1] = 1;
+ // Or is it a ' '? (a null char - in which case insert a '0')
+ else if(instring[(i*8)] == 0 &&
+ instring[(i*8)-1] == 0 &&
+ instring[(i*8)-2] == 0 &&
+ instring[(i*8)-3] == 0 &&
+ instring[(i*8)-4] == 0 &&
+ instring[(i*8)-5] == 0 &&
+ instring[(i*8)-6] == 0 &&
+ instring[(i*8)-7] == 0)
+ to_bits[i-1] = 0;
+ else
+ begin
+ $display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring);
+ $finish;
+ end
+ end
+ end
+ end
+ endfunction
+
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+
+`undef all1s
+`undef all0s
+`undef allXs
+
+`endif
trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_REG_FD_V3_0.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/blkmemdp_v3_0.v
===================================================================
--- trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/blkmemdp_v3_0.v (nonexistent)
+++ trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/blkmemdp_v3_0.v (revision 784)
@@ -0,0 +1,1040 @@
+/**************************************************************************
+ * $Id: blkmemdp_v3_0.v,v 1.1 2002-03-28 20:50:04 lampret Exp $
+ **************************************************************************
+ * Dual Port Block Memory - Verilog Behavioral Model
+ * ************************************************************************
+ *
+ *
+ * This File is owned and controlled by Xilinx and must be used solely
+ * for design, simulation, implementation and creation of design files
+ * limited to Xilinx devices or technologies. Use with non-Xilinx
+ * devices or technologies is expressly prohibited and immediately
+ * terminates your license.
+ *
+ * Xilinx products are not intended for use in life support
+ * appliances, devices, or systems. Use in such applications is
+ * expressly prohibited.
+ *
+ * ****************************
+ * ** Copyright Xilinx, Inc. **
+ * ** All rights reserved. **
+ * ****************************
+ *
+ *
+ *************************************************************************
+ * Filename: BLKMEMDP_V3_0.v
+ *
+ * Description: The Verilog behavioral model for the Dual Port Block Memory
+ *
+ * ***********************************************************************
+ */
+
+
+`celldefine
+
+
+`define c_dp_rom 4
+`define c_dp_ram 2
+`define c_write_first 0
+`define c_read_first 1
+`define c_no_change 2
+
+module BLKMEMDP_V3_0(DOUTA, DOUTB, ADDRA, CLKA, DINA, ENA, SINITA, WEA, NDA, RFDA, RDYA, ADDRB, CLKB, DINB, ENB, SINITB, WEB,NDB, RFDB, RDYB);
+
+
+
+ parameter c_addra_width = 11 ;
+ parameter c_addrb_width = 9 ;
+ parameter c_default_data = "0"; // indicates string of hex characters used to initialize memory
+ parameter c_depth_a = 2048 ;
+ parameter c_depth_b = 512 ;
+ parameter c_enable_rlocs = 0 ; // core includes placement constraints
+ parameter c_has_default_data = 1;
+ parameter c_has_dina = 1 ; // indicate port A has data input pins
+ parameter c_has_dinb = 1 ; // indicate port B has data input pins
+ parameter c_has_douta = 1 ; // indicates port A has output
+ parameter c_has_doutb = 1 ; // indicates port B has output
+ parameter c_has_ena = 1 ; // indicates port A has a ENA pin
+ parameter c_has_enb = 1 ; // indicates port B has a ENB pin
+ parameter c_has_limit_data_pitch = 1 ;
+ parameter c_has_nda = 0 ; // Port A has a new data pin
+ parameter c_has_ndb = 0 ; // Port B has a new data pin
+ parameter c_has_rdya = 0 ; // Port A has result ready pin
+ parameter c_has_rdyb = 0 ; // Port B has result ready pin
+ parameter c_has_rfda = 0 ; // Port A has ready for data pin
+ parameter c_has_rfdb = 0 ; // Port B has ready for data pin
+ parameter c_has_sinita = 1 ; // indicates port A has a SINITA pin
+ parameter c_has_sinitb = 1 ; // indicates port B has a SINITB pin
+ parameter c_has_wea = 1 ; // indicates port A has a WEA pin
+ parameter c_has_web = 1 ; // indicates port B has a WEB pin
+ parameter c_limit_data_pitch = 16 ;
+ parameter c_mem_init_file = "null.mif"; // controls which .mif file used to initialize memory
+ parameter c_pipe_stages_a = 0 ; // indicates the number of pipe stages needed in port A
+ parameter c_pipe_stages_b = 0 ; // indicates the number of pipe stages needed in port B
+ parameter c_reg_inputsa = 0 ; // indicates we, addr, and din of port A are registered
+ parameter c_reg_inputsb = 0 ; // indicates we, addr, and din of port B are registered
+ parameter c_sinita_value = "0000"; // indicates string of hex used to initialize A output registers
+ parameter c_sinitb_value = "0000"; // indicates string of hex used to initialize B output resisters
+ parameter c_width_a = 8 ;
+ parameter c_width_b = 32 ;
+ parameter c_write_modea = 2; // controls which write modes shall be used
+ parameter c_write_modeb = 2; // controls which write modes shall be used
+
+
+
+
+// IO ports
+
+
+
+ output [c_width_a-1:0] DOUTA;
+
+ input [c_addra_width-1:0] ADDRA;
+ input [c_width_a-1:0] DINA;
+ input ENA, CLKA, WEA, SINITA, NDA;
+ output RFDA, RDYA;
+
+ output [c_width_b-1:0] DOUTB;
+
+ input [c_addrb_width-1:0] ADDRB;
+ input [c_width_b-1:0] DINB;
+ input ENB, CLKB, WEB, SINITB, NDB;
+ output RFDB, RDYB;
+
+
+// internal signals
+
+ reg [c_width_a-1:0] douta_mux_out ; // output of multiplexer --
+ wire [c_width_a-1:0] DOUTA = douta_mux_out;
+ reg RFDA, RDYA ;
+
+ reg [c_width_b-1:0] doutb_mux_out ; // output of multiplexer --
+ wire [c_width_b-1:0] DOUTB = doutb_mux_out;
+ reg RFDB, RDYB;
+
+
+ reg [c_width_a-1:0] douta_out_q; // registered output of douta_out
+ reg [c_width_a-1:0] doa_out; // output of Port A RAM
+ reg [c_width_a-1:0] douta_out; // output of pipeline mux for port A
+
+ reg [c_width_b-1:0] doutb_out_q ; // registered output for doutb_out
+ reg [c_width_b-1:0] dob_out; // output of Port B RAM
+ reg [c_width_b-1:0] doutb_out ; // output of pipeline mux for port B
+
+ reg [c_depth_a*c_width_a-1 : 0] mem;
+ reg [24:0] count ;
+ reg [1:0] wr_mode_a, wr_mode_b;
+
+ reg [(c_width_a-1) : 0] pipelinea [0 : c_pipe_stages_a];
+ reg [(c_width_b-1) : 0] pipelineb [0 : c_pipe_stages_b];
+ reg sub_rdy_a[0 : c_pipe_stages_a];
+ reg sub_rdy_b[0 : c_pipe_stages_b];
+
+ reg [10:0] ci, cj;
+ reg [10:0] dmi, dmj, dni, dnj, doi, doj, dai, daj, dbi, dbj, dci, dcj, ddi, ddj;
+ reg [10:0] pmi, pmj, pni, pnj, poi, poj, pai, paj, pbi, pbj, pci, pcj, pdi, pdj;
+ integer ai, aj, ak, al, am, an, ap ;
+ integer bi, bj, bk, bl, bm, bn, bp ;
+ integer i, j, k, l, m, n, p;
+
+ wire [c_addra_width-1:0] addra_i = ADDRA;
+ reg [c_width_a-1:0] dia_int ;
+ reg [c_width_a-1:0] dia_q ;
+ wire [c_width_a-1:0] dia_i ;
+ wire ena_int ;
+ reg ena_q ;
+ wire clka_int = CLKA ;
+ reg wea_int ;
+ wire wea_i ;
+ reg wea_q ;
+ wire ssra_int ;
+ wire nda_int ;
+ wire nda_i ;
+ reg rfda_int ;
+ reg rdya_int ;
+ reg nda_q ;
+ reg new_data_a ;
+ reg new_data_a_q ;
+ reg [c_addra_width-1:0] addra_q;
+ reg [c_addra_width-1:0] addra_int;
+ reg [c_width_a-1:0] sinita_value ; // initialization value for output registers of Port A
+
+ wire [c_addrb_width-1:0] addrb_i = ADDRB;
+ reg [c_width_b-1:0] dib_int ;
+ reg [c_width_b-1:0] dib_q ;
+ wire [c_width_b-1:0] dib_i ;
+ wire enb_int ;
+ reg enb_q ;
+ wire clkb_int = CLKB ;
+ reg web_int ;
+ wire web_i ;
+ reg web_q ;
+ wire ssrb_int ;
+ wire ndb_int ;
+ wire ndb_i ;
+ reg rfdb_int ;
+ reg rdyb_int ;
+ reg ndb_q ;
+ reg new_data_b ;
+ reg new_data_b_q ;
+ reg [c_addrb_width-1:0] addrb_q ;
+ reg [c_addrb_width-1:0] addrb_int ;
+ reg [c_width_b-1:0] sinitb_value ; // initialization value for output registers of Port B
+
+// variables used to initialize memory contents to default values.
+
+ reg [c_width_a-1:0] bitval ;
+ reg [c_width_a-1:0] ram_temp [0:c_depth_a-1] ;
+ reg [c_width_a-1:0] default_data ;
+
+// variables used to detect address collision on dual port Rams
+
+ reg recovery_a, recovery_b;
+ reg address_collision;
+
+ wire clka_enable = ena_int && wea_int && enb_int && address_collision;
+ wire clkb_enable = enb_int && web_int && ena_int && address_collision;
+ wire collision = clka_enable || clkb_enable;
+
+// tri0 GSR = glbl.GSR;
+
+ assign dia_i = (c_has_dina === 1)?DINA:'b0;
+ assign ena_int = defval(ENA, c_has_ena, 1);
+ assign ssra_int = defval( SINITA , c_has_sinita , 0);
+ assign nda_i = defval( NDA, c_has_nda, 1);
+ assign dib_i = (c_has_dinb === 1)?DINB:'b0;
+ assign enb_int = defval(ENB, c_has_enb, 1);
+ assign ssrb_int = defval( SINITB, c_has_sinitb, 0);
+ assign ndb_i = defval( NDB, c_has_ndb, 1);
+
+// RAM/ROM functionality
+
+ assign wea_i = (c_has_wea == 1) ? WEA:1'b0 ;
+ assign web_i = (c_has_web == 1) ? WEB:1'b0 ;
+
+
+
+ function defval;
+ input i;
+ input hassig;
+ input val;
+ begin
+ if(hassig == 1)
+ defval = i;
+ else
+ defval = val;
+ end
+ endfunction
+
+ function max;
+ input a;
+ input b;
+ begin
+ max = (a > b) ? a : b;
+ end
+ endfunction
+
+ function a_is_X;
+ input [c_width_a-1 : 0] i;
+ integer j ;
+ begin
+ a_is_X = 1'b0;
+ for(j = 0; j < c_width_a; j = j + 1)
+ begin
+ if(i[j] === 1'bx)
+ a_is_X = 1'b1;
+ end // loop
+ end
+ endfunction
+
+ function b_is_X;
+ input [c_width_b-1 : 0] i;
+ integer j ;
+ begin
+ b_is_X = 1'b0;
+ for(j = 0; j < c_width_b; j = j + 1)
+ begin
+ if(i[j] === 1'bx)
+ b_is_X = 1'b1;
+ end // loop
+ end
+ endfunction
+
+ function [c_width_a-1:0] hexstr_conv;
+ input [(c_width_a*8)-1:0] def_data;
+
+ integer index,i,j;
+ reg [3:0] bin;
+
+ begin
+ index = 0;
+ hexstr_conv = 'b0;
+ for( i=c_width_a-1; i>=0; i=i-1 )
+ begin
+ case (def_data[7:0])
+ 8'b00000000 :
+ begin
+ bin = 4'b0000;
+ i = -1;
+ end
+ 8'b00110000 : bin = 4'b0000;
+ 8'b00110001 : bin = 4'b0001;
+ 8'b00110010 : bin = 4'b0010;
+ 8'b00110011 : bin = 4'b0011;
+ 8'b00110100 : bin = 4'b0100;
+ 8'b00110101 : bin = 4'b0101;
+ 8'b00110110 : bin = 4'b0110;
+ 8'b00110111 : bin = 4'b0111;
+ 8'b00111000 : bin = 4'b1000;
+ 8'b00111001 : bin = 4'b1001;
+ 8'b01000001 : bin = 4'b1010;
+ 8'b01000010 : bin = 4'b1011;
+ 8'b01000011 : bin = 4'b1100;
+ 8'b01000100 : bin = 4'b1101;
+ 8'b01000101 : bin = 4'b1110;
+ 8'b01000110 : bin = 4'b1111;
+ 8'b01100001 : bin = 4'b1010;
+ 8'b01100010 : bin = 4'b1011;
+ 8'b01100011 : bin = 4'b1100;
+ 8'b01100100 : bin = 4'b1101;
+ 8'b01100101 : bin = 4'b1110;
+ 8'b01100110 : bin = 4'b1111;
+ default :
+ begin
+ $display("ERROR : NOT A HEX CHARACTER");
+ bin = 4'bx;
+ end
+ endcase
+ for( j=0; j<4; j=j+1)
+ begin
+ if ((index*4)+j < c_width_a)
+ begin
+ hexstr_conv[(index*4)+j] = bin[j];
+ end
+ end
+ index = index + 1;
+ def_data = def_data >> 8;
+ end
+ end
+ endfunction
+
+ function [c_width_b-1:0] hexstr_conv_b;
+ input [(c_width_b*8)-1:0] def_data;
+
+ integer index,i,j;
+ reg [3:0] bin;
+
+ begin
+ index = 0;
+ hexstr_conv_b = 'b0;
+ for( i=c_width_b-1; i>=0; i=i-1 )
+ begin
+ case (def_data[7:0])
+ 8'b00000000 :
+ begin
+ bin = 4'b0000;
+ i = -1;
+ end
+ 8'b00110000 : bin = 4'b0000;
+ 8'b00110001 : bin = 4'b0001;
+ 8'b00110010 : bin = 4'b0010;
+ 8'b00110011 : bin = 4'b0011;
+ 8'b00110100 : bin = 4'b0100;
+ 8'b00110101 : bin = 4'b0101;
+ 8'b00110110 : bin = 4'b0110;
+ 8'b00110111 : bin = 4'b0111;
+ 8'b00111000 : bin = 4'b1000;
+ 8'b00111001 : bin = 4'b1001;
+ 8'b01000001 : bin = 4'b1010;
+ 8'b01000010 : bin = 4'b1011;
+ 8'b01000011 : bin = 4'b1100;
+ 8'b01000100 : bin = 4'b1101;
+ 8'b01000101 : bin = 4'b1110;
+ 8'b01000110 : bin = 4'b1111;
+ 8'b01100001 : bin = 4'b1010;
+ 8'b01100010 : bin = 4'b1011;
+ 8'b01100011 : bin = 4'b1100;
+ 8'b01100100 : bin = 4'b1101;
+ 8'b01100101 : bin = 4'b1110;
+ 8'b01100110 : bin = 4'b1111;
+ default :
+ begin
+ $display("ERROR : NOT A HEX CHARACTER");
+ bin = 4'bx;
+ end
+ endcase
+ for( j=0; j<4; j=j+1)
+ begin
+ if ((index*4)+j < c_width_b)
+ begin
+ hexstr_conv_b[(index*4)+j] = bin[j];
+ end
+ end
+ index = index + 1;
+ def_data = def_data >> 8;
+ end
+ end
+ endfunction
+
+
+
+
+
+// Initialize memory contents to 0 for now .
+
+ initial begin
+
+ sinita_value = 'b0 ;
+ sinitb_value = 'b0 ;
+
+ default_data = hexstr_conv(c_default_data);
+ if (c_has_sinita == 1 )
+ sinita_value = hexstr_conv(c_sinita_value);
+ if (c_has_sinitb == 1 )
+ sinitb_value = hexstr_conv_b(c_sinitb_value);
+ for(i = 0; i < c_depth_a; i = i + 1)
+ ram_temp[i] = default_data;
+ if (c_has_default_data == 0)
+ $readmemb(c_mem_init_file, ram_temp) ;
+
+ for(i = 0; i < c_depth_a; i = i + 1)
+ for(j = 0; j < c_width_a; j = j + 1)
+ begin
+ bitval = (1'b1 << j);
+ mem[(i*c_width_a) + j] = (ram_temp[i] & bitval) >> j;
+ end
+ recovery_a = 0;
+ recovery_b = 0;
+ for (k = 0; k <= c_pipe_stages_a; k = k + 1)
+ pipelinea[k] = sinita_value ;
+ for (l = 0; l <= c_pipe_stages_b; l = l + 1)
+ pipelineb[l] = sinitb_value ;
+ for (m = 0; m <= c_pipe_stages_a; m = m + 1)
+ sub_rdy_a[m] = 0 ;
+ for (n = 0; n <= c_pipe_stages_b; n = n + 1)
+ sub_rdy_b[n] = 0 ;
+ doa_out = sinita_value ;
+ dob_out = sinitb_value ;
+ nda_q = 0;
+ ndb_q = 0;
+ new_data_a_q = 0 ;
+ new_data_b_q = 0 ;
+ dia_q = 0;
+ dib_q = 0;
+ addra_q = 0;
+ addrb_q = 0;
+ wea_q = 0;
+ web_q = 0;
+ end
+
+
+ always @(addra_int or addrb_int) begin // check address collision
+ address_collision <= 1'b0;
+ for (ci = 0; ci < c_width_a; ci = ci + 1) begin // absolute address A
+ for (cj = 0; cj < c_width_b; cj = cj + 1) begin // absolute address B
+ if ((addra_int * c_width_a + ci) == (addrb_int * c_width_b + cj)) begin
+ address_collision <= 1'b1;
+ end
+ end
+ end
+ end
+
+ // Data
+ always @(posedge recovery_a or posedge recovery_b) begin
+ if (((wr_mode_a == 2'b01) && (wr_mode_b == 2'b01)) ||
+ ((wr_mode_a != 2'b01) && (wr_mode_b != 2'b01))) begin
+ if (wea_int == 1 && web_int == 1) begin
+ if (addra_int < c_depth_a)
+ for (dmi = 0; dmi < c_width_a; dmi = dmi + 1) begin
+ for (dmj = 0; dmj < c_width_b; dmj = dmj + 1) begin
+ if ((addra_int * c_width_a + dmi) == (addrb_int * c_width_b + dmj)) begin
+ mem[addra_int * c_width_a + dmi] <= 1'bX;
+ end
+ end
+ end
+ else
+ $display("Warning : Memory out of range");
+ end
+ end
+ recovery_a <= 0;
+ recovery_b <= 0;
+ end
+
+ always @(posedge recovery_a or posedge recovery_b) begin
+ if ((wr_mode_a == 2'b01) && (wr_mode_b != 2'b01)) begin
+ if (wea_int == 1 && web_int == 1) begin
+ if (addra_int < c_depth_a)
+ for (dni = 0; dni < c_width_a; dni = dni + 1) begin
+ for (dnj = 0; dnj < c_width_b; dnj = dnj + 1) begin
+ if ((addra_int * c_width_a + dni) == (addrb_int * c_width_b + dnj)) begin
+ mem[addra_int * c_width_a + dni] <= dia_int[dni];
+ end
+ end
+ end
+ else
+ $display("Warning : Memory out of range");
+ end
+ end
+ end
+
+ always @(posedge recovery_a or posedge recovery_b) begin
+ if ((wr_mode_a != 2'b01) && (wr_mode_b == 2'b01)) begin
+ if (wea_int == 1 && web_int == 1) begin
+ if (addrb_int < c_depth_b)
+ for (doi = 0; doi < c_width_a; doi = doi + 1) begin
+ for (doj = 0; doj < c_width_b; doj = doj + 1) begin
+ if ((addra_int * c_width_a + doi) == (addrb_int * c_width_b + doj)) begin
+ mem[addrb_int * c_width_b + doj] <= dib_int[doj];
+ end
+ end
+ end
+ else
+ $display("Warning : Memory out of range");
+ end
+ end
+ end
+
+ always @(posedge recovery_a or posedge recovery_b) begin
+ if ((wr_mode_b == 2'b00) || (wr_mode_b == 2'b10)) begin
+ if ((wea_int == 0) && (web_int == 1) && (ssra_int == 0)) begin
+ if (addra_int < c_depth_a)
+ for (dai = 0; dai < c_width_a; dai = dai + 1) begin
+ for (daj = 0; daj < c_width_b; daj = daj + 1) begin
+ if ((addra_int * c_width_a + dai) == (addrb_int * c_width_b + daj)) begin
+ doa_out[dai] <= 1'bX;
+ end
+ end
+ end
+ else
+ $display("Warning : Memory out of range");
+ end
+ end
+ end
+
+ always @(posedge recovery_a or posedge recovery_b) begin
+ if ((wr_mode_a == 2'b00) || (wr_mode_a == 2'b10)) begin
+ if ((wea_int == 1) && (web_int == 0) && (ssrb_int == 0)) begin
+ if (addrb_int < c_depth_b)
+ for (dbi = 0; dbi < c_width_a; dbi = dbi + 1) begin
+ for (dbj = 0; dbj < c_width_b; dbj = dbj + 1) begin
+ if ((addra_int * c_width_a + dbi) == (addrb_int * c_width_b + dbj)) begin
+ dob_out[dbj] <= 1'bX;
+ end
+ end
+ end
+ else
+ $display("Warning : Memory out of range");
+ end
+ end
+ end
+
+ always @(posedge recovery_a or posedge recovery_b) begin
+ if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) ||
+ ((wr_mode_a != 2'b10) && (wr_mode_b == 2'b10)) ||
+ ((wr_mode_a == 2'b01) && (wr_mode_b == 2'b00))) begin
+ if ((wea_int == 1) && (web_int == 1) && (ssra_int == 0)) begin
+ if (addra_int < c_depth_a)
+ for (dci = 0; dci < c_width_a; dci = dci + 1) begin
+ for (dcj = 0; dcj < c_width_b; dcj = dcj + 1) begin
+ if ((addra_int * c_width_a + dci) == (addrb_int * c_width_b + dcj)) begin
+ doa_out[dci] <= 1'bX;
+ end
+ end
+ end
+ else
+ $display("Warning : Memory out of range");
+ end
+ end
+ end
+
+ always @(posedge recovery_a or posedge recovery_b) begin
+ if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) ||
+ ((wr_mode_a == 2'b10) && (wr_mode_b != 2'b10)) ||
+ ((wr_mode_a == 2'b00) && (wr_mode_b == 2'b01))) begin
+ if ((wea_int == 1) && (web_int == 1) && (ssrb_int == 0)) begin
+ if (addrb_int < c_depth_b)
+ for (ddi = 0; ddi < c_width_a; ddi = ddi + 1) begin
+ for (ddj = 0; ddj < c_width_b; ddj = ddj + 1) begin
+ if ((addra_int * c_width_a + ddi) == (addrb_int * c_width_b + ddj)) begin
+ dob_out[ddj] <= 1'bX;
+ end
+ end
+ end
+ else
+ $display("Warning : Memory out of range");
+ end
+ end
+ end
+
+ // Parity Section is deleted
+
+ initial begin
+ case (c_write_modea)
+ `c_write_first : wr_mode_a <= 2'b00;
+ `c_read_first : wr_mode_a <= 2'b01;
+ `c_no_change : wr_mode_a <= 2'b10;
+ default : begin
+ $display("Error : c_write_modea = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.", c_write_modea);
+ $finish;
+ end
+ endcase
+ end
+
+ initial begin
+ case (c_write_modeb)
+ `c_write_first : wr_mode_b <= 2'b00;
+ `c_read_first : wr_mode_b <= 2'b01;
+ `c_no_change : wr_mode_b <= 2'b10;
+ default : begin
+ $display("Error : c_write_modeb = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.", c_write_modeb);
+ $finish;
+ end
+ endcase
+ end
+
+// Port A
+
+
+// Generate ouput control signals for Port A: RFDA and RDYA
+
+ always @ (rfda_int or rdya_int)
+ begin
+ if (c_has_rfda == 1)
+ RFDA = rfda_int ;
+ else
+ RFDA = 1'b0 ;
+
+ if ((c_has_rdya == 1) && (c_has_nda == 1) && (c_has_rfda == 1) )
+ RDYA = rdya_int;
+ else
+ RDYA = 1'b0 ;
+ end
+
+ always @ (ena_int )
+ begin
+ if (ena_int == 1'b1)
+ rfda_int <= 1'b1 ;
+ else
+ rfda_int <= 1'b0 ;
+ end
+
+// Gate nd signal with en
+
+ assign nda_int = ena_int && nda_i ;
+
+// Register hanshaking signals for port A
+
+ always @ (posedge clka_int)
+ begin
+ if (ena_int == 1'b1)
+ begin
+ if (ssra_int == 1'b1)
+ nda_q <= 1'b0 ;
+ else
+ nda_q <= nda_int ;
+ end
+ else
+ nda_q <= nda_q ;
+ end
+
+// Register data/ address / we inputs for port A
+
+ always @ (posedge clka_int)
+ begin
+ if (ena_int == 1'b1)
+ begin
+ dia_q <= dia_i ;
+ addra_q <= addra_i ;
+ wea_q <= wea_i ;
+ end
+ end
+
+
+// Select registered or non-registered write enable for Port A
+
+ always @ ( wea_i or wea_q )
+ begin
+ if (c_reg_inputsa == 1)
+ wea_int = wea_q ;
+ else
+ wea_int = wea_i ;
+ end
+
+// Select registered or non-registered data/address/nd inputs for Port A
+
+ always @ ( dia_i or dia_q )
+ begin
+ if ( c_reg_inputsa == 1)
+ dia_int = dia_q;
+ else
+ dia_int = dia_i;
+ end
+
+ always @ ( addra_i or addra_q or nda_q or nda_int )
+ begin
+ if ( c_reg_inputsa == 1)
+ begin
+ addra_int = addra_q ;
+ new_data_a = nda_q ;
+ end
+ else
+ begin
+ addra_int = addra_i;
+ new_data_a = nda_int ;
+ end
+ end
+
+// Register the new_data signal for Port A to track the synchronous RAM output
+
+ always @(posedge clka_int)
+ begin
+ if (ena_int == 1'b1)
+ begin
+ if (ssra_int == 1'b1)
+ new_data_a_q <= 1'b0 ;
+ else
+ new_data_a_q <= new_data_a ;
+ end
+ end
+
+// Generate data outputs for Port A
+
+ always @(posedge clka_int) begin
+ if (ena_int == 1'b1) begin
+ if (ssra_int == 1'b1) begin
+ for ( ai = 0; ai < c_width_a; ai = ai + 1)
+ doa_out[ai] <= sinita_value[ai];
+ end
+ else begin
+ if (wea_int == 1'b1) begin
+ if (wr_mode_a == 2'b00) begin
+ if (addra_int < c_depth_a)
+ for ( aj = 0; aj < c_width_a; aj = aj + 1)
+ doa_out[aj] <= dia_int[aj] ;
+ else
+ $display("Warning : Memory out of range");
+ end
+ else if (wr_mode_a == 2'b01) begin
+ if (addra_int < c_depth_a)
+ for ( ak = 0; ak < c_width_a; ak = ak + 1)
+ doa_out[ak] <= mem[(addra_int*c_width_a) + ak];
+ else
+ $display("Warning : Memory out of range");
+ end
+ else begin
+ if (addra_int < c_depth_a)
+ doa_out <= doa_out;
+ else
+ $display("Warning : Memory out of range");
+ end
+ end
+ else begin
+ if (addra_int < c_depth_a)
+ for ( al = 0; al < c_width_a; al = al + 1)
+ doa_out[al] <= mem[(addra_int*c_width_a) + al];
+ else
+ $display("Warning : Memory out of range");
+ end
+ end
+ end
+ end
+
+ always @(posedge clka_int) begin
+ if (ena_int == 1'b1 && wea_int == 1'b1) begin
+ if (addra_int < c_depth_a)
+ for ( am = 0; am < c_width_a; am = am + 1)
+ mem[(addra_int*c_width_a) + am] <= dia_int[am];
+ else
+ $display("Warning : Memory out of range");
+ end
+ end
+
+ // output pipelines for Port A
+
+ always @(posedge clka_int) begin
+ if (ena_int == 1'b1)
+ begin
+ for (i = c_pipe_stages_a; i > 1; i = i -1 )
+ begin
+ if (ssra_int == 1'b1 && ena_int == 1'b1 )
+ begin
+ pipelinea[i] <= sinita_value ;
+ sub_rdy_a[i] <= 0 ;
+ end
+ else
+ begin
+ pipelinea[i] <= pipelinea[i-1] ;
+ sub_rdy_a[i] <= sub_rdy_a[i-1] ;
+ end
+ end
+ if (ssra_int == 1'b1 && ena_int == 1'b1 )
+ begin
+ pipelinea[1]<= sinita_value ;
+ sub_rdy_a[1] <= 0 ;
+ end
+ else
+ begin
+ pipelinea[1] <= doa_out ;
+ sub_rdy_a[1] <= new_data_a_q ;
+ end
+ end
+ end
+
+// Select pipeline output if c_pipe_stages_a > 0
+
+ always @( pipelinea[c_pipe_stages_a] or sub_rdy_a[c_pipe_stages_a] or new_data_a_q or doa_out ) begin
+ if (c_pipe_stages_a == 0 )
+ begin
+ douta_out = doa_out ;
+ rdya_int = new_data_a_q;
+ end
+ else
+ begin
+ douta_out = pipelinea[c_pipe_stages_a];
+ rdya_int = sub_rdy_a[c_pipe_stages_a];
+ end
+ end
+
+
+ // Select Port A data outputs based on c_has_douta parameter
+
+ always @( douta_out ) begin
+ if ( c_has_douta == 1)
+ douta_mux_out = douta_out ;
+ else
+ douta_mux_out = 0 ;
+ end
+
+
+
+// Port B
+
+
+
+// Generate output control signals for Port B: RFDB and RDYB
+
+ always @ (rfdb_int or rdyb_int)
+ begin
+ if (c_has_rfdb == 1)
+ RFDB = rfdb_int ;
+ else
+ RFDB = 1'b0 ;
+
+ if ((c_has_rdyb == 1) && (c_has_ndb == 1) && (c_has_rfdb == 1) )
+ RDYB = rdyb_int;
+ else
+ RDYB = 1'b0 ;
+ end
+
+ always @ (enb_int )
+ begin
+ if ( enb_int == 1'b1 )
+ rfdb_int = 1'b1 ;
+ else
+ rfdb_int = 1'b0 ;
+ end
+
+// Gate nd signal with en
+
+ assign ndb_int = enb_int && ndb_i ;
+
+// Register hanshaking signals for port B
+
+ always @ (posedge clkb_int)
+ begin
+ if (enb_int == 1'b1)
+ begin
+ if (ssrb_int == 1'b1)
+ ndb_q <= 1'b0 ;
+ else
+ ndb_q <= ndb_int ;
+ end
+ else
+ ndb_q <= ndb_q;
+ end
+
+// Register data / address / we inputs for port B
+
+ always @ (posedge clkb_int)
+ begin
+ if (enb_int == 1'b1)
+ begin
+ dib_q <= dib_i ;
+ addrb_q <= addrb_i ;
+ web_q <= web_i ;
+ end
+ end
+
+// Select registered or non-registered write enable for port B
+
+ always @ (web_i or web_q )
+ begin
+ if (c_reg_inputsb == 1)
+ web_int = web_q ;
+ else
+ web_int = web_i ;
+ end
+
+
+
+// Select registered or non-registered data/address/nd inputs for Port B
+
+ always @ ( dib_i or dib_q )
+ begin
+ if ( c_reg_inputsb == 1)
+ dib_int = dib_q;
+ else
+ dib_int = dib_i;
+ end
+
+ always @ ( addrb_i or addrb_q or ndb_q or ndb_int)
+ begin
+ if ( c_reg_inputsb == 1)
+ begin
+ addrb_int = addrb_q ;
+ new_data_b = ndb_q ;
+ end
+ else
+ begin
+ addrb_int = addrb_i;
+ new_data_b = ndb_int ;
+ end
+ end
+
+// Register the new_data signal for Port B to track the synchronous RAM output
+
+ always @(posedge clkb_int)
+ begin
+ if (enb_int == 1'b1 )
+ begin
+ if (ssrb_int == 1'b1)
+ new_data_b_q <= 1'b0 ;
+ else
+ new_data_b_q <= new_data_b ;
+ end
+ end
+
+
+
+
+
+// Generate data outputs for Port B
+
+ always @(posedge clkb_int) begin
+ if (enb_int == 1'b1) begin
+ if (ssrb_int == 1'b1) begin
+ for (bi = 0; bi < c_width_b; bi = bi + 1)
+ dob_out[bi] <= sinitb_value[bi];
+ end
+ else begin
+ if (web_int == 1'b1) begin
+ if (wr_mode_b == 2'b00) begin
+ if (addrb_int < c_depth_b)
+ for (bj = 0; bj < c_width_b; bj = bj + 1)
+ dob_out[bj] <= dib_int[bj];
+ else
+ $display("Warning : Memory out of range");
+ end
+ else if (wr_mode_b == 2'b01) begin
+ if (addrb_int < c_depth_b)
+ for (bk = 0; bk < c_width_b; bk = bk + 1)
+ dob_out[bk] <= mem[(addrb_int*c_width_b) + bk];
+ else
+ $display("Warning : Memory out of range");
+ end
+ else begin
+ if (addrb_int < c_depth_b)
+ dob_out <= dob_out ;
+ else
+ $display("Warning : Memory out of range");
+ end
+ end
+ else begin
+ if (addrb_int < c_depth_b)
+ for (bl = 0; bl < c_width_b; bl = bl + 1)
+ dob_out[bl] <= mem[(addrb_int*c_width_b) + bl];
+ else
+ $display("Warning : Memory out of range");
+ end
+ end
+ end
+ end
+
+ always @(posedge clkb_int) begin
+ if (enb_int == 1'b1 && web_int == 1'b1) begin
+ if (addrb_int < c_depth_b)
+ for (bm = 0; bm < c_width_b; bm = bm + 1)
+ mem[(addrb_int*c_width_b) + bm] <= dib_int[bm];
+ else
+ $display("Warning : Memory out of range");
+ end
+ end
+
+ // output pipelines for Port B
+
+ always @(posedge clkb_int) begin
+ if (enb_int == 1'b1)
+ begin
+ for (j = c_pipe_stages_b; j > 1; j = j -1 )
+ begin
+ if (ssrb_int == 1'b1 && enb_int == 1'b1 )
+ begin
+ pipelineb[j] <= sinitb_value ;
+ sub_rdy_b[j] <= 0 ;
+ end
+ else
+ begin
+ pipelineb[j] <= pipelineb[j-1] ;
+ sub_rdy_b[j] <= sub_rdy_b[j-1] ;
+ end
+ end
+ if (ssrb_int == 1'b1 && enb_int == 1'b1)
+ begin
+ pipelineb[1] <= sinitb_value ;
+ sub_rdy_b[1] <= 0 ;
+ end
+ else
+ begin
+ pipelineb[1] <= dob_out ;
+ sub_rdy_b[1] <= new_data_b_q ;
+ end
+ end
+ end
+
+// Select pipeline for B if c_pipe_stages_b > 0
+
+ always @(pipelineb[c_pipe_stages_b] or sub_rdy_b[c_pipe_stages_b] or new_data_b_q or dob_out) begin
+ if ( c_pipe_stages_b == 0 )
+ begin
+ doutb_out = dob_out ;
+ rdyb_int = new_data_b_q;
+ end
+ else
+ begin
+ rdyb_int = sub_rdy_b[c_pipe_stages_b];
+ doutb_out = pipelineb[c_pipe_stages_b];
+ end
+ end
+
+
+// Select Port B data outputs based on c_has_doutb parameter
+
+ always @( doutb_out) begin
+ if ( c_has_doutb == 1)
+ doutb_mux_out = doutb_out ;
+ else
+ doutb_mux_out = 0 ;
+ end
+
+
+
+
+
+ specify
+ $recovery (posedge CLKB, posedge CLKA &&& collision, 1, recovery_b);
+ $recovery (posedge CLKA, posedge CLKB &&& collision, 1, recovery_a);
+ endspecify
+
+endmodule
+
+`endcelldefine
trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/blkmemdp_v3_0.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_GATE_BIT_V3_0.v
===================================================================
--- trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_GATE_BIT_V3_0.v (nonexistent)
+++ trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_GATE_BIT_V3_0.v (revision 784)
@@ -0,0 +1,426 @@
+/* $Id: C_GATE_BIT_V3_0.v,v 1.1 2002-03-28 20:50:04 lampret Exp $
+--
+-- Filename - C_GATE_BIT_V3_0.v
+-- Author - Xilinx
+-- Creation - 25 Jan 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BIT_V3_0 module
+*/
+
+`ifdef C_GATE_BIT_V3_0_DEF
+`else
+`define C_GATE_BIT_V3_0_DEF
+
+`ifdef C_REG_FD_V3_0_DEF
+`else
+`include "XilinxCoreLib/C_REG_FD_V3_0.v"
+`endif
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_and 0
+`define c_nand 1
+`define c_or 2
+`define c_nor 3
+`define c_xor 4
+`define c_xnor 5
+
+module C_GATE_BIT_V3_0 (I, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q);
+
+ parameter C_AINIT_VAL = "0";
+ parameter C_ENABLE_RLOCS = 0;
+ parameter C_GATE_TYPE = `c_and;
+ parameter C_HAS_ACLR = 0;
+ parameter C_HAS_AINIT = 0;
+ parameter C_HAS_ASET = 0;
+ parameter C_HAS_CE = 0;
+ parameter C_HAS_O = 0;
+ parameter C_HAS_Q = 1;
+ parameter C_HAS_SCLR = 0;
+ parameter C_HAS_SINIT = 0;
+ parameter C_HAS_SSET = 0;
+ parameter C_INPUTS = 2;
+ parameter C_INPUT_INV_MASK = "";
+ parameter C_PIPE_STAGES = 0;
+ parameter C_SINIT_VAL = "0";
+ parameter C_SYNC_ENABLE = `c_override;
+ parameter C_SYNC_PRIORITY = `c_clear;
+
+
+ input [C_INPUTS-1 : 0] I;
+ input CLK;
+ input CE;
+ input ACLR;
+ input ASET;
+ input AINIT;
+ input SCLR;
+ input SSET;
+ input SINIT;
+ output O;
+ output Q;
+
+ // Internal values to drive signals when input is missing
+ wire intCE;
+ reg intO;
+ wire intQ;
+ reg lastCLK;
+
+ reg [C_PIPE_STAGES+2 : 0] intQpipe;
+ reg intQpipeend;
+
+ wire Q = (C_HAS_Q == 1 ? intQ : 1'bx);
+ wire O = (C_HAS_O == 1 ? intO : 1'bx);
+
+ // Sort out default values for missing ports
+
+ assign intCE = defval(CE, C_HAS_CE, 1);
+
+ integer j;
+ integer pipe;
+
+ reg [C_INPUTS-1 : 0] tmpsig;
+ reg tmpres;
+
+ // Output register
+ C_REG_FD_V3_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+ C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+ C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+ reg1 (.D(intQpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+ .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+ .Q(intQ));
+
+ initial
+ begin
+
+ #1;
+
+ intQpipe = 'b0;
+
+ if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate?
+ tmpres = 1;
+ else
+ tmpres = 0;
+
+ tmpsig = to_bits(C_INPUT_INV_MASK);
+
+ for(j = 0; j < C_INPUTS; j = j + 1)
+ begin
+ if(tmpsig[j] == 1)
+ begin
+ if(C_GATE_TYPE == 0) // AND gate
+ begin
+ if(I[j] !== 1'bx)
+ tmpres = tmpres & ~I[j];
+ else if(tmpres === 1'b1)
+ tmpres = 1'bx;
+ end
+ else if(C_GATE_TYPE == 1) // NAND gate
+ begin
+ if(I[j] !== 1'bx)
+ tmpres = tmpres & ~I[j];
+ else if(tmpres === 1'b1)
+ tmpres = 1'bx;
+ end
+ else if(C_GATE_TYPE == 2) // OR gate
+ begin
+ if(I[j] !== 1'bx)
+ tmpres = tmpres | ~I[j];
+ else if(tmpres === 1'b0)
+ tmpres = 1'bx;
+ end
+ else if(C_GATE_TYPE == 3) // NOR gate
+ begin
+ if(I[j] !== 1'bx)
+ tmpres = tmpres | ~I[j];
+ else if(tmpres === 1'b0)
+ tmpres = 1'bx;
+ end
+ else if(C_GATE_TYPE == 4) // XOR gate
+ begin
+ if(I[j] !== 1'bx)
+ tmpres = tmpres ^ ~I[j];
+ else
+ tmpres = 1'bx;
+ end
+ else if(C_GATE_TYPE == 5) // XNOR gate
+ begin
+ if(I[j] !== 1'bx)
+ tmpres = tmpres ^ ~I[j];
+ else
+ tmpres = 1'bx;
+ end
+ end
+ else // No input inversion on bit j of input
+ begin
+ if(C_GATE_TYPE == 0) // AND gate
+ begin
+ if(I[j] !== 1'bx)
+ tmpres = tmpres & I[j];
+ else if(tmpres === 1'b1)
+ tmpres = 1'bx;
+ end
+ else if(C_GATE_TYPE == 1) // NAND gate
+ begin
+ if(I[j] !== 1'bx)
+ tmpres = tmpres & I[j];
+ else if(tmpres === 1'b1)
+ tmpres = 1'bx;
+ end
+ else if(C_GATE_TYPE == 2) // OR gate
+ begin
+ if(I[j] !== 1'bx)
+ tmpres = tmpres | I[j];
+ else if(tmpres === 1'b0)
+ tmpres = 1'bx;
+ end
+ else if(C_GATE_TYPE == 3) // NOR gate
+ begin
+ if(I[j] !== 1'bx)
+ tmpres = tmpres | I[j];
+ else if(tmpres === 1'b0)
+ tmpres = 1'bx;
+ end
+ else if(C_GATE_TYPE == 4) // XOR gate
+ begin
+ if(I[j] !== 1'bx)
+ tmpres = tmpres ^ I[j];
+ else
+ tmpres = 1'bx;
+ end
+ else if(C_GATE_TYPE == 5) // XNOR gate
+ begin
+ if(I[j] !== 1'bx)
+ tmpres = tmpres ^ I[j];
+ else
+ tmpres = 1'bx;
+ end
+ end
+ end
+
+ if(C_GATE_TYPE == 1 || C_GATE_TYPE == 3 || C_GATE_TYPE == 5)
+ tmpres = ~tmpres;
+
+ intO <= tmpres;
+
+ if(C_PIPE_STAGES < 2) // No pipeline
+ intQpipeend = intO;
+ else // Pipeline stages required
+ begin
+ intQpipeend = intQpipe[2];
+ end
+ end
+
+ always @(CLK)
+ lastCLK <= CLK;
+
+ always@(I)
+ begin
+ if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate?
+ tmpres = 1;
+ else
+ tmpres = 0;
+ for(j = 0; j < C_INPUTS; j = j + 1)
+ begin
+ if(tmpsig[j] == 1)
+ begin
+ if(C_GATE_TYPE == 0) // AND gate
+ begin
+ if(I[j] !== 1'bx)
+ tmpres = tmpres & ~I[j];
+ else if(tmpres === 1'b1)
+ tmpres = 1'bx;
+ end
+ else if(C_GATE_TYPE == 1) // NAND gate
+ begin
+ if(I[j] !== 1'bx)
+ tmpres = tmpres & ~I[j];
+ else if(tmpres === 1'b1)
+ tmpres = 1'bx;
+ end
+ else if(C_GATE_TYPE == 2) // OR gate
+ begin
+ if(I[j] !== 1'bx)
+ tmpres = tmpres | ~I[j];
+ else if(tmpres === 1'b0)
+ tmpres = 1'bx;
+ end
+ else if(C_GATE_TYPE == 3) // NOR gate
+ begin
+ if(I[j] !== 1'bx)
+ tmpres = tmpres | ~I[j];
+ else if(tmpres === 1'b0)
+ tmpres = 1'bx;
+ end
+ else if(C_GATE_TYPE == 4) // XOR gate
+ begin
+ if(I[j] !== 1'bx)
+ tmpres = tmpres ^ ~I[j];
+ else
+ tmpres = 1'bx;
+ end
+ else if(C_GATE_TYPE == 5) // XNOR gate
+ begin
+ if(I[j] !== 1'bx)
+ tmpres = tmpres ^ ~I[j];
+ else
+ tmpres = 1'bx;
+ end
+ end
+ else // No input inversion on bit j of input
+ begin
+ if(C_GATE_TYPE == 0) // AND gate
+ begin
+ if(I[j] !== 1'bx)
+ tmpres = tmpres & I[j];
+ else if(tmpres === 1'b1)
+ tmpres = 1'bx;
+ end
+ else if(C_GATE_TYPE == 1) // NAND gate
+ begin
+ if(I[j] !== 1'bx)
+ tmpres = tmpres & I[j];
+ else if(tmpres === 1'b1)
+ tmpres = 1'bx;
+ end
+ else if(C_GATE_TYPE == 2) // OR gate
+ begin
+ if(I[j] !== 1'bx)
+ tmpres = tmpres | I[j];
+ else if(tmpres === 1'b0)
+ tmpres = 1'bx;
+ end
+ else if(C_GATE_TYPE == 3) // NOR gate
+ begin
+ if(I[j] !== 1'bx)
+ tmpres = tmpres | I[j];
+ else if(tmpres === 1'b0)
+ tmpres = 1'bx;
+ end
+ else if(C_GATE_TYPE == 4) // XOR gate
+ begin
+ if(I[j] !== 1'bx)
+ tmpres = tmpres ^ I[j];
+ else
+ tmpres = 1'bx;
+ end
+ else if(C_GATE_TYPE == 5) // XNOR gate
+ begin
+ if(I[j] !== 1'bx)
+ tmpres = tmpres ^ I[j];
+ else
+ tmpres = 1'bx;
+ end
+ end
+ end
+
+ if(C_GATE_TYPE == 1 || C_GATE_TYPE == 3 || C_GATE_TYPE == 5)
+ tmpres = ~tmpres;
+
+ intO <= #1 tmpres;
+ end
+
+ always@(posedge CLK)
+ begin
+ if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines!
+ begin
+ for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1)
+ begin
+ intQpipe[pipe] <= intQpipe[pipe+1];
+ end
+ intQpipe[C_PIPE_STAGES] <= intO;
+ end
+ else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines!
+ begin
+ for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1)
+ begin
+ if(intQpipe[pipe] !== intQpipe[pipe+1])
+ intQpipe[pipe] <= 1'bx;
+ end
+ if(intQpipe[C_PIPE_STAGES] !== intO)
+ intQpipe[C_PIPE_STAGES] <= 1'bx;
+ end
+ end
+
+ always@(intO or intQpipe[2])
+ begin
+ if(C_PIPE_STAGES < 2) // No pipeline
+ intQpipeend <= intO;
+ else // Pipeline stages required
+ begin
+ intQpipeend <= intQpipe[2];
+ end
+ end
+
+ function defval;
+ input i;
+ input hassig;
+ input val;
+ begin
+ if(hassig == 1)
+ defval = i;
+ else
+ defval = val;
+ end
+ endfunction
+
+ function [C_INPUTS - 1 : 0] to_bits;
+ input [C_INPUTS*8 : 1] instring;
+ integer i;
+ begin
+ for(i = C_INPUTS; i > 0; i = i - 1)
+ begin // Is this character a '0'? (ASCII = 48 = 00110000)
+ if(instring[(i*8)] == 0 &&
+ instring[(i*8)-1] == 0 &&
+ instring[(i*8)-2] == 1 &&
+ instring[(i*8)-3] == 1 &&
+ instring[(i*8)-4] == 0 &&
+ instring[(i*8)-5] == 0 &&
+ instring[(i*8)-6] == 0 &&
+ instring[(i*8)-7] == 0)
+ to_bits[i-1] = 0;
+ // Or is it a '1'?
+ else if(instring[(i*8)] == 0 &&
+ instring[(i*8)-1] == 0 &&
+ instring[(i*8)-2] == 1 &&
+ instring[(i*8)-3] == 1 &&
+ instring[(i*8)-4] == 0 &&
+ instring[(i*8)-5] == 0 &&
+ instring[(i*8)-6] == 0 &&
+ instring[(i*8)-7] == 1)
+
+ to_bits[i-1] = 1;
+ // Or is it a ' '? (a null char - in which case insert a '0')
+ else if(instring[(i*8)] == 0 &&
+ instring[(i*8)-1] == 0 &&
+ instring[(i*8)-2] == 0 &&
+ instring[(i*8)-3] == 0 &&
+ instring[(i*8)-4] == 0 &&
+ instring[(i*8)-5] == 0 &&
+ instring[(i*8)-6] == 0 &&
+ instring[(i*8)-7] == 0)
+ to_bits[i-1] = 0;
+ else
+ begin
+ $display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring);
+ $finish;
+ end
+ end
+ end
+ endfunction
+
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_and
+`undef c_nand
+`undef c_or
+`undef c_nor
+`undef c_xor
+`undef c_xnor
+
+`endif
trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_GATE_BIT_V3_0.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/async_fifo_v3_0.v
===================================================================
--- trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/async_fifo_v3_0.v (nonexistent)
+++ trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/async_fifo_v3_0.v (revision 784)
@@ -0,0 +1,2649 @@
+// ************************************************************************
+// $Id: async_fifo_v3_0.v,v 1.1 2002-03-28 20:50:04 lampret Exp $
+// ************************************************************************
+// Copyright 2000 - Xilinx, Inc.
+// All rights reserved.
+// ************************************************************************
+//-- Filename: async_fifo_v3_0.v
+//-- Author : Xilinx, Inc.
+//-- Creation ; Sept. 7th, 1999
+//-- Description: This file contains the verilog behavioral model for the asynchornous fifo core.
+//**********************************************************************************************//
+//**********************************************************************************************//
+// Last Change : 11/15/99 VK: Removing references to c_ports_differ and c_read_width etc. //
+// : 12/01/99 CE: Added XCS Header (Id), cleaned up code (removed comments etc.) //
+// : 12/01/99 CE: Removed timescale directive //
+// : 12/07/99 CE: Fixes for CR 118497 //
+// : 12/15/99 CE: Fix for CR 118819, behavioral model of C_COUNTER_BINARY changed //
+// : 12/16/99 CE: Added initial values to all four flag registers //
+// : 1/28/00 VK: Capitalised top level module name, ports names //
+// : 5/08/00 CE: V1 to V2 Conversion //
+// : 5/18/00 CE: Delayed WR_EN & RD_EN inputs, for simulation functionality //
+// : 6/12/00 CE: Added C_HAS_QDP0(SPO)_RST parameters (C_DIST_MEM_V3_0) //
+// : 06/12/00 CE: V1 to V3 conversions //
+// : 06/20/00 CE: Fix for CR124696 & CR124692 & CR124109 //
+// : 08/11/00 KM: V2 to V3 conversions //
+//**********************************************************************************************//
+/* ***************************************************************************
+ * Last Modified 09/26/00 by jogden
+ * : Updated to new block memory and fixed CR.
+ *
+ * jogden 10/4/00 Placed module declaration all on one line.
+ * robertle 10/13/00 Changed all V2 to V3
+ * robertle 10/16/00 Add 1 to C_LATENCY for C_ADDSUB_V3
+ * robertle 10/19/00 Fix Port size problem in memory block
+ * **************************************************************************/
+//`timescale 1 ns/10ps
+
+`define true 1
+`define false 0
+
+`ifdef async_fifo_v3_0_def
+`else
+`define async_fifo_v3_0_def
+
+
+
+`ifdef C_REG_FD_V3_0_DEF
+`else
+`include "XilinxCoreLib/C_REG_FD_V3_0.v"
+`define C_REG_FD_V3_0_DEF
+`endif
+
+`ifdef C_GATE_BIT_V3_0_DEF
+`else
+`include "XilinxCoreLib/C_GATE_BIT_V3_0.v"
+`define C_GATE_BIT_V3_0_DEF
+`endif
+
+`ifdef C_ADDSUB_V3_0_DEF
+`else
+`include "XilinxCoreLib/C_ADDSUB_V3_0.v"
+`define C_ADDSUB_V3_0_DEF
+`endif
+
+
+`ifdef C_COMPARE_V3_0_DEF
+`else
+`include "XilinxCoreLib/C_COMPARE_V3_0.v"
+`define C_COMPARE_V3_0_DEF
+`endif
+
+
+`ifdef C_MUX_BUS_V3_0_DEF
+`else
+`include "XilinxCoreLib/C_MUX_BUS_V3_0.v"
+`define C_MUX_BUS_V3_0_DEF
+`endif
+
+
+`ifdef C_COUNTER_BINARY_V3_0_DEF
+`else
+`include "XilinxCoreLib/C_COUNTER_BINARY_V3_0.v"
+`define C_COUNTER_BINARY_V3_0_DEF
+`endif
+
+`ifdef C_DIST_MEM_V3_0_DEF
+`else
+`include "XilinxCoreLib/C_DIST_MEM_V3_0.v"
+`define C_DIST_MEM_V3_0_DEF
+`endif
+
+`ifdef C_BLKMEMDP_V3_0_DEF
+`else
+`include "XilinxCoreLib/blkmemdp_v3_0.v"
+`define C_BLKMEMDP_V3_0_DEF
+`endif
+
+
+
+`define width 6
+
+`define c_enable_rlocs 0
+`define c_data_width 16
+`define c_read_data_width 16
+`define c_ports_differ 0
+`define c_fifo_depth 63
+`define c_has_almost_full 1
+`define c_has_almost_empty 1
+`define c_has_wr_count 1
+`define c_has_rd_count 1
+`define c_wr_count_width 6
+`define c_rd_count_width 6
+`define c_has_rd_ack 1
+`define c_rd_ack_low 0
+`define c_has_rd_err 1
+`define c_rd_err_low 0
+`define c_has_wr_ack 1
+`define c_wr_ack_low 0
+`define c_has_wr_err 1
+`define c_wr_err_low 0
+`define c_use_blockmem 1
+
+
+
+
+
+
+ /* Memory Module */
+module memory_v2 (d, wa, ra, we, wclk, re, rclk, q);
+
+parameter use_blockmem =1; //= c_use_blockmem;
+parameter c_enable_rlocs =0; //= 0;
+parameter address_width =6; //= width;
+parameter rd_addr_width =6; //= width;
+parameter depth =64; //= c_fifo_depth +1;
+parameter rd_depth =64; //= c_fifo_depth +1;
+parameter data_width =16; //= c_data_width;
+parameter rd_data_width =16; //= c_data_width;
+
+
+input [data_width-1 : 0] d;
+input [address_width-1 : 0] wa;
+input [rd_addr_width-1 : 0] ra;
+input we;
+input wclk;
+input re;
+input rclk;
+output [rd_data_width-1 : 0] q;
+
+
+wire port_enabled;
+wire [data_width-1 : 0] sourceless;
+wire [address_width-1 : 0] sourceless_addr;
+wire [rd_data_width-1 : 0] sourceless_dib;
+wire sourceless_net;
+wire [data_width-1 : 0] spo_dummy;
+wire [data_width-1 : 0] qspo_dummy;
+wire [data_width-1 : 0] dpo_dummy;
+wire [data_width-1 : 0] doa_dummy_a;
+wire [data_width-1 : 0] doa_dummy_b;
+wire [rd_data_width-1 : 0] dob_bmem_a;
+wire [rd_data_width-1 : 0] dob_bmem_b;
+wire [rd_data_width-1 : 0] q_dist_mem;
+
+
+parameter zero = 8'b00110000; //ascii 0
+
+parameter default_data = {data_width{zero}};
+parameter default_rd_data = {rd_data_width{zero}};
+
+assign sourceless_net = 0;
+assign port_enabled = 1;
+assign sourceless_dib = {data_width-1{zero}};
+assign sourceless_addr = {address_width{zero}};
+
+
+/* ***************************************************************************
+ * Modified 9/26/00 by jogden
+ * Changed the block memory to blkmemdp_v3_0
+ * **************************************************************************/
+ wire unconnected_port;
+ wire [data_width-1 : 0] unconnected_douta;
+ wire [rd_data_width-1 : 0] unconnected_dinb;
+ wire unconnected_ena;
+ wire unconnected_nda;
+ wire unconnected_ndb;
+ wire unconnected_sinita;
+ wire unconnected_sinitb;
+ wire unconnected_web;
+
+ assign unconnected_dinb = {rd_data_width{zero}};
+ assign unconnected_ena = 1'b1;
+ assign unconnected_sinita = 1'b0;
+ assign unconnected_sinitb = 1'b0;
+ assign unconnected_web = 1'b0;
+
+
+BLKMEMDP_V3_0 #(
+ address_width, //c_addra_width
+ rd_addr_width, //c_addrb_width
+ default_data, //c_default_data
+ depth, //c_depth_a
+ rd_depth, //c_depth_b
+ 0, //c_enable_rlocs
+ 1, //c_has_default_data
+ 1, //c_has_dina
+ 0, //c_has_dinb
+ 0, //c_has_douta
+ 1, //c_has_doutb
+ 0, //c_has_ena
+ 1, //c_has_enb
+ 0, //c_has_limit_data_pitch
+ 0, //c_has_nda
+ 0, //c_has_ndb
+ 0, //c_has_rdya
+ 0, //c_has_rdyb
+ 0, //c_has_rfda
+ 0, //c_has_rfdb
+ 0, //c_has_sinita
+ 0, //c_has_sinitb
+ 1, //c_has_wea
+ 0, //c_has_web
+ 18, //c_limit_data_pitch
+ "null.mif" ,
+ 0, //c_pipe_stages_a
+ 0, //c_pipe_stages_b
+ 0, //c_reg_inputsa
+ 0, //c_reg_inputsb
+ default_data, //c_sinita_value
+ default_data, //c_sinitb_value
+ data_width, //c_width_a
+ rd_data_width, //c_width_b
+ 2, //c_write_modea
+ 2 //c_write_modeb
+ )
+ bmem_a (.ADDRA(wa),
+ .ADDRB(ra),
+ .CLKA(wclk),
+ .CLKB(rclk),
+ .DINA(d),
+ .DINB(sourceless_dib),
+ .DOUTA(unconnected_douta),
+ .DOUTB(dob_bmem_a),
+ .ENA(unconnected_ena),
+ .ENB(re),
+ .NDA(unconnected_nda),
+ .NDB(unconnected_ndb),
+ .RDYA(unconnected_port),
+ .RDYB(unconnected_port),
+ .RFDA(unconnected_port),
+ .RFDB(unconnected_port),
+ .SINITA(unconnected_sinita),
+ .SINITB(unconnected_sinitb),
+ .WEA(we),
+ .WEB(unconnected_web)
+ );
+
+/*
+blkmem1: IF (use_blockmem AND (address_width >= rd_addr_width)) GENERATE
+*/
+/*
+ C_MEM_DP_BLOCK_V1_0 #(
+ address_width,
+ rd_addr_width,
+ 1,
+ 1,
+ default_data,
+ depth,
+ rd_depth,
+ 1,
+ 1,
+ 0,
+ 1,
+ 1,
+ 0,
+ 1,
+ 1,
+ 1,
+ 0,
+ 0,
+ 1,
+ 1,
+ "null.mif",
+ 2,
+ 0,
+ 0,
+ 1,
+ 1,
+ 1,
+ 1,
+ data_width,
+ rd_data_width
+ )
+ bmem_a (.ADDRA(wa),
+ .ADDRB(ra),
+ .DIA(d),
+ .DIB(sourceless_dib),
+ .CLKA(wclk),
+ .CLKB(rclk),
+ .WEA(we),
+ .WEB(sourceless_net),
+ .ENA(port_enabled),
+ .ENB(re),
+ .RSTA(sourceless_net),
+ .RSTB(sourceless_net),
+ .DOA(doa_dummy_a),
+ .DOB(dob_bmem_a)
+ );
+
+*/
+
+/*
+blkmen2:IF (use_blockmem AND (address_width < rd_addr_width)) GENERATE
+--Swap all the ports (because depth of A port must be >= depth of B port)?
+--Only needed for the non-symmetric data port case
+*/
+
+/*
+
+ C_MEM_DP_BLOCK_V1_0 #(
+ address_width,
+ rd_addr_width,
+ 1,
+ 1,
+ default_rd_data,
+ rd_depth,
+ depth,
+ 1,
+ 1,
+ 0,
+ 1,
+ 1,
+ 0,
+ 1,
+ 1,
+ 1,
+ 0,
+ 0,
+ 1,
+ 1,
+ "null.mif",
+ 2,
+ 0,
+ 0,
+ 1,
+ 1,
+ 1,
+ 1,
+ rd_data_width,
+ data_width
+ )
+ bmem_b (.ADDRA(ra),
+ .ADDRB(wa),
+ .DIA(sourceless_dib),
+ .DIB(d),
+ .CLKA(rclk),
+ .CLKB(wclk),
+ .WEA(sourceless_net),
+ .WEB(we),
+ .ENA(re),
+ .ENB(port_enabled),
+ .RSTA(sourceless_net),
+ .RSTB(sourceless_net),
+ .DOA(dob_bmem_b),
+ .DOB(doa_dummy_b)
+ );
+*/
+
+
+/* ***************************************************************************
+ * END OF BLOCK MEMORY MODIFICATION (by jogden 9/26/00)
+ * **************************************************************************/
+
+
+
+
+ C_DIST_MEM_V3_0 #(address_width,
+ default_data,
+ 2, //c_default_data_radix
+ depth,
+ 1,
+ 0,
+ 1,
+ 1, //c_has_d
+ 0,
+ 1,
+ 0, //c_has_i_ce
+ 1,
+ 1,
+ 1,
+ 0, //c_has_qdpo_rst
+ 1, //c_has_qspo
+ 1,
+ 0, //c_has_qspo_rst
+ 0, //c_has_rd_en
+ 0,
+ 0,
+ 1,
+ "", //c_mem_init_file
+ 2,
+ 2,
+ 0,
+ 1,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ data_width,
+ 2
+ )
+ dist_mem (.A(wa),
+ .SPO(spo_dummy),
+ .QSPO(qspo_dummy),
+ .CLK(wclk),
+ .WE(we),
+ .RD_EN(sourceless_net),
+ .D(d),
+ .I_CE(sourceless_net),
+ .SPRA(sourceless_addr),
+ .DPRA(ra),
+ .DPO(dpo_dummy),
+ .QSPO_CE(sourceless_net),
+ .QDPO(q_dist_mem),
+ .QDPO_CLK(rclk),
+ .QDPO_CE(re)
+ );
+
+
+
+assign q = use_blockmem ? (address_width >= rd_addr_width ? dob_bmem_a : dob_bmem_b) : q_dist_mem;
+
+
+endmodule
+ /* End Memory Module */
+
+ /* Binary Counter Module. bcount_up_ainit.v */
+
+
+module bcount_up_ainit_v2 (init, cen, clk, cnt);
+
+
+parameter cnt_size = 6;
+parameter init_val ="000000";
+parameter c_enable_rlocs=1;
+
+wire gnd = 1'b0;
+wire vcc = 1'b1;
+parameter no =0;
+parameter yes =1;
+wire unused_1 = 1'b0;
+wire unused_2 = 1'b0;
+wire unused_3 = 1'b0;
+wire unused_4 = 1'b0;
+wire [cnt_size-1 : 0] dummy_val;
+
+
+input init;
+input cen;
+input clk;
+output [cnt_size-1 : 0] cnt;
+
+C_COUNTER_BINARY_V3_0 #(init_val,
+ "1",
+ 0,
+ init_val,
+ c_enable_rlocs,
+ no,
+ yes,
+ no,
+ yes,
+ no,
+ no,
+ no,
+ no,
+ no,
+ no,
+ no,
+ no,
+ no,
+ no,
+ no,
+ 0,
+ 0,
+ 1,
+ 0,
+ init_val,
+ 1,
+ 1,
+ init_val,
+ init_val,
+ cnt_size
+ )
+
+ count_bin (.Q(cnt),
+ .CLK(clk),
+ .UP(vcc),
+ .THRESH0(unused_1),
+ .Q_THRESH0(unused_2),
+ .THRESH1(unused_3),
+ .Q_THRESH1(unused_4),
+ .CE(cen),
+ .LOAD(gnd),
+ .L(dummy_val),
+ .IV(dummy_val),
+ .ACLR(gnd),
+ .ASET(gnd),
+ .AINIT(init),
+ .SCLR(gnd),
+ .SSET(gnd),
+ .SINIT(gnd)
+ );
+
+endmodule
+
+
+/* Behavioral description of binary_to_gray */
+module binary_to_gray_v2 (rst, clk, cen, bin, gray);
+
+parameter reg_size = 6;
+parameter init_val = "";
+parameter c_enable_rlocs = 1;
+
+input rst;
+input clk;
+input cen;
+input [reg_size-1:0] bin;
+output [reg_size-1:0] gray;
+
+reg [reg_size-1:0] AIV;
+reg [reg_size-1:0] gray;
+
+
+initial
+begin
+ AIV = to_bits(init_val);
+end
+
+
+always @(posedge clk or posedge rst)
+begin
+if (rst == 1'b1)
+ gray = AIV;
+else if (cen == 1'b1)
+ begin : loop
+ integer i;
+ for (i=0; i<=reg_size-1; i=i+1)
+ if (i == reg_size-1)
+ gray[i] = bin[i];
+ else
+ gray[i] = bin[i+1] ^ bin[i];
+ end
+end
+
+
+function [reg_size-1 : 0] to_bits;
+ input [reg_size*8 : 1] instring;
+ integer i;
+ integer non_null_string;
+ begin
+ non_null_string = 0;
+ for(i = reg_size; i > 0; i = i - 1)
+ begin // Is the string empty?
+ if(instring[(i*8)] == 0 &&
+ instring[(i*8)-1] == 0 &&
+ instring[(i*8)-2] == 0 &&
+ instring[(i*8)-3] == 0 &&
+ instring[(i*8)-4] == 0 &&
+ instring[(i*8)-5] == 0 &&
+ instring[(i*8)-6] == 0 &&
+ instring[(i*8)-7] == 0 &&
+ non_null_string == 0)
+ non_null_string = 0; // Use the return value to flag a non-empty string
+ else
+ non_null_string = 1; // Non-null character!
+ end
+ if(non_null_string == 0) // String IS empty! Just return the value to be all '0's
+ begin
+ for(i = reg_size; i > 0; i = i - 1)
+ to_bits[i-1] = 0;
+ end
+ else
+ begin
+ for(i = reg_size; i > 0; i = i - 1)
+ begin // Is this character a '0'? (ASCII = 48 = 00110000)
+ if(instring[(i*8)] == 0 &&
+ instring[(i*8)-1] == 0 &&
+ instring[(i*8)-2] == 1 &&
+ instring[(i*8)-3] == 1 &&
+ instring[(i*8)-4] == 0 &&
+ instring[(i*8)-5] == 0 &&
+ instring[(i*8)-6] == 0 &&
+ instring[(i*8)-7] == 0)
+ to_bits[i-1] = 0;
+ // Or is it a '1'?
+ else if(instring[(i*8)] == 0 &&
+ instring[(i*8)-1] == 0 &&
+ instring[(i*8)-2] == 1 &&
+ instring[(i*8)-3] == 1 &&
+ instring[(i*8)-4] == 0 &&
+ instring[(i*8)-5] == 0 &&
+ instring[(i*8)-6] == 0 &&
+ instring[(i*8)-7] == 1)
+ to_bits[i-1] = 1;
+ // Or is it a ' '? (a null char - in which case insert a '0')
+ else if(instring[(i*8)] == 0 &&
+ instring[(i*8)-1] == 0 &&
+ instring[(i*8)-2] == 0 &&
+ instring[(i*8)-3] == 0 &&
+ instring[(i*8)-4] == 0 &&
+ instring[(i*8)-5] == 0 &&
+ instring[(i*8)-6] == 0 &&
+ instring[(i*8)-7] == 0)
+ to_bits[i-1] = 0;
+ else
+ begin
+ $display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring);
+ $finish;
+ end
+ end
+ end
+ end
+ endfunction
+
+endmodule
+/* End Behavioral Description of Binary To Gray Module */
+
+
+/* Equality Comparator Module (eq_compare.v) */
+module eq_compare_v2 (a, b, eq);
+
+parameter c_width =6;
+parameter c_enable_rlocs=1;
+
+input [c_width-1 : 0] a;
+input [c_width-1 : 0] b;
+output eq;
+
+wire gnd = 1'b0;
+wire vcc = 1'b1;
+parameter no =0;
+parameter yes =1;
+parameter zero=1'b0;
+parameter dummy_val={c_width-1{zero}};
+
+
+wire dummy_out_1;
+wire dummy_out_2;
+wire dummy_out_3;
+wire dummy_out_4;
+wire dummy_out_5;
+wire dummy_out_6;
+wire dummy_out_7;
+wire dummy_out_8;
+wire dummy_out_9;
+wire dummy_out_10;
+wire dummy_out_11;
+
+C_COMPARE_V3_0 #( "",
+ no,
+ dummy_val,
+ 1,
+ c_enable_rlocs,
+ no,
+ no,
+ yes,
+ no,
+ no,
+ no,
+ no,
+ no,
+ no,
+ no,
+ no,
+ no,
+ no,
+ no,
+ no,
+ no,
+ no,
+ 1,
+ 1,
+ 1,
+ c_width)
+
+ eq_comp (.A(a),
+ .B(b),
+ .A_EQ_B(eq),
+ .CLK(gnd),
+ .CE(gnd),
+ .ACLR(gnd),
+ .ASET(gnd),
+ .SCLR(gnd),
+ .SSET(gnd),
+ .A_GT_B(dummy_out_1),
+ .A_GE_B(dummy_out_2),
+ .A_LT_B(dummy_out_3),
+ .A_LE_B(dummy_out_4),
+ .A_NE_B(dummy_out_5),
+ .QA_GT_B(dummy_out_6),
+ .QA_GE_B(dummy_out_7),
+ .QA_LT_B(dummy_out_8),
+ .QA_LE_B(dummy_out_9),
+ .QA_EQ_B(dummy_out_10),
+ .QA_NE_B(dummy_out_11)
+ );
+
+endmodule
+/* End Equality Comparator Module */
+
+
+/* reg_ainit.v Module */
+module reg_ainit_v2 (rst, clk, cen, din, qout);
+
+parameter reg_size =6;
+parameter init_val ="000000";
+parameter c_enable_rlocs=1;
+
+input rst;
+input clk;
+input cen;
+input [reg_size-1 : 0] din;
+output [reg_size-1 :0] qout;
+
+parameter no =0;
+parameter yes =1;
+wire gnd = 1'b0;
+wire vcc = 1'b1;
+
+C_REG_FD_V3_0 #(init_val,
+ c_enable_rlocs,
+ no,
+ yes,
+ no,
+ yes,
+ no,
+ no,
+ no,
+ init_val,
+ 1,
+ 1,
+ reg_size)
+ reg_fd (.D(din),
+ .Q(qout),
+ .CLK(clk),
+ .CE(cen),
+ .ACLR(gnd),
+ .ASET(gnd),
+ .AINIT(rst),
+ .SCLR(gnd),
+ .SSET(gnd),
+ .SINIT(gnd)
+ );
+endmodule
+/* End reg_ainit.v */
+
+
+/* and_a_b.v */
+module and_a_b_v2 (a_in, b_in, and_out);
+
+input a_in;
+input b_in;
+output and_out;
+
+parameter no =0;
+parameter yes =1;
+wire fake_in = 0;
+wire fake_out;
+wire [1: 0] and_in = {a_in, b_in};
+
+C_GATE_BIT_V3_0 #("0",
+ 0,
+ 0,
+ no,
+ no,
+ no,
+ no,
+ yes,
+ no,
+ no,
+ no,
+ no,
+ 2,
+ "00",
+ 0,
+ "0",
+ 0,
+ 1)
+
+ and_a_b (.I(and_in),
+ .O(and_out),
+ .CLK(fake_in),
+ .Q(fake_out),
+ .CE(fake_in),
+ .AINIT(fake_in),
+ .ASET(fake_in),
+ .ACLR(fake_in),
+ .SINIT(fake_in),
+ .SSET(fake_in),
+ .SCLR(fake_in)
+ );
+endmodule
+/* End and_a_b.v */
+
+
+/* Behvioral Model of or_a_b.v */
+module or_a_b_v2 (a_in, b_in, or_out);
+
+input a_in;
+input b_in;
+output or_out;
+
+wire or_out = a_in | b_in;
+
+endmodule
+/* End Behavioral of or_a_b.v */
+
+
+/* Behavioral Model of and_a_notb */
+module and_a_notb_v2 (a_in, b_in, and_out);
+
+parameter c_enable_rlocs =1;
+input a_in;
+input b_in;
+output and_out;
+
+assign and_out = a_in & !b_in;
+
+endmodule
+/* End Behavioral of and_a_notb */
+
+
+/* and_a_notb_fd */
+module and_a_notb_fd_v2 (a_in, b_in, clk, rst, q_out);
+
+parameter init_val ="0";
+parameter c_enable_rlocs = 1;
+
+input a_in;
+input b_in;
+input clk;
+input rst;
+output q_out;
+
+parameter no =0;
+parameter yes =1;
+
+wire vcc = 1'b1;
+wire fake_in =0;
+wire fake_out;
+wire [1 : 0] and_in;
+
+assign and_in = {b_in, a_in};
+
+C_GATE_BIT_V3_0 #(init_val,
+ c_enable_rlocs,
+ 0,
+ no,
+ yes,
+ no,
+ no,
+ no,
+ yes,
+ no,
+ no,
+ no,
+ 2,
+ "10",
+ 1, //c_pipe_stages ?
+ "0",
+ 0,
+ 1
+ )
+ and_fd (.I(and_in),
+ .O(fake_out),
+ .CLK(clk),
+ .Q(q_out),
+ .CE(vcc),
+ .AINIT(rst),
+ .ASET(fake_in),
+ .ACLR(fake_in),
+ .SINIT(fake_in),
+ .SSET(fake_in),
+ .SCLR(fake_in)
+ );
+endmodule
+/* End and_a_notb_fd */
+
+
+/* nand_a_notb_fd */
+module nand_a_notb_fd_v2 (a_in, b_in, clk, rst, q_out);
+
+parameter init_val ="0";
+parameter no =0;
+parameter yes =1;
+
+input a_in;
+input b_in;
+input clk;
+input rst;
+output q_out;
+
+wire vcc =1;
+wire fake_in =0;
+wire fake_out;
+wire [1 : 0] nand_in;
+
+assign nand_in = {b_in, a_in};
+
+C_GATE_BIT_V3_0 #(init_val,
+ yes,
+ 1,
+ no,
+ yes,
+ no,
+ no,
+ no,
+ yes,
+ no,
+ no,
+ no,
+ 2,
+ "10",
+ 1,
+ "0",
+ 0,
+ 1
+ )
+ nand_fd (.I(nand_in),
+ .O(fake_out),
+ .CLK(clk),
+ .Q(q_out),
+ .CE(vcc),
+ .AINIT(rst),
+ .ASET(fake_in),
+ .ACLR(fake_in),
+ .SINIT(fake_in),
+ .SSET(fake_in),
+ .SCLR(fake_in)
+ );
+endmodule
+/* end nand_a_notb_fd */
+
+
+/* Behavioral Model of and_a_b_notc */
+module and_a_b_notc_v2 (a_in, b_in, c_in, and_out);
+
+input a_in;
+input b_in;
+input c_in;
+output and_out;
+
+
+wire and_out = a_in & b_in & !c_in;
+
+endmodule
+/* End Behavioral of end and_a_b_notc */
+
+
+/* Behavioral Model of and_a_b_c_notd */
+module and_a_b_c_notd_v2 (a_in, b_in, c_in, d_in, and_out);
+
+input a_in;
+input b_in;
+input c_in;
+input d_in;
+output and_out;
+
+wire and_out = a_in & b_in & c_in & !d_in;
+
+endmodule
+/* End Behavioral Model of and_a_b_c_notd */
+
+ /* or_fd */
+module or_fd_v2 (a_in, b_in, clk, rst, q_out);
+
+parameter init_val ="0";
+
+input a_in;
+input b_in;
+input clk;
+input rst;
+output q_out;
+
+parameter no =0;
+parameter yes =1;
+
+wire vcc = 1'b1;
+wire fake_in =0;
+wire fake_out;
+wire [1 : 0] or_in;
+
+assign or_in = {b_in, a_in};
+
+C_GATE_BIT_V3_0 #(init_val,
+ yes,
+ 2,
+ no,
+ yes,
+ no,
+ no,
+ no,
+ yes,
+ no,
+ no,
+ no,
+ 2,
+ "00",
+ 1,
+ "0",
+ 0,
+ 1
+ )
+ or_fd (.I(or_in),
+ .O(fake_out),
+ .CLK(clk),
+ .Q(q_out),
+ .CE(vcc),
+ .AINIT(rst),
+ .ASET(fake_in),
+ .ACLR(fake_in),
+ .SINIT(fake_in),
+ .SSET(fake_in),
+ .SCLR(fake_in)
+ );
+endmodule
+/* end or_fd */
+
+
+/* and_fd */
+module and_fd_v2 (a_in, b_in, clk, rst, q_out);
+
+parameter init_val ="0";
+parameter c_enable_rlocs =1;
+
+input a_in;
+input b_in;
+input clk;
+input rst;
+output q_out;
+
+parameter no =0;
+parameter yes =1;
+
+wire vcc = 1'b1;
+wire fake_in =0;
+wire fake_out;
+wire [1 : 0] and_in;
+
+assign and_in = {b_in, a_in};
+
+C_GATE_BIT_V3_0 #(init_val,
+ c_enable_rlocs,
+ 0,
+ no,
+ yes,
+ no,
+ no,
+ no,
+ yes,
+ no,
+ no,
+ no,
+ 2,
+ "00",
+ 1,
+ "0",
+ 0,
+ 1
+ )
+ and_fd (.I(and_in),
+ .O(fake_out),
+ .CLK(clk),
+ .Q(q_out),
+ .CE(vcc),
+ .AINIT(rst),
+ .ASET(fake_in),
+ .ACLR(fake_in),
+ .SINIT(fake_in),
+ .SSET(fake_in),
+ .SCLR(fake_in)
+ );
+
+endmodule
+/* end and_fd */
+
+
+/* nand_fd */
+module nand_fd_v2 (a_in, b_in, clk, rst, q_out);
+
+parameter init_val ="0";
+parameter c_enable_rlocs =1;
+
+input a_in;
+input b_in;
+input clk;
+input rst;
+output q_out;
+
+parameter no =0;
+parameter yes =1;
+
+wire vcc= 1'b1;
+wire fake_in=0;
+wire fake_out;
+wire [1 : 0] nand_in;
+
+assign nand_in = {b_in, a_in};
+
+C_GATE_BIT_V3_0 #(init_val,
+ c_enable_rlocs,
+ 1,
+ no,
+ yes,
+ no,
+ no,
+ no,
+ yes,
+ no,
+ no,
+ no,
+ 2,
+ "00",
+ 1,
+ "0",
+ 0,
+ 1
+ )
+ nand_fd (.I(nand_in),
+ .O(fake_out),
+ .CLK(clk),
+ .Q(q_out),
+ .CE(vcc),
+ .AINIT(rst),
+ .ASET(fake_in),
+ .ACLR(fake_in),
+ .SINIT(fake_in),
+ .SSET(fake_in),
+ .SCLR(fake_in)
+ );
+endmodule
+/* end nand_fd */
+
+
+/* or3_fd */
+module or3_fd_v2 (a_in, b_in, c_in, clk, rst, q_out);
+
+parameter init_val ="0";
+
+input a_in;
+input b_in;
+input c_in;
+input clk;
+input rst;
+output q_out;
+
+parameter no =0;
+parameter yes =1;
+
+wire vcc = 1'b1;
+wire fake_in =0;
+wire fake_out;
+wire [2 : 0] or_in;
+
+assign or_in = {a_in, b_in, c_in};
+
+C_GATE_BIT_V3_0 #(init_val,
+ yes,
+ 2,
+ no,
+ yes,
+ no,
+ no,
+ no,
+ yes,
+ no,
+ no,
+ no,
+ 3,
+ "000",
+ 1,
+ "0",
+ 0,
+ 1
+ )
+ or3_fd (.I(or_in),
+ .O(fake_out),
+ .CLK(clk),
+ .Q(q_out),
+ .CE(vcc),
+ .AINIT(rst),
+ .ASET(fake_in),
+ .ACLR(fake_in),
+ .SINIT(fake_in),
+ .SSET(fake_in),
+ .SCLR(fake_in)
+ );
+endmodule
+/* end or3_fd */
+
+
+/* almost_reg */
+module almost_reg_v2 (a_in, b_in, c_in, d_in, clk, rst, q_out);
+
+parameter init_val ="0";
+
+input a_in;
+input b_in;
+input c_in;
+input d_in;
+input clk;
+input rst;
+output q_out;
+
+and_a_b_v2 and_gate (.a_in(c_in),
+ .b_in(d_in),
+ .and_out(and_out)
+ );
+
+or3_fd_v2 #(init_val)
+ or3_reg (.a_in(a_in),
+ .b_in(b_in),
+ .c_in(and_out),
+ .clk(clk),
+ .rst(rst),
+ .q_out(q_out)
+ );
+
+endmodule
+/* end almost_reg */
+
+
+/*count_sub_reg */
+module count_sub_reg_v2 (a_in, b_in, clk, rst_a, rst_b, q_out);
+
+parameter width =6;
+parameter a_width =6;
+parameter b_width =6;
+parameter q_width =2;
+parameter c_enable_rlocs=1;
+
+input [a_width-1 : 0] a_in;
+input [b_width-1 : 0] b_in;
+input clk;
+input rst_a;
+input rst_b;
+output [q_width-1 : 0] q_out;
+
+parameter no =0;
+parameter yes =1;
+parameter zero =1'b0;
+parameter zerostring ={(width+1){zero}};
+parameter initstring ={q_width{zero}};
+
+parameter a_pad =width-a_width;
+parameter b_pad =width-b_width;
+
+wire dummy_in =0;
+wire [q_width-1 : 0] load_0;
+wire load_1;
+wire load_2;
+wire load_3;
+wire load_4;
+wire load_5;
+wire load_6;
+wire reset;
+wire [width : 0] a;
+wire [width : 0] b;
+wire [q_width-1 : 0] addsub_out;
+wire gnd = 1'b0;
+wire vcc = 1'b1;
+wire [q_width-1 : 0] q_out = addsub_out;
+
+integer i;
+
+assign a = {vcc, a_in} ;
+assign b = {gnd, b_in};
+
+ C_ADDSUB_V3_0 #(1,
+ initstring,
+ 1,
+ width +1,
+ no,
+ no,
+ no,
+ 1,
+ zerostring,
+ width +1,
+ c_enable_rlocs,
+ no,
+ no,
+ yes,
+ no,
+ no,
+ no,
+ no,
+ no,
+ no,
+ no,
+ no,
+ no,
+ no,
+ yes,
+ no,
+ no,
+ no,
+ no,
+ no,
+ no,
+ no,
+ width-1,
+ 1, // Add this for C_LATENCY in version 3, robertle
+ width-q_width,
+ width+1,
+ 1,
+ initstring,
+ 1,
+ 1)
+ count_sub_reg (.A(a),
+ .B(b),
+ .Q(addsub_out),
+ .S(load_0),
+ .CLK(clk),
+ .ADD(dummy_in),
+ .OVFL(load_1),
+ .Q_OVFL(load_2),
+ .C_IN(dummy_in),
+ .C_OUT(load_3),
+ .Q_C_OUT(load_4),
+ .B_IN(dummy_in),
+ .B_OUT(load_5),
+ .Q_B_OUT(load_6),
+ .CE(dummy_in),
+ .BYPASS(dummy_in),
+ .A_SIGNED(dummy_in),
+ .B_SIGNED(dummy_in),
+ .ACLR(dummy_in),
+ .ASET(dummy_in),
+ .AINIT(reset),
+ .SCLR(dummy_in),
+ .SSET(dummy_in),
+ .SINIT(dummy_in)
+ );
+
+or_a_b_v2 or_gate (.a_in(rst_a),
+ .b_in(rst_b),
+ .or_out(reset)
+ );
+endmodule
+/* end count_sub_reg */
+
+
+/* ***************************************************************************
+ * This block removed 09/26/00 by jogden to fix CR 126807 where empty flag
+ * was causing wr_count to reset.
+ * **************************************************************************/
+
+ /* pulse_reg */
+
+//module pulse_reg_v2 (sclr_in, sset_in, clk, rst, q_out);
+//
+//input sclr_in;
+//input sset_in;
+//input clk;
+//input rst;
+//output q_out;
+//
+//wire gnd = 1'b0;
+//wire vcc = 1'b1;
+//parameter no =0;
+//parameter yes =1;
+//wire sclr;
+//wire [0:0] reg_out;
+//wire b_tmp = reg_out[0];
+//wire q_out = reg_out[0];
+//
+//and_a_b_v2 and_gate (.a_in(sclr_in),
+// .b_in(b_tmp),
+// .and_out(sclr)
+// );
+//
+//C_REG_FD_V3_0 #("0",
+// no,
+// no,
+// yes,
+// no,
+// no,
+// yes,
+// no,
+// yes,
+// "0",
+// 1,
+// 1,
+// 1
+// )
+// reg_fd (.D(reg_out),
+// .Q(reg_out),
+// .CLK(clk),
+// .CE(vcc),
+// .ACLR(gnd),
+// .ASET(gnd),
+// .AINIT(rst),
+// .SCLR(sclr),
+// .SSET(sset_in),
+// .SINIT(gnd)
+// );
+//endmodule
+
+/* end pulse_reg */
+
+
+/* xor_gate_bit */
+module xor_gate_bit_v2 (a, xor_out);
+
+parameter input_width = 6;
+input [input_width-1 : 0] a;
+output xor_out;
+
+parameter zero =1'b0;
+parameter zerostring ={input_width{zero}};
+
+wire sourceless_net =0;
+wire dummy_load_0;
+
+C_GATE_BIT_V3_0 #("0",
+ 0,
+ 4,
+ 0,
+ 0,
+ 0,
+ 0,
+ 1,
+ 0,
+ 0,
+ 0,
+ 0,
+ input_width,
+ zerostring,
+ 0,
+ "0",
+ 0,
+ 1
+ )
+ xor_mod (.I(a),
+ .CLK(sourceless_net),
+ .CE(sourceless_net),
+ .AINIT(sourceless_net),
+ .ASET(sourceless_net),
+ .ACLR(sourceless_net),
+ .SINIT(sourceless_net),
+ .SSET(sourceless_net),
+ .SCLR(sourceless_net),
+ .Q(dummy_load_0),
+ .O(xor_out)
+ );
+endmodule
+/* end xor_gate_bit */
+
+
+/* Behavioral Model of gray_to_binary */
+module gray_to_binary_v2 (bin_reg, grey_reg, reset, clk);
+
+parameter num_of_bits = 6;
+parameter init_val = "";
+parameter c_enable_rlocs = 1;
+
+input reset;
+input clk;
+input [num_of_bits-1:0] grey_reg;
+output [num_of_bits-1:0] bin_reg;
+
+reg [num_of_bits-1 : 0] AIV;
+reg [num_of_bits-1 : 0] bin_reg;
+reg [num_of_bits-1 : 0] bin_reg_d;
+reg temp;
+
+initial
+ begin
+ AIV = to_bits(init_val);
+ end
+
+always @(grey_reg)
+ begin : temp_loop
+ integer i;
+ for (i=num_of_bits-1; i>=0; i=i-1)
+ if (i == num_of_bits-1)
+ begin
+ temp = grey_reg[i];
+ bin_reg_d[i] = temp;
+ end
+ else
+ begin
+ temp = grey_reg[i] ^ temp;
+ bin_reg_d[i] = temp;
+ end
+ end
+
+
+
+always @(posedge clk or posedge reset)
+begin
+ if (reset == 1)
+ bin_reg = AIV;
+ else
+ bin_reg = bin_reg_d;
+end
+
+
+function [num_of_bits - 1 : 0] to_bits;
+ input [num_of_bits*8 : 1] instring;
+ integer i;
+ integer non_null_string;
+ begin
+ non_null_string = 0;
+ for(i = num_of_bits; i > 0; i = i - 1)
+ begin // Is the string empty?
+ if(instring[(i*8)] == 0 &&
+ instring[(i*8)-1] == 0 &&
+ instring[(i*8)-2] == 0 &&
+ instring[(i*8)-3] == 0 &&
+ instring[(i*8)-4] == 0 &&
+ instring[(i*8)-5] == 0 &&
+ instring[(i*8)-6] == 0 &&
+ instring[(i*8)-7] == 0 &&
+ non_null_string == 0)
+ non_null_string = 0; // Use the return value to flag a non-empty string
+ else
+ non_null_string = 1; // Non-null character!
+ end
+ if(non_null_string == 0) // String IS empty! Just return the value to be all '0's
+ begin
+ for(i = num_of_bits; i > 0; i = i - 1)
+ to_bits[i-1] = 0;
+ end
+ else
+ begin
+ for(i = num_of_bits; i > 0; i = i - 1)
+ begin // Is this character a '0'? (ASCII = 48 = 00110000)
+ if(instring[(i*8)] == 0 &&
+ instring[(i*8)-1] == 0 &&
+ instring[(i*8)-2] == 1 &&
+ instring[(i*8)-3] == 1 &&
+ instring[(i*8)-4] == 0 &&
+ instring[(i*8)-5] == 0 &&
+ instring[(i*8)-6] == 0 &&
+ instring[(i*8)-7] == 0)
+ to_bits[i-1] = 0;
+ // Or is it a '1'?
+ else if(instring[(i*8)] == 0 &&
+ instring[(i*8)-1] == 0 &&
+ instring[(i*8)-2] == 1 &&
+ instring[(i*8)-3] == 1 &&
+ instring[(i*8)-4] == 0 &&
+ instring[(i*8)-5] == 0 &&
+ instring[(i*8)-6] == 0 &&
+ instring[(i*8)-7] == 1)
+ to_bits[i-1] = 1;
+ // Or is it a ' '? (a null char - in which case insert a '0')
+ else if(instring[(i*8)] == 0 &&
+ instring[(i*8)-1] == 0 &&
+ instring[(i*8)-2] == 0 &&
+ instring[(i*8)-3] == 0 &&
+ instring[(i*8)-4] == 0 &&
+ instring[(i*8)-5] == 0 &&
+ instring[(i*8)-6] == 0 &&
+ instring[(i*8)-7] == 0)
+ to_bits[i-1] = 0;
+ else
+ begin
+ $display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring);
+ $finish;
+ end
+ end
+ end
+ end
+ endfunction
+endmodule
+/* End Behavioral of gray_to_binary */
+
+
+/* full_flag */
+module full_flag_reg_v2 (rst, flag_clk, flag_ce1, flag_ce2, reg_clk, reg_ce, a_in, b_in, dlyd_out, flag_out, to_almost_logic);
+
+parameter addr_width =6;
+parameter c_enable_rlocs=0;
+
+input rst;
+input flag_clk;
+input flag_ce1;
+input flag_ce2;
+input reg_clk ;
+input reg_ce ;
+input [addr_width-1 : 0] a_in;
+input [addr_width-1 : 0] b_in;
+output [addr_width-1 : 0] dlyd_out;
+output flag_out ;
+output to_almost_logic;
+
+
+wire gnd = 0;
+wire pwr =1;
+wire flag_d;
+reg flag_q;
+reg [addr_width-1 : 0] b_dlyd;
+
+wire flag_ce;
+integer i;
+
+
+assign dlyd_out = b_dlyd;
+assign #1 flag_out = flag_q;
+assign to_almost_logic = flag_d;
+assign flag_ce = flag_ce1 || flag_ce2;
+assign flag_d = ( ( (a_in== b_in)&&(flag_q == 1) ) || ((a_in == b_dlyd)&&(flag_q == 0)) ) ? 1 : 0;
+
+initial
+begin
+ flag_q <= 1'b1;
+end
+
+always @(posedge rst or posedge flag_clk)
+begin
+ if (rst == 1)
+ flag_q <= 1'b1;
+ else
+ flag_q <= (flag_ce) ? flag_d : flag_q;
+end
+
+
+always @(posedge rst or posedge reg_clk)
+begin
+ if (rst == 1)
+ begin
+ for (i=0; i <= addr_width-1; i=i+1)
+ begin
+ b_dlyd[i] <= (i==0 || i==1 || i==addr_width-1) ? 1 : 0;
+ end //for
+ end
+ else
+ b_dlyd <= (reg_ce ) ? b_in : b_dlyd;
+end
+endmodule
+/* end full_flag */
+
+
+/* empty_flag */
+module empty_flag_reg_v2 (rst, flag_clk, flag_ce1, flag_ce2, reg_clk, reg_ce, a_in, b_in, dlyd_out, flag_out, to_almost_logic);
+
+parameter addr_width =6;
+parameter c_enable_rlocs=0;
+
+input rst;
+input flag_clk;
+input flag_ce1;
+input flag_ce2;
+input reg_clk ;
+input reg_ce ;
+input [addr_width-1 : 0] a_in;
+input [addr_width-1 : 0] b_in;
+output [addr_width-1 : 0] dlyd_out;
+output flag_out ;
+output to_almost_logic;
+
+
+wire flag_d;
+reg flag_q;
+reg [addr_width-1 : 0] b_dlyd;
+
+wire flag_ce;
+integer i;
+
+assign dlyd_out = b_dlyd;
+assign #1 flag_out = flag_q;
+assign to_almost_logic = flag_d;
+assign flag_ce = flag_ce1 || flag_ce2;
+assign flag_d = ( ( (a_in== b_in)&&(flag_q == 1) ) || ((a_in == b_dlyd)&&(flag_q == 0)) ) ? 1 : 0;
+
+initial
+begin
+ flag_q <= 1'b1;
+end
+
+always @(posedge rst or posedge flag_clk)
+begin
+ if (rst == 1)
+ flag_q <= 1'b1;
+ else
+ flag_q <= (flag_ce) ? flag_d : flag_q;
+end
+
+
+always @(posedge rst or posedge reg_clk)
+begin
+ if (rst == 1)
+ begin
+ for (i=0; i <= addr_width-1; i=i+1)
+ begin
+ b_dlyd[i] <= (i==0 || i==addr_width-1) ? 1 : 0;
+ end //for
+ end
+ else
+ b_dlyd <= (reg_ce ) ? b_in : b_dlyd;
+end
+endmodule
+/* end empty_flag */
+
+
+/* almst_full flag */
+module almst_full_v2 (rst, flag_clk, flag_ce, reg_clk, reg_ce, a_in, b_in, rqst_in, flag_comb_in, flag_q_in, flag_out);
+
+parameter addr_width = 6;
+parameter c_enable_rlocs = 0;
+
+input rst;
+input flag_clk;
+input flag_ce;
+input reg_clk;
+input reg_ce;
+input [addr_width-1 : 0] a_in;
+input [addr_width-1 : 0] b_in;
+input rqst_in;
+input flag_comb_in;
+input flag_q_in;
+output flag_out;
+
+
+wire flag_d;
+reg flag_q;
+reg [addr_width-1 : 0] b_dlyd;
+
+wire comp_mux;
+wire rqst_mux;
+wire comb_or;
+
+assign #1 flag_out = flag_q;
+
+integer i;
+
+assign comp_mux = ( ( (a_in == b_in) && (flag_q_in== 1) ) || ( (a_in == b_dlyd ) && (flag_q_in== 0 ) ) ) ? 1: 0;
+assign rqst_mux = ( (comp_mux==1) && ((rqst_in==1) || (flag_q_in==1)) ) ? 1 : 0;
+assign comb_or = ( (rqst_mux==1) || (flag_comb_in==1) ) ? 1: 0;
+assign flag_d = comb_or;
+
+initial
+begin
+ flag_q <= 1'b1;
+end
+
+always @(posedge rst or posedge flag_clk)
+begin
+ if (rst == 1)
+ flag_q <= 1'b1;
+ else
+ flag_q <= (flag_ce == 1) ? flag_d : flag_q;
+end
+
+always @(posedge rst or posedge reg_clk)
+begin
+ if (rst == 1)
+ begin
+ for (i=0; i<=addr_width-1; i=i+1)
+ begin
+ b_dlyd[i] <= (i==1 || i==addr_width-1) ? 1 : 0;
+ end //for
+ end
+ else
+ b_dlyd <= (reg_ce == 1) ? b_in : b_dlyd;
+end
+endmodule
+/* end almst_full flag */
+
+
+/* almst_empty flag */
+module almst_empty_v2 (rst, flag_clk, flag_ce, reg_clk, reg_ce, a_in, b_in, rqst_in, flag_comb_in, flag_q_in, flag_out);
+
+parameter addr_width = 6;
+parameter c_enable_rlocs = 0;
+
+input rst;
+input flag_clk;
+input flag_ce;
+input reg_clk;
+input reg_ce;
+input [addr_width-1 : 0] a_in;
+input [addr_width-1 : 0] b_in;
+input rqst_in;
+input flag_comb_in;
+input flag_q_in;
+output flag_out;
+
+
+wire flag_d;
+reg flag_q;
+reg [addr_width-1 : 0] b_dlyd;
+
+wire comp_mux;
+wire rqst_mux;
+wire comb_or;
+
+integer i;
+
+assign #1 flag_out = flag_q;
+
+assign comp_mux = ( ( (a_in == b_in) && (flag_q_in== 1) ) || ( (a_in == b_dlyd ) && (flag_q_in== 0 ) ) ) ? 1: 0;
+assign rqst_mux = ( (comp_mux==1) && ((rqst_in==1) || (flag_q_in==1)) ) ? 1 : 0;
+assign comb_or = ( (rqst_mux==1) || (flag_comb_in==1) ) ? 1: 0;
+assign flag_d = comb_or;
+
+initial
+begin
+ flag_q <= 1'b1;
+end
+
+always @(posedge rst or posedge flag_clk)
+begin
+ if (rst == 1)
+ flag_q <= 1'b1;
+ else
+ flag_q <= (flag_ce == 1) ? flag_d : flag_q;
+end
+
+always @(posedge rst or posedge reg_clk)
+begin
+ if (rst == 1)
+ begin
+ for (i=0; i<=addr_width-1; i=i+1)
+ begin
+ b_dlyd[i] <= (i==0 || i==1 || i==addr_width-1) ? 1 : 0;
+ end //for
+ end
+ else
+ b_dlyd <= (reg_ce == 1) ? b_in : b_dlyd;
+end
+endmodule
+/* end almst_empty flag */
+
+
+/* Fifo Control Module. fifoctlr_ns.v */
+module fifoctlr_ns_v2 (fifo_reset_in, read_clock_in, write_clock_in, read_request_in,
+ write_request_in, read_enable_out, write_enable_out, full_flag_out,
+ empty_flag_out, almost_full_out, almost_empty_out, read_addr_out,
+ write_addr_out, wrsync_count_out, rdsync_count_out, read_ack,
+ read_error, write_ack, write_error);
+
+
+parameter width =6;
+parameter wr_width =6;
+parameter rd_width =6;
+parameter c_enable_rlocs =1;
+parameter c_has_almost_full =1;
+parameter c_has_almost_empty =1;
+parameter c_has_wrsync_dcount =1;
+parameter wrsync_dcount_width =6;
+parameter c_has_rdsync_dcount =1;
+parameter rdsync_dcount_width =6;
+parameter c_has_rd_ack =1;
+parameter c_rd_ack_low =0;
+parameter c_has_rd_error =1;
+parameter c_rd_error_low =0;
+parameter c_has_wr_ack =1;
+parameter c_wr_ack_low =0;
+parameter c_has_wr_error =1;
+parameter c_wr_error_low =0;
+
+
+input fifo_reset_in;
+input read_clock_in;
+input write_clock_in;
+input read_request_in;
+input write_request_in;
+output read_enable_out;
+output write_enable_out;
+output full_flag_out;
+output empty_flag_out;
+output almost_full_out;
+output almost_empty_out;
+output [rd_width-1 : 0] read_addr_out;
+output [wr_width-1 : 0] write_addr_out;
+output [wrsync_dcount_width-1 : 0] wrsync_count_out;
+output [rdsync_dcount_width-1 : 0] rdsync_count_out;
+output read_ack;
+output read_error;
+output write_ack;
+output write_error;
+
+parameter no = 0;
+parameter yes =1;
+
+parameter greater_width = (wr_width > rd_width ) ? wr_width : rd_width;
+
+wire gnd = 0;
+wire vcc = 1;
+wire reset;
+wire rd_clk;
+wire wr_clk;
+wire rd_en;
+wire rd_en_ram;
+wire wr_en;
+wire wr_en_ram;
+wire full_flag;
+wire almost_full;
+wire rdsync_full_flag;
+wire cond_full;
+wire cond_full_less1;
+wire cond_full_less2;
+wire empty_flag;
+wire almost_empty;
+wire cond_empty;
+wire cond_empty_plus1;
+wire cond_empty_plus2;
+//wire wrsync_empty_pulse; //removed 9-26-00 by jogden for CR 126807
+wire [rd_width-1 : 0] rd_addr_bin;
+wire [rd_width-1 : 0] rd_last_bin;
+wire [rd_width-1 : 0] rd_last_gray;
+wire [width-1 : 0] rd_last_trunc;
+wire [width-1 : 0] rd_dly1_gray;
+wire [width-1 : 0] rd_dly2_gray;
+wire [rd_width-1 : 0] wrsync_rd_last_gray;
+wire [rd_width-1 : 0] wrsync_rd_last_bin;
+wire [wr_width-1 : 0] wr_addr_bin;
+wire [wr_width-1 : 0] wr_last_bin;
+wire [wr_width-1 : 0] wr_last_gray;
+wire [width-1 : 0] wr_last_trunc;
+
+wire [width-1 : 0] wr_dly1_gray;
+wire [wr_width-1 : 0] rdsync_wr_last_gray;
+wire [wr_width-1 : 0] rdsync_wr_last_bin;
+wire [rdsync_dcount_width-1 : 0] rdsync_data_count;
+wire [wrsync_dcount_width-1 : 0] wrsync_data_count;
+
+wire fflag_comb;
+wire eflag_comb;
+
+wire read_error_low;
+wire read_error_high;
+wire read_ack_high;
+wire read_ack_low;
+wire almost_empty_temp;
+wire write_error_low;
+wire write_error_high;
+wire write_ack_high;
+wire write_ack_low;
+wire almost_full_temp;
+wire [wrsync_dcount_width-1 : 0] wrsync_data_count_temp;
+wire [rdsync_dcount_width-1 : 0] rdsync_data_count_temp;
+wire read_error;
+wire write_error;
+wire read_ack;
+wire write_ack;
+
+
+/* Fifoctlr_ns functions */
+parameter ascii_zero = 8'b00110000;
+parameter ascii_one = 8'b00110001;
+parameter zeros_width = {width{ascii_zero}};
+parameter ones_width = {width{ascii_one}};
+parameter gray_tc_width = {ascii_one,{(width-1){ascii_zero}}};
+parameter tc_less1_width = {ascii_one,{(width-2){ascii_zero}},ascii_one};
+parameter tc_less2_width = {{2{ascii_one}},{(width-3){ascii_zero}},ascii_one};
+parameter tc_less3_width = {{3{ascii_one}},{(width-4){ascii_zero}},ascii_one};
+
+/* End Fifoctlr_ns functions */
+
+
+assign reset = fifo_reset_in;
+assign rd_clk = read_clock_in;
+assign wr_clk = write_clock_in;
+assign read_enable_out = rd_en_ram;
+assign write_enable_out = wr_en_ram;
+assign full_flag_out = full_flag;
+assign empty_flag_out = empty_flag;
+assign almost_full_out = almost_full;
+assign almost_empty_out = almost_empty;
+assign read_addr_out = rd_addr_bin;
+assign write_addr_out = wr_addr_bin;
+assign rdsync_count_out = rdsync_data_count;
+assign wrsync_count_out = wrsync_data_count;
+
+
+integer i;
+
+assign rd_last_trunc = rd_last_gray[rd_width-1 : rd_width-width];
+assign wr_last_trunc = wr_last_gray[wr_width-1 : wr_width-width];
+
+and_a_notb_v2 #(c_enable_rlocs)
+ rd_en_and (.a_in(read_request_in),
+ .b_in(empty_flag),
+ .and_out(rd_en)
+ );
+
+and_a_notb_v2 #(c_enable_rlocs)
+ rd_en_to_ram (.a_in(read_request_in),
+ .b_in(empty_flag),
+ .and_out(rd_en_ram)
+ );
+/*
+----------------------------------------------------------------
+-- Generate read handshake signals (ACK/ERROR) if requested
+----------------------------------------------------------------
+*/
+
+// if (c_has_rd_error == 1 && c_rd_error_low == 0) begin //rd_error_hi
+ and_fd_v2 #("0",
+ c_enable_rlocs)
+ rd_error_fd_hi (.a_in(read_request_in),
+ .b_in(empty_flag),
+ .clk(rd_clk),
+ .rst(reset),
+ .q_out(read_error_high)
+ );
+// end //if rd_error_hi
+
+// if (c_has_rd_error == 1 && c_rd_error_low == 1) begin //rd_error_lo
+ nand_fd_v2 #("1",
+ c_enable_rlocs)
+ rd_error_fd_lo (.a_in(read_request_in),
+ .b_in(empty_flag),
+ .clk(rd_clk),
+ .rst(reset),
+ .q_out(read_error_low)
+ );
+// end //if rd_error_lo
+
+
+
+// if (c_has_rd_ack == 1 && c_rd_ack_low == 0) begin //rd_ack_hi
+ and_a_notb_fd_v2 #("0",
+ c_enable_rlocs)
+ rd_ack_fd_hi (.a_in(read_request_in),
+ .b_in(empty_flag),
+ .clk(rd_clk),
+ .rst(reset),
+ .q_out(read_ack_high)
+ );
+// end // if
+
+// if (c_has_rd_ack == 1 && c_rd_ack_low == 1) begin //rd_ack_lo
+ nand_a_notb_fd_v2 #("1", //CR124696
+
+ c_enable_rlocs)
+ rd_ack_fd_lo(.a_in(read_request_in),
+ .b_in(empty_flag),
+ .clk(rd_clk),
+ .rst(reset),
+ .q_out(read_ack_low)
+ );
+// end //if rd_ack_lo
+
+
+
+
+
+/*
+----------------------------------------------------------------
+-- --
+-- Generation of Read address pointers. The primary one is --
+-- binary (rd_addr_bin), and the Gray-code derivatives are --
+-- generated via pipelining the binary-to-Gray-code result. --
+-- The initial values are important, so they're in sequence. --
+-- Gray-code addresses are used so that the registered --
+-- Full and Empty flags are always clean, and never in an --
+-- unknown state due to the asynchonous relationship of the --
+-- Read and Write clocks. In the worst case scenario, Full --
+-- and Empty would simply stay active one cycle longer, but --
+-- it would not generate an error or give false values. --
+-- --
+----------------------------------------------------------------
+*/
+
+
+ bcount_up_ainit_v2 #(rd_width,
+ zeros_width, //changed to rd_width
+ c_enable_rlocs
+ )
+ rd_addr_counter (.init(reset),
+ .cen(rd_en),
+ .clk(rd_clk),
+ .cnt(rd_addr_bin)
+ );
+
+
+
+ binary_to_gray_v2 #(rd_width,
+ gray_tc_width, //gray_tc_string(rd_width),
+ c_enable_rlocs
+ )
+ rd_last_gray_reg(.rst(reset),
+ .clk(rd_clk),
+ .cen(rd_en),
+ .bin(rd_addr_bin),
+ .gray(rd_last_gray)
+ );
+/*
+---------------------------------------------------------------
+-- --
+-- Empty flag is set on reset (initial), or when gray --
+-- code counters are equal, or when there is one word in --
+-- the FIFO, and a Read operation will be performed on the --
+-- next read clock --
+-- --
+---------------------------------------------------------------
+*/
+
+ empty_flag_reg_v2 #(width,
+ c_enable_rlocs)
+ empty_flag_logic (.rst(reset),
+ .flag_clk(rd_clk),
+ .flag_ce1(read_request_in),
+ .flag_ce2(empty_flag),
+ .reg_clk(wr_clk),
+ .reg_ce ( wr_en),
+ .a_in(rd_last_trunc),
+ .b_in(wr_last_trunc),
+ .dlyd_out(wr_dly1_gray),
+ .flag_out(empty_flag),
+ .to_almost_logic(eflag_comb )
+ );
+
+
+/*
+---------------------------------------------------------------
+-- --
+-- Almost Empty flag is set on reset (initial). Or when the --
+-- read gray code counter (rd_last_gray) is equal or one --
+-- behind the last write gray code address(wr_lasy_gray, --
+-- wr_dly1_gray). Or when the rd_last_gray is equal to --
+-- wr_dly2_gray and a read operation is about to be per- --
+-- formed. (Note that the next two process and --
+-- wr_dly2_gray_grey represent the overhead for this --
+-- function --
+-- --
+---------------------------------------------------------------
+*/
+
+// if (c_has_almost_empty == 1) begin //almost_empty_gen
+ almst_empty_v2 #(width,
+ c_enable_rlocs)
+ almst_empty_logic(.rst(reset),
+ .flag_clk(rd_clk),
+ .flag_ce(vcc),
+ .reg_clk(wr_clk),
+ .reg_ce(wr_en),
+ .a_in(rd_last_trunc),
+ .b_in(wr_dly1_gray),
+ .rqst_in(read_request_in),
+ .flag_comb_in(eflag_comb),
+ .flag_q_in(empty_flag),
+ .flag_out(almost_empty_temp)
+ );
+// end //if almost_empty_gen
+/*
+----------------------------------------------------------------
+-- wr_en <= (write_request_in AND NOT full_flag);
+----------------------------------------------------------------
+*/
+
+ and_a_notb_v2 #(c_enable_rlocs)
+ wr_en_and (.a_in(write_request_in),
+ .b_in(full_flag),
+ .and_out(wr_en)
+ );
+/*
+----------------------------------------------------------------
+-- wr_en_ram <= (write_request_in AND NOT full_flag);
+-- This is a shadow of wr_en to reduce fanout for performance
+----------------------------------------------------------------
+*/
+
+ and_a_notb_v2 #(c_enable_rlocs)
+ wr_en_to_ram (.a_in(write_request_in),
+ .b_in(full_flag),
+ .and_out(wr_en_ram)
+ );
+/*----------------------------------------------------------------
+-- Generate write handshake signals (ACK/ERROR) if requested
+----------------------------------------------------------------
+*/
+
+// if (c_has_wr_error == 1 && c_wr_error_low == 0) begin
+ and_fd_v2 #("0",
+ c_enable_rlocs)
+ wr_error_fd_hi (.a_in(write_request_in),
+ .b_in(full_flag),
+ .clk(wr_clk),
+ .rst(reset),
+ .q_out(write_error_high)
+ );
+// end // if
+// if (c_has_wr_error == 1 && c_wr_error_low == 1) begin // wr_eror_lo
+ nand_fd_v2 #("1",
+ c_enable_rlocs)
+ wr_error_fd_lo (.a_in(write_request_in),
+ .b_in(full_flag),
+ .clk(wr_clk),
+ .rst(reset),
+ .q_out(write_error_low)
+ );
+// end // if wr_error_lo
+
+// if (c_has_wr_ack == 1 && c_wr_ack_low == 0) begin //wr_ack_hi
+ and_a_notb_fd_v2 #("0",
+ c_enable_rlocs)
+ wr_ack_fd_hi (.a_in(write_request_in),
+ .b_in(full_flag),
+ .clk(wr_clk),
+ .rst(reset),
+ .q_out(write_ack_high)
+ );
+// end //if wr_ack_hi
+
+// if (c_has_wr_ack == 1 && c_wr_ack_low == 1) begin //wr_ack_lo
+ nand_a_notb_fd_v2 #("1", //CR124696
+ c_enable_rlocs)
+ wr_ack_fd_lo (.a_in(write_request_in),
+ .b_in(full_flag),
+ .clk(wr_clk),
+ .rst(reset),
+ .q_out(write_ack_low)
+ );
+// end // if wr_ack_lo
+
+
+ bcount_up_ainit_v2 #(wr_width,
+ zeros_width, //zero_string, //(wr_width),
+ c_enable_rlocs)
+ wr_addr_counter (.init(reset),
+ .cen(wr_en),
+ .clk(wr_clk),
+ .cnt(wr_addr_bin)
+ );
+
+ binary_to_gray_v2 #(wr_width,
+ gray_tc_width, //gray_tc_string(wr_width),
+ c_enable_rlocs)
+ wr_last_gray_reg (.rst(reset),
+ .clk(wr_clk),
+ .cen(wr_en),
+ .bin(wr_addr_bin),
+ .gray(wr_last_gray)
+ );
+
+/*
+---------------------------------------------------------------
+-- --
+-- Full flag is set on reset (initial, but it is cleared --
+-- on the first valid write clock edge after reset is --
+-- de-asserted), or when Gray-code counters are one away --
+-- from being equal (the Write Gray-code address is equal --
+-- to the Last Read Gray-code address), or when the Next --
+-- Write Gray-code address is equal to the Last Read Gray- --
+-- code address, and a Write operation is about to be --
+-- performed. --
+-- --
+---------------------------------------------------------------
+*/
+
+ reg_ainit_v2 #(width,
+ tc_less1_width, //gray_tc_less1(width),
+ c_enable_rlocs)
+ rd_dly1_gray_reg (.rst(reset),
+ .clk(rd_clk),
+ .cen(rd_en),
+ .din(rd_last_trunc),
+ .qout(rd_dly1_gray)
+ );
+/*
+---------------------------------------------------------------
+-- --
+-- Almost Full flag is set on reset (initial, but it is --
+-- cleared on the first valid write clock edge after reset --
+-- is de-asserted). Or when the write Gray-code address --
+-- (wr_last_gray) is equal one behind the Last Read Gray- --
+-- code address(rd_dly1_gray, rd_dly2_gray). Or when the --
+-- write_last_gray is equal to rd_dly3_gray and a Write --
+-- operation is about to be performed. Note that the next --
+-- two process and rd_dly3_grag_reg represent the overhead --
+-- for this function. --
+-- --
+---------------------------------------------------------------
+*/
+
+// if (c_has_almost_full == 1) begin //gen_almost_full
+ almst_full_v2 #(width,
+ c_enable_rlocs)
+ almst_full_logic (.rst(reset),
+ .flag_clk(wr_clk),
+ .flag_ce(vcc),
+ .reg_clk(rd_clk),
+ .reg_ce(rd_en),
+ .a_in(wr_last_trunc),
+ .b_in(rd_dly2_gray),
+ .rqst_in(write_request_in),
+ .flag_comb_in(fflag_comb),
+ .flag_q_in(full_flag),
+ .flag_out(almost_full_temp)
+ );
+// end //if gen_almost_full
+
+ full_flag_reg_v2 #(width,
+ c_enable_rlocs)
+ full_flag_logic (.rst(reset),
+ .flag_clk(wr_clk),
+ .flag_ce1(write_request_in),
+ .flag_ce2(full_flag),
+ .reg_clk(rd_clk),
+ .reg_ce(rd_en),
+ .a_in(wr_last_trunc),
+ .b_in(rd_dly1_gray),
+ .dlyd_out(rd_dly2_gray),
+ .flag_out(full_flag),
+ .to_almost_logic(fflag_comb)
+ );
+
+
+
+
+
+/*
+----------------------------------------------------------------
+-- --
+-- Generation of data_count output. data_count reflects how --
+-- full FIFO is, based on how far the Write pointer is ahead --
+-- of the Read pointer. data_count will lag true FIFO state --
+-- by a couple of clock cycles, if the enables are inactive --
+-- for a few cycles data_count will converge to match FIFO's --
+-- data_count could be made synchronous to either clock --
+-- domain. The following code uses the write clock domain --
+-- --
+----------------------------------------------------------------
+*/
+
+// if (c_has_wrsync_dcount == 1) begin
+
+reg_ainit_v2 #(wr_width,
+ ones_width, //ones_string_wr, //(wr_width),
+ c_enable_rlocs)
+ wr_last_bin_reg (.rst(reset),
+ .clk(wr_clk),
+ .cen(wr_en),
+ .din(wr_addr_bin),
+ .qout(wr_last_bin)
+ );
+
+reg_ainit_v2 #(rd_width,
+ gray_tc_width, // gray_tc_string(rd_width),
+ c_enable_rlocs)
+ wrsync_rd_last_gray_reg (.rst(reset),
+ .clk(wr_clk),
+ .cen(vcc),
+ .din(rd_last_gray),
+ .qout(wrsync_rd_last_gray)
+ );
+
+gray_to_binary_v2 #(rd_width,
+ ones_width,
+ c_enable_rlocs)
+ wrsync_rd_last_bin_reg (.bin_reg(wrsync_rd_last_bin),
+ .grey_reg(wrsync_rd_last_gray),
+ .reset(reset),
+ .clk(wr_clk)
+ );
+
+/* ***************************************************************************
+ * This block removed 09/26/00 by jogden to fix CR 126807 where empty flag
+ * was causing wr_count to reset.
+ * **************************************************************************/
+//pulse_reg_v2 wrsync_empty_pulse_fd (.sclr_in(wr_en),
+// .sset_in(empty_flag),
+// .clk(wr_clk),
+// .rst(reset),
+// .q_out(wrsync_empty_pulse)
+// );
+
+count_sub_reg_v2 #(greater_width,
+ wr_width,
+ rd_width,
+ wrsync_dcount_width,
+ c_enable_rlocs)
+ wrsync_data_count_sub (.a_in(wr_last_bin),
+ .b_in(wrsync_rd_last_bin),
+ .clk(wr_clk),
+ .rst_a(reset),
+ //.rst_b(wrsync_empty_pulse),
+ .rst_b(gnd), //Connection removed 9-26-00
+ //by jogden to fix CR 126807
+ //regarding empty_pulse
+ //resetting wrsync_data_count
+ .q_out(wrsync_data_count_temp)
+ );
+
+
+// end //if
+//------------------------------------------------------------//
+// //
+// Generation of data_count output. data_count reflects how //
+// full FIFO is, based on how far the Write pointer is ahead //
+// of the Read pointer. data_count will lag true FIFO state //
+// by a couple of clock cycles, if the enables are inactive //
+// for a few cycles data_count will converge to match FIFO's //
+// data_count could be made synchronous to either clock //
+// domain. The following code uses the read clock domain //
+// //
+//------------------------------------------------------------//
+
+
+
+
+reg_ainit_v2 #(rd_width,
+ ones_width,
+ c_enable_rlocs)
+ rd_last_bin_reg (.rst(reset),
+ .clk(rd_clk),
+ .cen(rd_en),
+ .din(rd_addr_bin),
+ .qout(rd_last_bin)
+ );
+
+
+reg_ainit_v2 #(wr_width,
+ gray_tc_width,
+ c_enable_rlocs)
+ rdsync_wr_last_gray_reg (.rst(reset),
+ .clk(rd_clk),
+ .cen(vcc),
+ .din(wr_last_gray),
+ .qout(rdsync_wr_last_gray)
+ );
+
+gray_to_binary_v2 #(wr_width,
+ ones_width,
+ c_enable_rlocs)
+ rdsync_wr_last_bin_reg (.bin_reg(rdsync_wr_last_bin),
+ .grey_reg(rdsync_wr_last_gray),
+ .reset(reset),
+ .clk(rd_clk)
+ );
+count_sub_reg_v2 #(greater_width,
+ wr_width,
+ rd_width,
+ rdsync_dcount_width,
+ c_enable_rlocs)
+ rdsync_data_count_sub(.a_in(rdsync_wr_last_bin),
+ .b_in(rd_last_bin),
+ .clk(rd_clk),
+ .rst_a(reset),
+ .rst_b(reset),
+ .q_out(rdsync_data_count_temp)
+ );
+
+//------------------------------------------------------------//
+// //
+// The four conditions decoded with special carry logic are //
+// cond_empty, cond_empty_plus1, cond_full, cond_full_less1. //
+// These are used to determine the next state of the //
+// Full/Empty flags. //
+// //
+// When the Write/Read Gray-code addresses are equal, the //
+// FIFO is Empty, and cond_empty (combinatorial) is asserted.//
+// When the Write Gray-code address is equal to the Next //
+// Read Gray-code address (1 word in the FIFO), then the //
+// FIFO potentially could be going Empty (if rd_en is //
+// asserted, which is used in the logic that generates the //
+// registered version of Empty(empty_flag)). //
+// //
+// Similarly, when the Write Gray-code address is equal to //
+// the Last Read Gray-code address, the FIFO is full. To //
+// have utilized the full address space (512 addresses) //
+// would have required extra logic to determine Full/Empty //
+// on equal addresses, and this would have slowed down the //
+// overall performance. Lastly, when the Next Write Gray- //
+// code address is equal to the Last Read Gray-code address //
+// the FIFO is Almost Full, with only one word left, and //
+// it is conditional on write_enable being asserted. //
+// //
+//------------------------------------------------------------//
+
+
+assign read_error = (c_has_rd_error == 0 )? 1'bX :c_rd_error_low? read_error_low : read_error_high;
+assign read_ack = (c_has_rd_ack == 0 )? 1'bX :c_rd_ack_low? read_ack_low : read_ack_high;
+assign almost_empty = (c_has_almost_empty == 0 )? 1'bX : almost_empty_temp;
+assign write_error = (c_has_wr_error == 0 )? 1'bX : c_wr_error_low? write_error_low : write_error_high;
+assign write_ack = (c_has_wr_ack == 0 )? 1'bX : c_wr_ack_low ? write_ack_low : write_ack_high;
+assign almost_full = (c_has_almost_full == 0 )? 1'bX : almost_full_temp;
+assign wrsync_data_count = (c_has_wrsync_dcount == 0)? {wrsync_dcount_width{1'bX}} : wrsync_data_count_temp;
+assign rdsync_data_count = (c_has_rdsync_dcount == 0)? {rdsync_dcount_width{1'bX}} :rdsync_data_count_temp;
+
+endmodule
+/* End Fifo Control Module. fifoctlr_ns.v */
+
+
+/****************************************************************************/
+/* Top Level async_fifo */
+/****************************************************************************/
+
+
+module ASYNC_FIFO_V3_0 (DIN, WR_EN, WR_CLK, RD_EN, RD_CLK, AINIT, DOUT, FULL, EMPTY, ALMOST_FULL, ALMOST_EMPTY, WR_COUNT, RD_COUNT, RD_ACK, RD_ERR, WR_ACK, WR_ERR);
+
+
+/* Functions */
+
+function log2roundup;
+ input data_value ;
+ integer lower_limit;
+ integer upper_limit;
+ integer i;
+ begin
+ lower_limit=4;
+ upper_limit=16;
+ for (i=lower_limit-1; i<=upper_limit; i=i+1) begin
+ if (data_value <=0) begin
+ log2roundup=0;
+ end
+ else if (data_value > (1 << i)) begin
+ log2roundup = i + 1;
+ end
+ end
+ end
+endfunction
+/* End Functions */
+
+parameter C_DATA_WIDTH = 8;
+parameter C_ENABLE_RLOCS = 0;
+parameter C_FIFO_DEPTH = 511;
+parameter C_HAS_ALMOST_EMPTY = 1;
+parameter C_HAS_ALMOST_FULL = 1;
+parameter C_HAS_RD_ACK = 1;
+parameter C_HAS_RD_COUNT = 1;
+parameter C_HAS_RD_ERR = 1;
+parameter C_HAS_WR_ACK = 1;
+parameter C_HAS_WR_COUNT = 1;
+parameter C_HAS_WR_ERR = 1;
+parameter C_RD_ACK_LOW = 0;
+parameter C_RD_COUNT_WIDTH = 6;
+parameter C_RD_ERR_LOW = 0;
+parameter C_USE_BLOCKMEM = 1;
+parameter C_WR_ACK_LOW = 0;
+parameter C_WR_COUNT_WIDTH = 6;
+parameter C_WR_ERR_LOW = 0;
+
+
+input [C_DATA_WIDTH-1 : 0] DIN;
+input WR_EN;
+input WR_CLK;
+input RD_EN;
+input RD_CLK;
+input AINIT;
+output [C_DATA_WIDTH-1 : 0] DOUT;
+output FULL;
+output EMPTY;
+output ALMOST_FULL;
+output ALMOST_EMPTY;
+output [C_WR_COUNT_WIDTH-1 : 0] WR_COUNT;
+output [C_RD_COUNT_WIDTH-1 : 0] RD_COUNT;
+output RD_ACK;
+output RD_ERR;
+output WR_ACK;
+output WR_ERR;
+
+parameter depth_of_mem = C_FIFO_DEPTH +1;
+parameter address_width = (depth_of_mem == 16 ? 4:
+ (depth_of_mem == 32 ? 5:
+ (depth_of_mem == 64 ? 6 :
+ (depth_of_mem == 128 ? 7 :
+ (depth_of_mem == 256 ? 8 :
+ (depth_of_mem == 512 ? 9 :
+ (depth_of_mem == 1024 ? 10 :
+ (depth_of_mem == 2048 ? 11 :
+ (depth_of_mem == 4096 ? 12 :
+ (depth_of_mem == 8192 ? 13 :
+ (depth_of_mem == 16384 ? 14 :
+ (depth_of_mem == 32768 ? 15 :
+ (depth_of_mem == 65536 ? 16 : 6)))))))))))));
+
+
+wire [address_width-1 :0] read_address;
+wire [address_width-1 : 0] write_address;
+wire qualified_read_enable;
+wire qualified_write_request;
+
+wire #1 WR_EN_DLY = WR_EN ; //Delay WR_EN so a 1ns setup is enforced (CR124109)
+wire #1 RD_EN_DLY = RD_EN ; //Delay RD_EN so a 1ns setup is enforced (CR124109)
+
+
+ memory_v2 #(C_USE_BLOCKMEM,
+ C_ENABLE_RLOCS,
+ address_width,
+ address_width,
+ C_FIFO_DEPTH+1,
+ C_FIFO_DEPTH+1,
+ C_DATA_WIDTH,
+ C_DATA_WIDTH
+ )
+ mem (.d(DIN),
+ .wa(write_address),
+ .we(qualified_write_request),
+ .wclk(WR_CLK),
+ .re(qualified_read_enable),
+ .rclk(RD_CLK),
+ .ra(read_address),
+ .q(DOUT)
+ );
+
+ fifoctlr_ns_v2 #(
+ address_width,
+ address_width,
+ address_width,
+ C_ENABLE_RLOCS,
+ C_HAS_ALMOST_FULL,
+ C_HAS_ALMOST_EMPTY,
+ C_HAS_WR_COUNT,
+ C_WR_COUNT_WIDTH,
+ C_HAS_RD_COUNT,
+ C_RD_COUNT_WIDTH,
+ C_HAS_RD_ACK,
+ C_RD_ACK_LOW,
+ C_HAS_RD_ERR,
+ C_RD_ERR_LOW,
+ C_HAS_WR_ACK,
+ C_WR_ACK_LOW,
+ C_HAS_WR_ERR,
+ C_WR_ERR_LOW
+ )
+ control (.fifo_reset_in(AINIT),
+ .read_clock_in(RD_CLK),
+ .write_clock_in(WR_CLK),
+ .read_request_in(RD_EN_DLY),
+ .write_request_in(WR_EN_DLY),
+ .read_enable_out(qualified_read_enable),
+ .write_enable_out(qualified_write_request),
+ .full_flag_out(FULL),
+ .empty_flag_out(EMPTY),
+ .almost_full_out(ALMOST_FULL),
+ .almost_empty_out(ALMOST_EMPTY),
+ .read_addr_out(read_address),
+ .write_addr_out(write_address),
+ .wrsync_count_out(WR_COUNT),
+ .rdsync_count_out(RD_COUNT),
+ .read_ack(RD_ACK),
+ .read_error(RD_ERR),
+ .write_ack(WR_ACK),
+ .write_error(WR_ERR)
+ );
+
+
+
+endmodule
+/* End Top Level async_fifo */
+
+`endif
trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/async_fifo_v3_0.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_DIST_MEM_V3_0.v
===================================================================
--- trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_DIST_MEM_V3_0.v (nonexistent)
+++ trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_DIST_MEM_V3_0.v (revision 784)
@@ -0,0 +1,845 @@
+/* $Id: C_DIST_MEM_V3_0.v,v 1.1 2002-03-28 20:50:04 lampret Exp $
+--
+-- Filename - C_DIST_MEM_V3_0.v
+-- Author - Xilinx
+-- Creation - 24 Mar 1999
+--
+-- Description
+-- Distributed RAM Simulation Model
+*/
+`ifdef C_DIST_MEM_V3_0_DEF
+`else
+`define C_DIST_MEM_V3_0_DEF
+
+`ifdef C_REG_FD_V3_0_DEF
+`else
+`include "XilinxCoreLib/C_REG_FD_V3_0.v"
+`define C_REG_FD_V3_0_DEF
+`endif
+
+`define all0s 'b0
+`define all1s {C_WIDTH{1'b1}}
+`define allXs {C_WIDTH{1'bx}}
+`define allZs {C_WIDTH{1'bz}}
+`define addrallXs {C_ADDR_WIDTH{1'bx}}
+
+`define c_rom 0
+`define c_sp_ram 1
+`define c_dp_ram 2
+`define c_srl16 3
+
+`define c_lut_based 0
+`define c_buft_based 1
+
+module C_DIST_MEM_V3_0 (A, D, DPRA, SPRA, CLK, WE, I_CE, RD_EN, QSPO_CE, QDPO_CE, QDPO_CLK, QSPO_RST, QDPO_RST, SPO, DPO, QSPO, QDPO);
+
+ parameter C_ADDR_WIDTH = 6;
+ parameter C_DEFAULT_DATA = "0";
+ parameter C_DEFAULT_DATA_RADIX = 1;
+ parameter C_DEPTH = 64;
+ parameter C_ENABLE_RLOCS = 1;
+ parameter C_GENERATE_MIF = 0;
+ parameter C_HAS_CLK = 1;
+ parameter C_HAS_D = 1;
+ parameter C_HAS_DPO = 0;
+ parameter C_HAS_DPRA = 0;
+ parameter C_HAS_I_CE = 0;
+ parameter C_HAS_QDPO = 0;
+ parameter C_HAS_QDPO_CE = 0;
+ parameter C_HAS_QDPO_CLK = 0;
+ parameter C_HAS_QDPO_RST = 0; // RSTB
+ parameter C_HAS_QSPO = 0;
+ parameter C_HAS_QSPO_CE = 0;
+ parameter C_HAS_QSPO_RST = 0; // RSTA
+ parameter C_HAS_RD_EN = 0;
+ parameter C_HAS_SPO = 1;
+ parameter C_HAS_SPRA = 0;
+ parameter C_HAS_WE = 1;
+ parameter C_MEM_INIT_FILE = "null.mif";
+ parameter C_MEM_INIT_RADIX = 1; // for backwards compatibility
+ parameter C_MEM_TYPE = 1; // c_sp_ram
+ parameter C_MUX_TYPE = 0; // c_lut_based
+ parameter C_PIPE_STAGES = 0;
+ parameter C_QCE_JOINED = 0;
+ parameter C_QUALIFY_WE = 0;
+ parameter C_READ_MIF = 0;
+ parameter C_REG_A_D_INPUTS = 0;
+ parameter C_REG_DPRA_INPUT = 0;
+ parameter C_WIDTH = 16;
+ parameter radix = (C_DEFAULT_DATA_RADIX == 1 ? C_MEM_INIT_RADIX : C_DEFAULT_DATA_RADIX);
+
+ input [C_ADDR_WIDTH-1 - (C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0] A;
+ input [C_WIDTH-1 : 0] D;
+ input [C_ADDR_WIDTH-1 : 0] DPRA;
+ input [C_ADDR_WIDTH-1 : 0] SPRA;
+ input CLK;
+ input WE;
+ input I_CE;
+ input RD_EN;
+ input QSPO_CE;
+ input QDPO_CE;
+ input QDPO_CLK;
+ input QSPO_RST;
+ input QDPO_RST;
+ output [C_WIDTH-1 : 0] SPO;
+ output [C_WIDTH-1 : 0] QSPO;
+ output [C_WIDTH-1 : 0] DPO;
+ output [C_WIDTH-1 : 0] QDPO;
+
+ // Address signal connected to memory
+ wire [C_ADDR_WIDTH - 1 : 0] a_int;
+ // Read Address signal connected to srl16-based memory
+ wire [C_ADDR_WIDTH - 1 : 0] spra_int;
+ // Registered Address signal connected to memory
+ wire [C_ADDR_WIDTH - 1 : 0] a_int1;
+ // Registered Read Address signal connected to srl16-based memory
+ wire [C_ADDR_WIDTH - 1 : 0] spra_int1;
+ // DP port address signal connected to memory
+ wire [C_ADDR_WIDTH - 1 : 0] dpra_int;
+ // DP port address signal connected to memory
+ wire [C_ADDR_WIDTH - 1 : 0] dpra_int1;
+ // Input data signal connected to memory
+ wire [C_WIDTH - 1 : 0] d_int;
+ // Registered Input data signal connected to memory
+ wire [C_WIDTH - 1 : 0] d_int1;
+ // DP output register clock
+ wire doclk;
+ // Input data/address/WE register Clock Enable
+ wire ice;
+ // Special address register Clock Enable for ROMs
+ wire a_reg_ice;
+ // DP read address port register clock enable
+// wire dpra_ce;
+ // WE wire connected to memory
+ wire we_int;
+ // Registered WE wire connected to memory
+ wire we_int1;
+ // Clock enable for the WE register
+ wire wece;
+ // Read Enable wire connected to BUFT-type output mux
+ wire re_int;
+ // Registered Read Enable wire connected to BUFT-type output mux
+ wire re_int1;
+ // unregistered version of qspo_ce
+ wire qspo_ce_int;
+ // possibly registered version of qspo_ce
+ wire qspo_ce_reg;
+ // registered version of qspo_ce
+ wire qspo_ce_reg1;
+ // unregistered version of qdpo_ce
+ wire qdpo_ce_int;
+ // possibly registered version of qdpo_ce
+ wire qdpo_ce_reg;
+ // registered version of qdpo_ce
+ wire qdpo_ce_reg1;
+ // possibly single port registered output reset
+ wire qspo_rst_int;
+ // possibly dual port registered output reset
+ wire qdpo_rst_int;
+ // Direct SP output from memory
+ reg [C_WIDTH - 1 : 0] spo_async;
+ // Direct DP output from memory
+ reg [C_WIDTH - 1 : 0] dpo_async;
+ // Possibly pipelined and/or registered SP output from memory
+ wire [C_WIDTH - 1 : 0] intQSPO;
+ // Possibly pipelined and/or registered DP output from memory
+ wire [C_WIDTH - 1 : 0] intQDPO;
+ // Pipeline signals
+ reg [C_WIDTH - 1 : 0] spo_pipe [C_PIPE_STAGES+2 : 0];
+ reg [C_WIDTH - 1 : 0] dpo_pipe [C_PIPE_STAGES+2 : 0];
+ // Possibly pipelined SP output from memory
+ reg [C_WIDTH - 1 : 0] spo_pipeend;
+ // Possibly pipelined DP output from memory
+ reg [C_WIDTH - 1 : 0] dpo_pipeend;
+
+ integer pipe, pipe1, pipe2, pipe3, pipe4, i, j, srl_start, srl_end;
+
+ // Array to hold ram data
+ reg [C_WIDTH-1 : 0] ram_data [C_DEPTH-1 : 0];
+ reg [C_WIDTH-1 : 0] tmp_data1;
+ reg [C_WIDTH-1 : 0] tmp_data2;
+
+ reg [C_WIDTH-1 : 0] default_data;
+ reg [C_WIDTH-1 : 0] spo_tmp;
+ reg [C_WIDTH-1 : 0] dpo_tmp;
+ reg [C_WIDTH-1 : 0] tmp_pipe1;
+ reg [C_WIDTH-1 : 0] tmp_pipe2;
+ reg [C_WIDTH-1 : 0] tmp_pipe3;
+ reg lastCLK;
+ reg lastdoclk;
+
+ function integer ADDR_IS_X;
+ input [C_ADDR_WIDTH-1 : 0] value;
+ integer i;
+ begin
+ ADDR_IS_X = 0;
+ for(i = 0; i < C_ADDR_WIDTH; i = i + 1)
+ if(value[i] === 1'bx)
+ ADDR_IS_X = 1;
+ end
+ endfunction
+
+ // Deal with the optional output signals...
+ wire [C_WIDTH - 1 : 0] SPO = (C_HAS_SPO && C_PIPE_STAGES < 2 ? spo_async : `allXs);
+ wire [C_WIDTH - 1 : 0] DPO = (C_HAS_DPO && C_PIPE_STAGES < 2 && C_MUX_TYPE != `c_buft_based && C_MEM_TYPE == `c_dp_ram ? dpo_async : `allXs);
+ wire [C_WIDTH - 1 : 0] QSPO = (C_HAS_QSPO ? intQSPO : `allXs);
+ wire [C_WIDTH - 1 : 0] QDPO = (C_HAS_QDPO ? intQDPO : `allXs);
+
+ // Deal with the optional input signals...
+
+ assign ice = (C_HAS_I_CE == 1 ? I_CE : 1'b1);
+ assign a_reg_ice = (C_MEM_TYPE == `c_rom ? qspo_ce_int : ice);
+ assign wece = (C_HAS_WE == 1 && C_REG_A_D_INPUTS == 1 && C_QUALIFY_WE == 1 ? ice : 1'b1);
+// assign dpra_ce = (C_HAS_QDPO_CE == 1 ? QDPO_CE : 1'b1);
+ assign doclk = (C_HAS_QDPO_CLK == 1 ? QDPO_CLK : CLK);
+ assign qspo_ce_int = (C_HAS_QSPO_CE == 1 ? QSPO_CE : 1'b1);
+ assign qdpo_ce_int = (C_HAS_QDPO_CE == 1 ? QDPO_CE :
+ (C_QCE_JOINED == 1 || (C_HAS_QSPO == 1 && C_MEM_TYPE == `c_srl16) ? qspo_ce_int : 1'b1));
+ assign qspo_rst_int = (C_HAS_QSPO_RST && C_HAS_QSPO ? QSPO_RST : 1'b0);
+ assign qdpo_rst_int = (C_HAS_QDPO_RST && C_HAS_QDPO ? QDPO_RST : 1'b0);
+
+ // (Optional) registers on SP address and on optional data/we/qspo_ce signals
+ C_REG_FD_V3_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+ 0, 0, 0, 0,
+ "0", 0, 0, 1)
+ qspo1_reg (.D(qspo_ce_int), .CLK(CLK),
+ .Q(qspo_ce_reg1));
+
+ C_REG_FD_V3_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+ 1, 0, 0, 0,
+ "0", 0, 0, (C_ADDR_WIDTH-(C_ADDR_WIDTH>4?(C_HAS_SPRA*4):0)))
+ a_rega (.D(A[C_ADDR_WIDTH - 1-(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]), .CLK(CLK), .CE(a_reg_ice),
+ .Q(a_int1[C_ADDR_WIDTH - 1-(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]));
+
+ C_REG_FD_V3_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+ 1, 0, 0, 0,
+ "0", 0, 0, C_ADDR_WIDTH)
+ spra_reg (.D(SPRA), .CLK(CLK), .CE(qspo_ce_int),
+ .Q(spra_int1));
+
+ C_REG_FD_V3_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+ 1, 0, 0, 0,
+ "0", 0, 0, 1)
+ we_reg (.D(WE), .CLK(CLK), .CE(wece),
+ .Q(we_int1));
+
+ C_REG_FD_V3_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+ 0, 0, 0, 0,
+ "0", 0, 0, 1)
+ re_reg (.D(RD_EN), .CLK(CLK),// .CE(qspo_ce_int),
+ .Q(re_int1));
+
+ C_REG_FD_V3_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+ 1, 0, 0, 0,
+ "0", 0, 0, C_WIDTH)
+ d_reg (.D(D), .CLK(CLK), .CE(ice),
+ .Q(d_int1));
+
+ // Deal with these optional registers
+ assign qspo_ce_reg = (C_REG_A_D_INPUTS == 0 ? (C_HAS_QSPO_CE == 1 ? qspo_ce_int : 1'b1) : (C_HAS_QSPO_CE == 1 ? qspo_ce_reg1 : 1'b1));
+ assign a_int = (C_REG_A_D_INPUTS == 0 ? (C_MEM_TYPE != `c_srl16 ? A : (C_ADDR_WIDTH>4 ? A[C_ADDR_WIDTH - 1 -(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]<<4 : 0)) :
+ (C_MEM_TYPE != `c_srl16 ? a_int1 : (C_ADDR_WIDTH>4 ? a_int1[C_ADDR_WIDTH - 1 -(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]<<4 : 0)));
+ assign spra_int = (C_REG_A_D_INPUTS == 0 ? (C_MEM_TYPE != `c_srl16 ? A : SPRA) :
+ (C_MEM_TYPE != `c_srl16 ? a_int1 : spra_int1));
+ assign we_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_WE == 1 ? WE : 1'b1) : (C_HAS_WE == 1 ? we_int1 : 1'b1));
+ assign re_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_RD_EN == 1 ? RD_EN : 1'b1) : (C_HAS_RD_EN == 1 ? re_int1 : 1'b1));
+ assign d_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_D == 1 ? D : `allXs) : (C_HAS_D == 1 ? d_int1 : `allXs));
+
+ // (Optional) DP Read Address and QDPO_CE registers
+
+ C_REG_FD_V3_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+ 1, 0, 0, 0,
+ "0", 0, 0, C_ADDR_WIDTH)
+ dpra_reg (.D(DPRA), .CLK(doclk), .CE(qdpo_ce_int),
+ .Q(dpra_int1));
+
+ C_REG_FD_V3_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+ 0, 0, 0, 0,
+ "0", 0, 0, 1)
+ qdpo1_reg (.D(qdpo_ce_int), .CLK(doclk),
+ .Q(qdpo_ce_reg1));
+
+ // Deal with these optional registers
+ assign qdpo_ce_reg = (C_REG_DPRA_INPUT == 0 ? (C_HAS_QDPO_CE == 1 ? qdpo_ce_int : (C_QCE_JOINED == 1 ? qdpo_ce_int : 1'b1)) :
+ (C_HAS_QDPO_CE == 1 ? qdpo_ce_reg1 : (C_QCE_JOINED == 1 || C_MEM_TYPE == `c_srl16 ? qdpo_ce_reg1 : 1'b1)));
+ assign dpra_int = (C_REG_DPRA_INPUT == 0 ? (C_HAS_DPRA == 1 ? DPRA : `allXs) : (C_HAS_DPRA == 1 ? dpra_int1 : `allXs));
+
+ // (Optional) pipeline registers
+
+ always@(posedge CLK)
+ begin
+ if(CLK === 1'b1 && lastCLK === 1'b0 && qspo_ce_reg === 1'b1) // OK! Update pipelines!
+ begin
+ for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1)
+ begin
+ spo_pipe[pipe] <= spo_pipe[pipe+1];
+ end
+ spo_pipe[C_PIPE_STAGES] <= spo_async;
+ end
+ else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || qspo_ce_reg === 1'bx) // POSSIBLY Update pipelines!
+ begin
+ for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1)
+ begin
+ tmp_pipe1 = spo_pipe[pipe];
+ tmp_pipe2 = spo_pipe[pipe+1];
+ for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1)
+ begin
+ if(tmp_pipe1[pipe1] !== tmp_pipe2[pipe1])
+ tmp_pipe1[pipe1] = 1'bx;
+ end
+ spo_pipe[pipe] <= tmp_pipe1;
+ end
+ tmp_pipe1 = spo_pipe[C_PIPE_STAGES];
+ for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1)
+ begin
+ if(tmp_pipe1[pipe1] !== spo_async[pipe1])
+ tmp_pipe1[pipe1] = 1'bx;
+ end
+ spo_pipe[C_PIPE_STAGES] <= tmp_pipe1;
+ end
+ end
+
+ always@(spo_async or spo_pipe[2])
+ begin
+ if(C_PIPE_STAGES < 2) // No pipeline
+ spo_pipeend <= spo_async;
+ else // Pipeline stages required
+ begin
+ spo_pipeend <= spo_pipe[2];
+ end
+ end
+
+ always@(posedge doclk)
+ begin
+ if(doclk === 1'b1 && lastdoclk === 1'b0 && qdpo_ce_reg === 1'b1) // OK! Update pipelines!
+ begin
+ for(pipe3 = 2; pipe3 <= C_PIPE_STAGES-1; pipe3 = pipe3 + 1)
+ begin
+ dpo_pipe[pipe3] <= dpo_pipe[pipe3+1];
+ end
+ dpo_pipe[C_PIPE_STAGES] <= dpo_async;
+ end
+ else if((doclk === 1'bx && lastdoclk === 1'b0) || (doclk === 1'b1 && lastdoclk === 1'bx) || qdpo_ce_reg === 1'bx) // POSSIBLY Update pipelines!
+ begin
+ for(pipe4 = 2; pipe4 <= C_PIPE_STAGES-1; pipe4 = pipe4 + 1)
+ begin
+ tmp_pipe3 = dpo_pipe[pipe4];
+ tmp_pipe2 = dpo_pipe[pipe4+1];
+ for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1)
+ begin
+ if(tmp_pipe3[pipe1] !== tmp_pipe2[pipe1])
+ tmp_pipe3[pipe1] = 1'bx;
+ end
+ dpo_pipe[pipe4] <= tmp_pipe3;
+ end
+ tmp_pipe3 = dpo_pipe[C_PIPE_STAGES];
+ for(pipe2 = 0; pipe2 < C_WIDTH; pipe2 = pipe2 + 1)
+ begin
+ if(tmp_pipe3[pipe2] !== dpo_async[pipe2])
+ tmp_pipe3[pipe2] = 1'bx;
+ end
+ dpo_pipe[C_PIPE_STAGES] <= tmp_pipe3;
+ end
+ end
+
+ always@(dpo_async or dpo_pipe[2])
+ begin
+ if(C_PIPE_STAGES < 2) // No pipeline
+ dpo_pipeend <= dpo_async;
+ else // Pipeline stages required
+ begin
+ dpo_pipeend <= dpo_pipe[2];
+ end
+ end
+
+ // (Optional) output registers at end of optional pipelines
+
+ C_REG_FD_V3_0 #("0", C_ENABLE_RLOCS, C_HAS_QSPO_RST, 0, 0,
+ 1, 0, 0, 0,
+ "0", 0, 0, C_WIDTH)
+ qspo_reg (.D(spo_pipeend), .CLK(CLK), .CE(qspo_ce_reg),
+ .ACLR(qspo_rst_int), .Q(intQSPO));
+
+ C_REG_FD_V3_0 #("0", C_ENABLE_RLOCS, C_HAS_QDPO_RST, 0, 0,
+ 1, 0, 0, 0,
+ "0", 0, 0, C_WIDTH)
+ qdpo_reg (.D(dpo_pipeend), .CLK(doclk), .CE(qdpo_ce_reg),
+ .ACLR(qdpo_rst_int), .Q(intQDPO));
+
+
+
+ // Startup behaviour
+ initial
+ begin
+ default_data = 'b0;
+ case (radix)
+ 3 : default_data = decstr_conv(C_DEFAULT_DATA);
+ 2 : default_data = binstr_conv(C_DEFAULT_DATA);
+ 1 : default_data = hexstr_conv(C_DEFAULT_DATA);
+ default : $display("ERROR : BAD DATA RADIX");
+ endcase
+
+ for(i = 0; i < C_DEPTH; i = i + 1)
+ ram_data[i] = default_data;
+
+ if(C_READ_MIF == 1)
+ begin
+ $readmemb(C_MEM_INIT_FILE, ram_data);
+ end
+ if (C_GENERATE_MIF == 1)
+ write_meminit_file;
+
+ spo_tmp = 'b0;
+ dpo_tmp = 'b0;
+ lastCLK = 1'b0;
+ lastdoclk = 1'b0;
+
+ for(i = 0; i < C_PIPE_STAGES+3; i = i + 1)
+ begin
+ spo_pipe[i] = `all0s;
+ dpo_pipe[i] = `all0s;
+ end
+ if(C_PIPE_STAGES < 2) // No pipeline
+ begin
+ spo_pipeend = spo_async;
+ dpo_pipeend = dpo_async;
+ end
+ else
+ begin
+ spo_pipeend = spo_pipe[2];
+ dpo_pipeend = dpo_pipe[2];
+ end
+ end
+
+ always @(CLK)
+ lastCLK <= CLK;
+
+ always @(doclk)
+ lastdoclk <= doclk;
+
+ always @(posedge CLK or a_int or we_int or spra_int or dpra_int or d_int or re_int)
+ begin
+ if(((CLK === 1'b1 && lastCLK === 1'b0) || C_HAS_CLK == 0) && C_MEM_TYPE != `c_rom)
+ begin
+ if(ADDR_IS_X(a_int) || a_int < C_DEPTH)
+ begin
+ if(we_int === 1'bx)
+ begin
+ if(ADDR_IS_X(a_int))
+ begin
+ for(i = 0; i < C_DEPTH; i = i + 1)
+ ram_data[i] = `allXs;
+ end
+ else
+ begin
+ if(C_MEM_TYPE == `c_srl16)
+ begin
+ srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int
+ srl_end = srl_start+16;
+ if(srl_end > C_DEPTH)
+ srl_end = C_DEPTH;
+ for(i = srl_end-1; i > srl_start; i = i - 1)
+ begin // Shift data through the SRL16s
+ tmp_data1 = ram_data[i];
+ tmp_data2 = ram_data[i-1];
+ for(j = 0; j < C_WIDTH; j = j + 1)
+ begin
+ if(tmp_data1[j] !== tmp_data2[j])
+ tmp_data1[j] = 1'bx;
+ end
+ ram_data[i] = tmp_data1;
+ end
+ tmp_data1 = ram_data[srl_start];
+ for(j = 0; j < C_WIDTH; j = j + 1)
+ begin
+ if(tmp_data1[j] !== d_int[j])
+ tmp_data1[j] = 1'bx;
+ end
+ ram_data[srl_start] = tmp_data1;
+ end
+ else
+ begin
+ tmp_data1 = ram_data[a_int];
+ for(j = 0; j < C_WIDTH; j = j + 1)
+ begin
+ if(tmp_data1[j] !== d_int[j])
+ tmp_data1[j] = 1'bx;
+ end
+ ram_data[a_int] = tmp_data1;
+ end
+ end
+ end
+ else if(we_int === 1'b1)
+ begin
+ if(ADDR_IS_X(a_int))
+ begin
+ for(i = 0; i < C_DEPTH; i = i + 1)
+ ram_data[i] = `allXs;
+ end
+ else
+ begin
+ if(C_MEM_TYPE == `c_srl16)
+ begin
+ srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int
+ srl_end = srl_start+16;
+ if(srl_end > C_DEPTH)
+ srl_end = C_DEPTH;
+ for(i = srl_end-1; i > srl_start; i = i - 1)
+ begin // Shift data through the SRL16s
+ ram_data[i] = ram_data[i-1];
+ end
+ ram_data[srl_start] = d_int;
+ end
+ else
+ begin
+ if (C_MEM_TYPE == `c_dp_ram && a_int == dpra_int)
+ begin
+ $display("WARNING: Memory Hazard: Reading and Writing to same dual port address!");
+ end
+ ram_data[a_int] = d_int;
+ end
+ end
+ end
+ end
+ else if(a_int >= C_DEPTH)
+ $display("WARNING: Writing to out-of-range address!!");
+ end
+ else if((C_HAS_CLK == 0 || ((CLK === 1'bx && lastCLK === 1'b0) || CLK === 1'b1 && lastCLK === 1'bx)) && C_MEM_TYPE != `c_rom)
+ begin
+ if(ADDR_IS_X(a_int) || a_int < C_DEPTH)
+ begin
+ if(we_int === 1'bx)
+ begin
+ if(ADDR_IS_X(a_int))
+ begin
+ for(i = 0; i < C_DEPTH; i = i + 1)
+ ram_data[i] = `allXs;
+ end
+ else
+ begin
+ if(C_MEM_TYPE == `c_srl16)
+ begin
+ srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int
+ srl_end = srl_start+16;
+ if(srl_end > C_DEPTH)
+ srl_end = C_DEPTH;
+ for(i = srl_end-1; i > srl_start; i = i - 1)
+ begin // Shift data through the SRL16s
+ tmp_data1 = ram_data[i];
+ tmp_data2 = ram_data[i-1];
+ for(j = 0; j < C_WIDTH; j = j + 1)
+ begin
+ if(tmp_data1[j] !== tmp_data2[j])
+ tmp_data1[j] = 1'bx;
+ end
+ ram_data[i] = tmp_data1;
+ end
+ tmp_data1 = ram_data[srl_start];
+ for(j = 0; j < C_WIDTH; j = j + 1)
+ begin
+ if(tmp_data1[j] !== d_int[j])
+ tmp_data1[j] = 1'bx;
+ end
+ ram_data[srl_start] = tmp_data1;
+ end
+ else
+ begin
+ tmp_data1 = ram_data[a_int];
+ for(j = 0; j < C_WIDTH; j = j + 1)
+ begin
+ if(tmp_data1[j] !== d_int[j])
+ tmp_data1[j] = 1'bx;
+ end
+ ram_data[a_int] = tmp_data1;
+ end
+ end
+ end
+ else if(we_int === 1'b1)
+ begin
+ if(ADDR_IS_X(a_int))
+ begin
+ for(i = 0; i < C_DEPTH; i = i + 1)
+ ram_data[i] = `allXs;
+ end
+ else
+ begin
+ if(C_MEM_TYPE == `c_srl16)
+ begin
+ srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int
+ srl_end = srl_start+16;
+ if(srl_end > C_DEPTH)
+ srl_end = C_DEPTH;
+ for(i = srl_end-1; i > srl_start; i = i - 1)
+ begin // Shift data through the SRL16s
+ tmp_data1 = ram_data[i];
+ tmp_data2 = ram_data[i-1];
+ for(j = 0; j < C_WIDTH; j = j + 1)
+ begin
+ if(tmp_data1[j] !== tmp_data2[j])
+ tmp_data1[j] = 1'bx;
+ end
+ ram_data[i] = tmp_data1;
+ end
+ tmp_data1 = ram_data[srl_start];
+ for(j = 0; j < C_WIDTH; j = j + 1)
+ begin
+ if(tmp_data1[j] !== d_int[j])
+ tmp_data1[j] = 1'bx;
+ end
+ ram_data[srl_start] = tmp_data1;
+ end
+ else
+ begin
+ if (C_MEM_TYPE == `c_dp_ram && a_int == dpra_int)
+ begin
+ $display("WARNING: Memory Hazard: Reading and Writing to same dual port address!");
+ end
+ tmp_data1 = ram_data[a_int];
+ for(j = 0; j < C_WIDTH; j = j + 1)
+ begin
+ if(tmp_data1[j] !== d_int[j])
+ tmp_data1[j] = 1'bx;
+ end
+ ram_data[a_int] = tmp_data1;
+ end
+ end
+ end
+ end
+ else if(a_int >= C_DEPTH)
+ $display("WARNING: Writing to out-of-range address!!");
+ end
+
+ // Read behaviour
+
+ if(re_int === 1'bx)
+ begin
+ spo_tmp = `allXs;
+ dpo_tmp = `allXs;
+ end
+ else if(re_int === 1'b1)
+ begin
+ if(ADDR_IS_X(spra_int))
+ spo_tmp = `allXs;
+ else
+ begin
+ if(spra_int < C_DEPTH)
+ spo_tmp = ram_data[spra_int];
+ else if(C_MUX_TYPE == `c_buft_based)
+ begin
+ $display("WARNING: Reading from out-of-range address!!");
+ spo_tmp = `allZs;
+ end
+ else
+ begin
+ $display("WARNING: Reading from out-of-range address!!");
+ spo_tmp = `all0s;
+ end
+ end
+
+ if(ADDR_IS_X(dpra_int))
+ dpo_tmp = `allXs;
+ else
+ begin
+ if(dpra_int < C_DEPTH)
+ dpo_tmp = ram_data[dpra_int];
+ else if(C_MUX_TYPE == `c_buft_based)
+ begin
+ $display("WARNING: Reading from out-of-range address!!");
+ dpo_tmp = `allZs;
+ end
+ else
+ begin
+ $display("WARNING: Reading from out-of-range address!!");
+ dpo_tmp = `all0s;
+ end
+ end
+ end
+ else // re_int == 0
+ begin
+ spo_tmp = `allZs;
+ dpo_tmp = `allZs;
+ end
+
+ spo_async <= spo_tmp;
+ dpo_async <= dpo_tmp;
+
+ end
+
+
+ function [C_WIDTH-1:0] binstr_conv;
+ input [(C_WIDTH*8)-1:0] def_data;
+
+ integer index,i;
+
+ begin
+ index = 0;
+ binstr_conv = 'b0;
+
+ for( i=C_WIDTH-1; i>=0; i=i-1 )
+ begin
+ case (def_data[7:0])
+ 8'b00000000 : i = -1;
+ 8'b00110000 : binstr_conv[index] = 1'b0;
+ 8'b00110001 : binstr_conv[index] = 1'b1;
+ default :
+ begin
+ $display("ERROR : NOT A BINARY CHARACTER");
+ binstr_conv[index] = 1'bx;
+ end
+ endcase
+ index = index + 1;
+ def_data = def_data >> 8;
+ end
+ end
+ endfunction
+
+ function [C_WIDTH-1:0] hexstr_conv;
+ input [(C_WIDTH*8)-1:0] def_data;
+
+ integer index,i,j;
+ reg [3:0] bin;
+
+ begin
+ index = 0;
+ hexstr_conv = 'b0;
+ for( i=C_WIDTH-1; i>=0; i=i-1 )
+ begin
+ case (def_data[7:0])
+ 8'b00000000 :
+ begin
+ bin = 4'b0000;
+ i = -1;
+ end
+ 8'b00110000 : bin = 4'b0000;
+ 8'b00110001 : bin = 4'b0001;
+ 8'b00110010 : bin = 4'b0010;
+ 8'b00110011 : bin = 4'b0011;
+ 8'b00110100 : bin = 4'b0100;
+ 8'b00110101 : bin = 4'b0101;
+ 8'b00110110 : bin = 4'b0110;
+ 8'b00110111 : bin = 4'b0111;
+ 8'b00111000 : bin = 4'b1000;
+ 8'b00111001 : bin = 4'b1001;
+ 8'b01000001 : bin = 4'b1010;
+ 8'b01000010 : bin = 4'b1011;
+ 8'b01000011 : bin = 4'b1100;
+ 8'b01000100 : bin = 4'b1101;
+ 8'b01000101 : bin = 4'b1110;
+ 8'b01000110 : bin = 4'b1111;
+ 8'b01100001 : bin = 4'b1010;
+ 8'b01100010 : bin = 4'b1011;
+ 8'b01100011 : bin = 4'b1100;
+ 8'b01100100 : bin = 4'b1101;
+ 8'b01100101 : bin = 4'b1110;
+ 8'b01100110 : bin = 4'b1111;
+ default :
+ begin
+ $display("ERROR : NOT A HEX CHARACTER");
+ bin = 4'bx;
+ end
+ endcase
+ for( j=0; j<4; j=j+1)
+ begin
+ if ((index*4)+j < C_WIDTH)
+ begin
+ hexstr_conv[(index*4)+j] = bin[j];
+ end
+ end
+ index = index + 1;
+ def_data = def_data >> 8;
+ end
+ end
+ endfunction
+
+ function [C_WIDTH-1:0] decstr_conv;
+ input [(C_WIDTH*8)-1:0] def_data;
+
+ integer index,i,j;
+ reg [3:0] bin;
+
+ begin
+ index = 0;
+ decstr_conv = 'b0;
+ for( i=C_WIDTH-1; i>=0; i=i-1 )
+ begin
+ case (def_data[7:0])
+ 8'b00000000 :
+ begin
+ bin = 4'b0000;
+ i = -1;
+ end
+ 8'b00110000 : bin = 4'b0000;
+ 8'b00110001 : bin = 4'b0001;
+ 8'b00110010 : bin = 4'b0010;
+ 8'b00110011 : bin = 4'b0011;
+ 8'b00110100 : bin = 4'b0100;
+ 8'b00110101 : bin = 4'b0101;
+ 8'b00110110 : bin = 4'b0110;
+ 8'b00110111 : bin = 4'b0111;
+ 8'b00111000 : bin = 4'b1000;
+ 8'b00111001 : bin = 4'b1001;
+ 8'b01000001 : bin = 4'b1010;
+ 8'b01000010 : bin = 4'b1011;
+ 8'b01000011 : bin = 4'b1100;
+ 8'b01000100 : bin = 4'b1101;
+ 8'b01000101 : bin = 4'b1110;
+ 8'b01000110 : bin = 4'b1111;
+ default :
+ begin
+ $display("ERROR : NOT A DECIMAL CHARACTER");
+ bin = 4'bx;
+ end
+ endcase
+ for( j=0; j<4; j=j+1)
+ begin
+ if ((index*4)+j < C_WIDTH)
+ begin
+ decstr_conv[(index*4)+j] = bin[j];
+ end
+ end
+ index = index + 1;
+ def_data = def_data >> 8;
+ end
+ end
+ endfunction
+
+ task write_meminit_file;
+
+ integer addrs, outfile, bit;
+
+ reg [C_WIDTH-1 : 0] conts;
+ reg anyX;
+
+ begin
+ outfile = $fopen(C_MEM_INIT_FILE);
+ for( addrs = 0; addrs < C_DEPTH; addrs=addrs+1)
+ begin
+ anyX = 1'b0;
+ conts = ram_data[addrs];
+ for(bit = 0; bit < C_WIDTH; bit=bit+1)
+ if(conts[bit] === 1'bx) anyX = 1'b1;
+ if(anyX == 1'b1)
+ $display("ERROR : MEMORY CONTAINS UNKNOWNS");
+ $fdisplay(outfile,"%b",ram_data[addrs]);
+ end
+ $fclose(outfile);
+ end
+ endtask
+
+endmodule
+
+`undef all0s
+`undef all1s
+`undef allXs
+`undef allZs
+`undef addrallXs
+
+`undef c_rom
+`undef c_sp_ram
+`undef c_dp_ram
+`undef c_srl16
+
+`undef c_lut_based
+`undef c_buft_based
+
+`endif
trunk/orp/orp_soc/lib/xilinx/coregen/XilinxCoreLib/C_DIST_MEM_V3_0.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property