URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 79 to Rev 80
- ↔ Reverse comparison
Rev 79 → Rev 80
/trunk/bench/verilog/tb_eth_top.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.11 2002/02/16 13:06:59 mohor |
// EXTERNAL_DMA used instead of WISHBONE_DMA. |
// |
// Revision 1.10 2002/02/16 07:22:15 mohor |
// Testbench fixed, code simplified, unused signals removed. |
// |
172,10 → 175,10
|
// WISHBONE slave |
.wb_adr_i(WB_ADR_I[11:2]), .wb_sel_i(WB_SEL_I), .wb_we_i(WB_WE_I), .wb_cyc_i(WB_CYC_I), |
.wb_stb_i(WB_STB_I), .wb_ack_o(WB_ACK_O), .wb_err_o(WB_ERR_O), .wb_ack_i(WB_ACK_I), |
.wb_stb_i(WB_STB_I), .wb_ack_o(WB_ACK_O), .wb_err_o(WB_ERR_O), |
|
`ifdef EXTERNAL_DMA |
.wb_req_o(WB_REQ_O), .wb_nd_o(WB_ND_O), .wb_rd_o(WB_RD_O), |
.wb_ack_i(WB_ACK_I), .wb_req_o(WB_REQ_O), .wb_nd_o(WB_ND_O), .wb_rd_o(WB_RD_O), |
`else |
// WISHBONE master |
.m_wb_adr_o(m_wb_adr_o), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o), .m_wb_dat_i(m_wb_dat_i), |
/trunk/rtl/verilog/eth_wishbone.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.12 2002/02/26 16:22:07 mohor |
// Interrupts changed |
// |
// Revision 1.11 2002/02/15 17:07:39 mohor |
// Status was not written correctly when frames were discarted because of |
// address mismatch. |
1847,7 → 1850,7
// bit 10 od rx je reserved |
// bit 9 od rx je reserved |
// bit 8 od rx je reserved |
// bit 7 od rx je reserved |
// bit 7 od rx je Miss still needs to be done |
// bit 6 od rx je RxOverrun |
// bit 5 od rx je InvalidSymbol |
// bit 4 od rx je DribbleNibble |
/trunk/rtl/verilog/eth_wishbonedma.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.15 2002/02/26 16:23:05 mohor |
// WB_SEL_I was unused and removed from design |
// |
// Revision 1.14 2002/02/12 17:03:47 mohor |
// RxOverRun added to statuses. |
// |
133,8 → 136,10
WillSendControlFrame, TxCtrlEndFrm, |
|
// Interrupts |
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ, |
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ, TxC_IRQ, RxC_IRQ, |
|
RxAbort, ReceivedPacketGood, |
|
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble, |
ReceivedPacketTooBig, RxLength, LoadRxStatus, RetryCntLatched, RetryLimit, |
LateCollLatched, DeferLatched, CarrierSenseLost |
213,12 → 218,17
input TX_BD_NUM_Wr; // RxBDNumber written |
input r_RecSmall; // Receive small frames |
|
input RxAbort; |
input ReceivedPacketGood; |
|
// Interrupts |
output TxB_IRQ; |
output TxE_IRQ; |
output RxB_IRQ; |
output RxF_IRQ; |
output RxE_IRQ; |
output Busy_IRQ; |
output TxC_IRQ; |
output RxC_IRQ; |
|
reg WB_REQ_O_RX; |
reg WB_ND_O_TX; // New descriptor |
1684,8 → 1694,10
assign TxB_IRQ = 1'b0; |
assign TxE_IRQ = 1'b0; |
assign RxB_IRQ = 1'b0; |
assign RxF_IRQ = 1'b0; |
assign RxE_IRQ = 1'b0; |
assign Busy_IRQ = 1'b0; |
assign TxC_IRQ = 1'b0; |
assign RxC_IRQ = 1'b0; |
|
|
endmodule |
/trunk/rtl/verilog/eth_top.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.21 2002/02/26 16:21:00 mohor |
// Interrupts changed in the top file |
// |
// Revision 1.20 2002/02/18 10:40:17 mohor |
// Small fixes. |
// |
625,10 → 628,7
.TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ), .TxC_IRQ(TxC_IRQ), |
.RxC_IRQ(RxC_IRQ), |
|
`ifdef EXTERNAL_DMA |
`else |
.RxAbort(RxAbort), |
`endif |
|
.InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt), |
.RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble), |