OpenCores
URL https://opencores.org/ocsvn/jart/jart/trunk

Subversion Repositories jart

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 79 to Rev 80
    ↔ Reverse comparison
  •

Rev 79 → Rev 80

/jart/branches/ver0branch/powerGrid.vhd
61,7 → 61,35
constant REGSZADD : WARRAY := (12,11,10);
constant CIDSZADD : DUPLA := ((1,0),(2,1),(4,2));
-- Unitary Ray Set.
-- Y component generation.
component yu
generic (
TOP : integer := 1024; -- Define the max counting number.. the number must be expressed as 2 power, cause the range of counting is going to be defined as top-1 downto top/2.
-- However this is going to be by now, cause in the future the ray generation will GO on for higher resolution images , and perhaps it would be required a more extended range for the yu component.
SCREENW : integer := 320
);
port (
clk,rst,ena : in std_logic;
lineDone : out std_logic;
ypos : out integer range TOP/2 to TOP-1
);
end component;
-- Z and X component generation
component zu
generic
(
VALSTART : integer := 9
);
port (
clk,rst,ena : in std_logic; -- The usual control signals
clr : in std_logic;
zpos : out integer range -1024 to 1023;
zneg : out integer range -1024 to 1023
);
end component;
 
-- Register blocks.....
744,4 → 772,25
inter : out std_logic_vector (D-1 downto 0)
);
end component;
end powerGrid;
function mylog2( x : in integer; s: string) return integer;
end powerGrid;
package body powerGrid is
function mylog2(x: integer; s : string) return integer is
variable accum : integer :=1;
variable i : integer range 0 to 32 := 1;
begin
while (accum<=x) loop
accum := accum*2;
i := i+1;
end loop;
if s="unsigned" then
return i-1;
else
return i;
end if;
end;
 
end package body;
/jart/branches/ver0branch/urs.vhd
116,13 → 116,21
slockq <='0';
urs <='0';
linecounter := 0;
gridindex := 0;
gridindex := 1;
elsif rising_edge(clk) and ena='1' then
y <= sypos;
-- Calculate the locked
if slockq = '1' then -- If we already load the initial ypos value, then we must be unlocked!
if slockd = '1' then
for i in 0 to GRIDS-1 loop
if gridindex=i then
grid_enable(i)<='1';
else
grid_enable(i)<='0';
end if;
end loop;
gridindex:=gridindex+1;
if slockd = '1' then -- This is the end.... of the line....... my friend... This is the end......
if linecounter = (SCREENW/2)-1 then
urs <= '1'; -- Finished the URS.
else
137,16 → 145,7
end if;
-- Calculate the enable. (One Hot Deco)
for i in 0 to GRIDS-1 loop
if i = gridindex then
grid_enable(i)<='1';
else
grid_enable(i)<='0';
end if;
end loop;
gridindex:=gridindex+1;
end if;
end process;
/jart/branches/ver0branch/yu.vhd
34,10 → 34,10
generic (
TOP : integer := 1024; -- Define the max counting number.. the number must be expressed as 2 power, cause the range of counting is going to be defined as TOP-1 downto TOP/2.
-- However this is going to be by now, cause in the future the ray generation will GO on for higher resolution images , and perhaps it would be required a more extended range for the yu component.
SCREENW : integer range 0 to 1023 := 320 -- resolution width is 320
SCREENW : integer := 320 -- resolution width is 320
);
port (
clk,ena,rst : in std_logic;
clk,rst,ena : in std_logic;
lineDone : out std_logic; -- Finished image row. once a hundred and sixty times....
ypos : out integer range TOP/2 to TOP-1
-- ocntr : out integer range 0 to SCREENW/2
128,9 → 128,8
if cc = 0 then
ypos <= f1;
f0 := f1;
lineDone <='1';
else
lineDone <='0';
ypos <= f0;
if sf0(0)='1' then
f0 := f0 - 1;
139,12 → 138,13
-- Count when reach linefeed +3 (159) then turn cc into 0, else turn it into cc+1!
if cc=linefeed+3 then
lineDone <='1';
if sf1(0) = '1' then
f1 := f1 - 1;
end if;
cc:=0;
else
lineDone <='0';
cc:=cc+1;
end if;
/jart/branches/ver0branch/zu.vhd
34,8 → 34,8
entity zu is
generic
(
VALSTART : integer := 9
TOP : integer := 1024;
VALSTART : integer := 4;
TOP : integer := 1024
);
port (
42,18 → 42,18
clk, rst, ena : in std_logic; -- The usual control signals
clr : in std_logic;
zpos : out integer range -TOP to TOP-1;
zneg : out integer range -TOP to TOP-1;
zneg : out integer range -TOP to TOP-1
);
 
end entity;
 
architecture rtl of zu is
signal pivot : std_logic;
begin
 
process (clk,rst,ena,clr)
variable pivot : integer range 0 to 31;
variable z : integer range -1024 to 1023;
variable z : integer range -TOP to TOP-1;
begin
if rst='0' then
61,19 → 61,19
zpos<=VALSTART;
zneg<=-VALSTART;
z:=VALSTART;
pivot:=0;
pivot<='0';
elsif rising_edge(clk) and ena='1' then
if clr='1' then
z:=VALSTART;
pivot:=0;
elsif pivot = 0 then
pivot<='0';
elsif pivot = '0' then
z:=z+3;
pivot:=1;
pivot <= '1';
else
z:=z+2;
pivot:=0;
pivot <= '0';
end if;
zpos <= z;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.