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URL https://opencores.org/ocsvn/pci_blue_interface/pci_blue_interface/trunk

Subversion Repositories pci_blue_interface

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    from Rev 79 to Rev 80
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Rev 79 → Rev 80

/trunk/pci_blue_interface.dsk
1,12 → 1,9
<!DOCTYPE Desktop SYSTEM "hdl-prj.dtd">
<Desktop>
<ProjectWindow X="53" Y="33" W="861" H="571">
<Column>542</Column>
<ProjectWindow X="50" Y="43" W="864" H="574">
<Column>501</Column>
<Column>60</Column>
<Column>50</Column>
<Column>50</Column>
</ProjectWindow>
<SourceWindow X="157" Y="197" W="931" H="438" File="pci_blue_master\pci_blue_master.v" Line="126"></SourceWindow>
<SourceWindow X="108" Y="100" W="931" H="438" File="pci_blue_interface\pci_blue_interface.v" Line="202"></SourceWindow>
<SourceWindow X="167" Y="25" W="931" H="438" File="pci_example_chip\pci_example_chip.v" Line="248"></SourceWindow>
</Desktop>
/trunk/pci_blue_interface.hpj
1,6 → 1,6
<!DOCTYPE SimulationProject SYSTEM "hdl-prj.dtd">
<SimulationProject Logfile="verilog.log" Keyfile="..\..\VLogger\verilog.key" Language="Verilog" DelayType="typical" AddTopLevelSignals="1" FileNamesShown="1" HideEmptyLists="1" ShowWatch="1" DumpWatch="0" InteractiveMode="1" ParametersAreWatchable="0" ClearLogBeforeCompile="1" AutoParseProject="0">
<FileList>
<UserSourceFileList>
<File IsIndirectlyAdded="0">pci_test_system\pci_test_top.v</File>
<File IsIndirectlyAdded="0">pci_example_chip\pci_example_chip.v</File>
<File IsIndirectlyAdded="0">pci_blue_arbiter\pci_blue_arbiter.v</File>
23,18 → 23,21
<File IsIndirectlyAdded="0">pci_example_chip\monitor_pci_interface_host_port.v</File>
<File IsIndirectlyAdded="0">Readme</File>
<File IsIndirectlyAdded="0">reminders.v</File>
</FileList>
<File IsIndirectlyAdded="0">..\misc\synchronizer_flop.v</File>
</UserSourceFileList>
<DirList>
<Directory>C:\SYNAPTICAD.7.4\</Directory>
<Directory>C:\SYNAPTICAD\</Directory>
<Directory>C:\VLOGGER\</Directory>
<Directory>pci_blue_include\</Directory>
<Directory>C:\free_ip\pci_blue_interface\</Directory>
<Directory>..\..\SYNAPTICAD.7.9F</Directory>
<Directory>..\..\SYNAPTICAD.7.4</Directory>
<Directory>..\..\SYNAPTICAD</Directory>
<Directory>..\..\VLOGGER</Directory>
<Directory>pci_blue_include</Directory>
<Directory></Directory>
</DirList>
<LibDirList>
<Directory>C:\SYNAPTICAD.7.4\lib\verilog\</Directory>
<Directory>C:\SYNAPTICAD\lib\verilog\</Directory>
<Directory>C:\VLOGGER\lib\verilog\</Directory>
<Directory>..\..\SYNAPTICAD.7.9F\lib\verilog</Directory>
<Directory>..\..\SYNAPTICAD.7.4\lib\verilog</Directory>
<Directory>..\..\SYNAPTICAD\lib\verilog</Directory>
<Directory>..\..\VLOGGER\lib\verilog</Directory>
</LibDirList>
<LibExtensionList>
<Extension>.v</Extension>
41,9 → 44,6
<Extension>.vo</Extension>
<Extension>.vh</Extension>
</LibExtensionList>
<NameOfModelUnderTest></NameOfModelUnderTest>
<ComponentInstantiation></ComponentInstantiation>
<ComponentDeclaration></ComponentDeclaration>
<TBenchProperties>
<TBenchProp Value="False">VerboseSamples</TBenchProp>
<TBenchProp Value="False">VerboseSequenceVerification</TBenchProp>
/trunk/pci_blue_include/pci_blue_constants.vh
1,5 → 1,5
//===========================================================================
// $Id: pci_blue_constants.vh,v 1.14 2001-08-15 10:31:46 bbeaver Exp $
// $Id: pci_blue_constants.vh,v 1.15 2001-09-26 09:48:46 bbeaver Exp $
//
// Copyright 2001 Blue Beaver. All Rights Reserved.
//
61,12 → 61,12
parameter PCI_COMMAND_SPECIAL_CYCLE = 4'b0001;
parameter PCI_COMMAND_IO_READ = 4'b0010;
parameter PCI_COMMAND_IO_WRITE = 4'b0011;
parameter PCI_COMMAND_RESERVED_4 = 4'b0100;
parameter PCI_COMMAND_RESERVED_5 = 4'b0101;
parameter PCI_COMMAND_RESERVED_READ_4 = 4'b0100;
parameter PCI_COMMAND_RESERVED_WRITE_5 = 4'b0101;
parameter PCI_COMMAND_MEMORY_READ = 4'b0110;
parameter PCI_COMMAND_MEMORY_WRITE = 4'b0111;
parameter PCI_COMMAND_RESERVED_8 = 4'b1000;
parameter PCI_COMMAND_RESERVED_9 = 4'b1001;
parameter PCI_COMMAND_RESERVED_READ_8 = 4'b1000;
parameter PCI_COMMAND_RESERVED_WRITE_9 = 4'b1001;
parameter PCI_COMMAND_CONFIG_READ = 4'b1010;
parameter PCI_COMMAND_CONFIG_WRITE = 4'b1011;
parameter PCI_COMMAND_MEMORY_READ_MULTIPLE = 4'b1100;
250,14 → 250,14
// be waited for to satisfy the Delayed Read Request.
// Tags the Host Controller sends across the Delayed_Read_Data FIFO to indicate
// progress made on transfers initiated by the external PCI Bus Master.
parameter PCI_HOST_DELAYED_READ_DATA_SPARE = 3'b000;
parameter PCI_HOST_DELAYED_READ_DATA_TARGET_ABORT = 3'b001;
parameter PCI_HOST_DELAYED_READ_DATA_SPARE_2 = 3'b010;
parameter PCI_HOST_DELAYED_READ_DATA_SPARE_3 = 3'b011;
parameter PCI_HOST_DELAYED_READ_DATA_VALID = 3'b100;
parameter PCI_HOST_DELAYED_READ_DATA_VALID_PERR = 3'b101;
parameter PCI_HOST_DELAYED_READ_DATA_VALID_LAST = 3'b110;
parameter PCI_HOST_DELAYED_READ_DATA_VALID_LAST_PERR = 3'b111;
parameter PCI_HOST_DELAYED_READ_DATA_SPARE = 3'b000;
parameter PCI_HOST_DELAYED_READ_DATA_TARGET_ABORT = 3'b001;
parameter PCI_HOST_DELAYED_READ_DATA_SPARE_2 = 3'b010;
parameter PCI_HOST_DELAYED_READ_DATA_FAST_RETRY = 3'b011;
parameter PCI_HOST_DELAYED_READ_DATA_VALID = 3'b100;
parameter PCI_HOST_DELAYED_READ_DATA_VALID_PERR = 3'b101;
parameter PCI_HOST_DELAYED_READ_DATA_VALID_LAST = 3'b110;
parameter PCI_HOST_DELAYED_READ_DATA_VALID_LAST_PERR = 3'b111;
 
 
// Macros which are used as paramaters in the Test Device code
/trunk/pci_blue_target/pci_blue_target.v
1,5 → 1,5
//===========================================================================
// $Id: pci_blue_target.v,v 1.24 2001-09-13 09:58:09 bbeaver Exp $
// $Id: pci_blue_target.v,v 1.25 2001-09-26 09:48:50 bbeaver Exp $
//
// Copyright 2001 Blue Beaver. All Rights Reserved.
//
1011,6 → 1011,7
 
// Calculate the parity which is received due to an external Master sending
// an Address or a Write Data item.
// NOTE: WORKING: This will have to be re-written for a 64-bit PCI interface
wire par_0 = (^pci_ad_in_prev[3:0]);
wire par_1 = (^pci_ad_in_prev[7:4]);
wire par_2 = (^pci_ad_in_prev[11:8]);
1025,6 → 1026,31
wire par_6_7 = par_6 ^ par_7 ^ pci_cbe_l_in_prev[2];
wire address_data_parity = par_0_1 ^ par_2_3 ^ par_4_5 ^ par_6_7;
 
// Classify the new reference based on the latched Command and sometimes
// the IDSEL and address lines.
 
wire pci_config_read =
(pci_cbe_l_in_prev[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_CONFIG_READ); // NOTE: WORKING: address, idsel!
wire pci_config_write =
(pci_cbe_l_in_prev[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_CONFIG_WRITE);
wire pci_mem_io_read =
(pci_cbe_l_in_prev[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_IO_READ)
| (pci_cbe_l_in_prev[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_MEMORY_READ)
| (pci_cbe_l_in_prev[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_MEMORY_READ_MULTIPLE)
| (pci_cbe_l_in_prev[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_MEMORY_READ_LINE);
wire pci_mem_io_write =
(pci_cbe_l_in_prev[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_IO_WRITE)
| (pci_cbe_l_in_prev[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_MEMORY_WRITE)
| (pci_cbe_l_in_prev[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_MEMORY_WRITE_INVALIDATE);
wire pci_invalid_command =
(pci_cbe_l_in_prev[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_INTERRUPT_ACKNOWLEDGE)
| (pci_cbe_l_in_prev[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_SPECIAL_CYCLE)
| (pci_cbe_l_in_prev[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_RESERVED_READ_4)
| (pci_cbe_l_in_prev[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_RESERVED_WRITE_5)
| (pci_cbe_l_in_prev[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_RESERVED_READ_8)
| (pci_cbe_l_in_prev[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_RESERVED_WRITE_9)
| (pci_cbe_l_in_prev[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_DUAL_ADDRESS_CYCLE);
 
// The Target State Machine as described in Appendix B.
// No Lock State Machine is implemented.
// At this time, this device only supports 32-bit addresses.
1203,19 → 1229,25
parameter PCI_TARGET_IDLE_000 = 6'b0_000_00; // 00 Idle
parameter PCI_TARGET_NOT_ME_000 = 6'b0_000_01; // 01 Not Me
 
parameter PCI_TARGET_DEVSEL_READ_WAIT_100 = 6'b0_100_00; // 10 DEVSEL Read
parameter PCI_TARGET_DEVSEL_READ_DATA_110 = 6'b0_110_00; // 18 Read Data
parameter PCI_TARGET_DEVSEL_READ_DATA_STOP_111 = 6'b0_111_00; // 1C Read Data Stop
parameter PCI_TARGET_DEVSEL_READ_STOP_101 = 6'b0_101_00; // 14 Read Stop
parameter PCI_TARGET_CONFIG_READ_WAIT_100 = 6'b0_100_01; // 11 DEVSEL Read
parameter PCI_TARGET_CONFIG_READ_DATA_110 = 6'b0_110_01; // 19 Read Data
 
parameter PCI_TARGET_MEMORY_READ_WAIT_100 = 6'b0_100_00; // 10 DEVSEL Read
parameter PCI_TARGET_MEMORY_READ_DATA_110 = 6'b0_110_00; // 18 Read Data
parameter PCI_TARGET_MEMORY_READ_DATA_STOP_111 = 6'b0_111_00; // 1C Read Data Stop
parameter PCI_TARGET_MEMORY_READ_RETRY_101 = 6'b0_101_00; // 14 Read Stop
 
parameter PCI_TARGET_READ_ABORT_FIRST_100 = 6'b0_100_01;
parameter PCI_TARGET_READ_ABORT_SECOND_001 = 6'b0_001_00; // 04 Read Target Abort
 
parameter PCI_TARGET_DEVSEL_WRITE_WAIT_100 = 6'b1_100_00; // 30 DEVSEL Write
parameter PCI_TARGET_DEVSEL_WRITE_DATA_110 = 6'b1_110_00; // 38 Write Data
parameter PCI_TARGET_DEVSEL_WRITE_DATA_STOP_111 = 6'b1_111_00; // 3C Write Data Stop
parameter PCI_TARGET_DEVSEL_WRITE_STOP_101 = 6'b1_101_00; // 34 Write Stop
parameter PCI_TARGET_CONFIG_WRITE_WAIT_100 = 6'b1_100_01; // 31 DEVSEL Write
parameter PCI_TARGET_CONFIG_WRITE_DATA_110 = 6'b1_110_01; // 39 Write Data
 
parameter PCI_TARGET_MEMORY_WRITE_WAIT_100 = 6'b1_100_00; // 30 DEVSEL Write
parameter PCI_TARGET_MEMORY_WRITE_DATA_110 = 6'b1_110_00; // 38 Write Data
parameter PCI_TARGET_MEMORY_WRITE_DATA_STOP_111 = 6'b1_111_00; // 3C Write Data Stop
parameter PCI_TARGET_MEMORY_WRITE_RETRY_101 = 6'b1_101_00; // 34 Write Stop
 
parameter PCI_TARGET_WRITE_ABORT_FIRST_100 = 6'b1_100_01;
parameter PCI_TARGET_WRITE_ABORT_SECOND_001 = 6'b1_001_00; // 24 Write Target Abort
 
1574,7 → 1606,7
 
function [TS_Range:0] Target_Next_State;
input [TS_Range:0] Target_Present_State;
input Response_FIFO_has_Room;
input Response_FIFO_has_Two_Words_Of_Room;
input DELAYED_READ_FIFO_CONTAINS_DATA;
input Timeout_Forces_Disconnect;
input frame_in_critical;
1585,6 → 1617,11
input irdy_in_prev_prev;
input address_parity;
input par_in_critical;
input config_read;
input config_write;
input mem_io_read;
input mem_io_write;
input invalid_command;
 
begin
// synopsys translate_off
1602,15 → 1639,79
case (Target_Present_State[TS_Range:0]) // synopsys parallel_case
PCI_TARGET_IDLE_000:
begin
if ( ({frame_in_prev, irdy_in_prev} == MASTER_WAIT)
& ( ({frame_in_prev_prev, irdy_in_prev_prev} == MASTER_IDLE)
| ({frame_in_prev_prev, irdy_in_prev_prev} == MASTER_DATA_LAST)))
if ( ({frame_in_prev, irdy_in_prev} == MASTER_WAIT) // starting transfer
& ( ({frame_in_prev_prev, irdy_in_prev_prev} == MASTER_IDLE) // idle previously
| ({frame_in_prev_prev, irdy_in_prev_prev} == MASTER_DATA_LAST))) // finishing previously
begin
Target_Next_State[TS_Range:0] = TS_X; // NOTE: WORKING
if (config_read) // Config Reads done without telling Target
begin
Target_Next_State[TS_Range:0] = PCI_TARGET_CONFIG_READ_WAIT_100;
end
else if (config_write) // Config Writes done without telling Target
begin
Target_Next_State[TS_Range:0] = PCI_TARGET_CONFIG_WRITE_WAIT_100;
end
else if (address_parity_check_enabled & ~parity OK) // punt on any detected Address Error
begin
Target_Next_State[TS_Range:0] = PCI_TARGET_NOT_ME_000;
end
else if (invalid_command) // punt if unrecognized command
begin
Target_Next_State[TS_Range:0] = PCI_TARGET_NOT_ME_000;
end
else if ( ~( (mem_address_match & mem_enabled & memory_command) // punt if no match possible
| (io_address_match & io_enabled & io_command) ) )
begin
Target_Next_State[TS_Range:0] = PCI_TARGET_NOT_ME_000;
end
else if (~Response_FIFO_has_Two_Words_Of_Room) // stall if impossible to send data to Target
begin
Target_Next_State[TS_Range:0] = PCI_TARGET_MEMORY_READ_RETRY_101;
end
else if (~delayed_read_in_progress & its a read) // start delayed read immediately
begin
Target_Next_State[TS_Range:0] = PCI_TARGET_MEMORY_READ_RETRY_101;
end
else if (delayed_read_in_progress & its a read & delayed address miss) // defer reads until delayed read done
begin
Target_Next_State[TS_Range:0] = PCI_TARGET_MEMORY_READ_RETRY_101;
end
else if (delayed_read_in_progress & its a read & delayed address hit & data available & its abort)
begin
Target_Next_State[TS_Range:0] = PCI_TARGET_READ_ABORT_FIRST_100;
end
else if (delayed_read_in_progress & its a read & delayed address hit & data available & its retry)
begin
Target_Next_State[TS_Range:0] = PCI_TARGET_MEMORY_READ_RETRY_101;
end
else if (delayed_read_in_progress & its a read & delayed address hit & data available & its last data)
begin
Target_Next_State[TS_Range:0] = PCI_TARGET_MEMORY_READ_DATA_STOP_111;
end
else if (delayed_read_in_progress & its a read & delayed address hit & data available & ~its last data & near_bank_end)
begin
Target_Next_State[TS_Range:0] = PCI_TARGET_MEMORY_READ_DATA_STOP_110;
end
else if (delayed_read_in_progress & its a read & delayed address hit & data available & ~its last data & ~near_bank_end)
begin
Target_Next_State[TS_Range:0] = PCI_TARGET_MEMORY_READ_DATA_110;
end
else if (delayed_read_in_progress & its a read & delayed address hit & no data available)
begin
Target_Next_State[TS_Range:0] = PCI_TARGET_MEMORY_READ_WAIT_100;
end
else if (~its a read & near_bank_end)
begin
Target_Next_State[TS_Range:0] = PCI_TARGET_MEMORY_WRITE_DATA_STOP_110;
end
else if (~its a read & ~near_bank_end)
begin
Target_Next_State[TS_Range:0] = PCI_TARGET_MEMORY_WRITE_DATA_110;
end
end
else
begin
Target_Next_State[TS_Range:0] = TS_X; // NOTE: WORKING
Target_Next_State[TS_Range:0] = PCI_TARGET_IDLE_000;
end
end
PCI_TARGET_NOT_ME_000:
1617,22 → 1718,30
begin
Target_Next_State[TS_Range:0] = TS_X; // NOTE: WORKING
end
PCI_TARGET_DEVSEL_READ_WAIT_100:
PCI_TARGET_CONFIG_READ_WAIT_100:
begin
Target_Next_State[TS_Range:0] = TS_X; // NOTE: WORKING
end
PCI_TARGET_DEVSEL_READ_DATA_110:
PCI_TARGET_CONFIG_READ_DATA_110:
begin
Target_Next_State[TS_Range:0] = TS_X; // NOTE: WORKING
end
PCI_TARGET_DEVSEL_READ_DATA_STOP_111:
PCI_TARGET_MEMORY_READ_WAIT_100:
begin
Target_Next_State[TS_Range:0] = TS_X; // NOTE: WORKING
end
PCI_TARGET_DEVSEL_READ_STOP_101:
PCI_TARGET_MEMORY_READ_DATA_110:
begin
Target_Next_State[TS_Range:0] = TS_X; // NOTE: WORKING
end
PCI_TARGET_MEMORY_READ_DATA_STOP_111:
begin
Target_Next_State[TS_Range:0] = TS_X; // NOTE: WORKING
end
PCI_TARGET_MEMORY_READ_STOP_101:
begin
Target_Next_State[TS_Range:0] = TS_X; // NOTE: WORKING
end
PCI_TARGET_READ_ABORT_FIRST_100:
begin
Target_Next_State[TS_Range:0] = TS_X; // NOTE: WORKING
1641,22 → 1750,30
begin
Target_Next_State[TS_Range:0] = TS_X; // NOTE: WORKING
end
PCI_TARGET_DEVSEL_WRITE_WAIT_100:
PCI_TARGET_CONFIG_WRITE_WAIT_100:
begin
Target_Next_State[TS_Range:0] = TS_X; // NOTE: WORKING
end
PCI_TARGET_DEVSEL_WRITE_DATA_110:
PCI_TARGET_CONFIG_WRITE_DATA_110:
begin
Target_Next_State[TS_Range:0] = TS_X; // NOTE: WORKING
end
PCI_TARGET_DEVSEL_WRITE_DATA_STOP_111:
PCI_TARGET_MEMORY_WRITE_WAIT_100:
begin
Target_Next_State[TS_Range:0] = TS_X; // NOTE: WORKING
end
PCI_TARGET_DEVSEL_WRITE_STOP_101:
PCI_TARGET_MEMORY_WRITE_DATA_110:
begin
Target_Next_State[TS_Range:0] = TS_X; // NOTE: WORKING
end
PCI_TARGET_MEMORY_WRITE_DATA_STOP_111:
begin
Target_Next_State[TS_Range:0] = TS_X; // NOTE: WORKING
end
PCI_TARGET_MEMORY_WRITE_STOP_101:
begin
Target_Next_State[TS_Range:0] = TS_X; // NOTE: WORKING
end
PCI_TARGET_WRITE_ABORT_FIRST_100:
begin
Target_Next_State[TS_Range:0] = TS_X; // NOTE: WORKING
1692,7 → 1809,12
pci_frame_in_prev_prev,
pci_irdy_in_prev_prev,
address_data_parity,
pci_par_in_critical
pci_par_in_critical,
pci_config_read,
pci_config_write,
pci_mem_io_read,
pci_mem_io_write,
pci_invalid_command
);
 
always @(posedge pci_clk)
/trunk/pci_example_chip/pci_example_host_controller.v
1,5 → 1,5
//===========================================================================
// $Id: pci_example_host_controller.v,v 1.11 2001-08-15 10:31:47 bbeaver Exp $
// $Id: pci_example_host_controller.v,v 1.12 2001-09-26 09:48:57 bbeaver Exp $
//
// Copyright 2001 Blue Beaver. All Rights Reserved.
//
203,7 → 203,7
task Clear_Example_Host_Command;
begin
hold_master_address[PCI_BUS_DATA_RANGE:0] <= `BUS_IMPOSSIBLE_VALUE;
hold_master_command[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_4;
hold_master_command[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_READ_4;
hold_master_data[PCI_BUS_DATA_RANGE:0] <= `BUS_IMPOSSIBLE_VALUE;
hold_master_byte_enables_l[PCI_BUS_CBE_RANGE:0] <= 4'hF;
hold_master_addr_par_err <= 1'b0;
/trunk/pci_example_chip/pci_example_chip.v
1,5 → 1,5
//===========================================================================
// $Id: pci_example_chip.v,v 1.14 2001-08-15 10:31:47 bbeaver Exp $
// $Id: pci_example_chip.v,v 1.15 2001-09-26 09:48:56 bbeaver Exp $
//
// Copyright 2001 Blue Beaver. All Rights Reserved.
//
199,7 → 199,7
// good timing. This will make verification simpler.
wire pci_reset_comb_sync;
 
pci_synchronizer_flop sync_reset_flop (
synchronizer_flop sync_reset_flop (
.data_in (1'b1),
.clk_out (pci_clk),
.sync_data_out (pci_reset_comb_sync), // Goes to 1'b0 on reset
/trunk/pci_bus_monitor/pci_bus_monitor.v
1,5 → 1,5
//===========================================================================
// $Id: pci_bus_monitor.v,v 1.12 2001-08-15 10:31:47 bbeaver Exp $
// $Id: pci_bus_monitor.v,v 1.13 2001-09-26 09:48:54 bbeaver Exp $
//
// Copyright 2001 Blue Beaver. All Rights Reserved.
//
940,10 → 940,10
PCI_COMMAND_IO_WRITE:
$display (" monitor - IO Write started, AD: 'h%x, CBE: 'h%x, at time %t",
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
PCI_COMMAND_RESERVED_4:
PCI_COMMAND_RESERVED_READ_4:
$display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
PCI_COMMAND_RESERVED_5:
PCI_COMMAND_RESERVED_WRITE_5:
$display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
PCI_COMMAND_MEMORY_READ:
952,10 → 952,10
PCI_COMMAND_MEMORY_WRITE:
$display (" monitor - Memory Write started, AD: 'h%x, CBE: 'h%x, at time %t",
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
PCI_COMMAND_RESERVED_8:
PCI_COMMAND_RESERVED_READ_8:
$display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
PCI_COMMAND_RESERVED_9:
PCI_COMMAND_RESERVED_WRITE_9:
$display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
PCI_COMMAND_CONFIG_READ:
/trunk/pci_behaviorial_device/pci_behaviorial_master.v
1,5 → 1,5
//===========================================================================
// $Id: pci_behaviorial_master.v,v 1.10 2001-08-15 10:31:46 bbeaver Exp $
// $Id: pci_behaviorial_master.v,v 1.11 2001-09-26 09:48:43 bbeaver Exp $
//
// Copyright 2001 Blue Beaver. All Rights Reserved.
//
502,7 → 502,7
begin // might have lost things after first step. Undrive everything.
master_ad_out[PCI_BUS_DATA_RANGE:0] <= `BUS_IMPOSSIBLE_VALUE;
master_ad_oe <= 1'b0;
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_4; // easy to see
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_READ_4; // easy to see
master_cbe_oe <= 1'b0;
master_debug_force_bad_par <= 1'b0;
master_got_master_abort <= 1'b0;
985,7 → 985,7
// Otherwise enforce an idle state
master_ad_out[PCI_BUS_DATA_RANGE:0] <= `BUS_IMPOSSIBLE_VALUE;
master_ad_oe <= 1'b0;
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_4; // easy to see
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_READ_4; // easy to see
master_cbe_oe <= 1'b0;
master_debug_force_bad_par <= 1'b0;
master_got_master_abort <= got_master_abort;
1212,7 → 1212,7
error_detected <= ~error_detected;
master_ad_out[PCI_BUS_DATA_RANGE:0] <= `BUS_IMPOSSIBLE_VALUE;
master_ad_oe <= 1'b0;
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_4; // easy to see
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_READ_4; // easy to see
master_cbe_oe <= 1'b0;
master_debug_force_bad_par <= 1'b0;
master_got_master_abort <= 1'b0;
1319,9 → 1319,9
Complain_That_Test_Not_Written (want_fast_back_to_back);
PCI_COMMAND_IO_WRITE:
Complain_That_Test_Not_Written (want_fast_back_to_back);
PCI_COMMAND_RESERVED_4:
PCI_COMMAND_RESERVED_READ_4:
Complain_That_Test_Not_Written (want_fast_back_to_back);
PCI_COMMAND_RESERVED_5:
PCI_COMMAND_RESERVED_WRITE_5:
Complain_That_Test_Not_Written (want_fast_back_to_back);
PCI_COMMAND_MEMORY_READ:
Execute_Master_PCI_Ref (TEST_MASTER_DOING_MEM_READ,
1329,9 → 1329,9
PCI_COMMAND_MEMORY_WRITE:
Execute_Master_PCI_Ref (TEST_MASTER_DOING_MEM_WRITE,
want_fast_back_to_back);
PCI_COMMAND_RESERVED_8:
PCI_COMMAND_RESERVED_READ_8:
Complain_That_Test_Not_Written (want_fast_back_to_back);
PCI_COMMAND_RESERVED_9:
PCI_COMMAND_RESERVED_WRITE_9:
Complain_That_Test_Not_Written (want_fast_back_to_back);
PCI_COMMAND_CONFIG_READ:
Execute_Master_PCI_Ref (TEST_MASTER_DOING_CONFIG_READ,
1365,7 → 1365,7
begin // park bus
master_ad_out[PCI_BUS_DATA_RANGE:0] <= `BUS_PARK_VALUE;
master_ad_oe <= 1'b1;
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_4;
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_READ_4;
master_cbe_oe <= 1'b1;
end
else
1372,7 → 1372,7
begin // unpark if grant is removed
master_ad_out[PCI_BUS_DATA_RANGE:0] <= `BUS_IMPOSSIBLE_VALUE;
master_ad_oe <= 1'b0;
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_4;
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_READ_4;
master_cbe_oe <= 1'b0;
end
// NOTE WORKING need to handle master_got_target_retry here
/trunk/pci_blue_interface/pci_blue_interface.v
1,5 → 1,5
//===========================================================================
// $Id: pci_blue_interface.v,v 1.24 2001-08-15 10:31:46 bbeaver Exp $
// $Id: pci_blue_interface.v,v 1.25 2001-09-26 09:48:48 bbeaver Exp $
//
// Copyright 2001 Blue Beaver. All Rights Reserved.
//
279,7 → 279,7
end
 
// First level synchronization of PCI Reset signal
pci_synchronizer_flop sync_reset_flop (
synchronizer_flop sync_reset_flop (
.data_in (pci_reset_comb),
.clk_out (host_sync_clk),
.sync_data_out (pci_reset_sync),
289,7 → 289,7
// Synchronization of signal which says PCI Interface sees some sort of error
wire target_config_reg_signals_some_error;
 
pci_synchronizer_flop sync_error_flop (
synchronizer_flop sync_error_flop (
.data_in (target_config_reg_signals_some_error),
.clk_out (host_sync_clk),
.sync_data_out (pci_config_reg_signals_some_error),
1122,7 → 1122,7
// Once SERR is debounced, it is safe to look at it in verilog.
wire SERR_sync;
 
pci_synchronizer_flop sync_SERR_flop (
synchronizer_flop sync_SERR_flop (
.data_in (pci_serr_in_prev),
.clk_out (pci_sync_clk),
.sync_data_out (SERR_sync),
/trunk/test_pci_master.dsk
1,6 → 1,6
<!DOCTYPE Desktop SYSTEM "hdl-prj.dtd">
<Desktop>
<ProjectWindow X="-4" Y="-28" W="1096" H="744">
<ProjectWindow X="50" Y="43" W="864" H="574">
<Column>450</Column>
<Column>60</Column>
<Column>50</Column>
/trunk/test_pci_master.hpj
6,7 → 6,7
<File IsIndirectlyAdded="0">pci_blue_fifos\pci_blue_fifo_flags.v</File>
<File IsIndirectlyAdded="0">pci_vendor_lib\pci_vendor_lib.v</File>
<File IsIndirectlyAdded="0">pci_blue_master\pci_blue_master.v</File>
<File IsIndirectlyAdded="0">function_lib\synchronizer_flop.v</File>
<File IsIndirectlyAdded="0">..\misc\synchronizer_flop.v</File>
<File IsIndirectlyAdded="1">pci_blue_include\pci_blue_options.vh</File>
<File IsIndirectlyAdded="1">pci_blue_include\pci_blue_constants.vh</File>
</UserSourceFileList>
/trunk/pci_test_system/pci_test_commander.v
1,5 → 1,5
//===========================================================================
// $Id: pci_test_commander.v,v 1.10 2001-08-15 10:31:47 bbeaver Exp $
// $Id: pci_test_commander.v,v 1.11 2001-09-26 09:48:59 bbeaver Exp $
//
// Copyright 2001 Blue Beaver. All Rights Reserved.
//
1339,7 → 1339,7
present_test_name[79:0] <= "Nowhere___";
test_master_number <= 3'h0;
test_address[PCI_BUS_DATA_RANGE:0] <= `PCI_BUS_DATA_ZERO;
test_command <= PCI_COMMAND_RESERVED_4;
test_command <= PCI_COMMAND_RESERVED_READ_4;
test_data[PCI_BUS_DATA_RANGE:0] <= `PCI_BUS_DATA_ZERO;
test_byte_enables_l[PCI_BUS_CBE_RANGE:0] <= `Test_All_Bytes;
test_size <= `Test_One_Word;

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