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URL https://opencores.org/ocsvn/v586/v586/trunk

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Rev 79 → Rev 80

/v586/trunk/xdc/TOP_SYS.xdc
17,7 → 17,7
# All timing constraint translations are rough conversions, intended to act as a template for further manual refinement. The translations should not be expected to produce semantically identical results to the original ucf. Each xdc timing constraint must be manually inspected and verified to ensure it captures the desired intent
 
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:3
create_clock -name clk100 -period 10.000 [get_ports clk100]
create_clock -period 10.000 -name clk100 [get_ports clk100]
 
set_property PACKAGE_PIN C4 [get_ports RXD]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:5
32,7 → 32,7
#NET "TXD_B" LOC = "V15" | IOSTANDARD = "LVCMOS33" ;
 
 
set_property PACKAGE_PIN U9 [get_ports rstn]
set_property PACKAGE_PIN C12 [get_ports rstn]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:12
# The conversion of 'IOSTANDARD' constraint on 'net' object 'rstn' has been applied to the port object 'rstn'.
set_property IOSTANDARD LVCMOS33 [get_ports rstn]
48,8 → 48,8
## Clock signal
#NET "clk" LOC = "E3" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L12P_T1_MRCC_35, Sch name = CLK100MHZ
#NET "clk" TNM_NET = sys_clk_pin;
#TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100 MHz HIGH 50%;
#TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100 MHz HIGH 50%;
 
## Switches
#NET "sw<0>" LOC = "U9" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L21P_T3_DQS_34, Sch name = SW0
#Bank = 34, Pin name = IO_25_34, Sch name = SW1
99,11 → 99,13
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:43
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpioA[0]' has been applied to the port object 'gpioA[0]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpioA[0]}]
 
## LEDs
#NET "dbg1" LOC = "T8" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L24N_T3_34, Sch name = LED0
#NET "dbg2" LOC = "V9" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L21N_T3_DQS_34, Sch name = LED1
#NET "gpioA<2>" LOC = "R8" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L24P_T3_34, Sch name = LED2
set_property PACKAGE_PIN R8 [get_ports {gpioA[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpioA[1]}]
#Bank = 34, Pin name = IO_L23N_T3_34, Sch name = LED3
set_property PACKAGE_PIN T6 [get_ports {gpioA[3]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:49
118,25 → 120,25
#NET "gpioA<6>" LOC = "U7" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L22P_T3_34, Sch name = LED6
#NET "gpioA<7>" LOC = "U6" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L22N_T3_34, Sch name = LED7
#Bank = 34, Pin name = IO_L10N_T1_34, Sch name = LED8
set_property PACKAGE_PIN V4 [get_ports {gpioB[0]}]
set_property PACKAGE_PIN V4 [get_ports {miso}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:54
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpioB[0]' has been applied to the port object 'gpioB[0]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpioB[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {miso}]
#Bank = 34, Pin name = IO_L8N_T1_34, Sch name = LED9
set_property PACKAGE_PIN U3 [get_ports {gpioB[1]}]
set_property PACKAGE_PIN U3 [get_ports {mosi}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:55
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpioB[1]' has been applied to the port object 'gpioB[1]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpioB[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {mosi}]
#Bank = 34, Pin name = IO_L7N_T1_34, Sch name = LED10#NET "debug<4>" LOC = "R1" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L17P_T2_34, Sch name = LED11
set_property PACKAGE_PIN V1 [get_ports {gpioB[2]}]
set_property PACKAGE_PIN V1 [get_ports {sclk}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:56
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpioB[2]' has been applied to the port object 'gpioB[2]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpioB[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sclk}]
#Bank = 34, Pin name = IO_L7N_T1_34, Sch name = LED10#NET "debug<4>" LOC = "R1" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L17P_T2_34, Sch name = LED11
set_property PACKAGE_PIN R1 [get_ports {gpioB[3]}]
#set_property PACKAGE_PIN R1 [get_ports {gpioB[3]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:57
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpioB[3]' has been applied to the port object 'gpioB[3]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpioB[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpioB[3]}]
#Bank = 34, Pin name = IO_L13N_T2_MRCC_34, Sch name = LED12
set_property PACKAGE_PIN P5 [get_ports {gpioB[4]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:58
192,28 → 194,28
#NET "btnL" LOC = "T16" | IOSTANDARD = "LVCMOS33"; #Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14, Sch name = BTNL
#NET "btnR" LOC = "R10" | IOSTANDARD = "LVCMOS33"; #Bank = 14, Pin name = IO_25_14, Sch name = BTNR
#NET "btnD" LOC = "V10" | IOSTANDARD = "LVCMOS33"; #Bank = 14, Pin name = IO_L21P_T3_DQS_14, Sch name = BTND
 
## Pmod Header JA
#Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name = JA1
set_property PACKAGE_PIN B13 [get_ports {gpioA[6]}]
#set_property PACKAGE_PIN B13 [get_ports {gpioA[6]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:99
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpioA[6]' has been applied to the port object 'gpioA[6]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpioA[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpioA[6]}]
#Bank = 15, Pin name = IO_L5N_T0_AD9N_15, Sch name = JA2
set_property PACKAGE_PIN F14 [get_ports {gpioA[4]}]
#set_property PACKAGE_PIN F14 [get_ports {gpioA[4]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:100
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpioA[4]' has been applied to the port object 'gpioA[4]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpioA[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpioA[4]}]
#Bank = 15, Pin name = IO_L16N_T2_A27_15, Sch name = JA3
set_property PACKAGE_PIN D17 [get_ports {gpioA[1]}]
#set_property PACKAGE_PIN D17 [get_ports {gpioA[1]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:101
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpioA[1]' has been applied to the port object 'gpioA[1]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpioA[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpioA[1]}]
#Bank = 15, Pin name = IO_L16P_T2_A28_15, Sch name = JA4
set_property PACKAGE_PIN E17 [get_ports {gpioA[2]}]
#set_property PACKAGE_PIN E17 [get_ports {gpioA[2]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:102
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpioA[2]' has been applied to the port object 'gpioA[2]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpioA[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpioA[2]}]
#NET "JA<4>" LOC = "G13" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_0_15, Sch name = JA7
#NET "JA<5>" LOC = "C17" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L20N_T3_A19_15, Sch name = JA8
#NET "JA<6>" LOC = "D18" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L21N_T3_A17_15, Sch name = JA9
227,8 → 229,8
#NET "JB<4>" LOC = "K16" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_25_15, Sch name = JB7
#NET "JB<5>" LOC = "R16" | IOSTANDARD = "LVCMOS33"; #Bank = CONFIG, Pin name = IO_L15P_T2_DQS_RWR_B_14, Sch name = JB8
#NET "JB<6>" LOC = "T9" | IOSTANDARD = "LVCMOS33"; #Bank = 14, Pin name = IO_L24P_T3_A01_D17_14, Sch name = JB9
#NET "JB<7>" LOC = "U11" | IOSTANDARD = "LVCMOS33"; #Bank = 14, Pin name = IO_L19N_T3_A09_D25_VREF_14, Sch name = JB10
#NET "JB<7>" LOC = "U11" | IOSTANDARD = "LVCMOS33"; #Bank = 14, Pin name = IO_L19N_T3_A09_D25_VREF_14, Sch name = JB10
 
## Pmod Header JC
#NET "JC<0>" LOC = "K2" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L23P_T3_35, Sch name = JC1
#NET "JC<1>" LOC = "E7" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L6P_T0_35, Sch name = JC2
238,7 → 240,7
#NET "JC<5>" LOC = "E6" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L5P_T0_AD13P_35, Sch name = JC8
#NET "JC<6>" LOC = "J2" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L22N_T3_35, Sch name = JC9
#NET "JC<7>" LOC = "G6" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L19P_T3_35, Sch name = JC10
 
## Pmod Header JD
#NET "JD<0>" LOC = "H4" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L21N_T2_DQS_35, Sch name = JD1
#NET "JD<1>" LOC = "H1" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L17P_T2_35, Sch name = JD2
248,7 → 250,7
#NET "JD<5>" LOC = "G4" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L20P_T3_35, Sch name = JD8
#NET "JD<6>" LOC = "G2" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L15N_T2_DQS_35, Sch name = JD9
#NET "JD<7>" LOC = "F3" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L13N_T2_MRCC_35, Sch name = JD10
 
## Pmod Header JXADC
#NET "JXADC<0>" LOC = "A13" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L9P_T1_DQS_AD3P_15, Sch name = XADC1_P -> XA1_P
#NET "JXADC<1>" LOC = "A15" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L8P_T1_AD10P_15, Sch name = XADC2_P -> XA2_P
256,7 → 258,7
#NET "JXADC<3>" LOC = "B18" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L10P_T1_AD11P_15, Sch name = XADC4_P -> XA4_P
#NET "JXADC<4>" LOC = "A14" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L9N_T1_DQS_AD3N_15, Sch name = XADC1_N -> XA1_N
#NET "JXADC<5>" LOC = "A16" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L8N_T1_AD10N_15, Sch name = XADC2_N -> XA2_N
#NET "JXADC<6>" LOC = "B17" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L7N_T1_AD2N_15, Sch name = XADC3_N -> XA3_N
#NET "JXADC<6>" LOC = "B17" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L7N_T1_AD2N_15, Sch name = XADC3_N -> XA3_N
#NET "JXADC<7>" LOC = "A18" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L10N_T1_AD11N_15, Sch name = XADC4_N -> XA4_N
 
## VGA Connector
293,12 → 295,51
#NET "sdVss" LOC = "D2" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L14N_T2_SRCC_35, Sch name = SD_DAT3
#NET "gpioA<6>" LOC = "C2" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L16P_T2_35, Sch name = SD_DAT0
#Bank = 35, Pin name = IO_L9N_T1_DQS_AD7N_35, Sch name = SD_CD
set_property PACKAGE_PIN A1 [get_ports {gpioA[7]}]
#set_property PACKAGE_PIN A1 [get_ports {gpioA[7]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:181
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpioA[7]' has been applied to the port object 'gpioA[7]'.
#set_property IOSTANDARD LVCMOS33 [get_ports {gpioA[7]}]
 
 
##Micro SD Connector
##Bank = 35, Pin name = IO_L14P_T2_SRCC_35, Sch name = SD_RESET
set_property PACKAGE_PIN E2 [get_ports {sdreset}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdreset}]
##Bank = 35, Pin name = IO_L9N_T1_DQS_AD7N_35, Sch name = SD_CD
#set_property PACKAGE_PIN A1 [get_ports {gpioA[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpioA[2]}]
##Bank = 35, Pin name = IO_L9P_T1_DQS_AD7P_35, Sch name = SD_SCK
set_property PACKAGE_PIN B1 [get_ports {gpioA[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpioA[4]}]
##Bank = 35, Pin name = IO_L16N_T2_35, Sch name = SD_CMD
set_property PACKAGE_PIN C1 [get_ports {gpioA[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpioA[6]}]
##Bank = 35, Pin name = IO_L16P_T2_35, Sch name = SD_DAT0
set_property PACKAGE_PIN C2 [get_ports {gpioA[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpioA[7]}]
##Bank = 35, Pin name = IO_L18N_T2_35, Sch name = SD_DAT1
#set_property PACKAGE_PIN E1 [get_ports {sdData[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sdData[1]}]
##Bank = 35, Pin name = IO_L18P_T2_35, Sch name = SD_DAT2
#set_property PACKAGE_PIN F1 [get_ports {sdData[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sdData[2]}]
##Bank = 35, Pin name = IO_L14N_T2_SRCC_35, Sch name = SD_DAT3
set_property PACKAGE_PIN D2 [get_ports {gpioA[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpioA[2]}]
 
set_property PACKAGE_PIN D13 [get_ports {gpioB[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpioB[0]}]
set_property PACKAGE_PIN B14 [get_ports {gpioB[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpioB[1]}]
set_property PACKAGE_PIN D15 [get_ports {gpioB[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpioB[2]}]
set_property PACKAGE_PIN C15 [get_ports gpioB[3]]
set_property IOSTANDARD LVCMOS33 [get_ports gpioB[3]]
 
set_property PACKAGE_PIN C16 [get_ports {aclInt1}]
set_property IOSTANDARD LVCMOS33 [get_ports {aclInt1}]
set_property PACKAGE_PIN E15 [get_ports {aclInt2}]
set_property IOSTANDARD LVCMOS33 [get_ports {aclInt2}]
 
## Accelerometer
#NET "aclMISO" LOC = "D13" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L6N_T0_VREF_15, Sch name = ACL_MISO
334,18 → 375,43
#NET "PS2Data" LOC = "B2" | PULLUP | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L10N_T1_AD15N_35, Sch name = PS2_DATA
 
## SMSC Ethernet PHY
#NET "PhyMdc" LOC = "C9" | IOSTANDARD = "LVCMOS33"; #Bank = 16, Pin name = IO_L11P_T1_SRCC_16, Sch name = ETH_MDC
#NET "PhyMdio" LOC = "A9" | IOSTANDARD = "LVCMOS33"; #Bank = 16, Pin name = IO_L14N_T2_SRCC_16, Sch name = ETH_MDIO
#NET "PhyRstn" LOC = "B3" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L10P_T1_AD15P_35, Sch name = ETH_RSTN
#NET "PhyCrs" LOC = "D9" | IOSTANDARD = "LVCMOS33"; #Bank = 16, Pin name = IO_L6N_T0_VREF_16, Sch name = ETH_CRSDV
#NET "PhyRxErr" LOC = "C10" | IOSTANDARD = "LVCMOS33"; #Bank = 16, Pin name = IO_L13N_T2_MRCC_16, Sch name = ETH_RXERR
#NET "PhyRxd<0>" LOC = "D10" | IOSTANDARD = "LVCMOS33"; #Bank = 16, Pin name = IO_L19N_T3_VREF_16, Sch name = ETH_RXD0
#NET "PhyRxd<1>" LOC = "C11" | IOSTANDARD = "LVCMOS33"; #Bank = 16, Pin name = IO_L13P_T2_MRCC_16, Sch name = ETH_RXD1
#NET "PhyTxEn" LOC = "B9" | IOSTANDARD = "LVCMOS33"; #Bank = 16, Pin name = IO_L11N_T1_SRCC_16, Sch name = ETH_TXEN
#NET "PhyTxd<0>" LOC = "A10" | IOSTANDARD = "LVCMOS33"; #Bank = 16, Pin name = IO_L14P_T2_SRCC_16, Sch name = ETH_TXD0
#NET "PhyTxd<1>" LOC = "A8" | IOSTANDARD = "LVCMOS33"; #Bank = 16, Pin name = IO_L12N_T1_MRCC_16, Sch name = ETH_TXD1
#NET "PhyClk50Mhz" LOC = "D5" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L11P_T1_SRCC_35, Sch name = ETH_REFCLK
#NET "PhyIntn" LOC = "B8" | IOSTANDARD = "LVCMOS33"; #Bank = 16, Pin name = IO_L12P_T1_MRCC_16, Sch name = ETH_INTN
##SMSC Ethernet PHY
##Bank = 16, Pin name = IO_L11P_T1_SRCC_16, Sch name = ETH_MDC
set_property PACKAGE_PIN C9 [get_ports PhyMdc]
set_property IOSTANDARD LVCMOS33 [get_ports PhyMdc]
##Bank = 16, Pin name = IO_L14N_T2_SRCC_16, Sch name = ETH_MDIO
set_property PACKAGE_PIN A9 [get_ports PhyMdio]
set_property IOSTANDARD LVCMOS33 [get_ports PhyMdio]
##Bank = 35, Pin name = IO_L10P_T1_AD15P_35, Sch name = ETH_RSTN
set_property PACKAGE_PIN B3 [get_ports PhyRstn]
set_property IOSTANDARD LVCMOS33 [get_ports PhyRstn]
##Bank = 16, Pin name = IO_L6N_T0_VREF_16, Sch name = ETH_CRSDV
set_property PACKAGE_PIN D9 [get_ports PhyCrs]
set_property IOSTANDARD LVCMOS33 [get_ports PhyCrs]
##Bank = 16, Pin name = IO_L13N_T2_MRCC_16, Sch name = ETH_RXERR
set_property PACKAGE_PIN C10 [get_ports PhyRxErr]
set_property IOSTANDARD LVCMOS33 [get_ports PhyRxErr]
##Bank = 16, Pin name = IO_L19N_T3_VREF_16, Sch name = ETH_RXD0
set_property PACKAGE_PIN D10 [get_ports {PhyRxd[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PhyRxd[0]}]
##Bank = 16, Pin name = IO_L13P_T2_MRCC_16, Sch name = ETH_RXD1
set_property PACKAGE_PIN C11 [get_ports {PhyRxd[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PhyRxd[1]}]
##Bank = 16, Pin name = IO_L11N_T1_SRCC_16, Sch name = ETH_TXEN
set_property PACKAGE_PIN B9 [get_ports PhyTxEn]
set_property IOSTANDARD LVCMOS33 [get_ports PhyTxEn]
##Bank = 16, Pin name = IO_L14P_T2_SRCC_16, Sch name = ETH_TXD0
set_property PACKAGE_PIN A10 [get_ports {PhyTxd[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PhyTxd[0]}]
##Bank = 16, Pin name = IO_L12N_T1_MRCC_16, Sch name = ETH_TXD1
set_property PACKAGE_PIN A8 [get_ports {PhyTxd[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PhyTxd[1]}]
##Bank = 35, Pin name = IO_L11P_T1_SRCC_35, Sch name = ETH_REFCLK
set_property PACKAGE_PIN D5 [get_ports PhyClk50Mhz]
set_property IOSTANDARD LVCMOS33 [get_ports PhyClk50Mhz]
##Bank = 16, Pin name = IO_L12P_T1_MRCC_16, Sch name = ETH_INTN
set_property PACKAGE_PIN B8 [get_ports PhyIntn]
set_property IOSTANDARD LVCMOS33 [get_ports PhyIntn]
 
## Quad SPI Flash
#NET "sdclk" LOC = "E9" ; #Bank = CONFIG, Pin name = CCLK_0, Sch name = QSPI_SCK
379,8 → 445,9
#Bank = 14, Pin name = IO_L14N_T2_SRCC_14, Sch name = CRAM_CLK
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:241
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extCLK' has been applied to the port object 'extCLK'.
set_property PACKAGE_PIN T15 [get_ports extCLK]
set_property IOSTANDARD LVCMOS33 [get_ports extCLK]
#Bank = 14, Pin name = IO_L23P_T3_A03_D19_14, Sch name = CRAM_ADVN
#Bank = 14, Pin name = IO_L23P_T3_A03_D19_14, Sch name = CRAM_ADVN
set_property PACKAGE_PIN T13 [get_ports extADV]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:242
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extADV' has been applied to the port object 'extADV'.
416,10 → 483,10
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extUB' has been applied to the port object 'extUB'.
set_property IOSTANDARD LVCMOS33 [get_ports extUB]
#Bank = 14, Pin name = IO_L14P_T2_SRCC_14, Sch name = CRAM_WAIT
set_property PACKAGE_PIN T14 [get_ports extWAIT]
#set_property PACKAGE_PIN T14 [get_ports extWAIT]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:249
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extWAIT' has been applied to the port object 'extWAIT'.
set_property IOSTANDARD LVCMOS33 [get_ports extWAIT]
#set_property IOSTANDARD LVCMOS33 [get_ports extWAIT]
 
#Bank = 14, Pin name = IO_L5P_T0_DQ06_14, Sch name = CRAM_DQ0
set_property PACKAGE_PIN R12 [get_ports {extDB[0]}]
612,12 → 679,27
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:289
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extA[22]' has been applied to the port object 'extA[22]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extA[22]}]
#Bank = 14, Pin name = IO_L23N_T3_A02_D18_14, Sch name = CRAM_A22
#Bank = 14, Pin name = IO_L23N_T3_A02_D18_14, Sch name = CRAM_A22
set_property PACKAGE_PIN U13 [get_ports {extA[23]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:290
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extA[23]' has been applied to the port object 'extA[23]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extA[23]}]
 
# PlanAhead Generated physical constraints
 
set_property PACKAGE_PIN T15 [get_ports extCLK]
 
#create_pblock pblock_i_vliw
#add_cells_to_pblock [get_pblocks pblock_i_vliw] [get_cells -quiet [list v586/ucore/i_vliw]]
#resize_pblock [get_pblocks pblock_i_vliw] -add {CLOCKREGION_X1Y2:CLOCKREGION_X1Y3}
#create_pblock pblock_i_deco
#add_cells_to_pblock [get_pblocks pblock_i_deco] [get_cells -quiet [list v586/ucore/i_deco]]
#resize_pblock [get_pblocks pblock_i_deco] -add {CLOCKREGION_X0Y3:CLOCKREGION_X1Y3}
#create_pblock pblock_i_useq
#add_cells_to_pblock [get_pblocks pblock_i_useq] [get_cells -quiet [list v586/ucore/i_useq]]
#resize_pblock [get_pblocks pblock_i_useq] -add {CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}
#create_pblock pblock_ubiu
#add_cells_to_pblock [get_pblocks pblock_ubiu] [get_cells -quiet [list v586/ubiu]]
#resize_pblock [get_pblocks pblock_ubiu] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y2}
 
 
 
 

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