URL
https://opencores.org/ocsvn/8051/8051/trunk
Subversion Repositories 8051
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 8 to Rev 9
- ↔ Reverse comparison
Rev 8 → Rev 9
/trunk/rtl/verilog/oc8051_defines.v
336,14 → 336,11
// |
// compare source select |
// |
`define OC8051_CSS_AZ 3'b000 // eq = accumulator == zero |
`define OC8051_CSS_AR 3'b001 // eq = accumulator == ram |
`define OC8051_CSS_AC 3'b010 // eq = accumulator == constant |
`define OC8051_CSS_CR 3'b011 // eq = constant == ram |
`define OC8051_CSS_DES 3'b100 // eq = destination == zero |
`define OC8051_CSS_CY 3'b101 // eq = cy |
`define OC8051_CSS_BIT 3'b110 // eq = b_in |
`define OC8051_CSS_DC 3'b000 // don't care |
`define OC8051_CSS_AZ 2'b00 // eq = accumulator == zero |
`define OC8051_CSS_DES 2'b01 // eq = destination == zero |
`define OC8051_CSS_CY 2'b10 // eq = cy |
`define OC8051_CSS_BIT 2'b11 // eq = b_in |
`define OC8051_CSS_DC 2'b00 // don't care |
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// |
/trunk/rtl/verilog/oc8051_comp.v
65,7 → 65,7
// |
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input [2:0] sel; |
input [1:0] sel; |
input b_in, cy; |
input [7:0] acc, ram, op2, des; |
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76,9 → 76,6
begin |
case (sel) |
`OC8051_CSS_AZ : eq = (acc == 8'h00); |
`OC8051_CSS_AR : eq = (acc == ram); |
`OC8051_CSS_AC : eq = (acc == op2); |
`OC8051_CSS_CR : eq = (op2 == ram); |
`OC8051_CSS_DES : eq = (des == 8'h00); |
`OC8051_CSS_CY : eq = cy; |
`OC8051_CSS_BIT : eq = b_in; |
/trunk/rtl/verilog/oc8051_top.v
167,7 → 167,7
// comp_sel select source1 and source2 to compare |
// eq result (from comp1 to decoder) |
// wad2, wad2_r write to accumulator from destination 2 |
wire [2:0] comp_sel; |
wire [1:0] comp_sel; |
wire eq, wad2, wad2_r; |
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/trunk/rtl/verilog/oc8051_decoder.v
97,9 → 97,9
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reg reti, write_x, rmw; |
reg wr, bit_addr, src_sel3, rom_addr_sel, ext_addr_sel, pc_wr, wad2; |
reg [1:0] psw_set, ram_rd_sel, src_sel1, src_sel2, pc_sel, cy_sel; |
reg [1:0] comp_sel, psw_set, ram_rd_sel, src_sel1, src_sel2, pc_sel, cy_sel; |
reg [3:0] alu_op; |
reg [2:0] comp_sel, ram_wr_sel, imm_sel; |
reg [2:0] ram_wr_sel, imm_sel; |
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// |
// state if 2'b00 then normal execution, sle instructin that need more than one clock |