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Subversion Repositories artec_dongle_ii_fpga
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/artec_dongle_ii_fpga/trunk/doc/FlexyICE_II_v23_datasheet_ver1_08.odt
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artec_dongle_ii_fpga/trunk/doc/FlexyICE_II_v23_datasheet_ver1_08.odt
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Index: artec_dongle_ii_fpga/trunk/altera_quartus_proj/dongle_syn.qpf
===================================================================
--- artec_dongle_ii_fpga/trunk/altera_quartus_proj/dongle_syn.qpf (revision 8)
+++ artec_dongle_ii_fpga/trunk/altera_quartus_proj/dongle_syn.qpf (revision 9)
@@ -1,23 +1,23 @@
-# Copyright (C) 1991-2006 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-
-
-
-QUARTUS_VERSION = "6.0"
-DATE = "13:34:29 August 31, 2006"
-
-
-# Revisions
-
-PROJECT_REVISION = "dongle_syn"
+# Copyright (C) 1991-2006 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+
+QUARTUS_VERSION = "6.0"
+DATE = "13:34:29 August 31, 2006"
+
+
+# Revisions
+
+PROJECT_REVISION = "dongle_syn"
Index: artec_dongle_ii_fpga/trunk/altera_quartus_proj/dongle_syn.qsf
===================================================================
--- artec_dongle_ii_fpga/trunk/altera_quartus_proj/dongle_syn.qsf (revision 8)
+++ artec_dongle_ii_fpga/trunk/altera_quartus_proj/dongle_syn.qsf (revision 9)
@@ -1,226 +1,247 @@
-# Copyright (C) 1991-2006 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-
-
-# The default values for assignments are stored in the file
-# dongle_syn_assignment_defaults.qdf
-# If this file doesn't exist, and for assignments not listed, see file
-# assignment_defaults.qdf
-
-# Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus II software
-# and any changes you make may be lost or overwritten.
-
-
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name DEVICE EP3C5F256C7
-set_global_assignment -name TOP_LEVEL_ENTITY design_top
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:34:29 AUGUST 31, 2006"
-set_global_assignment -name LAST_QUARTUS_VERSION 8.0
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
-set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256
-set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPCS1
-set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
-set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER ON
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to lad
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to fl_data
-set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to hdr
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to usb_bd
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to fl_addr
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to fl_ce_n
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to fl_oe_n
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to fl_rp_n
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to fl_we_n
-set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to led_green
-set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to led_red
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to scn_seg
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to seg_out
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to usb_rd_n
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to usb_wr
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hdr[3]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hdr[5]
-set_global_assignment -name VHDL_FILE ../src/postcode_ser/fifo.vhd
-set_global_assignment -name VHDL_FILE ../src/postcode_ser/pc_serializer.vhd
-set_global_assignment -name VHDL_FILE ../src/usb/usb2mem.vhd
-set_global_assignment -name VHDL_FILE ../src/lpc_proto/lpc_byte.vhd
-set_global_assignment -name VHDL_FILE ../src/flash/flsh_if.vhd
-set_global_assignment -name VHDL_FILE ../src/led_sys/led_coder.vhd
-set_global_assignment -name VHDL_FILE ../src/led_sys/byte_scan_mux.vhd
-set_global_assignment -name VHDL_FILE ../src/led_sys/led_sys.vhd
-set_global_assignment -name VHDL_FILE ../src/design_top/design_top_thincandbg.vhd
-set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
-set_global_assignment -name USE_CONFIGURATION_DEVICE ON
-set_global_assignment -name POWER_USE_INPUT_FILES OFF
-set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER sys_clk -section_id sys25
-set_instance_assignment -name CLOCK_SETTINGS design_top|lclk -to lclk
-set_instance_assignment -name CLOCK_SETTINGS design_top|sys_clk -to sys_clk
-set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF
-set_global_assignment -name FMAX_REQUIREMENT "25 MHz" -section_id design_top|sys_clk
-set_global_assignment -name FMAX_REQUIREMENT "33 MHz" -section_id design_top|lclk
-set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 100%
-set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 100%
-set_global_assignment -name POWER_USE_PVA OFF
-set_location_assignment PIN_L4 -to fl_data[0]
-set_location_assignment PIN_L1 -to fl_data[1]
-set_location_assignment PIN_K2 -to fl_data[2]
-set_location_assignment PIN_K5 -to fl_data[3]
-set_location_assignment PIN_J1 -to fl_data[4]
-set_location_assignment PIN_J6 -to fl_data[5]
-set_location_assignment PIN_P2 -to fl_data[6]
-set_location_assignment PIN_L6 -to fl_data[7]
-set_location_assignment PIN_L3 -to fl_data[8]
-set_location_assignment PIN_L2 -to fl_data[9]
-set_location_assignment PIN_K1 -to fl_data[10]
-set_location_assignment PIN_J2 -to fl_data[11]
-set_location_assignment PIN_K6 -to fl_data[12]
-set_location_assignment PIN_P1 -to fl_data[13]
-set_location_assignment PIN_R1 -to fl_data[14]
-set_location_assignment PIN_N2 -to fl_data[15]
-set_location_assignment PIN_N1 -to fl_sts
-set_location_assignment PIN_N3 -to fl_addr[0]
-set_location_assignment PIN_M7 -to fl_addr[1]
-set_location_assignment PIN_M8 -to fl_addr[2]
-set_location_assignment PIN_N8 -to fl_addr[3]
-set_location_assignment PIN_N6 -to fl_addr[4]
-set_location_assignment PIN_K8 -to fl_addr[5]
-set_location_assignment PIN_L7 -to fl_addr[6]
-set_location_assignment PIN_L8 -to fl_addr[7]
-set_location_assignment PIN_T8 -to fl_addr[8]
-set_location_assignment PIN_P8 -to fl_addr[9]
-set_location_assignment PIN_T7 -to fl_addr[10]
-set_location_assignment PIN_R7 -to fl_addr[11]
-set_location_assignment PIN_T6 -to fl_addr[12]
-set_location_assignment PIN_R6 -to fl_addr[13]
-set_location_assignment PIN_P6 -to fl_addr[14]
-set_location_assignment PIN_T5 -to fl_addr[15]
-set_location_assignment PIN_R5 -to fl_addr[16]
-set_location_assignment PIN_T4 -to fl_addr[17]
-set_location_assignment PIN_R4 -to fl_addr[18]
-set_location_assignment PIN_T3 -to fl_addr[19]
-set_location_assignment PIN_R3 -to fl_addr[20]
-set_location_assignment PIN_P3 -to fl_addr[21]
-set_location_assignment PIN_T2 -to fl_addr[22]
-set_location_assignment PIN_M6 -to fl_addr[23]
-set_location_assignment PIN_N5 -to fl_we_n
-set_location_assignment PIN_P9 -to ps_addr_val
-set_location_assignment PIN_R8 -to ps_clk
-set_location_assignment PIN_T9 -to ps_confr_en
-set_location_assignment PIN_R10 -to ps_lsb_en
-set_location_assignment PIN_M9 -to ps_msb_en
-set_location_assignment PIN_T10 -to ps_wait
-set_location_assignment PIN_T12 -to ee_clk
-set_location_assignment PIN_R12 -to ee_cs_n
-set_location_assignment PIN_P11 -to ee_di
-set_location_assignment PIN_R13 -to ee_do
-set_location_assignment PIN_R11 -to ee_hold_n
-set_location_assignment PIN_T13 -to ee_write
-set_location_assignment PIN_T11 -to fl_ce_n
-set_location_assignment PIN_R9 -to fl_oe_n
-set_location_assignment PIN_E5 -to usb_bd[0]
-set_location_assignment PIN_D1 -to usb_bd[1]
-set_location_assignment PIN_F3 -to usb_bd[2]
-set_location_assignment PIN_F1 -to usb_bd[3]
-set_location_assignment PIN_F2 -to usb_bd[4]
-set_location_assignment PIN_G2 -to usb_bd[5]
-set_location_assignment PIN_F5 -to usb_bd[6]
-set_location_assignment PIN_G1 -to usb_bd[7]
-set_location_assignment PIN_G5 -to usb_rd_n
-set_location_assignment PIN_B1 -to usb_rxf_n
-set_location_assignment PIN_C2 -to usb_txe_n
-set_location_assignment PIN_D4 -to usb_wr
-set_location_assignment PIN_E15 -to lclk
-set_location_assignment PIN_E1 -to sys_clk
-set_location_assignment PIN_B7 -to led_red
-set_location_assignment PIN_A7 -to led_green
-set_location_assignment PIN_B4 -to scn_seg[0]
-set_location_assignment PIN_A4 -to scn_seg[1]
-set_location_assignment PIN_A8 -to scn_seg[2]
-set_location_assignment PIN_B5 -to scn_seg[3]
-set_location_assignment PIN_A2 -to seg_out[0]
-set_location_assignment PIN_C3 -to seg_out[1]
-set_location_assignment PIN_B3 -to seg_out[2]
-set_location_assignment PIN_A3 -to seg_out[3]
-set_location_assignment PIN_A5 -to seg_out[4]
-set_location_assignment PIN_C6 -to seg_out[5]
-set_location_assignment PIN_B6 -to seg_out[6]
-set_location_assignment PIN_A6 -to seg_out[7]
-set_location_assignment PIN_D5 -to mode[0]
-set_location_assignment PIN_E6 -to mode[1]
-set_location_assignment PIN_D6 -to mode[2]
-set_location_assignment PIN_D3 -to buf_oe_n
-set_location_assignment PIN_C15 -to lad[0]
-set_location_assignment PIN_G11 -to lad[1]
-set_location_assignment PIN_C16 -to lad[2]
-set_location_assignment PIN_D16 -to lad[3]
-set_location_assignment PIN_D15 -to lreset_n
-set_location_assignment PIN_F13 -to lframe_n
-set_location_assignment PIN_K16 -to resetn
-set_location_assignment PIN_E9 -to hdr[0]
-set_location_assignment PIN_D9 -to hdr[1]
-set_location_assignment PIN_C9 -to hdr[2]
-set_location_assignment PIN_B9 -to hdr[3]
-set_location_assignment PIN_A9 -to hdr[4]
-set_location_assignment PIN_A10 -to hdr[5]
-set_location_assignment PIN_B10 -to hdr[6]
-set_location_assignment PIN_A11 -to hdr[7]
-set_location_assignment PIN_B11 -to hdr[8]
-set_location_assignment PIN_A12 -to hdr[9]
-set_location_assignment PIN_A13 -to hdr[10]
-set_location_assignment PIN_B12 -to hdr[11]
-set_location_assignment PIN_A14 -to hdr[12]
-set_location_assignment PIN_B13 -to hdr[13]
-set_location_assignment PIN_A15 -to hdr[14]
-set_location_assignment PIN_B14 -to hdr[15]
-set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS4
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to scn_seg[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to scn_seg[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to scn_seg[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to scn_seg[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg_out
-set_location_assignment PIN_B16 -to ldev_present
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hdr[1]
-set_location_assignment PIN_K11 -to hdr_b[0]
-set_location_assignment PIN_J11 -to hdr_b[1]
-set_location_assignment PIN_K12 -to hdr_b[2]
-set_location_assignment PIN_J12 -to hdr_b[3]
-set_location_assignment PIN_M12 -to hdr_b[4]
-set_location_assignment PIN_L13 -to hdr_b[5]
-set_location_assignment PIN_N14 -to hdr_b[6]
-set_location_assignment PIN_L12 -to hdr_b[7]
-set_location_assignment PIN_P15 -to hdr_b[8]
-set_location_assignment PIN_N13 -to hdr_b[9]
-set_location_assignment PIN_P16 -to hdr_b[10]
-set_location_assignment PIN_N15 -to hdr_b[11]
-set_location_assignment PIN_L14 -to hdr_b[12]
-set_location_assignment PIN_R16 -to hdr_b[13]
-set_location_assignment PIN_L16 -to hdr_b[14]
-set_location_assignment PIN_N16 -to hdr_b[15]
-set_location_assignment PIN_N9 -to ps_ram_en
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to buf_oe_n
-set_global_assignment -name VHDL_FILE ../src/spi_eeprom/spi_master.vhd
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ldev_present
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to ldev_present
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ps_ram_en
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to fl_we_n
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to fl_ce_n
\ No newline at end of file
+# Copyright (C) 1991-2006 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+# dongle_syn_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+# assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C5F256C7
+set_global_assignment -name TOP_LEVEL_ENTITY design_top
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:34:29 AUGUST 31, 2006"
+set_global_assignment -name LAST_QUARTUS_VERSION 11.0
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
+set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPCS1
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER ON
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to lad
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to fl_data
+set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to hdr
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to usb_bd
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to fl_addr
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to fl_ce_n
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to fl_oe_n
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to fl_rp_n
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to fl_we_n
+set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to led_green
+set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to led_red
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to scn_seg
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to seg_out
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to usb_rd_n
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to usb_wr
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hdr[3]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hdr[5]
+set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name POWER_USE_INPUT_FILES OFF
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER sys_clk -section_id sys25
+set_instance_assignment -name CLOCK_SETTINGS design_top|lclk -to lclk
+set_instance_assignment -name CLOCK_SETTINGS design_top|sys_clk -to sys_clk
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF
+set_global_assignment -name FMAX_REQUIREMENT "25 MHz" -section_id design_top|sys_clk
+set_global_assignment -name FMAX_REQUIREMENT "33 MHz" -section_id design_top|lclk
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 100%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 100%
+set_global_assignment -name POWER_USE_PVA OFF
+set_location_assignment PIN_L4 -to fl_data[0]
+set_location_assignment PIN_L1 -to fl_data[1]
+set_location_assignment PIN_K2 -to fl_data[2]
+set_location_assignment PIN_K5 -to fl_data[3]
+set_location_assignment PIN_J1 -to fl_data[4]
+set_location_assignment PIN_J6 -to fl_data[5]
+set_location_assignment PIN_P2 -to fl_data[6]
+set_location_assignment PIN_L6 -to fl_data[7]
+set_location_assignment PIN_L3 -to fl_data[8]
+set_location_assignment PIN_L2 -to fl_data[9]
+set_location_assignment PIN_K1 -to fl_data[10]
+set_location_assignment PIN_J2 -to fl_data[11]
+set_location_assignment PIN_K6 -to fl_data[12]
+set_location_assignment PIN_P1 -to fl_data[13]
+set_location_assignment PIN_R1 -to fl_data[14]
+set_location_assignment PIN_N2 -to fl_data[15]
+set_location_assignment PIN_N1 -to fl_sts
+set_location_assignment PIN_N3 -to fl_addr[0]
+set_location_assignment PIN_M7 -to fl_addr[1]
+set_location_assignment PIN_M8 -to fl_addr[2]
+set_location_assignment PIN_N8 -to fl_addr[3]
+set_location_assignment PIN_N6 -to fl_addr[4]
+set_location_assignment PIN_K8 -to fl_addr[5]
+set_location_assignment PIN_L7 -to fl_addr[6]
+set_location_assignment PIN_L8 -to fl_addr[7]
+set_location_assignment PIN_T8 -to fl_addr[8]
+set_location_assignment PIN_P8 -to fl_addr[9]
+set_location_assignment PIN_T7 -to fl_addr[10]
+set_location_assignment PIN_R7 -to fl_addr[11]
+set_location_assignment PIN_T6 -to fl_addr[12]
+set_location_assignment PIN_R6 -to fl_addr[13]
+set_location_assignment PIN_P6 -to fl_addr[14]
+set_location_assignment PIN_T5 -to fl_addr[15]
+set_location_assignment PIN_R5 -to fl_addr[16]
+set_location_assignment PIN_T4 -to fl_addr[17]
+set_location_assignment PIN_R4 -to fl_addr[18]
+set_location_assignment PIN_T3 -to fl_addr[19]
+set_location_assignment PIN_R3 -to fl_addr[20]
+set_location_assignment PIN_P3 -to fl_addr[21]
+set_location_assignment PIN_T2 -to fl_addr[22]
+set_location_assignment PIN_M6 -to fl_addr[23]
+set_location_assignment PIN_N5 -to fl_we_n
+set_location_assignment PIN_P9 -to ps_addr_val
+set_location_assignment PIN_R8 -to ps_clk
+set_location_assignment PIN_T9 -to ps_confr_en
+set_location_assignment PIN_R10 -to ps_lsb_en
+set_location_assignment PIN_M9 -to ps_msb_en
+set_location_assignment PIN_T10 -to ps_wait
+set_location_assignment PIN_T12 -to ee_clk
+set_location_assignment PIN_R12 -to ee_cs_n
+set_location_assignment PIN_P11 -to ee_di
+set_location_assignment PIN_R13 -to ee_do
+set_location_assignment PIN_R11 -to ee_hold_n
+set_location_assignment PIN_T13 -to ee_write
+set_location_assignment PIN_T11 -to fl_ce_n
+set_location_assignment PIN_R9 -to fl_oe_n
+set_location_assignment PIN_E5 -to usb_bd[0]
+set_location_assignment PIN_D1 -to usb_bd[1]
+set_location_assignment PIN_F3 -to usb_bd[2]
+set_location_assignment PIN_F1 -to usb_bd[3]
+set_location_assignment PIN_F2 -to usb_bd[4]
+set_location_assignment PIN_G2 -to usb_bd[5]
+set_location_assignment PIN_F5 -to usb_bd[6]
+set_location_assignment PIN_G1 -to usb_bd[7]
+set_location_assignment PIN_G5 -to usb_rd_n
+set_location_assignment PIN_B1 -to usb_rxf_n
+set_location_assignment PIN_C2 -to usb_txe_n
+set_location_assignment PIN_D4 -to usb_wr
+set_location_assignment PIN_E15 -to lclk
+set_location_assignment PIN_E1 -to sys_clk
+set_location_assignment PIN_A7 -to led_red
+set_location_assignment PIN_B7 -to led_green
+set_location_assignment PIN_A4 -to scn_seg[0]
+set_location_assignment PIN_B5 -to scn_seg[1]
+set_location_assignment PIN_C8 -to scn_seg[2]
+set_location_assignment PIN_D6 -to scn_seg[3]
+set_location_assignment PIN_A2 -to seg_out[0]
+set_location_assignment PIN_C3 -to seg_out[1]
+set_location_assignment PIN_B3 -to seg_out[2]
+set_location_assignment PIN_A3 -to seg_out[3]
+set_location_assignment PIN_E8 -to seg_out[4]
+set_location_assignment PIN_A6 -to seg_out[5]
+set_location_assignment PIN_B6 -to seg_out[6]
+set_location_assignment PIN_E7 -to seg_out[7]
+set_location_assignment PIN_D5 -to mode[0]
+set_location_assignment PIN_E6 -to mode[1]
+set_location_assignment PIN_F6 -to mode[2]
+set_location_assignment PIN_D3 -to buf_oe_n
+set_location_assignment PIN_C15 -to lad[0]
+set_location_assignment PIN_G11 -to lad[1]
+set_location_assignment PIN_C16 -to lad[2]
+set_location_assignment PIN_D16 -to lad[3]
+set_location_assignment PIN_D15 -to lreset_n
+set_location_assignment PIN_F13 -to lframe_n
+set_location_assignment PIN_T15 -to resetn
+set_location_assignment PIN_D9 -to hdr[0]
+set_location_assignment PIN_C9 -to hdr[1]
+set_location_assignment PIN_E9 -to hdr[2]
+set_location_assignment PIN_B9 -to hdr[3]
+set_location_assignment PIN_A9 -to hdr[4]
+set_location_assignment PIN_A10 -to hdr[5]
+set_location_assignment PIN_B10 -to hdr[6]
+set_location_assignment PIN_A11 -to hdr[7]
+set_location_assignment PIN_B11 -to hdr[8]
+set_location_assignment PIN_A12 -to hdr[9]
+set_location_assignment PIN_A13 -to hdr[10]
+set_location_assignment PIN_B12 -to hdr[11]
+set_location_assignment PIN_A14 -to hdr[12]
+set_location_assignment PIN_B13 -to hdr[13]
+set_location_assignment PIN_A15 -to hdr[14]
+set_location_assignment PIN_B14 -to hdr[15]
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS4
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to scn_seg[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to scn_seg[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to scn_seg[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to scn_seg[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg_out
+set_location_assignment PIN_B16 -to ldev_present
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hdr[1]
+set_location_assignment PIN_J11 -to hdr_b[0]
+set_location_assignment PIN_K11 -to hdr_b[1]
+set_location_assignment PIN_L12 -to hdr_b[2]
+set_location_assignment PIN_M12 -to hdr_b[3]
+set_location_assignment PIN_J12 -to hdr_b[4]
+set_location_assignment PIN_J14 -to hdr_b[5]
+set_location_assignment PIN_R16 -to hdr_b[6]
+set_location_assignment PIN_P16 -to hdr_b[7]
+set_location_assignment PIN_N15 -to hdr_b[8]
+set_location_assignment PIN_N16 -to hdr_b[9]
+set_location_assignment PIN_K15 -to hdr_b[10]
+set_location_assignment PIN_K16 -to hdr_b[11]
+set_location_assignment PIN_J15 -to hdr_b[12]
+set_location_assignment PIN_J16 -to hdr_b[13]
+set_location_assignment PIN_L15 -to hdr_b[14]
+set_location_assignment PIN_L16 -to hdr_b[15]
+set_location_assignment PIN_N9 -to ps_ram_en
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to buf_oe_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ldev_present
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to ldev_present
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ps_ram_en
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to fl_we_n
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to fl_ce_n
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 3.3V
+set_global_assignment -name MISC_FILE "C:/projects/Dongle_II_Board/altera_quartus_proj/dongle_syn.dpf"
+set_location_assignment PIN_B4 -to scn_seg2[0]
+set_location_assignment PIN_A5 -to scn_seg2[1]
+set_location_assignment PIN_A8 -to scn_seg2[2]
+set_location_assignment PIN_C6 -to scn_seg2[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to scn_seg2
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to scn_seg2
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_location_assignment PIN_G16 -to lserirq
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to lserirq
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name VHDL_FILE ../src/dongle_arch/dongle_arch.vhd
+set_global_assignment -name VHDL_FILE ../src/lpc_proto/serirq.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE ../src/serial_usb/serial_usb_package.vhd
+set_global_assignment -name VHDL_FILE ../src/serial_usb/serial_usb.vhd
+set_global_assignment -name VHDL_FILE ../src/postcode_ser/fifo.vhd
+set_global_assignment -name VHDL_FILE ../src/postcode_ser/pc_serializer.vhd
+set_global_assignment -name VHDL_FILE ../src/usb/usb2mem.vhd
+set_global_assignment -name VHDL_FILE ../src/lpc_proto/lpc_byte.vhd
+set_global_assignment -name VHDL_FILE ../src/flash/flsh_if.vhd
+set_global_assignment -name VHDL_FILE ../src/led_sys/led_coder.vhd
+set_global_assignment -name VHDL_FILE ../src/led_sys/byte_scan_mux.vhd
+set_global_assignment -name VHDL_FILE ../src/led_sys/led_sys.vhd
+set_global_assignment -name VHDL_FILE ../src/design_top/design_top_thincandbg.vhd
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
Index: artec_dongle_ii_fpga/trunk/altera_quartus_proj/dongle_syn_assignment_defaults.qdf
===================================================================
--- artec_dongle_ii_fpga/trunk/altera_quartus_proj/dongle_syn_assignment_defaults.qdf (revision 8)
+++ artec_dongle_ii_fpga/trunk/altera_quartus_proj/dongle_syn_assignment_defaults.qdf (revision 9)
@@ -1,422 +1,422 @@
-set_global_assignment -name EQC_BBOX_MERGE On
-set_global_assignment -name EQC_LVDS_MERGE On
-set_global_assignment -name EQC_RAM_UNMERGING On
-set_global_assignment -name EQC_DFF_SS_EMULATION On
-set_global_assignment -name EQC_IO_BUFFER_CONVERSION On
-set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
-set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
-set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
-set_global_assignment -name EQC_STRUCTURE_MATCHING On
-set_global_assignment -name EQC_AUTO_BREAK_CONE On
-set_global_assignment -name EQC_POWER_UP_COMPARE Off
-set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
-set_global_assignment -name EQC_AUTO_INVERSION On
-set_global_assignment -name EQC_AUTO_TERMINATE On
-set_global_assignment -name EQC_SUB_CONE_REPORT Off
-set_global_assignment -name EQC_RENAMING_RULES On
-set_global_assignment -name EQC_PARAMETER_CHECK On
-set_global_assignment -name EQC_AUTO_PORTSWAP On
-set_global_assignment -name EQC_DETECT_DONT_CARES On
-set_global_assignment -name NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT 10
-set_global_assignment -name NUMBER_OF_DESTINATION_TO_REPORT 10
-set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 200
-set_global_assignment -name DO_MIN_ANALYSIS -value OFF
-set_global_assignment -name DO_MIN_TIMING Off
-set_global_assignment -name REPORT_IO_PATHS_SEPARATELY Off
-set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK Off
-set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
-set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
-set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
-set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
-set_global_assignment -name DO_COMBINED_ANALYSIS Off
-set_global_assignment -name IGNORE_CLOCK_SETTINGS Off
-set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS -value ON
-set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS Off
-set_global_assignment -name ENABLE_CLOCK_LATENCY Off
-set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off
-set_global_assignment -name START_TIME 0ns
-set_global_assignment -name SIMULATION_MODE TIMING
-set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
-set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
-set_global_assignment -name SETUP_HOLD_DETECTION Off
-set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
-set_global_assignment -name CHECK_OUTPUTS Off
-set_global_assignment -name SIMULATION_COVERAGE On
-set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
-set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
-set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
-set_global_assignment -name GLITCH_DETECTION Off
-set_global_assignment -name GLITCH_INTERVAL 1ns
-set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
-set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF -value ON
-set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
-set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
-set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
-set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
-set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_IN_NORMAL_FLOW Off
-set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
-set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
-set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
-set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
-set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
-set_global_assignment -name SMART_RECOMPILE -value OFF
-set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
-set_global_assignment -name FLOW_ENABLE_HCII_COMPARE Off
-set_global_assignment -name HCII_OUTPUT_DIR hc_output
-set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
-set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
-set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
-set_global_assignment -name MERGE_HEX_FILE Off
-set_global_assignment -name GENERATE_SVF_FILE Off
-set_global_assignment -name GENERATE_ISC_FILE Off
-set_global_assignment -name GENERATE_JAM_FILE Off
-set_global_assignment -name GENERATE_JBC_FILE Off
-set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
-set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
-set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
-set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
-set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
-set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
-set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
-set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
-set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
-set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
-set_global_assignment -name POWER_USE_PVA On
-set_global_assignment -name POWER_USE_INPUT_FILE "No File"
-set_global_assignment -name POWER_USE_INPUT_FILES Off
-set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
-set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY On
-set_global_assignment -name POWER_REPORT_POWER_DISSIPATION On
-set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
-set_global_assignment -name POWER_USE_VOLTAGE NOMINAL
-set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
-set_global_assignment -name POWER_TJ_VALUE 25
-set_global_assignment -name POWER_USE_TA_VALUE 25
-set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
-set_global_assignment -name POWER_BOARD_TEMPERATURE 25
-set_global_assignment -name EDA_SIMULATION_TOOL ""
-set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL ""
-set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL ""
-set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL ""
-set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL ""
-set_global_assignment -name EDA_BOARD_DESIGN_TOOL ""
-set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL ""
-set_global_assignment -name EDA_RESYNTHESIS_TOOL ""
-set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off
-set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs"
-set_global_assignment -name MUX_RESTRUCTURE AUTO
-set_global_assignment -name ENABLE_IP_DEBUG Off
-set_global_assignment -name SAVE_DISK_SPACE On
-set_global_assignment -name DISABLE_OCP_HW_EVAL Off
-set_global_assignment -name DEVICE_FILTER_PACKAGE Any
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
-set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL ""
-set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
-set_global_assignment -name VHDL_INPUT_VERSION VHDL93
-set_global_assignment -name FAMILY Stratix
-set_global_assignment -name TRUE_WYSIWYG_FLOW Off
-set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
-set_global_assignment -name STATE_MACHINE_PROCESSING Auto
-set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
-set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
-set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS On
-set_global_assignment -name DSP_BLOCK_BALANCING Auto
-set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1"
-set_global_assignment -name NOT_GATE_PUSH_BACK On
-set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
-set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
-set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
-set_global_assignment -name IGNORE_CARRY_BUFFERS Off
-set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
-set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
-set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
-set_global_assignment -name IGNORE_LCELL_BUFFERS Off
-set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
-set_global_assignment -name IGNORE_SOFT_BUFFERS On
-set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
-set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
-set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
-set_global_assignment -name AUTO_GLOBAL_OE_MAX On
-set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
-set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
-set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
-set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
-set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
-set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
-set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
-set_global_assignment -name ALLOW_XOR_GATE_USAGE On
-set_global_assignment -name AUTO_LCELL_INSERTION On
-set_global_assignment -name CARRY_CHAIN_LENGTH 48
-set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
-set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
-set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
-set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
-set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
-set_global_assignment -name CASCADE_CHAIN_LENGTH 2
-set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
-set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
-set_global_assignment -name AUTO_CARRY_CHAINS On
-set_global_assignment -name AUTO_CASCADE_CHAINS On
-set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
-set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
-set_global_assignment -name REMOVE_DUPLICATE_LOGIC On
-set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
-set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME Off
-set_global_assignment -name ADV_NETLIST_OPT_RETIME_CORE_AND_IO On
-set_global_assignment -name AUTO_ROM_RECOGNITION On
-set_global_assignment -name AUTO_RAM_RECOGNITION On
-set_global_assignment -name AUTO_DSP_RECOGNITION On
-set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION On
-set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
-set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
-set_global_assignment -name FORCE_SYNCH_CLEAR Off
-set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
-set_global_assignment -name AUTO_RESOURCE_SHARING Off
-set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
-set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
-set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
-set_global_assignment -name MAX7000_FANIN_PER_CELL 100
-set_global_assignment -name IGNORE_DUPLICATE_DESIGN_ENTITY Off
-set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1"
-set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1"
-set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1"
-set_global_assignment -name IGNORE_TRANSLATE_OFF Off
-set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
-set_global_assignment -name SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT On
-set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
-set_global_assignment -name ADV_NETLIST_OPT_METASTABLE_REGS 2
-set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
-set_global_assignment -name HDL_MESSAGE_LEVEL Level2
-set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT Off
-set_global_assignment -name INCREMENTAL_COMPILATION Off
-set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
-set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE POST_FIT
-set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
-set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
-set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
-set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
-set_global_assignment -name DEVICE AUTO
-set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
-set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
-set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
-set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
-set_global_assignment -name STRATIX_UPDATE_MODE Standard
-set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
-set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
-set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name USER_START_UP_CLOCK Off
-set_global_assignment -name ENABLE_VREFA_PIN Off
-set_global_assignment -name ENABLE_VREFB_PIN Off
-set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
-set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
-set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
-set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
-set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
-set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name CRC_ERROR_CHECKING Off
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths"
-set_global_assignment -name OPTIMIZE_FAST_CORNER_TIMING Off
-set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
-set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
-set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
-set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING On
-set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
-set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
-set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
-set_global_assignment -name SEED 1
-set_global_assignment -name SLOW_SLEW_RATE Off
-set_global_assignment -name PCI_IO Off
-set_global_assignment -name TURBO_BIT On
-set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
-set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
-set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
-set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
-set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
-set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
-set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
-set_global_assignment -name AUTO_PACKED_REGISTERS Off
-set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
-set_global_assignment -name NORMAL_LCELL_INSERT On
-set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
-set_global_assignment -name AUTO_DELAY_CHAINS On
-set_global_assignment -name AUTO_MERGE_PLLS On
-set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
-set_global_assignment -name AUTO_TURBO_BIT ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
-set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
-set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
-set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
-set_global_assignment -name FITTER_EFFORT -value "AUTO FIT"
-set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
-set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
-set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
-set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
-set_global_assignment -name AUTO_GLOBAL_CLOCK On
-set_global_assignment -name AUTO_GLOBAL_OE On
-set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
-set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
-set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
-set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
-set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
-set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
-set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
-set_global_assignment -name DRC_REPORT_TOP_FANOUT On
-set_global_assignment -name DRC_TOP_FANOUT 50
-set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING On
-set_global_assignment -name DRC_FANOUT_EXCEEDING 30
-set_global_assignment -name SIGNALRACE_RULE_TRISTATE On
-set_global_assignment -name SIGNALRACE_RULE_RESET_RACE On
-set_global_assignment -name HCPY_PLL_MULTIPLE_CLK_NETWORK_TYPES On
-set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM On
-set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
-set_global_assignment -name ENABLE_DRC_SETTINGS Off
-set_global_assignment -name CLK_CAT On
-set_global_assignment -name CLK_RULE_COMB_CLOCK On
-set_global_assignment -name CLK_RULE_INV_CLOCK On
-set_global_assignment -name CLK_RULE_GATING_SCHEME On
-set_global_assignment -name CLK_RULE_INPINS_CLKNET On
-set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES On
-set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
-set_global_assignment -name CLK_RULE_MIX_EDGES On
-set_global_assignment -name RESET_CAT On
-set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET On
-set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET On
-set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET On
-set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN On
-set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN On
-set_global_assignment -name TIMING_CAT On
-set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE On
-set_global_assignment -name NONSYNCHSTRUCT_CAT On
-set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP On
-set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP On
-set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN On
-set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK On
-set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN On
-set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR On
-set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH On
-set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED On
-set_global_assignment -name SIGNALRACE_CAT On
-set_global_assignment -name ACLK_CAT On
-set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN On
-set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN On
-set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN On
-set_global_assignment -name HCPY_CAT On
-set_global_assignment -name HCPY_VREF_PINS On
-set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
-set_global_assignment -name COMPRESSION_MODE Off
-set_global_assignment -name CLOCK_SOURCE Internal
-set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
-set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
-set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
-set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
-set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
-set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
-set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
-set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
-set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off
-set_global_assignment -name SECURITY_BIT Off
-set_global_assignment -name USE_CONFIGURATION_DEVICE On
-set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
-set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
-set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
-set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
-set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
-set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
-set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
-set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
-set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
-set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
-set_global_assignment -name GENERATE_TTF_FILE Off
-set_global_assignment -name GENERATE_RBF_FILE Off
-set_global_assignment -name GENERATE_HEX_FILE Off
-set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
-set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
-set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
-set_global_assignment -name AUTO_RESTART_CONFIGURATION On
-set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
-set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
-set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
-set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY -value OFF
-set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
-set_global_assignment -name DUTY_CYCLE 50 -section_id ?
-set_global_assignment -name INVERT_BASE_CLOCK Off -section_id ?
-set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id ?
-set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id ?
-set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
-set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
-set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
-set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
-set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
-set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
-set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
-set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
-set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
-set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
-set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY Off -section_id ?
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
-set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
-set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
-set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
-set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
-set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
-set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
-set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "100 ns" -section_id ?
-set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
-set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
-set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id ?
-set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
-set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
-set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
-set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
-set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
-set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
-set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
-set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
-set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
-set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id ? -entity ?
-set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_IO_BUFFER_CONVERSION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT 10
+set_global_assignment -name NUMBER_OF_DESTINATION_TO_REPORT 10
+set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 200
+set_global_assignment -name DO_MIN_ANALYSIS -value OFF
+set_global_assignment -name DO_MIN_TIMING Off
+set_global_assignment -name REPORT_IO_PATHS_SEPARATELY Off
+set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK Off
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name IGNORE_CLOCK_SETTINGS Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS -value ON
+set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS Off
+set_global_assignment -name ENABLE_CLOCK_LATENCY Off
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF -value ON
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_IN_NORMAL_FLOW Off
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name SMART_RECOMPILE -value OFF
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_HCII_COMPARE Off
+set_global_assignment -name HCII_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY On
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION On
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_USE_VOLTAGE NOMINAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name EDA_SIMULATION_TOOL ""
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL ""
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL ""
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL ""
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL ""
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL ""
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL ""
+set_global_assignment -name EDA_RESYNTHESIS_TOOL ""
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs"
+set_global_assignment -name MUX_RESTRUCTURE AUTO
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name DISABLE_OCP_HW_EVAL Off
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL ""
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL93
+set_global_assignment -name FAMILY Stratix
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name REMOVE_DUPLICATE_LOGIC On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME Off
+set_global_assignment -name ADV_NETLIST_OPT_RETIME_CORE_AND_IO On
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION On
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name IGNORE_DUPLICATE_DESIGN_ENTITY Off
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1"
+set_global_assignment -name IGNORE_TRANSLATE_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name ADV_NETLIST_OPT_METASTABLE_REGS 2
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT Off
+set_global_assignment -name INCREMENTAL_COMPILATION Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE POST_FIT
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths"
+set_global_assignment -name OPTIMIZE_FAST_CORNER_TIMING Off
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING On
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS Off
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT -value "AUTO FIT"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name DRC_REPORT_TOP_FANOUT On
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING On
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name SIGNALRACE_RULE_TRISTATE On
+set_global_assignment -name SIGNALRACE_RULE_RESET_RACE On
+set_global_assignment -name HCPY_PLL_MULTIPLE_CLK_NETWORK_TYPES On
+set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM On
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_CAT On
+set_global_assignment -name CLK_RULE_COMB_CLOCK On
+set_global_assignment -name CLK_RULE_INV_CLOCK On
+set_global_assignment -name CLK_RULE_GATING_SCHEME On
+set_global_assignment -name CLK_RULE_INPINS_CLKNET On
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES On
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name CLK_RULE_MIX_EDGES On
+set_global_assignment -name RESET_CAT On
+set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET On
+set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET On
+set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET On
+set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN On
+set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN On
+set_global_assignment -name TIMING_CAT On
+set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE On
+set_global_assignment -name NONSYNCHSTRUCT_CAT On
+set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP On
+set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP On
+set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN On
+set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK On
+set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN On
+set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR On
+set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH On
+set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED On
+set_global_assignment -name SIGNALRACE_CAT On
+set_global_assignment -name ACLK_CAT On
+set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN On
+set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN On
+set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN On
+set_global_assignment -name HCPY_CAT On
+set_global_assignment -name HCPY_VREF_PINS On
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE On
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY -value OFF
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name INVERT_BASE_CLOCK Off -section_id ?
+set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id ?
+set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY Off -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "100 ns" -section_id ?
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
Index: artec_dongle_ii_fpga/trunk/altera_quartus_proj/dongle_syn.dpf
===================================================================
--- artec_dongle_ii_fpga/trunk/altera_quartus_proj/dongle_syn.dpf (nonexistent)
+++ artec_dongle_ii_fpga/trunk/altera_quartus_proj/dongle_syn.dpf (revision 9)
@@ -0,0 +1,12 @@
+
+
+
+
+
+
+
+
+
+
+
+
artec_dongle_ii_fpga/trunk/altera_quartus_proj/dongle_syn.dpf
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: artec_dongle_ii_fpga/trunk/altera_quartus_proj/dongle_syn.rbf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: artec_dongle_ii_fpga/trunk/altera_quartus_proj/dongle_syn.rbf
===================================================================
--- artec_dongle_ii_fpga/trunk/altera_quartus_proj/dongle_syn.rbf (nonexistent)
+++ artec_dongle_ii_fpga/trunk/altera_quartus_proj/dongle_syn.rbf (revision 9)
artec_dongle_ii_fpga/trunk/altera_quartus_proj/dongle_syn.rbf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: artec_dongle_ii_fpga/trunk/altera_quartus_proj/make_bin_output_file.cof
===================================================================
--- artec_dongle_ii_fpga/trunk/altera_quartus_proj/make_bin_output_file.cof (nonexistent)
+++ artec_dongle_ii_fpga/trunk/altera_quartus_proj/make_bin_output_file.cof (revision 9)
@@ -0,0 +1,18 @@
+
+
+ NONE
+ dongle_syn.rpd
+ 1
+ 1
+ 7
+
+ 1
+
+ dongle_syn.pof
+
+
+ 4
+
+ 1
+
+
\ No newline at end of file
artec_dongle_ii_fpga/trunk/altera_quartus_proj/make_bin_output_file.cof
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: artec_dongle_ii_fpga/trunk/altera_quartus_proj/dongle_syn.cdf
===================================================================
--- artec_dongle_ii_fpga/trunk/altera_quartus_proj/dongle_syn.cdf (revision 8)
+++ artec_dongle_ii_fpga/trunk/altera_quartus_proj/dongle_syn.cdf (revision 9)
@@ -1,13 +1,13 @@
-/* Quartus II Version 8.0 Build 215 05/29/2008 SJ Web Edition */
-JedecChain;
- FileRevision(JESD32A);
- DefaultMfr(6E);
-
- P ActionCode(Cfg)
- Device PartName(EPCS4) Path("C:/projects/gDongle_Board/altera_quartus_proj/") File("dongle_syn.pof") MfrSpec(OpMask(1) Child_OpMask(1 1));
-
-ChainEnd;
-
-AlteraBegin;
- ChainType(asc);
-AlteraEnd;
+/* Quartus II 64-Bit Version 11.0 Build 157 04/27/2011 SJ Full Version */
+JedecChain;
+ FileRevision(JESD32A);
+ DefaultMfr(6E);
+
+ P ActionCode(Cfg)
+ Device PartName(EPCS4) Path("C:/projects/075_Artec_Group/Dongle_II_Board/altera_quartus_proj/") File("dongle_syn.pof") MfrSpec(OpMask(3) Child_OpMask(1 3));
+
+ChainEnd;
+
+AlteraBegin;
+ ChainType(asc);
+AlteraEnd;
Index: artec_dongle_ii_fpga/trunk/src/bus_arbiter/bus_arbiter.vhd
===================================================================
--- artec_dongle_ii_fpga/trunk/src/bus_arbiter/bus_arbiter.vhd (revision 8)
+++ artec_dongle_ii_fpga/trunk/src/bus_arbiter/bus_arbiter.vhd (revision 9)
@@ -1,78 +1,78 @@
-------------------------------------------------------------------
--- Universal dongle board source code
---
--- Copyright (C) 2006 Artec Design
---
--- This source code is free hardware; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
---
--- This source code is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--- Lesser General Public License for more details.
---
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
---
---
--- The complete text of the GNU Lesser General Public License can be found in
--- the file 'lesser.txt'.
-
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-use IEEE.std_logic_arith.all;
-
-use bus_arbiter_pkg.all;
-
-
-
-entity bus_arbiter is
- generic (
- dev_count: integer:= 1;
- has_clock: array(integer range 0 to dev_count-1) of std_logic:=(others=>'0') --if provided clock should be used
- );
- port (
- clk : in std_logic; --default system clock
- reset_n : in std_logic;
- -- mem Bus out
-
- mem_clk : out std_logic;
- mem_rstn : out std_logic; --reset to mem block (used when mux'ing clock)
- mem_addr : out std_logic_vector(23 downto 0);
- mem_do : out std_logic_vector(15 downto 0);
- mem_di : in std_logic_vector(15 downto 0);
-
- mem_wr : out std_logic; --write not read signal
- mem_val : out std_logic;
- mem_ack : in std_logic;
-
-
- -- dev Bus in
- dev_clk : in array(integer range 0 to dev_count-1) of std_logic; --clock option
- dev_addr : in array(integer range 0 to dev_count-1) of std_logic_vector(23 downto 0);
- dev_do : out array(integer range 0 to dev_count-1) of std_logic_vector(15 downto 0);
- dev_di : in array(integer range 0 to dev_count-1) of std_logic_vector(15 downto 0);
-
- dev_wr : in array(integer range 0 to dev_count-1) of std_logic; --write not read signal
- dev_val : in array(integer range 0 to dev_count-1) of std_logic;
- dev_ack : out array(integer range 0 to dev_count-1) of std_logic
- );
-end bus_arbiter;
-
-
-
-architecture RTL of bus_arbiter is
-
-
-begin
-
-
-
-
-end RTL;
-
+------------------------------------------------------------------
+-- Universal dongle board source code
+--
+-- Copyright (C) 2006 Artec Design
+--
+-- This source code is free hardware; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This source code is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+--
+--
+-- The complete text of the GNU Lesser General Public License can be found in
+-- the file 'lesser.txt'.
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+use bus_arbiter_pkg.all;
+
+
+
+entity bus_arbiter is
+ generic (
+ dev_count: integer:= 1;
+ has_clock: array(integer range 0 to dev_count-1) of std_logic:=(others=>'0') --if provided clock should be used
+ );
+ port (
+ clk : in std_logic; --default system clock
+ reset_n : in std_logic;
+ -- mem Bus out
+
+ mem_clk : out std_logic;
+ mem_rstn : out std_logic; --reset to mem block (used when mux'ing clock)
+ mem_addr : out std_logic_vector(23 downto 0);
+ mem_do : out std_logic_vector(15 downto 0);
+ mem_di : in std_logic_vector(15 downto 0);
+
+ mem_wr : out std_logic; --write not read signal
+ mem_val : out std_logic;
+ mem_ack : in std_logic;
+
+
+ -- dev Bus in
+ dev_clk : in array(integer range 0 to dev_count-1) of std_logic; --clock option
+ dev_addr : in array(integer range 0 to dev_count-1) of std_logic_vector(23 downto 0);
+ dev_do : out array(integer range 0 to dev_count-1) of std_logic_vector(15 downto 0);
+ dev_di : in array(integer range 0 to dev_count-1) of std_logic_vector(15 downto 0);
+
+ dev_wr : in array(integer range 0 to dev_count-1) of std_logic; --write not read signal
+ dev_val : in array(integer range 0 to dev_count-1) of std_logic;
+ dev_ack : out array(integer range 0 to dev_count-1) of std_logic
+ );
+end bus_arbiter;
+
+
+
+architecture RTL of bus_arbiter is
+
+
+begin
+
+
+
+
+end RTL;
+
Index: artec_dongle_ii_fpga/trunk/src/bus_arbiter/bus_arbiter_pkg.vhd
===================================================================
--- artec_dongle_ii_fpga/trunk/src/bus_arbiter/bus_arbiter_pkg.vhd (revision 8)
+++ artec_dongle_ii_fpga/trunk/src/bus_arbiter/bus_arbiter_pkg.vhd (revision 9)
@@ -1,19 +1,19 @@
-package bus_arbiter_pkg is
-
-type vci_master is
- record
- dev_clk : array(integer range 0 to dev_count-1) of std_logic; --clock option
- dev_addr : array(integer range 0 to dev_count-1) of std_logic_vector(23 downto 0);
- dev_do : array(integer range 0 to dev_count-1) of std_logic_vector(15 downto 0);
- dev_di : array(integer range 0 to dev_count-1) of std_logic_vector(15 downto 0);
-
- dev_wr : array(integer range 0 to dev_count-1) of std_logic; --write not read signal
- dev_val : array(integer range 0 to dev_count-1) of std_logic;
- dev_ack : array(integer range 0 to dev_count-1) of std_logic;
-
- end record;
-
-
-
-
+package bus_arbiter_pkg is
+
+type vci_master is
+ record
+ dev_clk : array(integer range 0 to dev_count-1) of std_logic; --clock option
+ dev_addr : array(integer range 0 to dev_count-1) of std_logic_vector(23 downto 0);
+ dev_do : array(integer range 0 to dev_count-1) of std_logic_vector(15 downto 0);
+ dev_di : array(integer range 0 to dev_count-1) of std_logic_vector(15 downto 0);
+
+ dev_wr : array(integer range 0 to dev_count-1) of std_logic; --write not read signal
+ dev_val : array(integer range 0 to dev_count-1) of std_logic;
+ dev_ack : array(integer range 0 to dev_count-1) of std_logic;
+
+ end record;
+
+
+
+
end bus_arbiter_pkg;
\ No newline at end of file
Index: artec_dongle_ii_fpga/trunk/src/lpc_proto/lpc_byte.vhd
===================================================================
--- artec_dongle_ii_fpga/trunk/src/lpc_proto/lpc_byte.vhd (revision 8)
+++ artec_dongle_ii_fpga/trunk/src/lpc_proto/lpc_byte.vhd (revision 9)
@@ -1,303 +1,335 @@
-------------------------------------------------------------------
--- Universal dongle board source code
---
--- Copyright (C) 2006 Artec Design
---
--- This source code is free hardware; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
---
--- This source code is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--- Lesser General Public License for more details.
---
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
---
---
--- The complete text of the GNU Lesser General Public License can be found in
--- the file 'lesser.txt'.
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-use IEEE.std_logic_arith.all;
-
-
-entity lpc_iow is
- port (
- --system signals
- lreset_n : in std_logic;
- lclk : in std_logic;
- lena_mem_r : in std_logic; --enable lpc regular memory read cycles also (default is only LPC firmware read)
- lena_reads : in std_logic; --enable read capabilities
- --LPC bus from host
- lad_i : in std_logic_vector(3 downto 0);
- lad_o : out std_logic_vector(3 downto 0);
- lad_oe : out std_logic;
- lframe_n : in std_logic;
- --memory interface
- lpc_addr : out std_logic_vector(23 downto 0); --shared address
- lpc_wr : out std_logic; --shared write not read
- lpc_data_i : in std_logic_vector(7 downto 0);
- lpc_data_o : out std_logic_vector(7 downto 0);
- lpc_val : out std_logic;
- lpc_ack : in std_logic
- );
-end lpc_iow;
-
-architecture rtl of lpc_iow is
-type state is (RESETs,STARTs,ADDRs,TARs,SYNCs,DATAs,LOCAL_TARs); -- simple LCP states
-type cycle is (LPC_IO_W,LPC_MEM_R,LPC_FW_R); -- simple LPC bus cycle types
-
-signal CS : state;
-signal r_lad : std_logic_vector(3 downto 0);
-signal r_addr : std_logic_vector(31 downto 0); --should consider saving max
- --adress 23 bits on flash
-signal r_data : std_logic_vector(7 downto 0);
-signal r_cnt : std_logic_vector(2 downto 0);
-signal cycle_type : cycle;
---signal r_fw_msize : std_logic_vector(3 downto 0);
-
-
-signal data_valid : std_logic;
-
-signal lad_rising_o : std_logic_vector(3 downto 0);
-signal lad_rising_oe : std_logic;
-
-constant START_FW_READ : std_logic_vector(3 downto 0):="1101";
-constant START_LPC : std_logic_vector(3 downto 0):="0000";
-constant IDSEL_FW_BOOT : std_logic_vector(3 downto 0):="0000"; --0000 is boot device on ThinCan
-constant MSIZE_FW_1B : std_logic_vector(3 downto 0):="0000"; --0000 is 1 byte read
-constant SYNC_OK : std_logic_vector(3 downto 0):="0000"; --sync done
-constant SYNC_WAIT : std_logic_vector(3 downto 0):="0101"; --sync wait device holds the bus
-constant SYNC_LWAIT : std_logic_vector(3 downto 0):="0110"; --sync long wait expected device holds the bus
-constant TAR_OK : std_logic_vector(3 downto 0):="1111"; --accepted tar constant for master and slave
-
-
-
-
-begin -- rtl
-
-lad_o<= lad_rising_o;
-lad_oe <= lad_rising_oe;
-
-
-
---Pass the whole LPC address to the system
-lpc_addr <= r_addr(23 downto 0);
-lpc_data_o<= r_data;
-
-
-
-
--- purpose: LPC IO write/LPC MEM read/LPC FW read handler
--- type : sequential
--- inputs : lclk, lreset_n
--- outputs:
-LPC: process (lclk, lreset_n)
-begin -- process LPC
- if lreset_n = '0' then -- asynchronous reset (active low)
- CS<= RESETs;
- lad_rising_oe<='0';
- data_valid <='1';
- lad_rising_o<="0000";
- lpc_val <='0';
- lpc_wr <='0';
- r_lad <= (others=>'0');
- cycle_type <= LPC_IO_W; --initial value
- r_addr <= (others=>'0');
- r_cnt <= (others=>'0');
- elsif lclk'event and lclk = '1' then -- rising clock edge
- case CS is
- when RESETs => ----------------------------------------------------------
- lpc_wr <='0';
- lpc_val <='0';
- if lframe_n='0' then
- CS <= STARTs;
- r_lad <= lad_i;
- else
- CS <= RESETs;
- end if;
- when STARTs => ----------------------------------------------------------
- if lframe_n = '0' then
- r_lad <= lad_i; -- latch lad state for next cycle
- CS <= STARTs;
- elsif r_lad = START_LPC then
- --must identify CYCTYPE
- if lad_i(3 downto 1)="001" then --IO WRITE WILL HAPPEN
- --next 4 states must be address states
- CS<=ADDRs;
- cycle_type <= LPC_IO_W;
- r_cnt <= "000";
- elsif lad_i(3 downto 1)="010" and lena_mem_r='1' and lena_reads='1' then --MEM READ ALLOWED
- CS<=ADDRs;
- cycle_type <= LPC_MEM_R;
- r_cnt <= "000";
- else
- CS<= RESETs;
- end if;
- elsif r_lad = START_FW_READ then --FW READ is always allowed
- if lad_i = IDSEL_FW_BOOT and lena_reads='1' then
- CS<=ADDRs;
- cycle_type <= LPC_FW_R;
- r_cnt <= "000";
- else
- CS<= RESETs;
- end if;
- end if;
- when ADDRs => -----------------------------------------------------------
- case cycle_type is
- when LPC_IO_W => --IO write cycle
- if r_cnt ="011" then
- if r_addr(11 downto 0)=x"008" and lad_i(3 downto 2)="00" then
- r_addr<= r_addr(27 downto 0)&lad_i;
- r_cnt <= "000";
- CS<=DATAs;
- elsif r_addr(11 downto 0)=x"008" and lad_i(3 downto 0)=x"8" then --for debug switch
- r_addr<= r_addr(27 downto 0)&lad_i;
- r_cnt <= "000";
- CS<=DATAs;
- else
- --not for this device
- CS<=RESETs;
- end if;
- else
- r_addr<= r_addr(27 downto 0)&lad_i;
- r_cnt<=r_cnt + 1;
- CS<=ADDRs;
- end if;
- when LPC_MEM_R => --Memory read cycle
- if r_cnt ="111" then
- r_addr<= r_addr(27 downto 0)&lad_i;
- r_cnt <= "000";
- lpc_wr <='0'; --memory read mus accure
- lpc_val <='1';
- data_valid <='0';
- CS<=TARs;
- else
- r_addr<= r_addr(27 downto 0)&lad_i;
- r_cnt<=r_cnt + 1;
- CS<=ADDRs;
- end if;
- when LPC_FW_R => --Firmware read
- if r_cnt ="111" then
- --r_fw_msize <= lad_i; --8'th cycle on FW read is mem size
- r_cnt <= "000";
- lpc_wr <='0'; --memory read must accure
- lpc_val <='1';
- data_valid <='0';
- if lad_i = MSIZE_FW_1B then
- CS<=TARs;
- else
- --over byte fw read not supported
- CS<=RESETs;
- end if;
- else
- r_addr<= r_addr(27 downto 0)&lad_i; --28 bit address is given
- r_cnt<=r_cnt + 1;
- CS<=ADDRs;
- end if;
-
- when others => null;
- end case;
- when DATAs => -----------------------------------------------------------
- case cycle_type is
- when LPC_IO_W => --IO write cycle
- if r_cnt ="001" then
- r_data <= lad_i&r_data(7 downto 4); --LSB first from io cycle
- r_cnt <= "000";
- lpc_wr <='1'; --IO write must accure
- lpc_val <='1';
- CS <= TARs;
- else
- r_data <= lad_i&r_data(7 downto 4); --LSB first from io cycle
- r_cnt<=r_cnt + 1;
- CS <= DATAs;
- end if;
- when LPC_MEM_R | LPC_FW_R => --Memory/FW read cycle
- if r_cnt ="001" then
- lad_rising_o<= r_data(7 downto 4);
- r_cnt <= "000";
- CS <= LOCAL_TARs;
- else
- lad_rising_o<= r_data(3 downto 0);
- r_cnt<=r_cnt + 1;
- CS <= DATAs;
- end if;
- when others => null;
- end case;
- when TARs => ------------------------------------------------------------
- if cycle_type /= LPC_IO_W and lpc_ack='1' and r_cnt ="001" then --if mem_read or fr_read
- r_data <= lpc_data_i;
- lpc_val <='0';
- data_valid <='1';
- CS<= SYNCs;
- r_cnt <= "000";
- elsif lpc_ack='1' and r_cnt ="001" then
- lad_rising_o<=SYNC_OK; --added to avoid trouble as SYNC is OK allready
- lpc_val <='0';
- CS<= SYNCs;
- r_cnt <= "000";
- end if;
-
- if r_cnt ="001" then
- if lpc_ack='0' then
- lad_rising_o <= SYNC_LWAIT; --added to avoid trouble
- end if;
- lad_rising_oe<='1';
- elsif lad_i = TAR_OK then
- r_cnt<=r_cnt + 1;
- --lad_rising_oe<='1'; --BUG fix by LPC stanard TAR cycle part 2 must be tri-stated by host and device
- lad_rising_o <= TAR_OK; --drive to F on the bus
- CS <= TARs;
- else
- CS <= RESETs; --some error in protocol master must drive lad to "1111" on 1st TAR
- end if;
- when SYNCs => -----------------------------------------------------------
- case cycle_type is
- when LPC_IO_W => --IO write cycle
- -- just passing r_lad on bus again
- lad_rising_o<= TAR_OK;
- CS <= LOCAL_TARs;
- when LPC_MEM_R | LPC_FW_R => --Memory/FW read cycle
- if data_valid ='1' then
- lad_rising_o<=SYNC_OK;
- CS <= DATAs;
- else
- if lpc_ack='1' then
- r_data <= lpc_data_i;
- data_valid <= '1';
- lad_rising_o<=SYNC_OK; --SYNC ok now
- lpc_val <='0';
- CS <= DATAs;
- end if;
- end if;
- when others => null;
- end case;
- when LOCAL_TARs => ------------------------------------------------------
- case cycle_type is
- when LPC_IO_W => --IO write cycle
- lpc_wr <='0';
- lad_rising_oe <='0';
- CS <= RESETs;
- when LPC_MEM_R | LPC_FW_R => --Memory read cycle
- if r_cnt ="000" then
- lad_rising_o<= TAR_OK;
- r_cnt <= r_cnt + 1;
- else
- lad_rising_oe <= '0';
- r_cnt <="000";
- CS <= RESETs;
- end if;
- when others => null;
- end case;
- end case; -----------------------------------------------------------------
- end if;
-end process LPC;
-
-end rtl;
+------------------------------------------------------------------
+-- Universal dongle board source code
+--
+-- Copyright (C) 2006 Artec Design
+--
+-- This source code is free hardware; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This source code is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+--
+--
+-- The complete text of the GNU Lesser General Public License can be found in
+-- the file 'lesser.txt'.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+entity lpc_iow is
+ port(
+ --system signals
+ lreset_n : in std_logic;
+ lclk : in std_logic;
+ lena_mem_r : in std_logic; --enable lpc regular memory read cycles also (default is only LPC firmware read)
+ lena_reads : in std_logic; --enable read capabilities
+ uart_addr : in std_logic_vector(15 downto 0); -- define UART address to listen to
+ --LPC bus from host
+ lad_i : in std_logic_vector(3 downto 0);
+ lad_o : out std_logic_vector(3 downto 0);
+ lad_oe : out std_logic;
+ lframe_n : in std_logic;
+ --memory interface
+ lpc_addr : out std_logic_vector(23 downto 0); --shared address
+ lpc_wr : out std_logic; --shared write not read
+ lpc_io : out std_logic; --io access not mem access select
+ lpc_uart : out std_logic; --uart mapped cycle coming
+ lpc_gpioled: out std_logic; --gpio led cycle coming
+ lpc_data_i : in std_logic_vector(7 downto 0);
+ lpc_data_o : out std_logic_vector(7 downto 0);
+ lpc_val : out std_logic;
+ lpc_ack : in std_logic
+ );
+end lpc_iow;
+
+architecture rtl of lpc_iow is
+ type state is (RESETs, STARTs, ADDRs, TARs, SYNCs, DATAs, LOCAL_TARs); -- simple LCP states
+ type cycle is (LPC_IO_W, LPC_IO_R, LPC_MEM_R, LPC_FW_R); -- simple LPC bus cycle types
+
+ signal CS : state;
+ signal r_lad : std_logic_vector(3 downto 0);
+ signal r_addr : std_logic_vector(31 downto 0); --should consider saving max
+ --adress 23 bits on flash
+ signal r_data : std_logic_vector(7 downto 0);
+ signal r_cnt : std_logic_vector(2 downto 0);
+ signal cycle_type : cycle;
+ --signal r_fw_msize : std_logic_vector(3 downto 0);
+
+
+ signal data_valid : std_logic;
+
+ signal lad_rising_o : std_logic_vector(3 downto 0);
+ signal lad_rising_oe : std_logic;
+
+ constant START_FW_READ : std_logic_vector(3 downto 0) := "1101";
+ constant START_LPC : std_logic_vector(3 downto 0) := "0000";
+ constant IDSEL_FW_BOOT : std_logic_vector(3 downto 0) := "0000"; --0000 is boot device on ThinCan
+ constant MSIZE_FW_1B : std_logic_vector(3 downto 0) := "0000"; --0000 is 1 byte read
+ constant SYNC_OK : std_logic_vector(3 downto 0) := "0000"; --sync done
+ constant SYNC_WAIT : std_logic_vector(3 downto 0) := "0101"; --sync wait device holds the bus
+ constant SYNC_LWAIT : std_logic_vector(3 downto 0) := "0110"; --sync long wait expected device holds the bus
+ constant TAR_OK : std_logic_vector(3 downto 0) := "1111"; --accepted tar constant for master and slave
+
+
+begin -- rtl
+
+ lad_o <= lad_rising_o;
+ lad_oe <= lad_rising_oe;
+
+ --Pass the whole LPC address to the system
+ lpc_addr <= r_addr(23 downto 0);
+ lpc_data_o <= r_data;
+
+ -- purpose: LPC IO write/LPC MEM read/LPC FW read handler
+ -- type : sequential
+ -- inputs : lclk, lreset_n
+ -- outputs:
+ LPC : process(lclk, lreset_n)
+ begin -- process LPC
+ if lreset_n = '0' then -- asynchronous reset (active low)
+ CS <= RESETs;
+ lad_rising_oe <= '0';
+ data_valid <= '1';
+ lad_rising_o <= "0000";
+ lpc_val <= '0';
+ lpc_uart <= '0';
+ lpc_gpioled <= '0';
+ lpc_io <= '0';
+ lpc_wr <= '0';
+ r_lad <=(others => '0');
+ cycle_type <= LPC_IO_W; --initial value
+ r_addr <=(others => '0');
+ r_cnt <=(others => '0');
+ elsif lclk'event and lclk = '1' then -- rising clock edge
+ case CS is
+ when RESETs => ----------------------------------------------------------
+ lpc_wr <= '0';
+ lpc_val <= '0';
+ lpc_uart<= '0';
+ lpc_gpioled<= '0';
+ r_addr<=(others => '0');
+ lpc_io<='0';
+ if lframe_n = '0' then
+ CS <= STARTs;
+ r_lad <= lad_i;
+ else
+ CS <= RESETs;
+ end if;
+ when STARTs => ----------------------------------------------------------
+ if lframe_n = '0' then
+ r_lad <= lad_i; -- latch lad state for next cycle
+ CS <= STARTs;
+ elsif r_lad = START_LPC then
+ --must identify CYCTYPE
+ if lad_i(3 downto 1) = "001" then --IO WRITE WILL HAPPEN
+ --next 4 states must be address states
+ CS <= ADDRs;
+ cycle_type <= LPC_IO_W;
+ lpc_io<='1';
+ r_cnt <= "000";
+ elsif lad_i(3 downto 1) = "000" then --IO READ WILL HAPPEN
+ --next 4 states must be address states
+ CS <= ADDRs;
+ cycle_type <= LPC_IO_R;
+ lpc_io<='1';
+ r_cnt <= "000";
+ elsif lad_i(3 downto 1) = "010" and lena_mem_r = '1' and lena_reads = '1' then --MEM READ ALLOWED
+ CS <= ADDRs;
+ cycle_type <= LPC_MEM_R;
+ lpc_io<='0';
+ r_cnt <= "000";
+ else
+ CS <= RESETs;
+ end if;
+ elsif r_lad = START_FW_READ then --FW READ is always allowed
+ if lad_i = IDSEL_FW_BOOT and lena_reads = '1' then
+ lpc_io<='0';
+ CS <= ADDRs;
+ cycle_type <= LPC_FW_R;
+ r_cnt <= "000";
+ else
+ CS <= RESETs;
+ end if;
+ end if;
+ when ADDRs => -----------------------------------------------------------
+ case cycle_type is
+ when LPC_IO_W | LPC_IO_R => --IO write cycle or IO read cycle
+ if r_cnt = "011" then
+ if r_addr(11 downto 0) = x"008" and lad_i(3 downto 2) = "00" and cycle_type=LPC_IO_W then
+ CS <= DATAs;
+ elsif r_addr(11 downto 0) = x"008" and lad_i(3 downto 0) = x"4" then --LED and jumpers
+ lpc_gpioled<='1'; --must decode
+ if cycle_type=LPC_IO_W then
+ CS <= DATAs;
+ else
+ r_cnt <= "000";
+ lpc_wr <= '0'; --IO read must accure
+ lpc_val <= '1';
+ data_valid <= '0';
+ CS <= TARs; --on read we must do sync for read over clock grossing
+ end if;
+ elsif r_addr(11 downto 0) = x"008" and lad_i(3 downto 0) = x"8" and cycle_type=LPC_IO_W then --for debug switch
+ CS <= DATAs;
+ elsif uart_addr(3)='1' and r_addr(11 downto 0)=uart_addr(15 downto 4) and uart_addr(3)=lad_i(3) then --UART selected and enabled by leagal uart addr
+ lpc_uart<='1'; --decoded an uart cycle
+ if cycle_type=LPC_IO_W then
+ CS <= DATAs;
+ else
+ r_cnt <= "000";
+ lpc_wr <= '0'; --IO read must accure
+ lpc_val <= '1';
+ data_valid <= '0';
+ CS <= TARs; --on read we must do sync for read over clock grossing
+ end if;
+ else
+ --not for this device
+ CS <= RESETs;
+ end if;
+ r_addr <= r_addr(27 downto 0) & lad_i;
+ r_cnt <= "000";
+ else
+ r_addr <= r_addr(27 downto 0) & lad_i;
+ r_cnt <= r_cnt + 1;
+ CS <= ADDRs;
+ end if;
+ when LPC_MEM_R => --Memory read cycle
+ if r_cnt = "111" then
+ r_addr <= r_addr(27 downto 0) & lad_i;
+ r_cnt <= "000";
+ lpc_wr <= '0'; --memory read mus accure
+ lpc_val <= '1';
+ data_valid <= '0';
+ CS <= TARs;
+ else
+ r_addr <= r_addr(27 downto 0) & lad_i;
+ r_cnt <= r_cnt + 1;
+ CS <= ADDRs;
+ end if;
+ when LPC_FW_R => --Firmware read
+ if r_cnt = "111" then
+ --r_fw_msize <= lad_i; --8'th cycle on FW read is mem size
+ r_cnt <= "000";
+ lpc_wr <= '0'; --memory read must accure
+ lpc_val <= '1';
+ data_valid <= '0';
+ if lad_i = MSIZE_FW_1B then
+ CS <= TARs;
+ else
+ --over byte fw read not supported
+ CS <= RESETs;
+ end if;
+ else
+ r_addr <= r_addr(27 downto 0) & lad_i; --28 bit address is given
+ r_cnt <= r_cnt + 1;
+ CS <= ADDRs;
+ end if;
+
+ when others => null;
+ end case;
+ when DATAs => -----------------------------------------------------------
+ case cycle_type is
+ when LPC_IO_W => --IO write cycle
+ if r_cnt = "001" then
+ r_data <= lad_i & r_data(7 downto 4); --LSB first from io cycle
+ r_cnt <= "000";
+ lpc_wr <= '1'; --IO write must accure
+ lpc_val <= '1';
+ CS <= TARs;
+ else
+ r_data <= lad_i & r_data(7 downto 4); --LSB first from io cycle
+ r_cnt <= r_cnt + 1;
+ CS <= DATAs;
+ end if;
+ when LPC_MEM_R | LPC_FW_R | LPC_IO_R => --Memory/FW/IO read cycle
+ if r_cnt = "001" then
+ lad_rising_o <= r_data(7 downto 4);
+ r_cnt <= "000";
+ CS <= LOCAL_TARs;
+ else
+ lad_rising_o <= r_data(3 downto 0);
+ r_cnt <= r_cnt + 1;
+ CS <= DATAs;
+ end if;
+ when others => null;
+ end case;
+ when TARs => ------------------------------------------------------------
+ if cycle_type /= LPC_IO_W and lpc_ack = '1' and r_cnt = "001" then --if mem_read or fr_read
+ r_data <= lpc_data_i;
+ lpc_val <= '0';
+ data_valid <= '1';
+ CS <= SYNCs;
+ r_cnt <= "000";
+ elsif lpc_ack = '1' and r_cnt = "001" then
+ lad_rising_o <= SYNC_OK; --added to avoid trouble as SYNC is OK allready
+ lpc_val <= '0';
+ CS <= SYNCs;
+ r_cnt <= "000";
+ end if;
+
+ if r_cnt = "001" then
+ if lpc_ack = '0' then
+ lad_rising_o <= SYNC_LWAIT; --added to avoid trouble
+ end if;
+ lad_rising_oe <= '1';
+ elsif lad_i = TAR_OK then
+ r_cnt <= r_cnt + 1;
+ --lad_rising_oe<='1'; --BUG fix by LPC stanard TAR cycle part 2 must be tri-stated by host and device
+ lad_rising_o <= TAR_OK; --drive to F on the bus
+ CS <= TARs;
+ else
+ CS <= RESETs; --some error in protocol master must drive lad to "1111" on 1st TAR
+ end if;
+ when SYNCs => -----------------------------------------------------------
+ case cycle_type is
+ when LPC_IO_W => --IO write cycle
+ -- just passing r_lad on bus again
+ lad_rising_o <= TAR_OK;
+ CS <= LOCAL_TARs;
+ when LPC_MEM_R | LPC_FW_R | LPC_IO_R => --Memory/FW/IO read cycle
+ if data_valid = '1' then
+ lad_rising_o <= SYNC_OK;
+ CS <= DATAs;
+ else
+ if lpc_ack = '1' then
+ r_data <= lpc_data_i;
+ data_valid <= '1';
+ lad_rising_o <= SYNC_OK; --SYNC ok now
+ lpc_val <= '0';
+ CS <= DATAs;
+ end if;
+ end if;
+ when others => null;
+ end case;
+ when LOCAL_TARs => ------------------------------------------------------
+ case cycle_type is
+ when LPC_IO_W => --IO write cycle
+ lpc_wr <= '0';
+ lad_rising_oe <= '0';
+ CS <= RESETs;
+ when LPC_MEM_R | LPC_FW_R | LPC_IO_R => -- read cycle
+ if r_cnt = "000" then
+ lad_rising_o <= TAR_OK;
+ r_cnt <= r_cnt + 1;
+ else
+ lad_rising_oe <= '0';
+ r_cnt <= "000";
+ CS <= RESETs;
+ end if;
+ when others => null;
+ end case;
+ end case; -----------------------------------------------------------------
+ end if;
+ end process LPC;
+
+end rtl;
Index: artec_dongle_ii_fpga/trunk/src/lpc_proto/serirq.vhd
===================================================================
--- artec_dongle_ii_fpga/trunk/src/lpc_proto/serirq.vhd (nonexistent)
+++ artec_dongle_ii_fpga/trunk/src/lpc_proto/serirq.vhd (revision 9)
@@ -0,0 +1,128 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+entity serirq is
+ port (
+ clock : in std_logic;
+ reset_n : in std_logic;
+ slot_sel : in std_logic_vector(4 downto 0); --clk no of IRQ defined in Ser irq for PCI systems spec.
+ serirq : inout std_logic;
+ irq : in std_logic
+ );
+end entity serirq;
+
+architecture RTL of serirq is
+
+ type reg_type is
+ record
+ irq_idle : boolean; --idle mode only host can start irq cycles quiet mode is entered by 2 clock stop, 3 clock stop keeps or enters idle mode
+ irq_frame : boolean; --currently in running irq frame
+ serirq_oe : std_logic; --oe does pulldown
+ low_count : std_logic_vector(3 downto 0);
+ slot_count : std_logic_vector(7 downto 0);
+ irq_count : std_logic_vector(3 downto 0); --wait before irq auto issue
+
+ irq_sync : std_logic; --sync stage
+ end record;
+
+ signal reg, reg_in : reg_type;
+ signal comb_oe : std_logic;
+
+
+begin
+
+ serirq<='0' when comb_oe='1' else
+ 'Z';
+
+
+ -- Design pattern process 1 Implementation
+ comb : process (serirq,slot_sel,irq,reg)
+ variable reg_v : reg_type;
+ begin
+ -- Design pattern
+ reg_v:=reg; --pre set default var state
+ ------------------------------------
+ --- ---
+ ------------------------------------
+ reg_v.irq_sync:=irq;
+ --clear signel cycle oe
+ reg_v.serirq_oe:='0'; --disable pulldown (this can never be longer than 1 cycle)
+
+ --Frame start contition wait
+ if reg_v.irq_idle and not reg_v.irq_frame then -- Idle mode wait for host to start
+ if serirq='0' then -- count low cycles
+ reg_v.low_count:=reg_v.low_count + 1;
+ else -- see if the event is a start frame event
+ if reg_v.low_count>"0011" then -- cycle start
+ reg_v.irq_frame:=true;
+ end if;
+ reg_v.low_count:=(others=>'0');
+ end if;
+ elsif not reg_v.irq_idle and not reg_v.irq_frame and reg.irq_sync='1' then -- in active mode we can start the irq frame
+ if reg_v.irq_count>"0010" then
+ reg_v.serirq_oe:='1'; --enable pulldonw
+ reg_v.irq_frame:=true; -- frame should start
+ else
+ reg_v.irq_count:=reg_v.irq_count + 1;
+ end if;
+ else -- in frame
+ reg_v.irq_count:=(others=>'0'); --
+ end if;
+
+ --In IRQ frame
+ if reg_v.irq_frame and reg_v.slot_count'0'); --reset when out of frame
+ end if;
+
+ --Slot sel must use register value as it is incremented above in the variable for next cycle
+ if reg_v.irq_frame and slot_sel/="00000" and reg.slot_count(7 downto 0)="000"&slot_sel and reg.irq_sync='1' then --when slot and irq active to pull on the serirq
+ reg_v.serirq_oe:='1'; --enable pulldonw
+ end if;
+
+ -- End irq frame and enter idle or active mode
+ if reg_v.irq_frame then
+ if serirq='0' then -- count low cycles
+ reg_v.low_count:=reg_v.low_count + 1;
+ else -- see type of stop frame frame event
+ if reg_v.low_count=x"2" then
+ reg_v.irq_frame:=false;
+ reg_v.irq_idle:=false; --enter active mode
+ elsif reg_v.low_count>x"2" then
+ reg_v.irq_idle:=true; --enter idle mode
+ reg_v.irq_frame:=false;
+ end if;
+ reg_v.low_count:=(others=>'0');
+ end if;
+ end if;
+
+ -- Design pattern
+ -- drive register input signals
+ reg_in<=reg_v;
+ -- drive module outputs signals
+ --port_comb_out<= reg_v.port_comb; --combinatorial output example
+ --port_reg_out<= reg.port_reg; --registered output example
+ comb_oe<=reg_v.serirq_oe; --cominatorial out
+ end process;
+
+ -- Pattern process 2, Registers
+ regs : process (clock,reset_n)
+ begin
+ if reset_n='0' then
+ reg.irq_idle<=true; -- start up in idle mode
+ reg.irq_frame<=false; --start up out of irq frame
+ reg.slot_count<=(others=>'0');
+ reg.low_count<=(others=>'0');
+ reg.irq_count<=(others=>'0');
+ reg.irq_sync<='0';
+ reg.serirq_oe<='0'; -- on reset all agents enter tristated mode
+ elsif rising_edge(clock) then
+ reg<=reg_in;
+ end if;
+ end process;
+
+
+end architecture RTL;
artec_dongle_ii_fpga/trunk/src/lpc_proto/serirq.vhd
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: artec_dongle_ii_fpga/trunk/src/lpc_proto/CLOK_PLL.qip
===================================================================
Index: artec_dongle_ii_fpga/trunk/src/lpc_proto/CLOK_PLL.qip
===================================================================
--- artec_dongle_ii_fpga/trunk/src/lpc_proto/CLOK_PLL.qip (nonexistent)
+++ artec_dongle_ii_fpga/trunk/src/lpc_proto/CLOK_PLL.qip (revision 9)
artec_dongle_ii_fpga/trunk/src/lpc_proto/CLOK_PLL.qip
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: artec_dongle_ii_fpga/trunk/src/led_sys/byte_scan_mux.vhd
===================================================================
--- artec_dongle_ii_fpga/trunk/src/led_sys/byte_scan_mux.vhd (revision 8)
+++ artec_dongle_ii_fpga/trunk/src/led_sys/byte_scan_mux.vhd (revision 9)
@@ -1,111 +1,111 @@
-------------------------------------------------------------------
--- Universal dongle board source code
---
--- Copyright (C) 2006 Artec Design
---
--- This source code is free hardware; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
---
--- This source code is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--- Lesser General Public License for more details.
---
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
---
---
--- The complete text of the GNU Lesser General Public License can be found in
--- the file 'lesser.txt'.
-
-
-
--- bit 0,A
--- ----------
--- | |
--- | |
--- 5,F| | 1,B
--- | 6,G |
--- ----------
--- | |
--- | |
--- 4,E| | 2,C
--- | 3,D |
--- ----------
--- # 7,H
-
-
--- Select signal order
--- --- --- --- ---
--- | | | | | | | |
--- | | | | | | | |
--- --- --- --- ---
--- | | | | | | | |
--- | | | | | | | |
--- --- --- --- ---
--- sel(3) sel(2) sel(1) sel(0)
-
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-use IEEE.std_logic_arith.all;
-
-
-entity byte_scan is
- port (
- clk : in std_logic;
- hi_seg_1 : in std_logic_vector(7 downto 0);
- lo_seg_1 : in std_logic_vector(7 downto 0);
- hi_seg_0 : in std_logic_vector(7 downto 0);
- lo_seg_0 : in std_logic_vector(7 downto 0);
- seg_out : out std_logic_vector(7 downto 0);
- sel_out : out std_logic_vector(3 downto 0)
- );
-end byte_scan;
-
-architecture rtl of byte_scan is
-
-signal sel_p : std_logic_vector(3 downto 0);
-signal count : std_logic_vector(1 downto 0):="00";
-signal hi_seg_1_3 : std_logic_vector(7 downto 0);
-signal lo_seg_1_3 : std_logic_vector(7 downto 0);
-signal hi_seg_0_2 : std_logic_vector(7 downto 0);
-signal lo_seg_0_2 : std_logic_vector(7 downto 0);
-
-begin -- rtl
-
-
-hi_seg_1_3 <= hi_seg_1; -- when sel_hib_n ='1' else hi_seg_3;
-lo_seg_1_3 <= lo_seg_1; --when sel_hib_n ='1' else lo_seg_3;
-hi_seg_0_2 <= hi_seg_0; --when sel_hib_n ='1' else hi_seg_2;
-lo_seg_0_2 <= lo_seg_0; --when sel_hib_n ='1' else lo_seg_2;
-
-
-seg_out <=hi_seg_1_3 when count="01" else
- lo_seg_1_3 when count="10" else
- hi_seg_0_2 when count="11" else
- lo_seg_0_2 when count="00";
-
-sel_out <= not sel_p;
-
-sel_p <= "1110" when count="00" else
- "0111" when count="01" else
- "1011" when count="10" else
- "1101" when count="11";
-
-
-
-
-process (clk) --enable the scanning while in reset (simulation will be incorrect)
-begin -- process
- if clk'event and clk = '1' then -- rising clock edge
- count <= count + 1;
- end if;
-end process;
-
-end rtl;
+------------------------------------------------------------------
+-- Universal dongle board source code
+--
+-- Copyright (C) 2006 Artec Design
+--
+-- This source code is free hardware; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This source code is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+--
+--
+-- The complete text of the GNU Lesser General Public License can be found in
+-- the file 'lesser.txt'.
+
+
+
+-- bit 0,A
+-- ----------
+-- | |
+-- | |
+-- 5,F| | 1,B
+-- | 6,G |
+-- ----------
+-- | |
+-- | |
+-- 4,E| | 2,C
+-- | 3,D |
+-- ----------
+-- # 7,H
+
+
+-- Select signal order
+-- --- --- --- ---
+-- | | | | | | | |
+-- | | | | | | | |
+-- --- --- --- ---
+-- | | | | | | | |
+-- | | | | | | | |
+-- --- --- --- ---
+-- sel(3) sel(2) sel(1) sel(0)
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+
+entity byte_scan is
+ port (
+ clk : in std_logic;
+ hi_seg_1 : in std_logic_vector(7 downto 0);
+ lo_seg_1 : in std_logic_vector(7 downto 0);
+ hi_seg_0 : in std_logic_vector(7 downto 0);
+ lo_seg_0 : in std_logic_vector(7 downto 0);
+ seg_out : out std_logic_vector(7 downto 0);
+ sel_out : out std_logic_vector(3 downto 0)
+ );
+end byte_scan;
+
+architecture rtl of byte_scan is
+
+signal sel_p : std_logic_vector(3 downto 0);
+signal count : std_logic_vector(1 downto 0):="00";
+signal hi_seg_1_3 : std_logic_vector(7 downto 0);
+signal lo_seg_1_3 : std_logic_vector(7 downto 0);
+signal hi_seg_0_2 : std_logic_vector(7 downto 0);
+signal lo_seg_0_2 : std_logic_vector(7 downto 0);
+
+begin -- rtl
+
+
+hi_seg_1_3 <= hi_seg_1; -- when sel_hib_n ='1' else hi_seg_3;
+lo_seg_1_3 <= lo_seg_1; --when sel_hib_n ='1' else lo_seg_3;
+hi_seg_0_2 <= hi_seg_0; --when sel_hib_n ='1' else hi_seg_2;
+lo_seg_0_2 <= lo_seg_0; --when sel_hib_n ='1' else lo_seg_2;
+
+
+seg_out <=hi_seg_1_3 when count="01" else
+ lo_seg_1_3 when count="10" else
+ hi_seg_0_2 when count="11" else
+ lo_seg_0_2;
+
+sel_out <= not sel_p;
+
+sel_p <= "1110" when count="00" else
+ "0111" when count="01" else
+ "1011" when count="10" else
+ "1101" when count="11";
+
+
+
+
+process (clk) --enable the scanning while in reset (simulation will be incorrect)
+begin -- process
+ if clk'event and clk = '1' then -- rising clock edge
+ count <= count + 1;
+ end if;
+end process;
+
+end rtl;
Index: artec_dongle_ii_fpga/trunk/src/led_sys/led_coder.vhd
===================================================================
--- artec_dongle_ii_fpga/trunk/src/led_sys/led_coder.vhd (revision 8)
+++ artec_dongle_ii_fpga/trunk/src/led_sys/led_coder.vhd (revision 9)
@@ -1,112 +1,112 @@
-------------------------------------------------------------------
--- Universal dongle board source code
---
--- Copyright (C) 2006 Artec Design
---
--- This source code is free hardware; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
---
--- This source code is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--- Lesser General Public License for more details.
---
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
---
---
--- The complete text of the GNU Lesser General Public License can be found in
--- the file 'lesser.txt'.
-
-
--- bit 0,A
--- ----------
--- | |
--- | |
--- 5,F| | 1,B
--- | 6,G |
--- ----------
--- | |
--- | |
--- 4,E| | 2,C
--- | 3,D |
--- ----------
--- # 7,H
-
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-use IEEE.std_logic_arith.all;
-
-
-entity led_coder is
- port (
- led_data_i : in std_logic_vector(7 downto 0);
- hi_seg : out std_logic_vector(7 downto 0);
- lo_seg : out std_logic_vector(7 downto 0)
- );
-end led_coder;
-
-architecture rtl of led_coder is
-signal r_led_data : std_logic_vector(7 downto 0);
-signal decoded_lo,decoded_hi : std_logic_vector(7 downto 0);
-
-begin -- rtl
-hi_seg <= not decoded_hi;
-lo_seg <= not decoded_lo;
-
- -- purpose: binary to led segments decoder
- -- type : combinational
- -- inputs : nibble,reset
- -- outputs:
- decode_nibble_lo: process (led_data_i)
- begin -- process decode_nibble
- case led_data_i(3 downto 0) is--HGFEDCBA
- when "0000" => decoded_lo <= "00111111"; -- 0
- when "0001" => decoded_lo <= "00000110"; -- 1
- when "0010" => decoded_lo <= "01011011"; -- 2
- when "0011" => decoded_lo <= "01001111"; -- 3
- when "0100" => decoded_lo <= "01100110"; -- 4
- when "0101" => decoded_lo <= "01101101"; -- 5
- when "0110" => decoded_lo <= "01111101"; -- 6
- when "0111" => decoded_lo <= "00000111"; -- 7
- when "1000" => decoded_lo <= "01111111"; -- 8
- when "1001" => decoded_lo <= "01101111"; -- 9
- when "1010" => decoded_lo <= "01110111"; -- a
- when "1011" => decoded_lo <= "01111100"; -- b
- when "1100" => decoded_lo <= "00111001"; -- c
- when "1101" => decoded_lo <= "01011110"; -- d
- when "1110" => decoded_lo <= "01111001"; -- e
- when others => decoded_lo <= "01110001"; -- f
- end case;
- end process decode_nibble_lo;
-
- decode_nibble_hi: process (led_data_i)
- begin -- process decode_nibble
- case led_data_i(7 downto 4) is--HGFEDCBA
- when "0000" => decoded_hi <= "00111111"; -- 0
- when "0001" => decoded_hi <= "00000110"; -- 1
- when "0010" => decoded_hi <= "01011011"; -- 2
- when "0011" => decoded_hi <= "01001111"; -- 3
- when "0100" => decoded_hi <= "01100110"; -- 4
- when "0101" => decoded_hi <= "01101101"; -- 5
- when "0110" => decoded_hi <= "01111101"; -- 6
- when "0111" => decoded_hi <= "00000111"; -- 7
- when "1000" => decoded_hi <= "01111111"; -- 8
- when "1001" => decoded_hi <= "01101111"; -- 9
- when "1010" => decoded_hi <= "01110111"; -- a
- when "1011" => decoded_hi <= "01111100"; -- b
- when "1100" => decoded_hi <= "00111001"; -- c
- when "1101" => decoded_hi <= "01011110"; -- d
- when "1110" => decoded_hi <= "01111001"; -- e
- when others => decoded_hi <= "01110001"; -- f
- end case;
- end process decode_nibble_hi;
-
-
-end rtl;
+------------------------------------------------------------------
+-- Universal dongle board source code
+--
+-- Copyright (C) 2006 Artec Design
+--
+-- This source code is free hardware; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This source code is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+--
+--
+-- The complete text of the GNU Lesser General Public License can be found in
+-- the file 'lesser.txt'.
+
+
+-- bit 0,A
+-- ----------
+-- | |
+-- | |
+-- 5,F| | 1,B
+-- | 6,G |
+-- ----------
+-- | |
+-- | |
+-- 4,E| | 2,C
+-- | 3,D |
+-- ----------
+-- # 7,H
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+
+entity led_coder is
+ port (
+ led_data_i : in std_logic_vector(7 downto 0);
+ hi_seg : out std_logic_vector(7 downto 0);
+ lo_seg : out std_logic_vector(7 downto 0)
+ );
+end led_coder;
+
+architecture rtl of led_coder is
+signal r_led_data : std_logic_vector(7 downto 0);
+signal decoded_lo,decoded_hi : std_logic_vector(7 downto 0);
+
+begin -- rtl
+hi_seg <= not decoded_hi;
+lo_seg <= not decoded_lo;
+
+ -- purpose: binary to led segments decoder
+ -- type : combinational
+ -- inputs : nibble,reset
+ -- outputs:
+ decode_nibble_lo: process (led_data_i)
+ begin -- process decode_nibble
+ case led_data_i(3 downto 0) is--HGFEDCBA
+ when "0000" => decoded_lo <= "00111111"; -- 0
+ when "0001" => decoded_lo <= "00000110"; -- 1
+ when "0010" => decoded_lo <= "01011011"; -- 2
+ when "0011" => decoded_lo <= "01001111"; -- 3
+ when "0100" => decoded_lo <= "01100110"; -- 4
+ when "0101" => decoded_lo <= "01101101"; -- 5
+ when "0110" => decoded_lo <= "01111101"; -- 6
+ when "0111" => decoded_lo <= "00000111"; -- 7
+ when "1000" => decoded_lo <= "01111111"; -- 8
+ when "1001" => decoded_lo <= "01101111"; -- 9
+ when "1010" => decoded_lo <= "01110111"; -- a
+ when "1011" => decoded_lo <= "01111100"; -- b
+ when "1100" => decoded_lo <= "00111001"; -- c
+ when "1101" => decoded_lo <= "01011110"; -- d
+ when "1110" => decoded_lo <= "01111001"; -- e
+ when others => decoded_lo <= "01110001"; -- f
+ end case;
+ end process decode_nibble_lo;
+
+ decode_nibble_hi: process (led_data_i)
+ begin -- process decode_nibble
+ case led_data_i(7 downto 4) is--HGFEDCBA
+ when "0000" => decoded_hi <= "00111111"; -- 0
+ when "0001" => decoded_hi <= "00000110"; -- 1
+ when "0010" => decoded_hi <= "01011011"; -- 2
+ when "0011" => decoded_hi <= "01001111"; -- 3
+ when "0100" => decoded_hi <= "01100110"; -- 4
+ when "0101" => decoded_hi <= "01101101"; -- 5
+ when "0110" => decoded_hi <= "01111101"; -- 6
+ when "0111" => decoded_hi <= "00000111"; -- 7
+ when "1000" => decoded_hi <= "01111111"; -- 8
+ when "1001" => decoded_hi <= "01101111"; -- 9
+ when "1010" => decoded_hi <= "01110111"; -- a
+ when "1011" => decoded_hi <= "01111100"; -- b
+ when "1100" => decoded_hi <= "00111001"; -- c
+ when "1101" => decoded_hi <= "01011110"; -- d
+ when "1110" => decoded_hi <= "01111001"; -- e
+ when others => decoded_hi <= "01110001"; -- f
+ end case;
+ end process decode_nibble_hi;
+
+
+end rtl;
Index: artec_dongle_ii_fpga/trunk/src/led_sys/led_sys.vhd
===================================================================
--- artec_dongle_ii_fpga/trunk/src/led_sys/led_sys.vhd (revision 8)
+++ artec_dongle_ii_fpga/trunk/src/led_sys/led_sys.vhd (revision 9)
@@ -1,169 +1,161 @@
-------------------------------------------------------------------
--- Universal dongle board source code
---
--- Copyright (C) 2006 Artec Design
---
--- This source code is free hardware; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
---
--- This source code is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--- Lesser General Public License for more details.
---
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
---
---
--- The complete text of the GNU Lesser General Public License can be found in
--- the file 'lesser.txt'.
-
-
--- bit 0,A
--- ----------
--- | |
--- | |
--- 5,F| | 1,B
--- | 6,G |
--- ----------
--- | |
--- | |
--- 4,E| | 2,C
--- | 3,D |
--- ----------
--- # 7,H
-
-
--- Select signal order
--- --- --- --- ---
--- | | | | | | | |
--- | | | | | | | |
--- --- --- --- ---
--- | | | | | | | |
--- | | | | | | | |
--- --- --- --- ---
--- sel(3) sel(2) sel(1) sel(0)
-
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-use IEEE.std_logic_arith.all;
-
-
-entity led_sys is --toplevel for led system
- generic(
- msn_hib : std_logic_vector(7 downto 0); --Most signif. of hi byte
- lsn_hib : std_logic_vector(7 downto 0); --Least signif. of hi byte
- msn_lob : std_logic_vector(7 downto 0); --Most signif. of hi byte
- lsn_lob : std_logic_vector(7 downto 0) --Least signif. of hi byte
- );
- port (
- clk : in std_logic;
- reset_n : in std_logic;
- led_data_i : in std_logic_vector(15 downto 0); --binary data in
- seg_out : out std_logic_vector(7 downto 0); --one segment out
- sel_out : out std_logic_vector(3 downto 0) --segment scanner with one bit low
- );
-end led_sys;
-
-architecture rtl of led_sys is
-
-component led_coder
- port (
- led_data_i : in std_logic_vector(7 downto 0);
- hi_seg : out std_logic_vector(7 downto 0);
- lo_seg : out std_logic_vector(7 downto 0)
- );
-end component;
-
-component byte_scan
- port (
- clk : in std_logic;
- hi_seg_1 : in std_logic_vector(7 downto 0);
- lo_seg_1 : in std_logic_vector(7 downto 0);
- hi_seg_0 : in std_logic_vector(7 downto 0);
- lo_seg_0 : in std_logic_vector(7 downto 0);
- seg_out : out std_logic_vector(7 downto 0);
- sel_out : out std_logic_vector(3 downto 0)
- );
-end component;
-
-
--- input signals
-signal hi_seg1 : std_logic_vector(7 downto 0);
-signal lo_seg1 : std_logic_vector(7 downto 0);
-signal hi_seg0 : std_logic_vector(7 downto 0);
-signal lo_seg0 : std_logic_vector(7 downto 0);
-
---data containing signals
-signal data_hi_seg1 : std_logic_vector(7 downto 0);
-signal data_lo_seg1 : std_logic_vector(7 downto 0);
-signal data_hi_seg0 : std_logic_vector(7 downto 0);
-signal data_lo_seg0 : std_logic_vector(7 downto 0);
-
---constant display
-signal cons_hi_seg1 : std_logic_vector(7 downto 0);
-signal cons_lo_seg1 : std_logic_vector(7 downto 0);
-signal cons_hi_seg0 : std_logic_vector(7 downto 0);
-signal cons_lo_seg0 : std_logic_vector(7 downto 0);
-
-signal disp_cnt : std_logic_vector(15 downto 0):=(others=>'0'); --this enables correct simulation
-
-begin -- rtl
----------------------------HGFEDCBA
-cons_hi_seg1 <= msn_hib;--"01111111"; --8
-cons_lo_seg1 <= lsn_hib;--"01111101"; --6
-cons_hi_seg0 <= msn_lob;--"01011100"; -- small o
-cons_lo_seg0 <= lsn_lob;--"01011100"; -- small o
-
-
-
-
-process (clk) --enable the scanning while in reset
-begin -- process
- if clk'event and clk = '0' then -- rising clock edge
- disp_cnt <= disp_cnt + 1;
- end if;
-end process;
-
-LED_CODE0: led_coder
- port map(
- led_data_i => led_data_i(7 downto 0), -- in std_logic_vector(7 downto 0);
- hi_seg => data_hi_seg0, -- out std_logic_vector(7 downto 0);
- lo_seg => data_lo_seg0 -- out std_logic_vector(7 downto 0)
- );
-
-LED_CODE1: led_coder
- port map(
- led_data_i => led_data_i(15 downto 8), -- in std_logic_vector(7 downto 0);
- hi_seg => data_hi_seg1, -- out std_logic_vector(7 downto 0);
- lo_seg => data_lo_seg1 -- out std_logic_vector(7 downto 0)
- );
-
-
-lo_seg1 <= data_lo_seg1; --when reset_n='1' else cons_hi_seg1;
-hi_seg1 <= data_hi_seg1; --when reset_n='1' else cons_lo_seg1;
-
-lo_seg0 <= data_lo_seg0; --when reset_n='1' else cons_hi_seg0;
-hi_seg0 <= data_hi_seg0; --when reset_n='1' else cons_lo_seg0;
-
-SCAN : byte_scan
- port map(
- clk => disp_cnt(15), -- in std_logic;
- hi_seg_1 => hi_seg1, -- in std_logic_vector(7 downto 0);
- lo_seg_1 => lo_seg1, -- in std_logic_vector(7 downto 0);
- hi_seg_0 => hi_seg0, -- in std_logic_vector(7 downto 0);
- lo_seg_0 => lo_seg0, -- in std_logic_vector(7 downto 0);
- seg_out => seg_out, -- out std_logic_vector(7 downto 0);
- sel_out => sel_out -- out std_logic_vector(3 downto 0)
- );
-
-
-
-
-end rtl;
+------------------------------------------------------------------
+-- Universal dongle board source code
+--
+-- Copyright (C) 2006 Artec Design
+--
+-- This source code is free hardware; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This source code is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+--
+--
+-- The complete text of the GNU Lesser General Public License can be found in
+-- the file 'lesser.txt'.
+
+
+-- bit 0,A
+-- ----------
+-- | |
+-- | |
+-- 5,F| | 1,B
+-- | 6,G |
+-- ----------
+-- | |
+-- | |
+-- 4,E| | 2,C
+-- | 3,D |
+-- ----------
+-- # 7,H
+
+
+-- Select signal order
+-- --- --- --- ---
+-- | | | | | | | |
+-- | | | | | | | |
+-- --- --- --- ---
+-- | | | | | | | |
+-- | | | | | | | |
+-- --- --- --- ---
+-- sel(3) sel(2) sel(1) sel(0)
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+
+entity led_sys is --toplevel for led system
+ generic(
+ msn_hib : std_logic_vector(7 downto 0); --Most signif. of hi byte
+ lsn_hib : std_logic_vector(7 downto 0); --Least signif. of hi byte
+ msn_lob : std_logic_vector(7 downto 0); --Most signif. of hi byte
+ lsn_lob : std_logic_vector(7 downto 0) --Least signif. of hi byte
+ );
+ port (
+ clk : in std_logic;
+ reset_n : in std_logic;
+ led_data_i : in std_logic_vector(15 downto 0); --binary data in
+ seg_out : out std_logic_vector(7 downto 0); --one segment out
+ sel_out : out std_logic_vector(3 downto 0) --segment scanner with one bit low
+ );
+end led_sys;
+
+architecture rtl of led_sys is
+
+component led_coder
+ port (
+ led_data_i : in std_logic_vector(7 downto 0);
+ hi_seg : out std_logic_vector(7 downto 0);
+ lo_seg : out std_logic_vector(7 downto 0)
+ );
+end component;
+
+component byte_scan
+ port (
+ clk : in std_logic;
+ hi_seg_1 : in std_logic_vector(7 downto 0);
+ lo_seg_1 : in std_logic_vector(7 downto 0);
+ hi_seg_0 : in std_logic_vector(7 downto 0);
+ lo_seg_0 : in std_logic_vector(7 downto 0);
+ seg_out : out std_logic_vector(7 downto 0);
+ sel_out : out std_logic_vector(3 downto 0)
+ );
+end component;
+
+
+-- input signals
+signal hi_seg1 : std_logic_vector(7 downto 0);
+signal lo_seg1 : std_logic_vector(7 downto 0);
+signal hi_seg0 : std_logic_vector(7 downto 0);
+signal lo_seg0 : std_logic_vector(7 downto 0);
+
+--data containing signals
+signal data_hi_seg1 : std_logic_vector(7 downto 0);
+signal data_lo_seg1 : std_logic_vector(7 downto 0);
+signal data_hi_seg0 : std_logic_vector(7 downto 0);
+signal data_lo_seg0 : std_logic_vector(7 downto 0);
+
+--constant display
+--signal cons_hi_seg1 : std_logic_vector(7 downto 0);
+--signal cons_lo_seg1 : std_logic_vector(7 downto 0);
+--signal cons_hi_seg0 : std_logic_vector(7 downto 0);
+--signal cons_lo_seg0 : std_logic_vector(7 downto 0);
+
+signal disp_cnt : std_logic_vector(15 downto 0):=(others=>'0'); --this enables correct simulation
+
+begin -- rtl
+
+process (clk) --enable the scanning while in reset
+begin -- process
+ if clk'event and clk = '0' then -- rising clock edge
+ disp_cnt <= disp_cnt + 1;
+ end if;
+end process;
+
+LED_CODE0: led_coder
+ port map(
+ led_data_i => led_data_i(7 downto 0), -- in std_logic_vector(7 downto 0);
+ hi_seg => data_hi_seg0, -- out std_logic_vector(7 downto 0);
+ lo_seg => data_lo_seg0 -- out std_logic_vector(7 downto 0)
+ );
+
+LED_CODE1: led_coder
+ port map(
+ led_data_i => led_data_i(15 downto 8), -- in std_logic_vector(7 downto 0);
+ hi_seg => data_hi_seg1, -- out std_logic_vector(7 downto 0);
+ lo_seg => data_lo_seg1 -- out std_logic_vector(7 downto 0)
+ );
+
+
+lo_seg1 <= data_lo_seg1; --when reset_n='1' else cons_hi_seg1;
+hi_seg1 <= data_hi_seg1; --when reset_n='1' else cons_lo_seg1;
+
+lo_seg0 <= data_lo_seg0; --when reset_n='1' else cons_hi_seg0;
+hi_seg0 <= data_hi_seg0; --when reset_n='1' else cons_lo_seg0;
+
+SCAN : byte_scan
+ port map(
+ clk => disp_cnt(15), -- in std_logic;
+ hi_seg_1 => hi_seg1, -- in std_logic_vector(7 downto 0);
+ lo_seg_1 => lo_seg1, -- in std_logic_vector(7 downto 0);
+ hi_seg_0 => hi_seg0, -- in std_logic_vector(7 downto 0);
+ lo_seg_0 => lo_seg0, -- in std_logic_vector(7 downto 0);
+ seg_out => seg_out, -- out std_logic_vector(7 downto 0);
+ sel_out => sel_out -- out std_logic_vector(3 downto 0)
+ );
+
+
+
+
+end rtl;
Index: artec_dongle_ii_fpga/trunk/src/spi_eeprom/spi_master.vhd
===================================================================
--- artec_dongle_ii_fpga/trunk/src/spi_eeprom/spi_master.vhd (revision 8)
+++ artec_dongle_ii_fpga/trunk/src/spi_eeprom/spi_master.vhd (revision 9)
@@ -1,147 +1,147 @@
-------------------------------------------------------------------
--- Universal dongle board source code
---
--- Copyright (C) 2008 Artec Design
---
--- This source code is free hardware; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
---
--- This source code is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--- Lesser General Public License for more details.
---
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
---
---
--- The complete text of the GNU Lesser General Public License can be found in
--- the file 'lesser.txt'.
-
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-use IEEE.std_logic_arith.all;
-
-entity spi_if is
- port (
- clk : in std_logic;
- reset_n : in std_logic;
- --------------------------
- -- EEPROM signals
- ee_do : out std_logic;
- ee_di : in std_logic;
- ee_hold_n : out std_logic;
- ee_cs_n : out std_logic;
- ee_clk : out std_logic;
- ee_wrp_n : out std_logic; --write protect signal active low
- -- Mem bus
- mem_addr : in std_logic_vector(23 downto 0);
- mem_do : out std_logic_vector(15 downto 0);
- mem_di : in std_logic_vector(15 downto 0);
-
- mem_wr : in std_logic; --write not read signal
- mem_val : in std_logic;
- mem_ack : out std_logic
-
- );
-end spi_if;
-
-
-architecture RTL of spi_if is
- type state_type is (RESETs,SPI_CYCLEs,WAITs);
- signal CS : state_type;
-
- signal spi_cnt : std_logic_vector(4 downto 0);
- signal spi_shiftr : std_logic_vector(0 to 23);
- signal spi_wren_done : std_logic;
-
-
- constant SPI_READ : std_logic_vector(0 to 2):="011";
- constant SPI_WRITE : std_logic_vector(0 to 2):="010";
- constant SPI_SET_WEN : std_logic_vector(0 to 2):="110";
- constant SPI_CLR_WEN : std_logic_vector(0 to 2):="100";
-
-
-begin
-
-
-ee_do <= spi_shiftr(0);
-
-SPI_SM: process (clk, reset_n)
-begin -- process READ
- if reset_n='0' then
- ee_cs_n <='1';
- CS <= RESETs;
- ee_clk <='0';
- ee_wrp_n <='1'; --active low write protect
- ee_hold_n <='1';
- spi_wren_done <='0';
- spi_cnt <=(others=>'0');
- elsif clk'event and clk = '1' then -- rising clock edge
-
- case CS is
- when RESETs =>
- mem_ack <='0';
- ee_cs_n <= (not mem_val); --chipselect 4 spi
- fl_we_n <= (not (mem_val and mem_wr)); --write enable 4 flash
- if spi_wren_done ='0' then
- spi_cnt <= "01111"; --only 8 bit command needs to be sent
- spi_shiftr(0 to 3) <="0000";
- spi_shiftr(4) <= '0';
- spi_shiftr(5 to 7) <= SPI_SET_WEN;
- CS <= SPI_CYCLEs;
- elsif mem_val='1' and mem_wr = '0' then --READ
- spi_cnt <=(others=>'0');
- spi_shiftr(0 to 3) <="0000";
- spi_shiftr(4) <= mem_addr(8);
- spi_shiftr(5 to 7) <= SPI_READ;
- spi_shiftr(8 to 15) <= mem_addr(7 downto 0);
- CS <= SPI_CYCLEs;
- elsif mem_val='1' and mem_wr = '1' then --WRITE
- spi_cnt <=(others=>'0');
- spi_shiftr(0 to 3) <="0000";
- spi_shiftr(4) <= mem_addr(8);
- spi_shiftr(5 to 7) <= SPI_WRITE;
- spi_shiftr(8 to 15) <= mem_addr(7 downto 0);
- spi_shiftr(16 to 23) <= mem_di(7 downto 0);
- CS <= SPI_CYCLEs;
- end if; --elsif mem_cmd
- when SPI_CYCLEs =>
- if spi_cnt < 24 then
- ee_clk <= not ee_clk;
- elsif
- mem_do <= x"00"&spi_shiftr(16 to 23); --this may be done always as this is don't care to all but read
- ee_clk <= '0';
- if spi_wren_done ='0' then
- spi_wren_done <='1';
- CS <= RESETs;
- else
- mem_ack <='1';
- CS <= WAITs;
- end if;
- end if;
-
- if ee_clk='1' then
- spi_shiftr <= spi_shiftr(1 to 23)&ee_di;
- spi_cnt <= spi_cnt + 1;
- end if;
- when WAITs =>
- if mem_val='0' then -- wait untill val is removed
- mem_ack <='0';
- CS <= RESETs;
- end if;
-
- end case;
-
- end if; --system
-end process SPI_SM;
-
-
-
-
+------------------------------------------------------------------
+-- Universal dongle board source code
+--
+-- Copyright (C) 2008 Artec Design
+--
+-- This source code is free hardware; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This source code is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+--
+--
+-- The complete text of the GNU Lesser General Public License can be found in
+-- the file 'lesser.txt'.
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+entity spi_if is
+ port (
+ clk : in std_logic;
+ reset_n : in std_logic;
+ --------------------------
+ -- EEPROM signals
+ ee_do : out std_logic;
+ ee_di : in std_logic;
+ ee_hold_n : out std_logic;
+ ee_cs_n : out std_logic;
+ ee_clk : out std_logic;
+ ee_wrp_n : out std_logic; --write protect signal active low
+ -- Mem bus
+ mem_addr : in std_logic_vector(23 downto 0);
+ mem_do : out std_logic_vector(15 downto 0);
+ mem_di : in std_logic_vector(15 downto 0);
+
+ mem_wr : in std_logic; --write not read signal
+ mem_val : in std_logic;
+ mem_ack : out std_logic
+
+ );
+end spi_if;
+
+
+architecture RTL of spi_if is
+ type state_type is (RESETs,SPI_CYCLEs,WAITs);
+ signal CS : state_type;
+
+ signal spi_cnt : std_logic_vector(4 downto 0);
+ signal spi_shiftr : std_logic_vector(0 to 23);
+ signal spi_wren_done : std_logic;
+
+
+ constant SPI_READ : std_logic_vector(0 to 2):="011";
+ constant SPI_WRITE : std_logic_vector(0 to 2):="010";
+ constant SPI_SET_WEN : std_logic_vector(0 to 2):="110";
+ constant SPI_CLR_WEN : std_logic_vector(0 to 2):="100";
+
+
+begin
+
+
+ee_do <= spi_shiftr(0);
+
+SPI_SM: process (clk, reset_n)
+begin -- process READ
+ if reset_n='0' then
+ ee_cs_n <='1';
+ CS <= RESETs;
+ ee_clk <='0';
+ ee_wrp_n <='1'; --active low write protect
+ ee_hold_n <='1';
+ spi_wren_done <='0';
+ spi_cnt <=(others=>'0');
+ elsif clk'event and clk = '1' then -- rising clock edge
+
+ case CS is
+ when RESETs =>
+ mem_ack <='0';
+ ee_cs_n <= (not mem_val); --chipselect 4 spi
+ fl_we_n <= (not (mem_val and mem_wr)); --write enable 4 flash
+ if spi_wren_done ='0' then
+ spi_cnt <= "01111"; --only 8 bit command needs to be sent
+ spi_shiftr(0 to 3) <="0000";
+ spi_shiftr(4) <= '0';
+ spi_shiftr(5 to 7) <= SPI_SET_WEN;
+ CS <= SPI_CYCLEs;
+ elsif mem_val='1' and mem_wr = '0' then --READ
+ spi_cnt <=(others=>'0');
+ spi_shiftr(0 to 3) <="0000";
+ spi_shiftr(4) <= mem_addr(8);
+ spi_shiftr(5 to 7) <= SPI_READ;
+ spi_shiftr(8 to 15) <= mem_addr(7 downto 0);
+ CS <= SPI_CYCLEs;
+ elsif mem_val='1' and mem_wr = '1' then --WRITE
+ spi_cnt <=(others=>'0');
+ spi_shiftr(0 to 3) <="0000";
+ spi_shiftr(4) <= mem_addr(8);
+ spi_shiftr(5 to 7) <= SPI_WRITE;
+ spi_shiftr(8 to 15) <= mem_addr(7 downto 0);
+ spi_shiftr(16 to 23) <= mem_di(7 downto 0);
+ CS <= SPI_CYCLEs;
+ end if; --elsif mem_cmd
+ when SPI_CYCLEs =>
+ if spi_cnt < 24 then
+ ee_clk <= not ee_clk;
+ elsif
+ mem_do <= x"00"&spi_shiftr(16 to 23); --this may be done always as this is don't care to all but read
+ ee_clk <= '0';
+ if spi_wren_done ='0' then
+ spi_wren_done <='1';
+ CS <= RESETs;
+ else
+ mem_ack <='1';
+ CS <= WAITs;
+ end if;
+ end if;
+
+ if ee_clk='1' then
+ spi_shiftr <= spi_shiftr(1 to 23)&ee_di;
+ spi_cnt <= spi_cnt + 1;
+ end if;
+ when WAITs =>
+ if mem_val='0' then -- wait untill val is removed
+ mem_ack <='0';
+ CS <= RESETs;
+ end if;
+
+ end case;
+
+ end if; --system
+end process SPI_SM;
+
+
+
+
end RTL;
\ No newline at end of file
Index: artec_dongle_ii_fpga/trunk/src/dongle_arch/dongle_arch.vhd
===================================================================
--- artec_dongle_ii_fpga/trunk/src/dongle_arch/dongle_arch.vhd (nonexistent)
+++ artec_dongle_ii_fpga/trunk/src/dongle_arch/dongle_arch.vhd (revision 9)
@@ -0,0 +1,45 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+
+package dongle_arch is
+
+
+--VCI bus types
+type vci_slave_in is record
+ lpc_addr : std_logic_vector(15 downto 0); --shared address
+ lpc_wr : std_logic; --shared write not read
+ lpc_data_o : std_logic_vector(7 downto 0);
+ lpc_val : std_logic;
+end record;
+
+type vci_slave_out is record
+ lpc_data_i : std_logic_vector(7 downto 0);
+ lpc_ack : std_logic;
+ lpc_irq : std_logic;
+end record;
+
+ procedure vci_slave_reset(signal vci : out vci_slave_out);
+
+
+end package dongle_arch;
+
+
+
+
+package body dongle_arch is
+
+ procedure vci_slave_reset(
+ signal vci : out vci_slave_out) is
+ variable v : vci_slave_out;
+ begin
+ v.lpc_ack:='0';
+ v.lpc_irq:='0';
+ v.lpc_data_i:=x"00";
+ vci<=v;
+ end procedure vci_slave_reset;
+
+
+end package body dongle_arch;
artec_dongle_ii_fpga/trunk/src/dongle_arch/dongle_arch.vhd
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: artec_dongle_ii_fpga/trunk/src/serial_usb/serial_usb_package.vhd
===================================================================
--- artec_dongle_ii_fpga/trunk/src/serial_usb/serial_usb_package.vhd (nonexistent)
+++ artec_dongle_ii_fpga/trunk/src/serial_usb/serial_usb_package.vhd (revision 9)
@@ -0,0 +1,271 @@
+------------------------------------------------------------------
+-- Universal dongle board source code
+--
+-- Copyright (C) 2006 Artec Design
+--
+-- This source code is free hardware; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This source code is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+--
+--
+-- The complete text of the GNU Lesser General Public License can be found in
+-- the file 'lesser.txt'.
+
+
+----------------------------------------------------------------------------------
+-- Company: Artec Design Ltd
+-- Engineer: Jüri Toomessoo
+--
+-- Create Date: 16:23 23/12/2011
+-- Design Name: UART CPU interface package
+-- Module Name: serial_usb_package
+-- Project Name: FlexyICE
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+package serial_usb_package is
+
+ type usbser_ctrl is record
+ mode_en : std_logic; -- enable this block
+ end record;
+
+ -- USB interface types
+
+ type usb_out is record
+ rx_oe_n : std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
+ tx_wr : std_logic; -- write performed on edge \ of signal
+ txdata : std_logic_vector(7 downto 0); --bus data
+ end record;
+
+ type usb_in is record
+ tx_empty_n : std_logic; -- tx fifo empty (redy for new data if low)
+ rx_full_n : std_logic; -- rx fifo empty (data redy if low)
+ rxdata : std_logic_vector(7 downto 0); --bus data
+ end record;
+
+ --UART register descriptions
+
+
+ --Interrupt Enable Register (IER)
+ constant SEL_IER_RXDATA_INT : natural := 0; --Enable Received Data Available Interrupt
+ constant SEL_IER_TXEMPY_INT : natural := 1; --Enable Transmitter Holding Register Empty Interrupt
+ constant SEL_IER_RXLINE_INT : natural := 2; --Enable Receiver Line Status Interrupt
+ constant SEL_IER_MODEM_INT : natural := 3; --Enable Modem Status Interrupt
+ --SEL_IER bit 7 downto 4 --Reserved
+ type uart_int_ena is record
+ reg : std_logic_vector(7 downto 0); --Register
+ end record;
+
+ --Interrupt Identification Register (IIR)
+ constant SEL_IIR_PENDING_N : natural := 0; -- No Interrupt Pending when set to '1'
+ subtype SEL_IIR_TYPE is natural range 3 downto 1; --
+ constant VAL_IIR_TYPE_MODEM : std_logic_vector(2 downto 0) := "000"; -- Modem Status Interrupt
+ constant VAL_IIR_TYPE_TXEMPTY : std_logic_vector(2 downto 0) := "001"; -- Transmitter Holding Register Empty Interrupt
+ constant VAL_IIR_TYPE_RXDATA : std_logic_vector(2 downto 0) := "010"; -- Received Data Available Interrupt
+ constant VAL_IIR_TYPE_RXLINE : std_logic_vector(2 downto 0) := "011"; -- Receiver Line Status Interrupt
+ constant SEL_IIR_TYPE_PENDING_N : std_logic_vector(2 downto 0) := "110"; -- 16550 Time-out Interrupt Pending when '1'
+ -- SEL_IIR bit 4 -- Reserved
+ constant SEL_IIR_TYPE_FIFOENAB_N : natural := 5; -- 64 Byte Fifo Enabled (16750 only)
+ subtype SEL_IIR_FIFO is natural range 7 downto 6; -- (16750 only)
+ constant VAL_IIR_FIFO_NONE : std_logic_vector(1 downto 0) := "00"; -- No fifo
+ constant VAL_IIR_FIFO_UNSTA : std_logic_vector(1 downto 0) := "01"; -- FIFO Enabled but Unusable
+ constant VAL_IIR_FIFO_ENAB : std_logic_vector(1 downto 0) := "11"; -- FIFO Enabled
+ type uart_int_id is record
+ reg : std_logic_vector(7 downto 0); --Register
+ end record;
+
+ --(TODO "Implement self clear for bits 1 and 2")
+ -- First In / First Out Control Register (FCR) (Write only)
+ constant SEL_FCR_FIFO_ENA : natural := 0; -- Enable FIFO's on '1' (data in fifo is lost when set '0')
+ constant SEL_FCR_FIFO_RXCLR : natural := 1; -- Clear Receive FIFO on '1' (Self clear bit)
+ constant SEL_FCR_FIFO_TXCLR : natural := 2; -- Clear Transmit FIFO '1' (Self clear bit)
+ constant SEL_FCR_DMA_MODE : natural := 3; -- DMA Mode Select. Change status of RXRDY & TXRDY pins from mode 1 to mode 2.
+ --SEL_FCR bit 4 -- Reserved
+ constant SEL_FCR_LARGEFIFO_ENA : natural := 5; -- Enable 64 Byte FIFO (16750 only)
+ subtype SEL_FCR_RXINTLEVEL is natural range 7 downto 6; -- Interrupt Trigger Level on RX FIFO
+ constant VAL_FCR_RXINTLEVEL_1 : std_logic_vector(1 downto 0) := "00"; -- 1 Byte
+ constant VAL_FCR_RXINTLEVEL_4 : std_logic_vector(1 downto 0) := "01"; -- 4 Bytes
+ constant VAL_FCR_RXINTLEVEL_8 : std_logic_vector(1 downto 0) := "10"; -- 8 Bytes
+ constant VAL_FCR_RXINTLEVEL_14 : std_logic_vector(1 downto 0) := "11"; -- 14 Bytes
+ type fifo_ctrl is record
+ reg : std_logic_vector(7 downto 0); --Register
+ end record;
+
+ --Line Control Register (LCR)
+ subtype SEL_LCR_WORDLEN is natural range 1 downto 0; --Word Length
+ constant VAL_LCR_WORDLEN_5 : std_logic_vector(1 downto 0) := "00"; -- 5 Bits
+ constant VAL_LCR_WORDLEN_6 : std_logic_vector(1 downto 0) := "01"; -- 6 Bits
+ constant VAL_LCR_WORDLEN_7 : std_logic_vector(1 downto 0) := "10"; -- 7 Bits
+ constant VAL_LCR_WORDLEN_8 : std_logic_vector(1 downto 0) := "11"; -- 8 Bits
+ constant SEL_LCR_STOPLEN : natural := 2; -- '0'One Stop Bit ; '1' 2 Stop bits for words of length 6,7 or 8 bits or 1.5 Stop Bits for Word lengths of 5 bits.
+ subtype SEL_LCR_PARITY is natural range 5 downto 3; --Parity Select
+ constant VAL_LCR_PARITY_ODD : std_logic_vector(2 downto 0) := "001"; -- Odd Parity
+ constant VAL_LCR_PARITY_EVEN : std_logic_vector(2 downto 0) := "011"; -- Even Parity
+ constant VAL_LCR_PARITY_HIGH : std_logic_vector(2 downto 0) := "101"; -- High Parity (Sticky)
+ constant VAL_LCR_PARITY_LOW : std_logic_vector(2 downto 0) := "111"; -- Low Parity (Sticky)
+ constant SEL_LCR_BREAKENA : natural := 6; -- Set Break Enable
+ constant SEL_LCR_DLAB : natural := 7; -- '1' Divisor Latch Access Bit ; '0' Access to Receiver buffer, Transmitter buffer & Interrupt Enable Register
+ type line_ctrl is record
+ reg : std_logic_vector(7 downto 0); --Register
+ end record;
+
+ -- TODO "Implement Loop back mode"
+ --Modem Control Register (MCR)
+ constant SEL_MCR_FTERMRDY : natural := 0; -- Force Data Terminal Ready
+ constant SEL_MCR_FREQSND : natural := 1; -- Force Request to Send
+ constant SEL_MCR_AUX1 : natural := 2; -- Aux Output 1
+ constant SEL_MCR_AUX2 : natural := 3; -- Aux Output 2
+ constant SEL_MCR_LOOP : natural := 4; -- LoopBack Mode
+ constant SEL_MCR_FLWCTRL : natural := 5; -- Autoflow Control Enabled (16750 only)
+ type modem_ctrl is record
+ reg : std_logic_vector(7 downto 0); --Register
+ end record;
+
+ --Line Status Register (LSR) (read only)
+ constant SEL_LSR_DATARDY : natural := 0; -- Data Ready TODO "Implement data ready"
+ constant SEL_LSR_OVRERR : natural := 1; -- Overrun Error (input reg over flow) TODO "Implement over run"
+ constant SEL_LSR_PARERR : natural := 2; -- Parity Error
+ constant SEL_LSR_FRMERR : natural := 3; -- Framing Error
+ constant SEL_LSR_BREAKINT : natural := 4; -- Break Interrupt
+ constant SEL_LSR_EMPTY_TXH : natural := 5; -- Empty Transmitter Holding Register
+ constant SEL_LSR_EMPTY_DH : natural := 6; -- Empty Data Holding Registers
+ constant SEL_LSR_RXFIFOERR : natural := 7; -- Error in Received FIFO
+ type line_status is record
+ reg : std_logic_vector(7 downto 0); --Register
+ end record;
+
+ --Modem Status Register (MSR)
+ constant SEL_MSR_CHN_CTS : natural := 0; -- Delta Clear to Send (auto falloff on reg read)
+ constant SEL_MSR_CHN_RDY : natural := 1; -- Delta Data Set Ready (auto falloff on reg read)
+ constant SEL_MSR_CHN_RING : natural := 2; -- Trailing Edge Ring Indicator (auto falloff on reg read)
+ constant SEL_MSR_CHN_CD : natural := 3; -- Delta Data Carrier Detect (auto falloff on reg read)
+ constant SEL_MSR_CTC : natural := 4; -- Clear To Send (signal state)
+ constant SEL_MSR_RDY : natural := 5; -- Data Set Ready (signal state)
+ constant SEL_MSR_RING : natural := 6; -- Ring Indicator (signal state)
+ constant SEL_MSR_CD : natural := 7; -- Carrier Detect (signal state)
+ type modem_status is record
+ reg : std_logic_vector(7 downto 0); --Register
+ end record;
+
+ -- Scratch Register
+ type scratch is record
+ reg : std_logic_vector(7 downto 0); --Register
+ end record;
+
+ type general_reg is record
+ reg : std_logic_vector(7 downto 0); --Register
+ end record;
+
+ type uart_registers is record
+ txhold : general_reg; --Register (Write) (OFS +0 DLAB=0) --Transmitter Holding Buffer
+ rxbuff : general_reg; --Register (Read) (OFS +0 DLAB=0) --Receiver Buffer
+ div_low : general_reg; --Register (R/W) (OFS +0 DLAB=1) --Divisor Latch Low Byte
+ ier : uart_int_ena; --Register (R/W) (OFS +1 DLAB=0) --Interrupt Enable Register
+ div_high : general_reg; --Register (R/W) (OFS +1 DLAB=1) --Divisor Latch High Byte
+ iir : uart_int_id; --Register (Read) (OFS +2 DLAB=-) --Interrupt Identification Register
+ fcr : fifo_ctrl; --Register (Write) (OFS +2 DLAB=-) --FIFO Control Register
+ lcr : line_ctrl; --Register (R/W) (OFS +3 DLAB=-) --Line Control Register
+ mcr : modem_ctrl; --Register (R/W) (OFS +4 DLAB=-) --Modem Control Register
+ lsr : line_status; --Register (Read) (OFS +5 DLAB=-) --Line Status Register
+ msr : modem_status; --Register (Read) (OFS +6 DLAB=-) --Modem Status Register
+ scr : scratch; --Register (R/W) (OFS +7 DLAB=-) --Scratch Register
+ end record;
+
+ procedure uart_reset(signal uart : out uart_registers);
+ procedure fifo_reset(signal fifo : out usb_out);
+
+ procedure set_uart_rx_int(variable uart : inout uart_registers);
+ procedure clr_uart_rx_int(variable uart : inout uart_registers);
+
+ procedure set_uart_tx_int(variable uart : inout uart_registers);
+ procedure clr_uart_tx_int(variable uart : inout uart_registers);
+
+
+end package serial_usb_package;
+package body serial_usb_package is
+
+ procedure fifo_reset(
+ signal fifo : out usb_out) is
+ variable f : usb_out;
+ begin
+ f.rx_oe_n:='1';
+ f.tx_wr:='0';
+ f.txdata:=(others=>'0');
+ fifo<=f;
+ end procedure fifo_reset;
+
+ procedure uart_reset(
+ signal uart : out uart_registers) is
+ variable u : uart_registers;
+ begin
+ u.txhold.reg := x"00"; --not needed direct write possible
+ u.rxbuff.reg := x"00";
+ u.div_low.reg := x"00";
+ u.ier.reg := x"00";
+ u.div_high.reg := x"01"; -- 115200 baud
+ u.iir.reg := x"41"; --no int pending, fifo enabled but unusable
+ u.fcr.reg := x"00"; --
+ u.lcr.reg := x"03"; -- set 8 bit data 1 stop no parity DLA 0
+ u.mcr.reg := x"00"; --
+ u.lsr.reg := x"60"; -- tx empty and rx empty flags set on reset
+ u.msr.reg := x"10"; -- Clear To Send is high after reset
+ u.scr.reg := x"00"; --
+ uart <= u;
+ end procedure uart_reset;
+
+
+ procedure set_uart_rx_int(variable uart : inout uart_registers) is
+ begin
+ if uart.ier.reg(SEL_IER_RXDATA_INT)='1' then --int enabled
+ uart.iir.reg(SEL_IIR_TYPE):=VAL_IIR_TYPE_RXDATA;
+ uart.iir.reg(SEL_IIR_PENDING_N):='0'; --set int pending
+ end if;
+ end procedure set_uart_rx_int;
+
+ procedure clr_uart_rx_int(variable uart : inout uart_registers) is
+ begin
+ if uart.iir.reg(SEL_IIR_TYPE)=VAL_IIR_TYPE_RXDATA and uart.iir.reg(SEL_IIR_PENDING_N)='0' then --suitable int
+ uart.iir.reg(SEL_IIR_PENDING_N):='1'; --clear int pending
+ end if;
+ end procedure clr_uart_rx_int;
+
+
+ procedure set_uart_tx_int(variable uart : inout uart_registers) is
+ begin
+ if uart.ier.reg(SEL_IER_TXEMPY_INT)='1' then --int enabled
+ uart.iir.reg(SEL_IIR_TYPE):=VAL_IIR_TYPE_TXEMPTY;
+ uart.iir.reg(SEL_IIR_PENDING_N):='0'; --set int pending
+ end if;
+ end procedure set_uart_tx_int;
+
+ procedure clr_uart_tx_int(variable uart : inout uart_registers) is
+ begin
+ if uart.iir.reg(SEL_IIR_TYPE)=VAL_IIR_TYPE_TXEMPTY and uart.iir.reg(SEL_IIR_PENDING_N)='0' then --suitable int
+ uart.iir.reg(SEL_IIR_PENDING_N):='1'; --clear int pending
+ end if;
+ end procedure clr_uart_tx_int;
+
+end package body serial_usb_package;
artec_dongle_ii_fpga/trunk/src/serial_usb/serial_usb_package.vhd
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: artec_dongle_ii_fpga/trunk/src/serial_usb/serial_usb.vhd
===================================================================
--- artec_dongle_ii_fpga/trunk/src/serial_usb/serial_usb.vhd (nonexistent)
+++ artec_dongle_ii_fpga/trunk/src/serial_usb/serial_usb.vhd (revision 9)
@@ -0,0 +1,249 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+use work.serial_usb_package.all;
+use work.dongle_arch.all;
+
+
+entity serial_usb is
+ port(
+ clock : in std_logic;
+ reset_n : in std_logic;
+ --VCI Port
+ vci_in : in vci_slave_in;
+ vci_out : out vci_slave_out;
+ --FTDI fifo interface
+ uart_ena : in usbser_ctrl;
+ fifo_out : out usb_out;
+ fifo_in : in usb_in
+ );
+end entity serial_usb;
+
+architecture rtl of serial_usb is
+
+ type reg_type is
+ record
+ uart : uart_registers;
+ fifo : usb_out;
+ fifo_sync: usb_in;
+ vci : vci_slave_out;
+ pc_loop : boolean;
+ vci_write_pending : boolean;
+ vci_read_pending : boolean;
+ tx_timer : std_logic_vector(2 downto 0);
+ rx_timer : std_logic_vector(2 downto 0);
+ ftdi_precharge : std_logic_vector(2 downto 0); --time between cycles
+ end record;
+
+ signal reg, reg_in : reg_type;
+
+begin
+
+ -- Design pattern process 1 Implementation
+ comb : process (vci_in,uart_ena,reg)
+ variable reg_v : reg_type;
+ begin
+ -- Design pattern
+ reg_v:=reg; --pre set default var state
+
+
+ --
+ --Debug code send repeating "0123456789" to UART
+ --
+-- if reg_v.uart.lsr.reg(SEL_LSR_EMPTY_TXH)='1' then
+-- reg_v.uart.lsr.reg(SEL_LSR_EMPTY_TXH):='0'; --set TX filled
+-- reg_v.uart.txhold.reg(3 downto 0):= reg_v.uart.txhold.reg(3 downto 0)+1;
+-- if reg_v.uart.txhold.reg(3 downto 0)=x"A" then
+-- reg_v.uart.txhold.reg(3 downto 0):=x"0";
+-- end if;
+-- reg_v.uart.txhold.reg(7 downto 4):=x"3";
+-- end if;
+
+ ------------------------------------
+ --- ---
+ ------------------------------------
+
+
+ --reduce precharge counter always
+ if reg_v.ftdi_precharge>"000" then
+ reg_v.ftdi_precharge:=reg_v.ftdi_precharge - 1;
+ end if;
+
+ --VCI write access request
+ if vci_in.lpc_val='1' and vci_in.lpc_wr='1' and reg_v.vci.lpc_ack='0' then
+ reg_v.vci_write_pending:=true;
+ end if;
+
+ --VCI read access request
+ if vci_in.lpc_val='1' and vci_in.lpc_wr='0' and reg_v.vci.lpc_ack='0' then
+ reg_v.vci_read_pending:=true;
+ end if;
+
+ --Writable conf registers
+ if reg_v.vci_write_pending then --write decode
+ case vci_in.lpc_addr(2 downto 0) is
+ when "000" =>
+ --select DLAB or not
+ if reg_v.uart.lcr.reg(SEL_LCR_DLAB)='0' then --Line Control Register (LCR) SEL_LCR_DLAB
+ reg_v.uart.txhold.reg:=vci_in.lpc_data_o; --Transmitter Holding Buffer
+ clr_uart_tx_int(reg_v.uart); --clear tx on tx buff write
+ if reg_v.uart.mcr.reg(SEL_MCR_LOOP)='0' then --loop not endabled
+ reg_v.uart.lsr.reg(SEL_LSR_EMPTY_TXH):='0'; -- TX not empty
+ reg_v.uart.lsr.reg(SEL_LSR_EMPTY_DH):='0'; -- TX not empty
+ else --do local loop
+ reg_v.uart.rxbuff.reg:=reg_v.uart.txhold.reg;
+ reg_v.uart.lsr.reg(SEL_LSR_DATARDY):='1'; --set data ready in register
+ set_uart_rx_int(reg_v.uart);
+ end if;
+ else
+ reg_v.uart.div_low.reg:=vci_in.lpc_data_o; --Divisor Latch Low Byte
+ end if;
+ when "001" =>
+ --select DLAB or not
+ if reg_v.uart.lcr.reg(SEL_LCR_DLAB)='0' then --Line Control Register (LCR) SEL_LCR_DLAB
+ reg_v.uart.ier.reg:=vci_in.lpc_data_o; --Interrupt Enable Register
+ else
+ reg_v.uart.div_high.reg:=vci_in.lpc_data_o; --Divisor Latch High Byte
+ end if;
+ when "011" => -- +3
+ reg_v.uart.lcr.reg:=vci_in.lpc_data_o; --Line Control Register (don't care except DLA bit)
+ when "100" => -- +4
+ reg_v.uart.mcr.reg:=vci_in.lpc_data_o; --Modem Control Register (don't care except loopback)
+ reg_v.uart.mcr.reg(SEL_MCR_FLWCTRL):='0'; --this is not supported so auto clear
+ when "111" => -- +7
+ reg_v.uart.scr.reg:=vci_in.lpc_data_o;
+ when others =>
+ null;
+ end case;
+ --we must ack the write always
+ reg_v.vci_write_pending:= false;
+ reg_v.vci.lpc_ack:='1'; --ack all writes to non writable addresses for VCI to work
+ end if;
+
+ --Readable conf registers
+ if reg_v.vci_read_pending then --write decode
+ case vci_in.lpc_addr(2 downto 0) is
+ when "000" =>
+ --select DLAB or not
+ if reg_v.uart.lcr.reg(SEL_LCR_DLAB)='0' then --Line Control Register (LCR) SEL_LCR_DLAB
+ reg_v.vci.lpc_data_i:=reg_v.uart.rxbuff.reg; --RX read data
+ reg_v.uart.lsr.reg(SEL_LSR_DATARDY):='0'; --data has been read
+ clr_uart_rx_int(reg_v.uart);
+ else
+ reg_v.vci.lpc_data_i:=reg_v.uart.div_low.reg;
+ end if;
+ when "001" =>
+ if reg_v.uart.lcr.reg(SEL_LCR_DLAB)='0' then --Interrupt Enable Register (IER) SEL_LCR_DLAB
+ reg_v.vci.lpc_data_i:=reg_v.uart.ier.reg;
+ else --Divisor Latch High Byte
+ reg_v.vci.lpc_data_i:=reg_v.uart.div_high.reg;
+ end if;
+ when "010" =>
+ reg_v.vci.lpc_data_i:=reg_v.uart.iir.reg; -- Interrupt Identification Register(IIR)
+ clr_uart_tx_int(reg_v.uart); --clear tx on iir read
+ when "011" =>
+ reg_v.vci.lpc_data_i:=reg_v.uart.lcr.reg;
+ when "100" =>
+ reg_v.vci.lpc_data_i:=reg_v.uart.mcr.reg;
+ when "101" =>
+ reg_v.vci.lpc_data_i:=reg_v.uart.lsr.reg;
+ when "110" =>
+ reg_v.vci.lpc_data_i:=reg_v.uart.msr.reg;
+ when "111" =>
+ reg_v.vci.lpc_data_i:=reg_v.uart.scr.reg;
+ when others =>
+ reg_v.vci.lpc_data_i:=(others=>'0'); -- return 0
+ end case;
+ --we must ack the read always
+ reg_v.vci_read_pending:= false;
+ reg_v.vci.lpc_ack:='1'; --ack all reads to non readable addresses for VCI to work
+ end if;
+
+ --UART Register state change handling
+ --TX haldler
+ if reg_v.fifo.rx_oe_n='1' and reg_v.ftdi_precharge="000" and reg_v.fifo_sync.tx_empty_n='0' and reg_v.tx_timer="000" and reg_v.uart.lsr.reg(SEL_LSR_EMPTY_TXH)='0' then --No ongoing read and can and has something to TX
+ reg_v.fifo.txdata:=reg_v.uart.txhold.reg;
+ reg_v.fifo.tx_wr:='1';
+ reg_v.tx_timer:="011"; --FDTI fifo timing 40 ns needed for write pulse high
+ end if;
+ if reg_v.tx_timer>"000" then -- TX cycle timer
+ reg_v.tx_timer:=reg_v.tx_timer-1;
+ if reg_v.tx_timer="000" then
+ reg_v.fifo.tx_wr:='0'; -- write happens on falling edge '''\,,,
+ reg_v.ftdi_precharge:="011"; --start cycle cap
+ reg_v.uart.lsr.reg(SEL_LSR_EMPTY_TXH):='1'; -- all sent
+ reg_v.uart.lsr.reg(SEL_LSR_EMPTY_DH):='1'; -- ready for new data
+ set_uart_tx_int(reg_v.uart);
+ end if;
+ end if;
+ --RX Handler
+
+
+ if (not reg_v.pc_loop) or reg_v.uart.lsr.reg(SEL_LSR_EMPTY_TXH)='1' then
+ if reg_v.fifo.tx_wr='0'and reg_v.ftdi_precharge="000" and reg_v.fifo_sync.rx_full_n='0' and reg_v.rx_timer="000" and reg_v.uart.lsr.reg(SEL_LSR_DATARDY)='0' then -- no ongoing TX and data in FTDI fifo and read buffer has been read
+ reg_v.fifo.rx_oe_n:='0'; -- output enable
+ reg_v.rx_timer:="100";
+ end if;
+ if reg_v.rx_timer>"000" then --RX cycle timer
+ reg_v.rx_timer:=reg_v.rx_timer-1;
+ if reg_v.rx_timer="000" then
+ reg_v.fifo.rx_oe_n:='1'; -- read happens on rising front ,,,,/'''' of oe_n
+ reg_v.ftdi_precharge:="101"; --start cycle cap
+ reg_v.uart.rxbuff.reg:=reg_v.fifo_sync.rxdata;
+ if reg_v.pc_loop then --pc test loop
+ reg_v.uart.txhold.reg:=reg_v.fifo_sync.rxdata;
+ reg_v.uart.lsr.reg(SEL_LSR_EMPTY_TXH):='0'; --do transmit
+ else
+ reg_v.uart.lsr.reg(SEL_LSR_DATARDY):='1'; --set data ready in register
+ set_uart_rx_int(reg_v.uart);
+ end if;
+ end if;
+ end if;
+ end if;
+
+ --UART Interrupt
+ if reg_v.uart.iir.reg(SEL_IIR_PENDING_N)='0' then
+ reg_v.vci.lpc_irq:='1'; --set up int signal
+ else
+ reg_v.vci.lpc_irq:='0';
+ end if;
+ --End UART
+
+ --VCI request end, clear ack when val drops
+ if vci_in.lpc_val='0' and reg_v.vci.lpc_ack='1' then
+ reg_v.vci.lpc_ack:='0';
+ end if;
+
+
+ -- Design pattern
+ -- drive register input signals
+ reg_in<=reg_v;
+ -- drive module outputs signals
+ --port_comb_out<= reg_v.port_comb; --combinatorial output
+ --port_reg_out<= reg.port_reg; --registered output
+ vci_out<=reg.vci;
+ fifo_out<= reg.fifo;
+ end process;
+
+ -- Pattern process 2, Registers
+ regs : process (clock,reset_n)
+ begin
+ if reset_n='0' then
+ reg.pc_loop<=false;
+ reg.rx_timer<=(others=>'0');
+ reg.tx_timer<=(others=>'0');
+ reg.ftdi_precharge<=(others=>'0');
+ reg.vci_read_pending<=false;
+ reg.vci_write_pending<=false;
+ uart_reset(reg.uart);
+ fifo_reset(reg.fifo);
+ vci_slave_reset(reg.vci);
+ elsif rising_edge(clock) then
+ reg<=reg_in;
+ reg.fifo_sync<=fifo_in;
+ end if;
+ end process;
+
+
+end rtl;
artec_dongle_ii_fpga/trunk/src/serial_usb/serial_usb.vhd
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: artec_dongle_ii_fpga/trunk/src/postcode_ser/fifo_inst.vhd
===================================================================
--- artec_dongle_ii_fpga/trunk/src/postcode_ser/fifo_inst.vhd (revision 8)
+++ artec_dongle_ii_fpga/trunk/src/postcode_ser/fifo_inst.vhd (revision 9)
@@ -1,12 +1,12 @@
-fifo_inst : fifo PORT MAP (
- aclr => aclr_sig,
- clock => clock_sig,
- data => data_sig,
- rdreq => rdreq_sig,
- wrreq => wrreq_sig,
- almost_full => almost_full_sig,
- empty => empty_sig,
- full => full_sig,
- q => q_sig,
- usedw => usedw_sig
- );
+fifo_inst : fifo PORT MAP (
+ aclr => aclr_sig,
+ clock => clock_sig,
+ data => data_sig,
+ rdreq => rdreq_sig,
+ wrreq => wrreq_sig,
+ almost_full => almost_full_sig,
+ empty => empty_sig,
+ full => full_sig,
+ q => q_sig,
+ usedw => usedw_sig
+ );
Index: artec_dongle_ii_fpga/trunk/src/postcode_ser/fifo.cmp
===================================================================
--- artec_dongle_ii_fpga/trunk/src/postcode_ser/fifo.cmp (revision 8)
+++ artec_dongle_ii_fpga/trunk/src/postcode_ser/fifo.cmp (revision 9)
@@ -1,30 +1,30 @@
---Copyright (C) 1991-2006 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions
---and other software and tools, and its AMPP partner logic
---functions, and any output files any of the foregoing
---(including device programming or simulation files), and any
---associated documentation or information are expressly subject
---to the terms and conditions of the Altera Program License
---Subscription Agreement, Altera MegaCore Function License
---Agreement, or other applicable license agreement, including,
---without limitation, that your use is for the sole purpose of
---programming logic devices manufactured by Altera and sold by
---Altera or its authorized distributors. Please refer to the
---applicable agreement for further details.
-
-
-component fifo
- PORT
- (
- aclr : IN STD_LOGIC ;
- clock : IN STD_LOGIC ;
- data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
- rdreq : IN STD_LOGIC ;
- wrreq : IN STD_LOGIC ;
- almost_full : OUT STD_LOGIC ;
- empty : OUT STD_LOGIC ;
- full : OUT STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
- usedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0)
- );
-end component;
+--Copyright (C) 1991-2006 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+component fifo
+ PORT
+ (
+ aclr : IN STD_LOGIC ;
+ clock : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ rdreq : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ almost_full : OUT STD_LOGIC ;
+ empty : OUT STD_LOGIC ;
+ full : OUT STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ usedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0)
+ );
+end component;
Index: artec_dongle_ii_fpga/trunk/src/postcode_ser/fifo.vhd
===================================================================
--- artec_dongle_ii_fpga/trunk/src/postcode_ser/fifo.vhd (revision 8)
+++ artec_dongle_ii_fpga/trunk/src/postcode_ser/fifo.vhd (revision 9)
@@ -1,201 +1,201 @@
--- megafunction wizard: %LPM_FIFO+%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: scfifo
-
--- ============================================================
--- File Name: fifo.vhd
--- Megafunction Name(s):
--- scfifo
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 6.0 Build 202 06/20/2006 SP 1 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2006 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions
---and other software and tools, and its AMPP partner logic
---functions, and any output files any of the foregoing
---(including device programming or simulation files), and any
---associated documentation or information are expressly subject
---to the terms and conditions of the Altera Program License
---Subscription Agreement, Altera MegaCore Function License
---Agreement, or other applicable license agreement, including,
---without limitation, that your use is for the sole purpose of
---programming logic devices manufactured by Altera and sold by
---Altera or its authorized distributors. Please refer to the
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY fifo IS
- PORT
- (
- aclr : IN STD_LOGIC ;
- clock : IN STD_LOGIC ;
- data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
- rdreq : IN STD_LOGIC ;
- wrreq : IN STD_LOGIC ;
- almost_full : OUT STD_LOGIC ;
- empty : OUT STD_LOGIC ;
- full : OUT STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
- usedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0)
- );
-END fifo;
-
-
-ARCHITECTURE SYN OF fifo IS
-
- SIGNAL sub_wire0 : STD_LOGIC ;
- SIGNAL sub_wire1 : STD_LOGIC_VECTOR (12 DOWNTO 0);
- SIGNAL sub_wire2 : STD_LOGIC ;
- SIGNAL sub_wire3 : STD_LOGIC_VECTOR (7 DOWNTO 0);
- SIGNAL sub_wire4 : STD_LOGIC ;
-
-
-
- COMPONENT scfifo
- GENERIC (
- add_ram_output_register : STRING;
- almost_full_value : NATURAL;
- intended_device_family : STRING;
- lpm_numwords : NATURAL;
- lpm_showahead : STRING;
- lpm_type : STRING;
- lpm_width : NATURAL;
- lpm_widthu : NATURAL;
- overflow_checking : STRING;
- underflow_checking : STRING;
- use_eab : STRING
- );
- PORT (
- almost_full : OUT STD_LOGIC ;
- usedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
- rdreq : IN STD_LOGIC ;
- empty : OUT STD_LOGIC ;
- aclr : IN STD_LOGIC ;
- clock : IN STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
- wrreq : IN STD_LOGIC ;
- data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
- full : OUT STD_LOGIC
- );
- END COMPONENT;
-
-BEGIN
- almost_full <= sub_wire0;
- usedw <= sub_wire1(12 DOWNTO 0);
- empty <= sub_wire2;
- q <= sub_wire3(7 DOWNTO 0);
- full <= sub_wire4;
-
- scfifo_component : scfifo
- GENERIC MAP (
- add_ram_output_register => "ON",
- almost_full_value => 8000,
- intended_device_family => "Cyclone",
- lpm_numwords => 8192,
- lpm_showahead => "OFF",
- lpm_type => "scfifo",
- lpm_width => 8,
- lpm_widthu => 13,
- overflow_checking => "ON",
- underflow_checking => "ON",
- use_eab => "ON"
- )
- PORT MAP (
- rdreq => rdreq,
- aclr => aclr,
- clock => clock,
- wrreq => wrreq,
- data => data,
- almost_full => sub_wire0,
- usedw => sub_wire1,
- empty => sub_wire2,
- q => sub_wire3,
- full => sub_wire4
- );
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
--- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
--- Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
--- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "8000"
--- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
--- Retrieval info: PRIVATE: Clock NUMERIC "0"
--- Retrieval info: PRIVATE: Depth NUMERIC "8192"
--- Retrieval info: PRIVATE: Empty NUMERIC "1"
--- Retrieval info: PRIVATE: Full NUMERIC "1"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
--- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
--- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
--- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
--- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
--- Retrieval info: PRIVATE: Optimize NUMERIC "1"
--- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
--- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
--- Retrieval info: PRIVATE: UsedW NUMERIC "1"
--- Retrieval info: PRIVATE: Width NUMERIC "8"
--- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
--- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
--- Retrieval info: PRIVATE: rsFull NUMERIC "1"
--- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
--- Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
--- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
--- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
--- Retrieval info: PRIVATE: wsFull NUMERIC "1"
--- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
--- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
--- Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "8000"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
--- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8192"
--- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
--- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
--- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "13"
--- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
--- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
--- Retrieval info: CONSTANT: USE_EAB STRING "ON"
--- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
--- Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
--- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
--- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
--- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
--- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
--- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
--- Retrieval info: USED_PORT: usedw 0 0 13 0 OUTPUT NODEFVAL usedw[12..0]
--- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
--- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
--- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
--- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
--- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
--- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
--- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
--- Retrieval info: CONNECT: usedw 0 0 13 0 @usedw 0 0 13 0
--- Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
--- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.bsf TRUE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_inst.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_waveforms.html TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wave*.jpg FALSE
+-- megafunction wizard: %LPM_FIFO+%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: scfifo
+
+-- ============================================================
+-- File Name: fifo.vhd
+-- Megafunction Name(s):
+-- scfifo
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 6.0 Build 202 06/20/2006 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2006 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY fifo IS
+ PORT
+ (
+ aclr : IN STD_LOGIC ;
+ clock : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ rdreq : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ almost_full : OUT STD_LOGIC ;
+ empty : OUT STD_LOGIC ;
+ full : OUT STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ usedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0)
+ );
+END fifo;
+
+
+ARCHITECTURE SYN OF fifo IS
+
+ SIGNAL sub_wire0 : STD_LOGIC ;
+ SIGNAL sub_wire1 : STD_LOGIC_VECTOR (12 DOWNTO 0);
+ SIGNAL sub_wire2 : STD_LOGIC ;
+ SIGNAL sub_wire3 : STD_LOGIC_VECTOR (7 DOWNTO 0);
+ SIGNAL sub_wire4 : STD_LOGIC ;
+
+
+
+ COMPONENT scfifo
+ GENERIC (
+ add_ram_output_register : STRING;
+ almost_full_value : NATURAL;
+ intended_device_family : STRING;
+ lpm_numwords : NATURAL;
+ lpm_showahead : STRING;
+ lpm_type : STRING;
+ lpm_width : NATURAL;
+ lpm_widthu : NATURAL;
+ overflow_checking : STRING;
+ underflow_checking : STRING;
+ use_eab : STRING
+ );
+ PORT (
+ almost_full : OUT STD_LOGIC ;
+ usedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
+ rdreq : IN STD_LOGIC ;
+ empty : OUT STD_LOGIC ;
+ aclr : IN STD_LOGIC ;
+ clock : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ wrreq : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ full : OUT STD_LOGIC
+ );
+ END COMPONENT;
+
+BEGIN
+ almost_full <= sub_wire0;
+ usedw <= sub_wire1(12 DOWNTO 0);
+ empty <= sub_wire2;
+ q <= sub_wire3(7 DOWNTO 0);
+ full <= sub_wire4;
+
+ scfifo_component : scfifo
+ GENERIC MAP (
+ add_ram_output_register => "ON",
+ almost_full_value => 8000,
+ intended_device_family => "Cyclone",
+ lpm_numwords => 8192,
+ lpm_showahead => "OFF",
+ lpm_type => "scfifo",
+ lpm_width => 8,
+ lpm_widthu => 13,
+ overflow_checking => "ON",
+ underflow_checking => "ON",
+ use_eab => "ON"
+ )
+ PORT MAP (
+ rdreq => rdreq,
+ aclr => aclr,
+ clock => clock,
+ wrreq => wrreq,
+ data => data,
+ almost_full => sub_wire0,
+ usedw => sub_wire1,
+ empty => sub_wire2,
+ q => sub_wire3,
+ full => sub_wire4
+ );
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
+-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "8000"
+-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "0"
+-- Retrieval info: PRIVATE: Depth NUMERIC "8192"
+-- Retrieval info: PRIVATE: Empty NUMERIC "1"
+-- Retrieval info: PRIVATE: Full NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: Width NUMERIC "8"
+-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+-- Retrieval info: PRIVATE: rsFull NUMERIC "1"
+-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
+-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
+-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
+-- Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "8000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8192"
+-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "13"
+-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
+-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
+-- Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
+-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
+-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
+-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+-- Retrieval info: USED_PORT: usedw 0 0 13 0 OUTPUT NODEFVAL usedw[12..0]
+-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
+-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
+-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
+-- Retrieval info: CONNECT: usedw 0 0 13 0 @usedw 0 0 13 0
+-- Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
+-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_inst.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wave*.jpg FALSE
Index: artec_dongle_ii_fpga/trunk/src/postcode_ser/pc_serializer.vhd
===================================================================
--- artec_dongle_ii_fpga/trunk/src/postcode_ser/pc_serializer.vhd (revision 8)
+++ artec_dongle_ii_fpga/trunk/src/postcode_ser/pc_serializer.vhd (revision 9)
@@ -1,327 +1,309 @@
-------------------------------------------------------------------
--- Universal dongle board source code
---
--- Copyright (C) 2006 Artec Design
---
--- This source code is free hardware; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
---
--- This source code is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--- Lesser General Public License for more details.
---
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
---
---
--- The complete text of the GNU Lesser General Public License can be found in
--- the file 'lesser.txt'.
-
-
-
-----------------------------------------------------------------------------------
--- Company: ArtecDesign
--- Engineer: Jüri Toomessoo
---
--- Create Date: 12:57:23 28/02/2008
--- Design Name: Postcode serial pipe Hardware
--- Module Name: pc_serializer - rtl
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity pc_serializer is
- Port ( --system signals
- sys_clk : in STD_LOGIC;
- resetn : in STD_LOGIC;
- --postcode data port
- dbg_data : in STD_LOGIC_VECTOR (7 downto 0);
- dbg_wr : in STD_LOGIC; --write not read
- dbg_full : out STD_LOGIC; --write not read
- dbg_almost_full : out STD_LOGIC;
- dbg_usedw : out STD_LOGIC_VECTOR (12 DOWNTO 0);
- --debug USB port
- dbg_usb_mode_en: in std_logic; -- enable this debug mode
- dbg_usb_wr : out std_logic; -- write performed on edge \ of signal
- dbg_usb_txe_n : in std_logic; -- tx fifo not full (redy for new data if low)
- dbg_usb_bd : inout std_logic_vector(7 downto 0) --bus data
-);
-
-end pc_serializer;
-
-architecture rtl of pc_serializer is
-
- component fifo
- PORT
- (
- aclr : IN STD_LOGIC ;
- clock : IN STD_LOGIC ;
- data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
- rdreq : IN STD_LOGIC ;
- wrreq : IN STD_LOGIC ;
- almost_full : OUT STD_LOGIC ;
- empty : OUT STD_LOGIC ;
- full : OUT STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
- usedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0)
-
- );
- end component;
-
-
-
- --type state is (RESETs, HEXMARKs,MSNIBBLEs,LSNIBBLEs,LINEFDs,CRs,START_WRITEs,END_WRITEs,WAITs); -- simple ASCII converter to USB fifo
- signal CS : std_logic_vector(8 downto 0);--state;
- signal RETS : std_logic_vector(8 downto 0); --state;
- signal next_char : std_logic_vector(7 downto 0); --bus data
- signal ascii_char : std_logic_vector(7 downto 0); --bus data
- signal in_nibble : std_logic_vector(3 downto 0); --bus data
- signal usb_send_char : std_logic_vector(7 downto 0); --bus data
-
- signal count : std_logic_vector(3 downto 0); --internal counter
- signal dly_count : std_logic_vector(15 downto 0); --internal counter
- signal dbg_wr_pulse : std_logic; --active reset
- signal dbg_wrd : std_logic; --active reset
- signal dbg_wr_len : std_logic; --active reset
- signal usb_send : std_logic; --active reset
-
-
- signal rdreq_sig : std_logic; --active reset
- signal empty_sig : std_logic; --active reset
- signal full_sig : std_logic; --active reset
- signal almost_full : std_logic; --active reset
-
- signal q_sig : std_logic_vector(7 downto 0); --bus data
-
- signal reset : std_logic; --active reset
- signal half_clk : std_logic; --active reset
-
-
- --RESETs, HEXMARKs,MSNIBBLEs,LSNIBBLEs,LINEFDs,CRs,START_WRITEs,END_WRITEs,WAITs
- constant RESETs: std_logic_vector(8 downto 0) := "000000001"; -- char /n
- constant HEXMARKs: std_logic_vector(8 downto 0) := "000000010"; -- char /n
- constant MSNIBBLEs: std_logic_vector(8 downto 0) := "000000100"; -- char /n
- constant LSNIBBLEs: std_logic_vector(8 downto 0) := "000001000"; -- char /n
- constant LINEFDs: std_logic_vector(8 downto 0) := "000010000"; -- char /n
- constant CRs: std_logic_vector(8 downto 0) := "000100000"; -- char /n
- constant START_WRITEs: std_logic_vector(8 downto 0):= "001000000"; -- char /n
- constant WAITs: std_logic_vector(8 downto 0) := "010000000"; -- char /n
- constant END_WRITEs: std_logic_vector(8 downto 0) := "100000000"; -- char /n
-
-
- constant CHAR_LF : std_logic_vector(7 downto 0):= x"0A"; -- char /n
- constant CHAR_CR : std_logic_vector(7 downto 0):= x"0D"; -- char /n
- constant CHAR_SP : std_logic_vector(7 downto 0):= x"20"; -- space
- constant CHAR_ux : std_logic_vector(7 downto 0):= x"58"; -- fifo full hex marker --upper case x
- constant CHAR_x : std_logic_vector(7 downto 0):= x"78"; -- regular hex marker
- constant CHAR_0 : std_logic_vector(7 downto 0):= x"30";
- constant CHAR_1 : std_logic_vector(7 downto 0):= x"31";
- constant CHAR_2 : std_logic_vector(7 downto 0):= x"32";
- constant CHAR_3 : std_logic_vector(7 downto 0):= x"33";
- constant CHAR_4 : std_logic_vector(7 downto 0):= x"34";
- constant CHAR_5 : std_logic_vector(7 downto 0):= x"35";
- constant CHAR_6 : std_logic_vector(7 downto 0):= x"36";
- constant CHAR_7 : std_logic_vector(7 downto 0):= x"37";
- constant CHAR_8 : std_logic_vector(7 downto 0):= x"38";
- constant CHAR_9 : std_logic_vector(7 downto 0):= x"39";
- constant CHAR_a : std_logic_vector(7 downto 0):= x"41";
- constant CHAR_b : std_logic_vector(7 downto 0):= x"42";
- constant CHAR_c : std_logic_vector(7 downto 0):= x"43";
- constant CHAR_d : std_logic_vector(7 downto 0):= x"44";
- constant CHAR_e : std_logic_vector(7 downto 0):= x"45";
- constant CHAR_f : std_logic_vector(7 downto 0):= x"46";
-
-
-
-begin
-
- ascii_char <=CHAR_0 when in_nibble = x"0" else
- CHAR_1 when in_nibble = x"1" else
- CHAR_2 when in_nibble = x"2" else
- CHAR_3 when in_nibble = x"3" else
- CHAR_4 when in_nibble = x"4" else
- CHAR_5 when in_nibble = x"5" else
- CHAR_6 when in_nibble = x"6" else
- CHAR_7 when in_nibble = x"7" else
- CHAR_8 when in_nibble = x"8" else
- CHAR_9 when in_nibble = x"9" else
- CHAR_a when in_nibble = x"a" else
- CHAR_b when in_nibble = x"b" else
- CHAR_c when in_nibble = x"c" else
- CHAR_d when in_nibble = x"d" else
- CHAR_e when in_nibble = x"e" else
- CHAR_f when in_nibble = x"f";
-
-
-
- dbg_usb_bd <= usb_send_char when dbg_usb_mode_en = '1' else
- (others=>'Z');
-
- dbg_usb_wr <= usb_send when dbg_usb_mode_en = '1' else
- 'Z';
-
- SER_SM: process (sys_clk,resetn)
- begin -- process
-
- if sys_clk'event and sys_clk = '1' then -- rising clock edge
- if resetn='0' then --active low reset
- CS<= RESETs;
- in_nibble <= (others=>'0');
- usb_send_char <= (others=>'0');
- dly_count<= (others=>'0');
- usb_send <='0';
- RETS <= RESETs;
- rdreq_sig <='0';
- count<= (others=>'1');
- else
- case CS is
- when RESETs => ----------------------------------------------------------
-
- if empty_sig ='0' and dbg_usb_txe_n='0' and dbg_usb_mode_en='1' then --is, can and may send
- rdreq_sig <='1';
- count <= count + 1;
- RETS <= HEXMARKs;
- dly_count <= x"000F";
- CS <= END_WRITEs; --cheat as 1 extra cycle is needed for fifo to output data
- else
- usb_send <='0';
- rdreq_sig <='0';
- CS <= RESETs; --cheat as 1 extra cycle is needed for fifo to output data
- end if;
- when HEXMARKs => ----------------------------------------------------------
- rdreq_sig <='0'; --data will be ready on output 'till next read request
- --if almost_full='0' then
- usb_send_char <= CHAR_x; --show fifo full status to user by hex x case
- --else
- -- usb_send_char <= CHAR_ux; --show fifo full status to user by hex x case
- --end if;
- in_nibble <= q_sig(7 downto 4); --take fifo output and put to decoder
- RETS <= MSNIBBLEs;
- CS <= START_WRITEs;
- when MSNIBBLEs => ----------------------------------------------------------
- usb_send_char <= ascii_char; --put MS nibble to output
- in_nibble <= q_sig(3 downto 0); --take fifo output and put to decoder
- RETS <= LSNIBBLEs;
- CS <= START_WRITEs;
- when LSNIBBLEs => ----------------------------------------------------------
- usb_send_char <= ascii_char; --put MS nibble to output
- if count = x"f" then
- RETS <= CRs;
- else
- RETS <= LINEFDs;
- end if;
- CS <= START_WRITEs;
- when CRs => ----------------------------------------------------------
- --if count = x"f" then
- usb_send_char <= CHAR_CR; --put line feed
- --else
- -- usb_send_char <= CHAR_SP; --put space
- --end if;
- RETS <= LINEFDs;
- CS <= START_WRITEs;
- when LINEFDs => ----------------------------------------------------------
- if count = x"f" then
- usb_send_char <= CHAR_LF; --put line feed
- else
- usb_send_char <= CHAR_SP; --put space
- end if;
- RETS <= RESETs;
- CS <= START_WRITEs;
-
- when START_WRITEs => ----------------------------------------------------------
- if dly_count /= x"0004" then
- if dbg_usb_txe_n='0' then
- usb_send <='1';
- dly_count <= dly_count + 1;
- else
- usb_send <='0'; --remove send signal when txe is falsely asserted
- end if;
- else
- usb_send <='0';
- CS <= WAITs;
- end if;
- when WAITs => ----------------------------------------------------------
- usb_send <='0';
- CS <= END_WRITEs;
- when END_WRITEs => ----------------------------------------------------------
- rdreq_sig <='0'; --used as intermeadiate cheat state when exiting resets
- if dly_count /= x"000F" then
- if dbg_usb_txe_n='0' then
- dly_count <= dly_count + 1;
- end if;
- else
- dly_count <= (others=>'0');
- CS <= RETS;
- end if;
- when others => null;
- end case;
- end if;
- end if;
- end process SER_SM;
-
-
- SYNCER: process (sys_clk,resetn) --make slower clock and 2 cycle write pulse
- begin -- process
- if sys_clk'event and sys_clk = '1' then -- rising clock edge
- if resetn='0' then --active low reset
- dbg_wr_pulse <='0';
- dbg_wr_len <='0';
- dbg_wrd <='0';
- else
- dbg_wrd <= dbg_wr;
- if dbg_wrd='0' and dbg_wr='1' then -- rising front on fifo write
- dbg_wr_pulse <='1';
- else
- dbg_wr_pulse <='0';
- end if;
- end if;
- end if;
- end process SYNCER;
-
-
- reset <= not resetn;
- dbg_full <= full_sig;
- dbg_almost_full<= almost_full;
- fifo_inst : fifo PORT MAP (
- --system signals
- aclr => reset,
- clock => sys_clk, --make serial back end work 2 times slower as FDTI chip max timing length is 80 ns
- -- push interface
- data => dbg_data,
- wrreq => dbg_wr_pulse,
- almost_full => almost_full,
- usedw => dbg_usedw,
- --pop interface
- rdreq => rdreq_sig,
- empty => empty_sig,
- full => full_sig,
- q => q_sig
- );
-
-
-
-
-end rtl;
-
+------------------------------------------------------------------
+-- Universal dongle board source code
+--
+-- Copyright (C) 2006 Artec Design
+--
+-- This source code is free hardware; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This source code is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+--
+--
+-- The complete text of the GNU Lesser General Public License can be found in
+-- the file 'lesser.txt'.
+
+
+----------------------------------------------------------------------------------
+-- Company: ArtecDesign
+-- Engineer: Jüri Toomessoo
+--
+-- Create Date: 12:57:23 28/02/2008
+-- Design Name: Postcode serial pipe Hardware
+-- Module Name: pc_serializer - rtl
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity pc_serializer is
+ Port( --system signals
+ sys_clk : in STD_LOGIC;
+ resetn : in STD_LOGIC;
+ --postcode data port
+ dbg_data : in STD_LOGIC_VECTOR(7 downto 0);
+ dbg_wr : in STD_LOGIC; --write not read
+ dbg_full : out STD_LOGIC; --write not read
+ dbg_almost_full : out STD_LOGIC;
+ dbg_usedw : out STD_LOGIC_VECTOR(12 DOWNTO 0);
+ --debug USB port
+ dbg_usb_mode_en : in std_logic; -- enable this debug mode
+ dbg_usb_wr : out std_logic; -- write performed on edge \ of signal
+ dbg_usb_txe_n : in std_logic; -- tx fifo not full (redy for new data if low)
+ dbg_usb_bd : out std_logic_vector(7 downto 0) --bus data
+ );
+
+end pc_serializer;
+
+architecture rtl of pc_serializer is
+ component fifo
+ PORT(
+ aclr : IN STD_LOGIC;
+ clock : IN STD_LOGIC;
+ data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ rdreq : IN STD_LOGIC;
+ wrreq : IN STD_LOGIC;
+ almost_full : OUT STD_LOGIC;
+ empty : OUT STD_LOGIC;
+ full : OUT STD_LOGIC;
+ q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ usedw : OUT STD_LOGIC_VECTOR(12 DOWNTO 0)
+ );
+ end component;
+
+ --type state is (RESETs, HEXMARKs,MSNIBBLEs,LSNIBBLEs,LINEFDs,CRs,START_WRITEs,END_WRITEs,WAITs); -- simple ASCII converter to USB fifo
+ signal CS : std_logic_vector(8 downto 0); --state;
+ signal RETS : std_logic_vector(8 downto 0); --state;
+ signal next_char : std_logic_vector(7 downto 0); --bus data
+ signal ascii_char : std_logic_vector(7 downto 0); --bus data
+ signal in_nibble : std_logic_vector(3 downto 0); --bus data
+ signal usb_send_char : std_logic_vector(7 downto 0); --bus data
+
+ signal count : std_logic_vector(3 downto 0); --internal counter
+ signal dly_count : std_logic_vector(15 downto 0); --internal counter
+ signal dbg_wr_pulse : std_logic; --active reset
+ signal dbg_wrd : std_logic; --active reset
+ --signal dbg_wr_len : std_logic; --active reset
+ signal usb_send : std_logic; --active reset
+
+
+ signal rdreq_sig : std_logic; --active reset
+ signal empty_sig : std_logic; --active reset
+ signal full_sig : std_logic; --active reset
+ signal almost_full : std_logic; --active reset
+
+ signal q_sig : std_logic_vector(7 downto 0); --bus data
+
+ signal reset : std_logic; --active reset
+ signal half_clk : std_logic; --active reset
+
+
+ --RESETs, HEXMARKs,MSNIBBLEs,LSNIBBLEs,LINEFDs,CRs,START_WRITEs,END_WRITEs,WAITs
+ constant RESETs : std_logic_vector(8 downto 0) := "000000001"; -- char /n
+ constant HEXMARKs : std_logic_vector(8 downto 0) := "000000010"; -- char /n
+ constant MSNIBBLEs : std_logic_vector(8 downto 0) := "000000100"; -- char /n
+ constant LSNIBBLEs : std_logic_vector(8 downto 0) := "000001000"; -- char /n
+ constant LINEFDs : std_logic_vector(8 downto 0) := "000010000"; -- char /n
+ constant CRs : std_logic_vector(8 downto 0) := "000100000"; -- char /n
+ constant START_WRITEs : std_logic_vector(8 downto 0) := "001000000"; -- char /n
+ constant WAITs : std_logic_vector(8 downto 0) := "010000000"; -- char /n
+ constant END_WRITEs : std_logic_vector(8 downto 0) := "100000000"; -- char /n
+
+
+ constant CHAR_LF : std_logic_vector(7 downto 0) := x"0A"; -- char /n
+ constant CHAR_CR : std_logic_vector(7 downto 0) := x"0D"; -- char /n
+ constant CHAR_SP : std_logic_vector(7 downto 0) := x"20"; -- space
+ constant CHAR_ux : std_logic_vector(7 downto 0) := x"58"; -- fifo full hex marker --upper case x
+ constant CHAR_x : std_logic_vector(7 downto 0) := x"78"; -- regular hex marker
+ constant CHAR_0 : std_logic_vector(7 downto 0) := x"30";
+ constant CHAR_1 : std_logic_vector(7 downto 0) := x"31";
+ constant CHAR_2 : std_logic_vector(7 downto 0) := x"32";
+ constant CHAR_3 : std_logic_vector(7 downto 0) := x"33";
+ constant CHAR_4 : std_logic_vector(7 downto 0) := x"34";
+ constant CHAR_5 : std_logic_vector(7 downto 0) := x"35";
+ constant CHAR_6 : std_logic_vector(7 downto 0) := x"36";
+ constant CHAR_7 : std_logic_vector(7 downto 0) := x"37";
+ constant CHAR_8 : std_logic_vector(7 downto 0) := x"38";
+ constant CHAR_9 : std_logic_vector(7 downto 0) := x"39";
+ constant CHAR_a : std_logic_vector(7 downto 0) := x"41";
+ constant CHAR_b : std_logic_vector(7 downto 0) := x"42";
+ constant CHAR_c : std_logic_vector(7 downto 0) := x"43";
+ constant CHAR_d : std_logic_vector(7 downto 0) := x"44";
+ constant CHAR_e : std_logic_vector(7 downto 0) := x"45";
+ constant CHAR_f : std_logic_vector(7 downto 0) := x"46";
+
+begin
+ ascii_char <= CHAR_0 when in_nibble = x"0" else
+ CHAR_1 when in_nibble = x"1" else
+ CHAR_2 when in_nibble = x"2" else
+ CHAR_3 when in_nibble = x"3" else
+ CHAR_4 when in_nibble = x"4" else
+ CHAR_5 when in_nibble = x"5" else
+ CHAR_6 when in_nibble = x"6" else
+ CHAR_7 when in_nibble = x"7" else
+ CHAR_8 when in_nibble = x"8" else
+ CHAR_9 when in_nibble = x"9" else
+ CHAR_a when in_nibble = x"a" else
+ CHAR_b when in_nibble = x"b" else
+ CHAR_c when in_nibble = x"c" else
+ CHAR_d when in_nibble = x"d" else
+ CHAR_e when in_nibble = x"e" else
+ CHAR_f when in_nibble = x"f";
+
+ dbg_usb_bd <= usb_send_char;
+
+ dbg_usb_wr <= usb_send;
+
+ SER_SM : process(sys_clk, resetn)
+ begin -- process
+
+ if sys_clk'event and sys_clk = '1' then -- rising clock edge
+ if resetn = '0' then --active low reset
+ CS <= RESETs;
+ in_nibble <=(others => '0');
+ usb_send_char <=(others => '0');
+ dly_count <=(others => '0');
+ usb_send <= '0';
+ RETS <= RESETs;
+ rdreq_sig <= '0';
+ count <=(others => '1');
+ else
+ case CS is
+ when RESETs => ----------------------------------------------------------
+
+ if empty_sig = '0' and dbg_usb_txe_n = '0' and dbg_usb_mode_en = '1' then --is, can and may send
+ rdreq_sig <= '1';
+ count <= count + 1;
+ RETS <= HEXMARKs;
+ dly_count <= x"000F";
+ CS <= END_WRITEs; --cheat as 1 extra cycle is needed for fifo to output data
+ else
+ usb_send <= '0';
+ rdreq_sig <= '0';
+ CS <= RESETs; --cheat as 1 extra cycle is needed for fifo to output data
+ end if;
+ when HEXMARKs => ----------------------------------------------------------
+ rdreq_sig <= '0'; --data will be ready on output 'till next read request
+ --if almost_full='0' then
+ usb_send_char <= CHAR_x; --show fifo full status to user by hex x case
+ --else
+ -- usb_send_char <= CHAR_ux; --show fifo full status to user by hex x case
+ --end if;
+ in_nibble <= q_sig(7 downto 4); --take fifo output and put to decoder
+ RETS <= MSNIBBLEs;
+ CS <= START_WRITEs;
+ when MSNIBBLEs => ----------------------------------------------------------
+ usb_send_char <= ascii_char; --put MS nibble to output
+ in_nibble <= q_sig(3 downto 0); --take fifo output and put to decoder
+ RETS <= LSNIBBLEs;
+ CS <= START_WRITEs;
+ when LSNIBBLEs => ----------------------------------------------------------
+ usb_send_char <= ascii_char; --put MS nibble to output
+ if count = x"f" then
+ RETS <= CRs;
+ else
+ RETS <= LINEFDs;
+ end if;
+ CS <= START_WRITEs;
+ when CRs => ----------------------------------------------------------
+ --if count = x"f" then
+ usb_send_char <= CHAR_CR; --put line feed
+ --else
+ -- usb_send_char <= CHAR_SP; --put space
+ --end if;
+ RETS <= LINEFDs;
+ CS <= START_WRITEs;
+ when LINEFDs => ----------------------------------------------------------
+ if count = x"f" then
+ usb_send_char <= CHAR_LF; --put line feed
+ else
+ usb_send_char <= CHAR_SP; --put space
+ end if;
+ RETS <= RESETs;
+ CS <= START_WRITEs;
+
+ when START_WRITEs => ----------------------------------------------------------
+ if dly_count /= x"0004" then
+ if dbg_usb_txe_n = '0' then
+ usb_send <= '1';
+ dly_count <= dly_count + 1;
+ else
+ usb_send <= '0'; --remove send signal when txe is falsely asserted
+ end if;
+ else
+ usb_send <= '0';
+ CS <= WAITs;
+ end if;
+ when WAITs => ----------------------------------------------------------
+ usb_send <= '0';
+ CS <= END_WRITEs;
+ when END_WRITEs => ----------------------------------------------------------
+ rdreq_sig <= '0'; --used as intermeadiate cheat state when exiting resets
+ if dly_count /= x"000F" then
+ if dbg_usb_txe_n = '0' then
+ dly_count <= dly_count + 1;
+ end if;
+ else
+ dly_count <=(others => '0');
+ CS <= RETS;
+ end if;
+ when others => null;
+ end case;
+ end if;
+ end if;
+ end process SER_SM;
+
+ SYNCER : process(sys_clk, resetn) --make slower clock and 2 cycle write pulse
+ begin -- process
+ if sys_clk'event and sys_clk = '1' then -- rising clock edge
+ if resetn = '0' then --active low reset
+ dbg_wr_pulse <= '0';
+ --dbg_wr_len <= '0';
+ dbg_wrd <= '0';
+ else
+ dbg_wrd <= dbg_wr;
+ if dbg_wrd = '0' and dbg_wr = '1' then -- rising front on fifo write
+ dbg_wr_pulse <= '1';
+ else
+ dbg_wr_pulse <= '0';
+ end if;
+ end if;
+ end if;
+ end process SYNCER;
+
+ reset <= not resetn;
+ dbg_full <= full_sig;
+ dbg_almost_full <= almost_full;
+ fifo_inst : fifo PORT MAP(
+ --system signals
+ aclr => reset,
+ clock => sys_clk, --make serial back end work 2 times slower as FDTI chip max timing length is 80 ns
+ -- push interface
+ data => dbg_data,
+ wrreq => dbg_wr_pulse,
+ almost_full => almost_full,
+ usedw => dbg_usedw,
+ --pop interface
+ rdreq => rdreq_sig,
+ empty => empty_sig,
+ full => full_sig,
+ q => q_sig
+ );
+
+end rtl;
+
Index: artec_dongle_ii_fpga/trunk/src/postcode_ser/fifo.bsf
===================================================================
--- artec_dongle_ii_fpga/trunk/src/postcode_ser/fifo.bsf (revision 8)
+++ artec_dongle_ii_fpga/trunk/src/postcode_ser/fifo.bsf (revision 9)
@@ -1,107 +1,107 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 1991-2006 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, Altera MegaCore Function License
-Agreement, or other applicable license agreement, including,
-without limitation, that your use is for the sole purpose of
-programming logic devices manufactured by Altera and sold by
-Altera or its authorized distributors. Please refer to the
-applicable agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 160 160)
- (text "fifo" (rect 72 1 90 17)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 144 25 156)(font "Arial" ))
- (port
- (pt 0 32)
- (input)
- (text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
- (text "data[7..0]" (rect 20 26 65 39)(font "Arial" (font_size 8)))
- (line (pt 0 32)(pt 16 32)(line_width 3))
- )
- (port
- (pt 0 56)
- (input)
- (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
- (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
- (line (pt 0 56)(pt 16 56)(line_width 1))
- )
- (port
- (pt 0 72)
- (input)
- (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
- (text "rdreq" (rect 20 66 44 79)(font "Arial" (font_size 8)))
- (line (pt 0 72)(pt 16 72)(line_width 1))
- )
- (port
- (pt 0 96)
- (input)
- (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
- (text "clock" (rect 26 90 49 103)(font "Arial" (font_size 8)))
- (line (pt 0 96)(pt 16 96)(line_width 1))
- )
- (port
- (pt 0 128)
- (input)
- (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
- (text "aclr" (rect 20 122 37 135)(font "Arial" (font_size 8)))
- (line (pt 0 128)(pt 16 128)(line_width 1))
- )
- (port
- (pt 160 32)
- (output)
- (text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
- (text "q[7..0]" (rect 111 26 141 39)(font "Arial" (font_size 8)))
- (line (pt 160 32)(pt 144 32)(line_width 3))
- )
- (port
- (pt 160 56)
- (output)
- (text "full" (rect 0 0 16 14)(font "Arial" (font_size 8)))
- (text "full" (rect 127 50 142 63)(font "Arial" (font_size 8)))
- (line (pt 160 56)(pt 144 56)(line_width 1))
- )
- (port
- (pt 160 72)
- (output)
- (text "almost_full" (rect 0 0 60 14)(font "Arial" (font_size 8)))
- (text "almost_full" (rect 90 66 142 79)(font "Arial" (font_size 8)))
- (line (pt 160 72)(pt 144 72)(line_width 1))
- )
- (port
- (pt 160 88)
- (output)
- (text "empty" (rect 0 0 34 14)(font "Arial" (font_size 8)))
- (text "empty" (rect 112 82 141 95)(font "Arial" (font_size 8)))
- (line (pt 160 88)(pt 144 88)(line_width 1))
- )
- (port
- (pt 160 104)
- (output)
- (text "usedw[12..0]" (rect 0 0 75 14)(font "Arial" (font_size 8)))
- (text "usedw[12..0]" (rect 77 98 136 111)(font "Arial" (font_size 8)))
- (line (pt 160 104)(pt 144 104)(line_width 3))
- )
- (drawing
- (text "8 bits x 8192 words" (rect 63 132 144 144)(font "Arial" ))
- (text "almost_full at 8000" (rect 64 122 144 134)(font "Arial" ))
- (line (pt 16 16)(pt 144 16)(line_width 1))
- (line (pt 144 16)(pt 144 144)(line_width 1))
- (line (pt 144 144)(pt 16 144)(line_width 1))
- (line (pt 16 144)(pt 16 16)(line_width 1))
- (line (pt 16 116)(pt 144 116)(line_width 1))
- (line (pt 16 90)(pt 22 96)(line_width 1))
- (line (pt 22 96)(pt 16 102)(line_width 1))
- )
-)
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2006 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 0 0 160 160)
+ (text "fifo" (rect 72 1 90 17)(font "Arial" (font_size 10)))
+ (text "inst" (rect 8 144 25 156)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+ (text "data[7..0]" (rect 20 26 65 39)(font "Arial" (font_size 8)))
+ (line (pt 0 32)(pt 16 32)(line_width 3))
+ )
+ (port
+ (pt 0 56)
+ (input)
+ (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+ (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
+ (line (pt 0 56)(pt 16 56)(line_width 1))
+ )
+ (port
+ (pt 0 72)
+ (input)
+ (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
+ (text "rdreq" (rect 20 66 44 79)(font "Arial" (font_size 8)))
+ (line (pt 0 72)(pt 16 72)(line_width 1))
+ )
+ (port
+ (pt 0 96)
+ (input)
+ (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+ (text "clock" (rect 26 90 49 103)(font "Arial" (font_size 8)))
+ (line (pt 0 96)(pt 16 96)(line_width 1))
+ )
+ (port
+ (pt 0 128)
+ (input)
+ (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
+ (text "aclr" (rect 20 122 37 135)(font "Arial" (font_size 8)))
+ (line (pt 0 128)(pt 16 128)(line_width 1))
+ )
+ (port
+ (pt 160 32)
+ (output)
+ (text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+ (text "q[7..0]" (rect 111 26 141 39)(font "Arial" (font_size 8)))
+ (line (pt 160 32)(pt 144 32)(line_width 3))
+ )
+ (port
+ (pt 160 56)
+ (output)
+ (text "full" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "full" (rect 127 50 142 63)(font "Arial" (font_size 8)))
+ (line (pt 160 56)(pt 144 56)(line_width 1))
+ )
+ (port
+ (pt 160 72)
+ (output)
+ (text "almost_full" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+ (text "almost_full" (rect 90 66 142 79)(font "Arial" (font_size 8)))
+ (line (pt 160 72)(pt 144 72)(line_width 1))
+ )
+ (port
+ (pt 160 88)
+ (output)
+ (text "empty" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+ (text "empty" (rect 112 82 141 95)(font "Arial" (font_size 8)))
+ (line (pt 160 88)(pt 144 88)(line_width 1))
+ )
+ (port
+ (pt 160 104)
+ (output)
+ (text "usedw[12..0]" (rect 0 0 75 14)(font "Arial" (font_size 8)))
+ (text "usedw[12..0]" (rect 77 98 136 111)(font "Arial" (font_size 8)))
+ (line (pt 160 104)(pt 144 104)(line_width 3))
+ )
+ (drawing
+ (text "8 bits x 8192 words" (rect 63 132 144 144)(font "Arial" ))
+ (text "almost_full at 8000" (rect 64 122 144 134)(font "Arial" ))
+ (line (pt 16 16)(pt 144 16)(line_width 1))
+ (line (pt 144 16)(pt 144 144)(line_width 1))
+ (line (pt 144 144)(pt 16 144)(line_width 1))
+ (line (pt 16 144)(pt 16 16)(line_width 1))
+ (line (pt 16 116)(pt 144 116)(line_width 1))
+ (line (pt 16 90)(pt 22 96)(line_width 1))
+ (line (pt 22 96)(pt 16 102)(line_width 1))
+ )
+)
Index: artec_dongle_ii_fpga/trunk/src/usb/usb2mem.vhd
===================================================================
--- artec_dongle_ii_fpga/trunk/src/usb/usb2mem.vhd (revision 8)
+++ artec_dongle_ii_fpga/trunk/src/usb/usb2mem.vhd (revision 9)
@@ -1,424 +1,409 @@
---COMMAND STRUCTURE OF SERAL USB PROTOCOL
-
--- MSBYTE LSBYTE
-
--- DATA CODE
-
---Dongle internal command codes
--- 0x00 0xC5 --Get Status data is don't care (must return) 0x3210 (3 is the MSNibble)
--- 0x01 0xC5 --Get Dongle version code
--- 0x02 0xC5 --PCB version code
--- 0x03 0xC5 --Get Mode switch setting
-
--- 0xC1 0xC5 --Release memeory interface to LPC
--- 0xC2 0xC5 --Put the device in USB programming mode (pulldown buf_en)
--- 0xC3 0xC5 --Force the dongle to indicate it's disconnected
--- 0xC4 0xC5 --Force the dongle to indicate it's connected
-
--- 0xC5 0xC5 --Force the dongle to lock memory interface
--- 0xC6 0xC5 --Force the dongle to unlock memory interface
-
--- 0x-- 0xC5 --Get Status data is don't care (must return) 0x3210 (3 is the MSNibble)
-
-
--- 0xNN 0xCD --Get Data from flash (performs read from current address) NN count of words auto increment address
--- 0xAA 0xA0 --Addr LSByte write
--- 0xAA 0xA1 --Addr Byte write
--- 0xAA 0xA2 --Addr MSByte write
--- 0x-- 0x3F --NOP
-
---Flash operations codes
--- 0xNN 0xE8 --Write to buffer returns extended satus NN is word count for USB machine
--- 0x-- 0xD0 -- 0xD0 is flash confirm command
-
---PSRAM operations codes
--- 0xNN 0xE9 --Write to buffer returns extended satus NN is word count for USB machine
--- 0xDD 0xDD --N+1 times data expected 0xF + 1 is the maximum
-
-
---write flash buffer sequence
--- ??? -- set address if needed
--- 0xNN 0xE8 --Write to buffer returns extended satus NN is word count for USB machine
--- 0x-- 0xNN --0xNN is word count for flash ges directly to flash and is wordCount - 1
--- 0xDD 0xDD --N+1 times data expected 0xF + 1 is the maximum
--- ...
--- 0x-- 0xD0 -- 0xD0 is flash confirm command
-
-
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-use IEEE.std_logic_arith.all;
-
-entity usb2mem is
- port (
- clk25 : in std_logic;
- reset_n : in std_logic;
- dongle_ver: in std_logic_vector(15 downto 0);
- pcb_ver : in std_logic_vector(15 downto 0);
- mode : in std_logic_vector(2 downto 0); --sel upper addr bits
- usb_buf_en : out std_logic;
- dev_present_n : out std_logic;
- -- mem Bus
- mem_busy_n: in std_logic;
- mem_idle : out std_logic; -- '1' if controller is idle (flash is safe for LPC reads)
- mem_addr : out std_logic_vector(23 downto 0);
- mem_do : out std_logic_vector(15 downto 0);
- mem_di : in std_logic_vector(15 downto 0);
- mem_wr : out std_logic;
- mem_val : out std_logic;
- mem_ack : in std_logic;
- mem_cmd : out std_logic;
- -- USB port
- usb_mode_en: in std_logic; -- enable this block
- usb_rd_n : out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
- usb_wr : out std_logic; -- write performed on edge \ of signal
- usb_txe_n : in std_logic; -- tx fifo empty (redy for new data if low)
- usb_rxf_n : in std_logic; -- rx fifo empty (data redy if low)
- usb_bd : inout std_logic_vector(7 downto 0) --bus data
- );
-end usb2mem;
-
-
-architecture RTL of usb2mem is
-
-
-
-
- type state_type is (RESETs,RXCMD0s,RXCMD1s,DECODEs,INTERNs,VCIRDs,VCIWRs,TXCMD0s,TXCMD1s,STS_WAITs);
- signal CS : state_type;
-
- signal data_reg_i : std_logic_vector(15 downto 0);
- signal data_reg_o : std_logic_vector(15 downto 0);
- signal data_oe : std_logic; -- rx fifo empty (data redy if low)
- signal usb_wr_d : std_logic; -- internal readable output state for write
- signal addr_reg: std_logic_vector(23 downto 0);
-
- --State machine
- signal cmd_cnt : std_logic_vector(15 downto 0);
- signal state_cnt : std_logic_vector(3 downto 0);
- --shyncro to USB
- signal usb_txe_nd : std_logic; -- tx fifo empty (redy for new data if low)
- signal usb_rxf_nd : std_logic; -- rx fifo empty (data redy if low)
- signal internal_cmd : std_logic; -- rx fifo empty (data redy if low)
-
- signal read_mode : std_logic;
- signal write_mode : std_logic;
- signal write_count : std_logic;
- signal first_word : std_logic;
- signal mem_busy_nd : std_logic;
-
-
-
-begin
-
---define internal command codes
-internal_cmd <='1' when data_reg_i(7 downto 0) = x"C5" else
- '1' when data_reg_i(7 downto 0) = x"CD" else
- '1' when data_reg_i(7 downto 0) = x"A0" else
- '1' when data_reg_i(7 downto 0) = x"A1" else
- '1' when data_reg_i(7 downto 0) = x"A2" else
- '1' when data_reg_i(7 downto 0) = x"3F" else
- --These are spechial attention Flash commands
- '1' when data_reg_i(7 downto 0) = x"E8" else
- '1' when data_reg_i(7 downto 0) = x"E9" else
- '0';
-
-
-usb_wr <= usb_wr_d when usb_mode_en='1' else
- 'Z';
-
-
--- this goes to byte buffer for that reason send LSB first and MSB second
-usb_bd <=data_reg_o(7 downto 0)when data_oe='1' and CS=TXCMD0s and usb_mode_en='1' else --LSB byte first
- data_reg_o(15 downto 8) when data_oe='1' and CS=TXCMD1s and usb_mode_en='1' else --MSB byte second
- (others=>'Z');
-
-
-process (clk25,reset_n) --enable the scanning while in reset (simulation will be incorrect)
-begin -- process
- if reset_n='0' then
- CS <= RESETs;
- usb_rd_n <= '1';
- usb_wr_d <= '0';
- usb_txe_nd <= '1';
- usb_rxf_nd <= '1';
- data_oe <='0';
- state_cnt <=(others=>'0'); --init command counter
- mem_do <= (others=>'Z');
- mem_addr <= (others=>'Z');
- addr_reg <= (others=>'0');
- mem_val <= '0';
- mem_wr <='0';
- mem_cmd <='0';
- cmd_cnt <= (others=>'0');
- read_mode <='0';
- write_mode <='0';
- write_count <='0';
- first_word <='0';
- mem_idle <='1'; --set idle
- mem_busy_nd <='1';
- usb_buf_en <='1'; -- default mode (USB prog disabled, buffer with HiZ outputs)
- dev_present_n <='0'; --indicate that device is present on LPC bus for thincans
- elsif clk25'event and clk25 = '1' then -- rising clock edge
- usb_txe_nd <= usb_txe_n; --syncronize
- usb_rxf_nd <= usb_rxf_n; --syncronize
- mem_busy_nd <=mem_busy_n; --syncronize
- case CS is
- when RESETs =>
- if usb_rxf_nd='0' and usb_mode_en='1' and mem_busy_nd='1' then
- state_cnt <=(others=>'0'); --init command counter
- data_oe <='0'; --we will read command in
- --mem_idle <='0'; --set busy untill return here
- CS <= RXCMD0s;
- end if;
- when RXCMD0s =>
- if state_cnt="0000" then
- usb_rd_n <='0'; -- set read low
- state_cnt <= state_cnt + 1;-- must be min 50ns long (two cycles)
- elsif state_cnt="0001" then
- state_cnt <= state_cnt + 1;-- one wait cycle
- elsif state_cnt="0010" then
- state_cnt <= state_cnt + 1;-- now is ok
- data_reg_i(15 downto 8) <= usb_bd; --get data form bus MSByte must come first
- elsif state_cnt="0011" then
- usb_rd_n <='1'; -- set read back to high
- state_cnt <= state_cnt + 1;-- start wait
- elsif state_cnt="0100" then
- state_cnt <= state_cnt + 1;-- wait (the usb_rxf_n toggles after each read and next data is not ready)
- elsif state_cnt="0101" then
- state_cnt <= state_cnt + 1;-- wait
- elsif state_cnt="0110" then
- state_cnt <= state_cnt + 1;-- now is ok prob.
- else
- if usb_rxf_nd='0' then --wait untill next byte is available
- state_cnt <=(others=>'0'); --init command counter
- CS <= RXCMD1s;
- end if;
- end if;
- when RXCMD1s =>
- if state_cnt="0000" then
- usb_rd_n <='0'; -- set read low
- state_cnt <= state_cnt + 1;-- must be min 50ns long (two cycles)
- elsif state_cnt="0001" then
- state_cnt <= state_cnt + 1;-- one wait cycle
- elsif state_cnt="0010" then
- state_cnt <= state_cnt + 1;-- now is ok
- data_reg_i(7 downto 0) <= usb_bd; --get data form bus LSByte must come last
- elsif state_cnt="0011" then
- state_cnt <= state_cnt + 1;-- now is ok
- usb_rd_n <='1'; -- set read back to high
- elsif state_cnt="0100" then
- state_cnt <= state_cnt + 1;-- wait (the usb_rxf_n toggles after each read and next data is not ready)
- elsif state_cnt="0101" then
- state_cnt <= state_cnt + 1;-- wait
- elsif state_cnt="0110" then
- state_cnt <= state_cnt + 1;-- now is ok prob.
- else
- state_cnt <=(others=>'0'); --init command counter
- CS <= INTERNs;
- end if;
- when INTERNs =>
- if cmd_cnt=x"0000" then
- if data_reg_i(7 downto 0)=x"A0" then
- addr_reg(7 downto 0)<= data_reg_i(15 downto 8);
- CS <= RESETs; --go back to resets
- elsif data_reg_i(7 downto 0)=x"A1" then
- addr_reg(15 downto 8)<= data_reg_i(15 downto 8);
- CS <= RESETs; --go back to resets
- elsif data_reg_i(7 downto 0)=x"A2" then
- addr_reg(23 downto 16)<= data_reg_i(15 downto 8);
- CS <= RESETs; --go back to resets
- elsif data_reg_i(7 downto 0)=x"3F" then
- CS <= RESETs; --go back to resets --NOP command
- elsif data_reg_i(7 downto 0)=x"C5" then
- if (data_reg_i(15 downto 8))=x"00" then
- data_reg_o <=x"3210";
- elsif(data_reg_i(15 downto 8))=x"01" then
- data_reg_o <=dongle_ver;
- elsif(data_reg_i(15 downto 8))=x"02" then
- data_reg_o <=pcb_ver;
- elsif(data_reg_i(15 downto 8))=x"03" then
- data_reg_o <="0000000000000"&mode;
- elsif(data_reg_i(15 downto 8))=x"C1" then --release flash to LPC interface
- data_reg_o <=x"C1C5";
- mem_idle <='1'; --set idle
- elsif(data_reg_i(15 downto 8))=x"C2" then --force USB prog mode
- usb_buf_en <='0';
- data_reg_o <=x"C2C5";
- elsif(data_reg_i(15 downto 8))=x"C3" then --fake dongle disconnect
- data_reg_o <=x"C3C5";
- dev_present_n <='0';
- elsif(data_reg_i(15 downto 8))=x"C4" then --fake dongle connect
- data_reg_o <=x"C4C5";
- dev_present_n <='1';
- elsif(data_reg_i(15 downto 8))=x"C5" then --fake dongle connect
- data_reg_o <=x"C5C5";
- mem_idle <='0'; --lock LPC out from memory interface
- elsif(data_reg_i(15 downto 8))=x"C6" then --fake dongle connect
- data_reg_o <=x"C6C5";
- mem_idle <='1'; --unlock memory interface
- else
- data_reg_o <=x"3210"; --always return even on unknown commands
- end if;
- CS <= TXCMD0s;
- elsif data_reg_i(7 downto 0)=x"CD" then
- if (data_reg_i(15 downto 8))=x"00" then --64K word read coming
- cmd_cnt <= (others=>'1'); --64K word count
- else
- cmd_cnt <= x"00"&data_reg_i(15 downto 8) - 1; -- -1 as one read will be done right now (cmd_cnt words)
- end if;
- CS <= VCIRDs; --go perform a read
- read_mode <='1';
- elsif data_reg_i(7 downto 0)=x"E8" then
- --write_mode <='1';
- write_count <='0';
- first_word <='0';
- cmd_cnt <= x"00"&data_reg_i(15 downto 8) + 1; --+2 for direct count write +1
- data_reg_i(15 downto 8)<=(others=>'0');
- CS <= VCIWRs; --go perform a write
- elsif data_reg_i(7 downto 0)=x"E9" then
- write_count <='1'; --no initial command write
- first_word <='0';
- if (data_reg_i(15 downto 8))=x"00" then --64K word write coming
- cmd_cnt <= (others=>'1'); --64K word count
- else
- cmd_cnt <= x"00"&data_reg_i(15 downto 8);
- end if;
- data_reg_i(15 downto 8)<=(others=>'0');
- CS <= RESETs; --PSRAM does not need command
- else
- CS <= VCIWRs;
- end if;
- else
- if cmd_cnt>x"0000" then
- cmd_cnt<= cmd_cnt - 1;
- if write_count='0' then
- write_count<='1';
- elsif write_count='1' and first_word ='0' then
- first_word <='1';
- elsif write_count='1' and first_word ='1' then
- addr_reg <= addr_reg + 1; --autoincrement address in in block mode
- end if;
- --if cmd_cnt>x"02" then --so not to increase too many times on write buffer
- -- addr_reg <= addr_reg + 1; --autoincrement address in in block mode
- --end if;
- end if;
- CS <= VCIWRs;
- end if;
- when VCIRDs => --flash read
- mem_wr <='0'; --this is VCI write_not_read
- mem_cmd <='0';
- mem_addr <= addr_reg(22 downto 0)&'0'; --translate byte address to word address
- mem_val <= '1';
- if mem_ack='1' then
- data_reg_o <= mem_di;
- mem_wr <='0'; --this is VCI write_not_read
- mem_cmd <='0';
- mem_val <= '0';
- CS <= TXCMD0s;
- end if;
- when VCIWRs => --flash write
- mem_addr <= addr_reg(22 downto 0)&'0'; --translate byte address to word address
- if mode(2)='1' then
- --this HW swap removes the need to swap bytes in python for PSRAM region
- mem_do <= data_reg_i(7 downto 0)&data_reg_i(15 downto 8); --SWAP data for PSRAM region
- else
- mem_do <= data_reg_i; --USB data in will go to mem_out
- end if;
- mem_wr <='1'; --this is VCI write_not_read
- mem_cmd <='1';
- mem_val <= '1';
- if mem_ack='1' then
- mem_do <= (others=>'Z');
- mem_wr <='0'; --this is VCI write_not_read
- mem_cmd <='0';
- mem_val <= '0';
- --if write_mode='0' then
-
- if cmd_cnt=x"0000" then --if flash command and not data
- state_cnt <=(others=>'0'); --init command counter
- CS <= STS_WAITs;
- else
- CS <= RESETs;
- end if;
- --else --else if was 0xE8 must read and return XSR
- -- write_mode <='0'; --XSR return will no follow clear this bit
- -- CS <= VCIRDs;
- --end if;
- end if;
- when TXCMD0s => --transmit over USB what ever is in data_reg_o MSB first
-
- if state_cnt="0000" then
- if usb_txe_nd='0' then
- usb_wr_d<='1'; -- data is mux'ed by state and data_oe in the beginning of arch
- state_cnt <= state_cnt + 1;-- now is ok
- end if;
- elsif state_cnt="0010" then
- data_oe<='1'; --this is to put data on bus befora falling edge of wr (max 20ns before)
- state_cnt <= state_cnt + 1;-- now is ok
- elsif state_cnt="0011" then
- usb_wr_d<='0'; --falling edge performs write must be high for atleast 50ns
- state_cnt <= state_cnt + 1;-- now is ok
- elsif state_cnt="0100" then
- state_cnt <= state_cnt + 1;-- now is ok
- data_oe<='0';
- elsif state_cnt="0111" then --must stay low at least 50ns
- CS <= TXCMD1s;
- state_cnt <= (others=>'0');
- else
- state_cnt <= state_cnt + 1;-- if intermediate cnt then count
- end if;
-
- when TXCMD1s =>
-
- if state_cnt="0000" then
- if usb_txe_nd='0' then
- usb_wr_d<='1'; -- data is mux'ed by state and data_oe in the beginning of arch
- state_cnt <= state_cnt + 1;-- now is ok
- end if;
- elsif state_cnt="0010" then
- data_oe<='1'; --this is to put data on bus befora falling edge of wr (max 20ns before)
- state_cnt <= state_cnt + 1;-- now is ok
- elsif state_cnt="0011" then
- usb_wr_d<='0'; --falling edge performs write must be high for atleast 50ns
- state_cnt <= state_cnt + 1;-- now is ok
- elsif state_cnt="0100" then
- state_cnt <= state_cnt + 1;-- now is ok
- data_oe<='0';
- elsif state_cnt="0111" then --must stay low at least 50ns
- if read_mode='0' then
- CS <= RESETs;
- elsif cmd_cnt="0000" then --last word sent
- addr_reg <= addr_reg + 1; --autoincrement address in read mode
- read_mode <='0';
- CS <= RESETs;
- else
- cmd_cnt<= cmd_cnt - 1;
- addr_reg <= addr_reg + 1; --autoincrement address in read mode
- CS <= VCIRDs; --more data to be read
- end if;
- state_cnt <= (others=>'0');
- else
- state_cnt <= state_cnt + 1;-- if intermediate cnt then count
- end if;
- when STS_WAITs =>
- if mem_busy_nd='0' or mode(2)='1' then --go to RESETs if PSRAM mode is selected
- CS <= RESETs; --now it's ok to go here
- else
- state_cnt <= state_cnt + 1;
- if state_cnt="1111" then
- --sts cant take longer than 500 ns to go low
- CS <= RESETs; --time out go to resets anyway
- end if;
- end if;
- when others => null;
- end case;
- end if;
-end process;
-
-
-
-end RTL;
-
+--COMMAND STRUCTURE OF SERAL USB PROTOCOL
+
+-- MSBYTE LSBYTE
+
+-- DATA CODE
+
+--Dongle internal command codes
+-- 0x00 0xC5 --Get Status data is don't care (must return) 0x3210 (3 is the MSNibble)
+-- 0x01 0xC5 --Get Dongle version code
+-- 0x02 0xC5 --PCB version code
+-- 0x03 0xC5 --Get Mode switch setting
+
+-- 0xC1 0xC5 --Release memeory interface to LPC
+-- 0xC2 0xC5 --Put the device in USB programming mode (pulldown buf_en)
+-- 0xC3 0xC5 --Force the dongle to indicate it's disconnected
+-- 0xC4 0xC5 --Force the dongle to indicate it's connected
+
+-- 0xC5 0xC5 --Force the dongle to lock memory interface
+-- 0xC6 0xC5 --Force the dongle to unlock memory interface
+
+-- 0x-- 0xC5 --Get Status data is don't care (must return) 0x3210 (3 is the MSNibble)
+
+
+-- 0xNN 0xCD --Get Data from flash (performs read from current address) NN count of words auto increment address
+-- 0xAA 0xA0 --Addr LSByte write
+-- 0xAA 0xA1 --Addr Byte write
+-- 0xAA 0xA2 --Addr MSByte write
+-- 0x-- 0x3F --NOP
+
+--Flash operations codes
+-- 0xNN 0xE8 --Write to buffer returns extended satus NN is word count for USB machine
+-- 0x-- 0xD0 -- 0xD0 is flash confirm command
+
+--PSRAM operations codes
+-- 0xNN 0xE9 --Write to buffer returns extended satus NN is word count for USB machine
+-- 0xDD 0xDD --N+1 times data expected 0xF + 1 is the maximum
+
+
+--write flash buffer sequence
+-- ??? -- set address if needed
+-- 0xNN 0xE8 --Write to buffer returns extended satus NN is word count for USB machine
+-- 0x-- 0xNN --0xNN is word count for flash ges directly to flash and is wordCount - 1
+-- 0xDD 0xDD --N+1 times data expected 0xF + 1 is the maximum
+-- ...
+-- 0x-- 0xD0 -- 0xD0 is flash confirm command
+
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+entity usb2mem is
+ port (
+ clk25 : in std_logic;
+ reset_n : in std_logic;
+ dongle_ver: in std_logic_vector(15 downto 0);
+ pcb_ver : in std_logic_vector(15 downto 0);
+ mode : in std_logic_vector(2 downto 0); --sel upper addr bits
+ usb_buf_en : out std_logic;
+ dev_present_n : out std_logic;
+ -- mem Bus
+ mem_busy_n: in std_logic;
+ mem_idle : out std_logic; -- '1' if controller is idle (flash is safe for LPC reads)
+ mem_addr : out std_logic_vector(23 downto 0);
+ mem_do : out std_logic_vector(15 downto 0);
+ mem_di : in std_logic_vector(15 downto 0);
+ mem_wr : out std_logic;
+ mem_val : out std_logic;
+ mem_ack : in std_logic;
+ mem_cmd : out std_logic;
+ -- USB port
+ usb_mode_en : in std_logic; -- enable this block
+ usb_rd_n : out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
+ usb_wr : out std_logic; -- write performed on edge \ of signal
+ usb_txe_n : in std_logic; -- tx fifo empty (redy for new data if low)
+ usb_rxf_n : in std_logic; -- rx fifo empty (data redy if low)
+ usb_bd_o : out std_logic_vector(7 downto 0); --bus data
+ usb_bd : in std_logic_vector(7 downto 0) --bus data
+ );
+end usb2mem;
+
+
+architecture RTL of usb2mem is
+
+
+
+
+ type state_type is (RESETs,RXCMD0s,RXCMD1s,DECODEs,INTERNs,VCIRDs,VCIWRs,TXCMD0s,TXCMD1s,STS_WAITs);
+ signal CS : state_type;
+
+ signal data_reg_i : std_logic_vector(15 downto 0);
+ signal data_reg_o : std_logic_vector(15 downto 0);
+ signal data_oe : std_logic; -- rx fifo empty (data redy if low)
+ signal usb_wr_d : std_logic; -- internal readable output state for write
+ signal addr_reg: std_logic_vector(23 downto 0);
+
+ --State machine
+ signal cmd_cnt : std_logic_vector(15 downto 0);
+ signal state_cnt : std_logic_vector(3 downto 0);
+ --shyncro to USB
+ signal usb_txe_nd : std_logic; -- tx fifo empty (redy for new data if low)
+ signal usb_rxf_nd : std_logic; -- rx fifo empty (data redy if low)
+ --signal internal_cmd : std_logic; -- rx fifo empty (data redy if low)
+
+ signal read_mode : std_logic;
+ --signal write_mode : std_logic;
+ signal write_count : std_logic;
+ signal first_word : std_logic;
+ signal mem_busy_nd : std_logic;
+
+
+
+begin
+
+usb_wr <= usb_wr_d;
+
+-- this goes to byte buffer for that reason send LSB first and MSB second
+usb_bd_o <=data_reg_o(7 downto 0)when data_oe='1' and CS=TXCMD0s and usb_mode_en='1' else --LSB byte first
+ data_reg_o(15 downto 8) when data_oe='1' and CS=TXCMD1s and usb_mode_en='1' else
+ (others=>'0');
+
+
+process (clk25,reset_n) --enable the scanning while in reset (simulation will be incorrect)
+begin -- process
+ if reset_n='0' then
+ CS <= RESETs;
+ usb_rd_n <= '1';
+ usb_wr_d <= '0';
+ usb_txe_nd <= '1';
+ usb_rxf_nd <= '1';
+ data_oe <='0';
+ state_cnt <=(others=>'0'); --init command counter
+ mem_do <= (others=>'0');
+ mem_addr <= (others=>'0');
+ addr_reg <= (others=>'0');
+ mem_val <= '0';
+ mem_wr <='0';
+ mem_cmd <='0';
+ cmd_cnt <= (others=>'0');
+ read_mode <='0';
+ write_count <='0';
+ first_word <='0';
+ mem_idle <='1'; --set idle
+ mem_busy_nd <='1';
+ usb_buf_en <='1'; -- default mode (USB prog disabled, buffer with HiZ outputs)
+ dev_present_n <='0'; --indicate that device is present on LPC bus for thincans
+ elsif clk25'event and clk25 = '1' then -- rising clock edge
+ usb_txe_nd <= usb_txe_n; --syncronize
+ usb_rxf_nd <= usb_rxf_n; --syncronize
+ mem_busy_nd <=mem_busy_n; --syncronize
+ case CS is
+ when RESETs =>
+ if usb_rxf_nd='0' and usb_mode_en='1' and mem_busy_nd='1' then
+ state_cnt <=(others=>'0'); --init command counter
+ data_oe <='0'; --we will read command in
+ --mem_idle <='0'; --set busy untill return here
+ CS <= RXCMD0s;
+ end if;
+ when RXCMD0s =>
+ if state_cnt="0000" then
+ usb_rd_n <='0'; -- set read low
+ state_cnt <= state_cnt + 1;-- must be min 50ns long (two cycles)
+ elsif state_cnt="0001" then
+ state_cnt <= state_cnt + 1;-- one wait cycle
+ elsif state_cnt="0010" then
+ state_cnt <= state_cnt + 1;-- now is ok
+ data_reg_i(15 downto 8) <= usb_bd; --get data form bus MSByte must come first
+ elsif state_cnt="0011" then
+ usb_rd_n <='1'; -- set read back to high
+ state_cnt <= state_cnt + 1;-- start wait
+ elsif state_cnt="0100" then
+ state_cnt <= state_cnt + 1;-- wait (the usb_rxf_n toggles after each read and next data is not ready)
+ elsif state_cnt="0101" then
+ state_cnt <= state_cnt + 1;-- wait
+ elsif state_cnt="0110" then
+ state_cnt <= state_cnt + 1;-- now is ok prob.
+ else
+ if usb_rxf_nd='0' then --wait untill next byte is available
+ state_cnt <=(others=>'0'); --init command counter
+ CS <= RXCMD1s;
+ end if;
+ end if;
+ when RXCMD1s =>
+ if state_cnt="0000" then
+ usb_rd_n <='0'; -- set read low
+ state_cnt <= state_cnt + 1;-- must be min 50ns long (two cycles)
+ elsif state_cnt="0001" then
+ state_cnt <= state_cnt + 1;-- one wait cycle
+ elsif state_cnt="0010" then
+ state_cnt <= state_cnt + 1;-- now is ok
+ data_reg_i(7 downto 0) <= usb_bd; --get data form bus LSByte must come last
+ elsif state_cnt="0011" then
+ state_cnt <= state_cnt + 1;-- now is ok
+ usb_rd_n <='1'; -- set read back to high
+ elsif state_cnt="0100" then
+ state_cnt <= state_cnt + 1;-- wait (the usb_rxf_n toggles after each read and next data is not ready)
+ elsif state_cnt="0101" then
+ state_cnt <= state_cnt + 1;-- wait
+ elsif state_cnt="0110" then
+ state_cnt <= state_cnt + 1;-- now is ok prob.
+ else
+ state_cnt <=(others=>'0'); --init command counter
+ CS <= INTERNs;
+ end if;
+ when INTERNs =>
+ if cmd_cnt=x"0000" then
+ if data_reg_i(7 downto 0)=x"A0" then
+ addr_reg(7 downto 0)<= data_reg_i(15 downto 8);
+ CS <= RESETs; --go back to resets
+ elsif data_reg_i(7 downto 0)=x"A1" then
+ addr_reg(15 downto 8)<= data_reg_i(15 downto 8);
+ CS <= RESETs; --go back to resets
+ elsif data_reg_i(7 downto 0)=x"A2" then
+ addr_reg(23 downto 16)<= data_reg_i(15 downto 8);
+ CS <= RESETs; --go back to resets
+ elsif data_reg_i(7 downto 0)=x"3F" then
+ CS <= RESETs; --go back to resets --NOP command
+ elsif data_reg_i(7 downto 0)=x"C5" then
+ if (data_reg_i(15 downto 8))=x"00" then
+ data_reg_o <=x"3210";
+ elsif(data_reg_i(15 downto 8))=x"01" then
+ data_reg_o <=dongle_ver;
+ elsif(data_reg_i(15 downto 8))=x"02" then
+ data_reg_o <=pcb_ver;
+ elsif(data_reg_i(15 downto 8))=x"03" then
+ data_reg_o <="0000000000000"&mode;
+ elsif(data_reg_i(15 downto 8))=x"C1" then --release flash to LPC interface
+ data_reg_o <=x"C1C5";
+ mem_idle <='1'; --set idle
+ elsif(data_reg_i(15 downto 8))=x"C2" then --force USB prog mode
+ usb_buf_en <='0';
+ data_reg_o <=x"C2C5";
+ elsif(data_reg_i(15 downto 8))=x"C3" then --fake dongle disconnect
+ data_reg_o <=x"C3C5";
+ dev_present_n <='0';
+ elsif(data_reg_i(15 downto 8))=x"C4" then --fake dongle connect
+ data_reg_o <=x"C4C5";
+ dev_present_n <='1';
+ elsif(data_reg_i(15 downto 8))=x"C5" then --fake dongle connect
+ data_reg_o <=x"C5C5";
+ mem_idle <='0'; --lock LPC out from memory interface
+ elsif(data_reg_i(15 downto 8))=x"C6" then --fake dongle connect
+ data_reg_o <=x"C6C5";
+ mem_idle <='1'; --unlock memory interface
+ else
+ data_reg_o <=x"3210"; --always return even on unknown commands
+ end if;
+ CS <= TXCMD0s;
+ elsif data_reg_i(7 downto 0)=x"CD" then
+ if (data_reg_i(15 downto 8))=x"00" then --64K word read coming
+ cmd_cnt <= (others=>'1'); --64K word count
+ else
+ cmd_cnt <= x"00"&data_reg_i(15 downto 8) - 1; -- -1 as one read will be done right now (cmd_cnt words)
+ end if;
+ CS <= VCIRDs; --go perform a read
+ read_mode <='1';
+ elsif data_reg_i(7 downto 0)=x"E8" then
+ --write_mode <='1';
+ write_count <='0';
+ first_word <='0';
+ cmd_cnt <= x"00"&data_reg_i(15 downto 8) + 1; --+2 for direct count write +1
+ data_reg_i(15 downto 8)<=(others=>'0');
+ CS <= VCIWRs; --go perform a write
+ elsif data_reg_i(7 downto 0)=x"E9" then
+ write_count <='1'; --no initial command write
+ first_word <='0';
+ if (data_reg_i(15 downto 8))=x"00" then --64K word write coming
+ cmd_cnt <= (others=>'1'); --64K word count
+ else
+ cmd_cnt <= x"00"&data_reg_i(15 downto 8);
+ end if;
+ data_reg_i(15 downto 8)<=(others=>'0');
+ CS <= RESETs; --PSRAM does not need command
+ else
+ CS <= VCIWRs;
+ end if;
+ else
+ if cmd_cnt>x"0000" then
+ cmd_cnt<= cmd_cnt - 1;
+ if write_count='0' then
+ write_count<='1';
+ elsif write_count='1' and first_word ='0' then
+ first_word <='1';
+ elsif write_count='1' and first_word ='1' then
+ addr_reg <= addr_reg + 1; --autoincrement address in in block mode
+ end if;
+ --if cmd_cnt>x"02" then --so not to increase too many times on write buffer
+ -- addr_reg <= addr_reg + 1; --autoincrement address in in block mode
+ --end if;
+ end if;
+ CS <= VCIWRs;
+ end if;
+ when VCIRDs => --flash read
+ mem_wr <='0'; --this is VCI write_not_read
+ mem_cmd <='0';
+ mem_addr <= addr_reg(22 downto 0)&'0'; --translate byte address to word address
+ mem_val <= '1';
+ if mem_ack='1' then
+ data_reg_o <= mem_di;
+ mem_wr <='0'; --this is VCI write_not_read
+ mem_cmd <='0';
+ mem_val <= '0';
+ CS <= TXCMD0s;
+ end if;
+ when VCIWRs => --flash write
+ mem_addr <= addr_reg(22 downto 0)&'0'; --translate byte address to word address
+ if mode(2)='1' then
+ --this HW swap removes the need to swap bytes in python for PSRAM region
+ mem_do <= data_reg_i(7 downto 0)&data_reg_i(15 downto 8); --SWAP data for PSRAM region
+ else
+ mem_do <= data_reg_i; --USB data in will go to mem_out
+ end if;
+ mem_wr <='1'; --this is VCI write_not_read
+ mem_cmd <='1';
+ mem_val <= '1';
+ if mem_ack='1' then
+ mem_do <= (others=>'Z');
+ mem_wr <='0'; --this is VCI write_not_read
+ mem_cmd <='0';
+ mem_val <= '0';
+ --if write_mode='0' then
+
+ if cmd_cnt=x"0000" then --if flash command and not data
+ state_cnt <=(others=>'0'); --init command counter
+ CS <= STS_WAITs;
+ else
+ CS <= RESETs;
+ end if;
+ --else --else if was 0xE8 must read and return XSR
+ -- write_mode <='0'; --XSR return will no follow clear this bit
+ -- CS <= VCIRDs;
+ --end if;
+ end if;
+ when TXCMD0s => --transmit over USB what ever is in data_reg_o MSB first
+
+ if state_cnt="0000" then
+ if usb_txe_nd='0' then
+ usb_wr_d<='1'; -- data is mux'ed by state and data_oe in the beginning of arch
+ state_cnt <= state_cnt + 1;-- now is ok
+ end if;
+ elsif state_cnt="0010" then
+ data_oe<='1'; --this is to put data on bus befora falling edge of wr (max 20ns before)
+ state_cnt <= state_cnt + 1;-- now is ok
+ elsif state_cnt="0011" then
+ usb_wr_d<='0'; --falling edge performs write must be high for atleast 50ns
+ state_cnt <= state_cnt + 1;-- now is ok
+ elsif state_cnt="0100" then
+ state_cnt <= state_cnt + 1;-- now is ok
+ data_oe<='0';
+ elsif state_cnt="0111" then --must stay low at least 50ns
+ CS <= TXCMD1s;
+ state_cnt <= (others=>'0');
+ else
+ state_cnt <= state_cnt + 1;-- if intermediate cnt then count
+ end if;
+
+ when TXCMD1s =>
+
+ if state_cnt="0000" then
+ if usb_txe_nd='0' then
+ usb_wr_d<='1'; -- data is mux'ed by state and data_oe in the beginning of arch
+ state_cnt <= state_cnt + 1;-- now is ok
+ end if;
+ elsif state_cnt="0010" then
+ data_oe<='1'; --this is to put data on bus befora falling edge of wr (max 20ns before)
+ state_cnt <= state_cnt + 1;-- now is ok
+ elsif state_cnt="0011" then
+ usb_wr_d<='0'; --falling edge performs write must be high for atleast 50ns
+ state_cnt <= state_cnt + 1;-- now is ok
+ elsif state_cnt="0100" then
+ state_cnt <= state_cnt + 1;-- now is ok
+ data_oe<='0';
+ elsif state_cnt="0111" then --must stay low at least 50ns
+ if read_mode='0' then
+ CS <= RESETs;
+ elsif cmd_cnt="0000" then --last word sent
+ addr_reg <= addr_reg + 1; --autoincrement address in read mode
+ read_mode <='0';
+ CS <= RESETs;
+ else
+ cmd_cnt<= cmd_cnt - 1;
+ addr_reg <= addr_reg + 1; --autoincrement address in read mode
+ CS <= VCIRDs; --more data to be read
+ end if;
+ state_cnt <= (others=>'0');
+ else
+ state_cnt <= state_cnt + 1;-- if intermediate cnt then count
+ end if;
+ when STS_WAITs =>
+ if mem_busy_nd='0' or mode(2)='1' then --go to RESETs if PSRAM mode is selected
+ CS <= RESETs; --now it's ok to go here
+ else
+ state_cnt <= state_cnt + 1;
+ if state_cnt="1111" then
+ --sts cant take longer than 500 ns to go low
+ CS <= RESETs; --time out go to resets anyway
+ end if;
+ end if;
+ when others => null;
+ end case;
+ end if;
+end process;
+
+
+
+end RTL;
+
Index: artec_dongle_ii_fpga/trunk/src/design_top/design_top_thincandbg.vhd
===================================================================
--- artec_dongle_ii_fpga/trunk/src/design_top/design_top_thincandbg.vhd (revision 8)
+++ artec_dongle_ii_fpga/trunk/src/design_top/design_top_thincandbg.vhd (revision 9)
@@ -1,640 +1,821 @@
-------------------------------------------------------------------
--- Universal dongle board source code
---
--- Copyright (C) 2006 Artec Design
---
--- This source code is free hardware; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
---
--- This source code is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--- Lesser General Public License for more details.
---
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
---
---
--- The complete text of the GNU Lesser General Public License can be found in
--- the file 'lesser.txt'.
-
-
-
--- Coding for seg_out(7:0)
---
--- bit 0,A
--- ----------
--- | |
--- | |
--- 5,F| | 1,B
--- | 6,G |
--- ----------
--- | |
--- | |
--- 4,E| | 2,C
--- | 3,D |
--- ----------
--- # 7,H
-
--- Revision history
---
--- Version 1.01
--- 15 oct 2006 version code 86 01 jyrit
--- Added IO write to address 0x0088 with commands F1 and F4 to
--- enable switching dongle to 4Meg mode for external reads
--- Changed USB interface to address all 4 Meg on any mode jumper configuration
---
--- Version 1.02
--- 04 dec 2006 version code 86 02 jyrit
--- Added listen only mode for mode pin configuration "00" to enable post code
--- spy mode (does not respond to external reads).
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-use IEEE.std_logic_arith.all;
-
-entity design_top is
- port (
- --system signals
- sys_clk : in std_logic; --25 MHz clk
- resetn : in std_logic;
- hdr : inout std_logic_vector(15 downto 0);
- hdr_b : inout std_logic_vector(15 downto 0);
- --alt_clk : out std_logic;
- mode : inout std_logic_vector(2 downto 0); --sel upper addr bits
- --lpc slave interf
- lad : inout std_logic_vector(3 downto 0);
- lframe_n : in std_logic;
- lreset_n : in std_logic;
- lclk : in std_logic;
- ldev_present: out std_logic;
- --led system
- seg_out : out std_logic_vector(7 downto 0);
- scn_seg : out std_logic_vector(3 downto 0);
- led_green : out std_logic;
- led_red : out std_logic;
- --flash interface
- fl_addr : out std_logic_vector(23 downto 0);
- fl_ce_n : out std_logic; --chip select
- fl_oe_n : out std_logic; --output enable for flash
- fl_we_n : out std_logic; --write enable
- fl_data : inout std_logic_vector(15 downto 0);
- fl_rp_n : out std_logic; --reset signal
- fl_sts : in std_logic; --status signal
- fl_sts_en : out std_logic; --enable status signal wiht highZ out
- -- PSRAM aditional signals to flash
- ps_ram_en : out std_logic;
- ps_clk : out std_logic; --PSRAM clock
- ps_wait : in std_logic;
- ps_addr_val: out std_logic; --active low
- ps_confr_en: out std_logic;
- ps_lsb_en : out std_logic;
- ps_msb_en : out std_logic;
- -- EEPROM signals
- ee_di : out std_logic;
- ee_do : in std_logic;
- ee_hold_n : out std_logic;
- ee_cs_n : out std_logic;
- ee_clk : out std_logic;
- ee_write : out std_logic;
- -- PROG enable
- buf_oe_n : out std_logic;
- --USB parallel interface
- usb_rd_n : inout std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
- usb_wr : inout std_logic; -- write performed on edge \ of signal
- usb_txe_n : in std_logic; -- transmit enable (redy for new data if low)
- usb_rxf_n : in std_logic; -- rx fifo has data if low
- usb_bd : inout std_logic_vector(7 downto 0) --bus data
- );
-end design_top;
-
-
-
-architecture rtl of design_top is
-
-component led_sys --toplevel for led system
- generic(
- msn_hib : std_logic_vector(7 downto 0); --Most signif. of hi byte
- lsn_hib : std_logic_vector(7 downto 0); --Least signif. of hi byte
- msn_lob : std_logic_vector(7 downto 0); --Most signif. of hi byte
- lsn_lob : std_logic_vector(7 downto 0) --Least signif. of hi byte
- );
- port (
- clk : in std_logic;
- reset_n : in std_logic;
- led_data_i : in std_logic_vector(15 downto 0); --binary data in
- seg_out : out std_logic_vector(7 downto 0); --one segment out
- sel_out : out std_logic_vector(3 downto 0) --segment scanner with one bit low
- );
-end component;
-
-
-component lpc_iow
- port (
- --system signals
- lreset_n : in std_logic;
- lclk : in std_logic;
- lena_mem_r : in std_logic; --enable full adress range covering memory read block
- lena_reads : in std_logic; --enable read capabilities
- --LPC bus from host
- lad_i : in std_logic_vector(3 downto 0);
- lad_o : out std_logic_vector(3 downto 0);
- lad_oe : out std_logic;
- lframe_n : in std_logic;
- --memory interface
- lpc_addr : out std_logic_vector(23 downto 0); --shared address
- lpc_wr : out std_logic; --shared write not read
- lpc_data_i : in std_logic_vector(7 downto 0);
- lpc_data_o : out std_logic_vector(7 downto 0);
- lpc_val : out std_logic;
- lpc_ack : in std_logic
- );
-end component;
-
-
-component flash_if
- port (
- clk : in std_logic;
- reset_n : in std_logic;
- mode : in std_logic_vector(2 downto 0); --sel upper addr bits
- --flash Bus
- fl_addr : out std_logic_vector(23 downto 0);
- fl_ce_n : out std_logic; --chip select
- fl_oe_n : out std_logic; --output enable for flash
- fl_we_n : out std_logic; --write enable
- fl_data : inout std_logic_vector(15 downto 0);
- fl_rp_n : out std_logic; --reset signal
- fl_byte_n : out std_logic; --hold in byte mode
- fl_sts : in std_logic; --status signal
- -- mem Bus
- mem_addr : in std_logic_vector(23 downto 0);
- mem_do : out std_logic_vector(15 downto 0);
- mem_di : in std_logic_vector(15 downto 0);
- mem_wr : in std_logic; --write not read signal
- mem_val : in std_logic;
- mem_ack : out std_logic
- );
-end component;
-
-
-component usb2mem
- port (
- clk25 : in std_logic;
- reset_n : in std_logic;
- dongle_ver: in std_logic_vector(15 downto 0);
- pcb_ver : in std_logic_vector(15 downto 0);
- mode : in std_logic_vector(2 downto 0); --sel upper addr bits
- usb_buf_en : out std_logic;
- dev_present_n : out std_logic;
- -- mem Bus
- mem_busy_n: in std_logic;
- mem_idle : out std_logic; -- '1' if controller is idle (flash is safe for LPC reads)
- mem_addr : out std_logic_vector(23 downto 0);
- mem_do : out std_logic_vector(15 downto 0);
- mem_di : in std_logic_vector(15 downto 0);
- mem_wr : out std_logic;
- mem_val : out std_logic;
- mem_ack : in std_logic;
- mem_cmd : out std_logic;
- -- USB port
- usb_mode_en: in std_logic; -- enable this block
- usb_rd_n : out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
- usb_wr : out std_logic; -- write performed on edge \ of signal
- usb_txe_n : in std_logic; -- tx fifo empty (redy for new data if low)
- usb_rxf_n : in std_logic; -- rx fifo empty (data redy if low)
- usb_bd : inout std_logic_vector(7 downto 0) --bus data
- );
-end component;
-
-component pc_serializer
- Port ( --system signals
- sys_clk : in STD_LOGIC;
- resetn : in STD_LOGIC;
- --postcode data port
- dbg_data : in STD_LOGIC_VECTOR (7 downto 0);
- dbg_wr : in STD_LOGIC; --write not read
- dbg_full : out STD_LOGIC; --write not read
- dbg_almost_full : out STD_LOGIC;
- dbg_usedw : out STD_LOGIC_VECTOR (12 DOWNTO 0);
- --debug USB port
- dbg_usb_mode_en: in std_logic; -- enable this debug mode
- dbg_usb_wr : out std_logic; -- write performed on edge \ of signal
- dbg_usb_txe_n : in std_logic; -- tx fifo not full (redy for new data if low)
- dbg_usb_bd : inout std_logic_vector(7 downto 0) --bus data
-);
-end component;
-
-
---LED signals
-signal data_to_disp : std_logic_vector(15 downto 0);
---END LED SIGNALS
-
---lpc signals
-signal lad_i : std_logic_vector(3 downto 0);
-signal lad_o : std_logic_vector(3 downto 0);
-signal lad_oe : std_logic;
-
-signal lpc_debug : std_logic_vector(31 downto 0);
-signal lpc_debug_cnt : std_logic_vector(15 downto 0);
-signal lpc_addr : std_logic_vector(23 downto 0); --shared address
-signal lpc_data_o : std_logic_vector(7 downto 0);
-signal lpc_data_i : std_logic_vector(7 downto 0);
-signal lpc_wr : std_logic; --shared write not read
-signal lpc_ack : std_logic;
-signal lpc_val : std_logic;
-signal lena_mem_r : std_logic; --enable full adress range covering memory read block
-signal lena_reads : std_logic; --enable/disables all read capabilty to make the device post code capturer
-
-signal c25_lpc_val : std_logic;
-signal c25_lpc_wr : std_logic; --shared write not read
-signal c25_lpc_wr_long : std_logic; --for led debug data latching
-
-signal c33_lpc_wr_long : std_logic; --for led debug data latching
-signal c33_lpc_wr : std_logic; --for led debug data latching
-signal c33_lpc_wr_wait: std_logic; --for led debug data latching
-signal c33_lpc_wr_waitd: std_logic; --for led debug data latching
-signal c33_wr_cnt : std_logic_vector(23 downto 0); --for led debug data latching
-
-
---End lpc signals
-
---Flash signals
-signal mem_addr : std_logic_vector(23 downto 0);
-signal mem_do : std_logic_vector(15 downto 0);
-signal mem_di : std_logic_vector(15 downto 0);
-signal mem_wr : std_logic; --write not read signal
-signal mem_val : std_logic;
-signal mem_ack : std_logic;
-
-signal c33_mem_ack : std_logic; --sync signal
-
-
-
-signal fl_ce_n_w : std_logic; --chip select
-signal fl_oe_n_w : std_logic; --output enable for flash
-signal fl_we_n_w : std_logic; --output enable for flash
-
-
-
---END flash signals
-
---USB signals
-signal dbg_data : STD_LOGIC_VECTOR (7 downto 0);
-signal c25_dbg_addr_d : STD_LOGIC_VECTOR (7 downto 0);
-signal c33_dbg_addr_d : STD_LOGIC_VECTOR (7 downto 0);
-
-signal dbg_wr : STD_LOGIC; --write not read
-signal dbg_full : STD_LOGIC; --write not read
-signal dbg_almost_full : STD_LOGIC;
-signal dbg_usedw : STD_LOGIC_VECTOR (12 DOWNTO 0);
-
-signal dbg_usb_mode_en : std_logic;
-signal usb_mode_en : std_logic;
-signal mem_idle : std_logic;
-signal umem_addr : std_logic_vector(23 downto 0);
-signal umem_do : std_logic_vector(15 downto 0);
-signal umem_wr : std_logic;
-signal umem_val : std_logic;
-signal umem_ack : std_logic;
-signal umem_cmd : std_logic;
-signal enable_4meg: std_logic;
-signal dongle_con_n : std_logic;
-
-signal jmp_settings : std_logic_vector(7 downto 0);
-signal jmp_value : std_logic_vector(7 downto 0);
-signal jmp_leds : std_logic_vector(7 downto 0);
-signal jmp_cnt : std_logic_vector(7 downto 0);
-
-constant dongle_ver : std_logic_vector(15 downto 0):=x"8620";
-constant pcb_ver : std_logic_vector(15 downto 0):=x"0835"; -- proj. no and PCB ver in hexademical
---END USB signals
-
-begin
-
-
-
---PSRAM static signals
-ps_lsb_en <='0';
-ps_msb_en <='0';
-ps_addr_val <='0'; --use async PSRAM access
-ps_clk <='0';
-ps_confr_en <='0';
-
-ps_ram_en <= fl_ce_n_w when mode(2)='1' else '1';
-
-
---GPIO PINS START
-fl_sts_en <='Z';
-
-
-JMP_FETCH: process (sys_clk, resetn) --c33
-begin
- if resetn = '0' then
- jmp_settings <=x"00";
- jmp_cnt <=x"00";
- jmp_leds <=x"FF";
- elsif sys_clk'event and sys_clk = '1' then -- rising clock edge
- jmp_cnt <= jmp_cnt + 1;
- if jmp_cnt = x"FE" then
- jmp_leds <= x"00"; --light leds
- elsif jmp_cnt = x"00" then
- jmp_settings <= jmp_value;
- jmp_leds <= jmp_settings; --show last settings this is ok as leds are slow
- end if;
-
- end if;
-end process JMP_FETCH;
-
-
-
-
-hdr(14) <= jmp_leds(7);
-hdr(12) <= jmp_leds(6);
-hdr(10) <= jmp_leds(5);
-hdr(8) <= jmp_leds(4);
-hdr(6) <= jmp_leds(3);
-hdr(4) <= jmp_leds(2);
-hdr(2) <= jmp_leds(1);
-hdr(0) <= jmp_leds(0);
-
-jmp_value(0) <= hdr(1);
-jmp_value(1) <= hdr(3);
-jmp_value(2) <= hdr(5);
-jmp_value(3) <= hdr(7);
-jmp_value(4) <= hdr(9);
-jmp_value(5) <= hdr(11);
-jmp_value(6) <= hdr(13);
-jmp_value(7) <= hdr(15);
-
-
-
-
---hdr(1) <= dongle_con_n; --commented out for firm rev 0x20
-
---hdr(1) <= fl_sts when resetn='1' else
--- '0';
-
---SETTING #0
---when jumper on then mem read and firmware read enabled else only firmware read
---hdr(0) <= '0'; --commented out for firm rev 0x20
-lena_mem_r <= not jmp_settings(0); -- disabled if jumper is not on header pins 1-2
-
---SETTING #1
--- jumper on pins 5,6 then postcode only mode (no mem device)
---hdr(2) <= '0'; --create low pin for jumper pair 5-6 (this pin is 6 on J1 header) --commented out for firm rev 0x20
-lena_reads <= jmp_settings(1) and mem_idle and (not dongle_con_n); -- disabled if jumper is on (jumper makes it a postcode only device) paired with hdr(2) pins 5,6 and when usb control is not accessing flash
-
-
---SETTING #2
--- when jumper on pins 7,8 then post code capture mode enabled
---hdr(4)<= '0'; --commented out for firm rev 0x20
-dbg_usb_mode_en <= not jmp_settings(2); --weak pullup on hdr(5) paired with hdr(4)
-usb_mode_en <= not dbg_usb_mode_en;
-
-
---GPIO PINS END
-
-
-
---LED SUBSYSTEM START
-data_to_disp <= x"86"&lpc_debug(7 downto 0) when usb_mode_en='1' and resetn='1' else --x"C0DE"; -- ASSIGN data to be displayed (should be regitered)
- "000"&dbg_usedw when usb_mode_en='0' and resetn='1' else
- dongle_ver; --show tx fifo state on leds when postcode capture mode
-
-
---########################################--
- --VERSION CONSTATNS
---########################################--
-led_red <= not enable_4meg;
-led_green <= not mem_val;
-
-LEDS: led_sys --toplevel for led system
- generic map(
- msn_hib => "01111111",--8 --Most signif. of hi byte
- lsn_hib => "01111101",--6 --Least signif. of hi byte
- msn_lob => "10111111",--0 --Most signif. of hi byte This is version code
- --lsn_lob => "01001111" --3 --Least signif. of hi byte This is version code
- --lsn_lob => "01100110" --4 --Least signif. of hi byte This is version code
- lsn_lob => "01101101" --5 --sync with dongle version const. Least signif. of hi byte This is version code
-
- )
- port map(
- clk => sys_clk , -- in std_logic;
- reset_n => resetn, -- in std_logic;
- led_data_i => data_to_disp, -- in std_logic_vector(15 downto 0); --binary data in
- seg_out => seg_out, -- out std_logic_vector(7 downto 0); --one segment out
- sel_out => scn_seg -- out std_logic_vector(3 downto 0) --segment scanner with one bit low
- );
-
---LED SUBSYSTEM END
-
-
---MAIN DATAPATH CONNECTIONS
---LPC bus logic
-lad_i <= lad;
-lad <= lad_o when lad_oe='1' else
- (others=>'Z');
-
---END LPC bus logic
-
-LPCBUS : lpc_iow
- port map(
- --system signals
- lreset_n => lreset_n, -- in std_logic;
- lclk => lclk, -- in std_logic;
- lena_mem_r => lena_mem_r, --: in std_logic; --enable full adress range covering memory read block
- lena_reads => lena_reads, -- : in std_logic; --enable read capabilities, : in std_logic; --enable read capabilities
- --LPC bus from host
- lad_i => lad_i, -- in std_logic_vector(3 downto 0);
- lad_o => lad_o, -- out std_logic_vector(3 downto 0);
- lad_oe => lad_oe, -- out std_logic;
- lframe_n => lframe_n, -- in std_logic;
- --memory interface
- lpc_addr => lpc_addr, -- out std_logic_vector(23 downto 0); --shared address
- lpc_wr => lpc_wr, -- out std_logic; --shared write not read
- lpc_data_i => lpc_data_i, -- in std_logic_vector(7 downto 0);
- lpc_data_o => lpc_data_o, -- out std_logic_vector(7 downto 0);
- lpc_val => lpc_val, -- out std_logic;
- lpc_ack => lpc_ack -- in std_logic
- );
-
-
---memory data bus logic
- mem_addr <= mode(1 downto 0)&"11"&lpc_addr(19 downto 0) when c25_lpc_val='1' and enable_4meg='0' else --use mode bist
- mode(1 downto 0)&lpc_addr(21 downto 0) when c25_lpc_val='1' and enable_4meg='1' else --use mode bist
- mode(1 downto 0)&umem_addr(21 downto 0) when umem_val='1' else --use mode bist
- (others=>'Z');
-
- mem_di <= (others=>'Z') when c25_lpc_val='1' else
- umem_do when umem_val='1' else
- (others=>'Z');
-
-
- mem_wr <= c25_lpc_wr when c25_lpc_val='1' and c25_lpc_wr='0' else --pass read olny
- umem_wr when umem_val='1' else
- '0';
-
- mem_val <= c25_lpc_val or umem_val;
-
-
-
- umem_ack <= mem_ack when umem_val='1' else
- '0';
-
-
- lpc_data_i <= mem_do(7 downto 0) when lpc_addr(0)='0' else
- mem_do(15 downto 8);
-
- lpc_ack <= c33_mem_ack when lpc_val='1' and lpc_wr='0' else
- (not dbg_almost_full) when lpc_val='1' and lpc_wr='1' else
- '0';
-
-
-
- SYNC1: process (lclk, lreset_n) --c33
- begin
- if lclk'event and lclk = '1' then -- rising clock edge
- c33_mem_ack <= mem_ack;
-
- end if;
- end process SYNC1;
-
-
- dbg_data <= lpc_debug(7 downto 0);
- SYNC2: process (sys_clk) --c25
- begin
- if sys_clk'event and sys_clk = '1' then -- rising clock edge
- c25_lpc_val <= lpc_val; --syncro two clock domains
- c25_lpc_wr <= c33_lpc_wr; --syncro two clock domains
- c25_dbg_addr_d <= c33_dbg_addr_d; --syncro two clock domains
- if usb_mode_en ='0' and c25_dbg_addr_d=x"80" then --don't fill fifo in regular mode
- dbg_wr<= c25_lpc_wr; --c33_lpc_wr_wait;--c33_lpc_wr_wait;
- else
- dbg_wr<='0'; --write never rises when usb_mode_en = 1
- end if;
- end if;
- end process SYNC2;
-
-
-
- LATCHled: process (lclk,lreset_n) --c33
- begin
- if lreset_n='0' then
- lpc_debug(7 downto 0)<=(others=>'0');
- c33_dbg_addr_d <=(others=>'0');
- enable_4meg <='0';
- c33_lpc_wr <='0';
- dongle_con_n <='0'; -- pin 3 in GPIO make it toggleable
- elsif lclk'event and lclk = '1' then -- rising clock edge
- c33_lpc_wr <= lpc_wr;
- if c33_lpc_wr='0' and lpc_wr='1' then
- c33_dbg_addr_d <= lpc_addr(7 downto 0);
- lpc_debug(7 downto 0)<= lpc_data_o;
- if lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"F4" then --Flash 4 Mega enable (LSN is first MSN is second)
- enable_4meg <='1';
- elsif lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"F1" then --Flash 1 Mega enalbe
- enable_4meg <='0';
- elsif lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"D1" then --Set Dongle not attached signal
- dongle_con_n <='1'; -- pin 3 in GPIO make it 1
- elsif lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"D0" then --Set Dongle attached signal
- dongle_con_n <='0'; -- pin 3 in GPIO make it 1
- end if;
- end if;
- end if;
- end process LATCHled;
-
-
-
-
-
-
---END memory data bus logic
-fl_ce_n<= fl_ce_n_w when mode(2)='0' else '1';
-fl_oe_n<= fl_oe_n_w;
-fl_we_n <= fl_we_n_w;
-
-FLASH : flash_if
- port map(
- clk => sys_clk, -- in std_logic;
- reset_n => resetn, -- in std_logic;
- mode => mode,-- : in std_logic_vector(2 downto 0); --sel upper addr bits
- --flash Bus
- fl_addr => fl_addr, -- out std_logic_vector(23 downto 0);
- fl_ce_n => fl_ce_n_w, -- out std_logic; --chip select
- fl_oe_n => fl_oe_n_w, -- buffer std_logic; --output enable for flash
- fl_we_n => fl_we_n_w, -- out std_logic; --write enable
- fl_data => fl_data, -- inout std_logic_vector(15 downto 0);
- fl_rp_n => fl_rp_n, -- out std_logic; --reset signal
- --fl_byte_n => fl_byte_n, -- out std_logic; --hold in byte mode
- fl_sts => fl_sts, -- in std_logic; --status signal
- -- mem Bus
- mem_addr => mem_addr, -- in std_logic_vector(23 downto 0);
- mem_do => mem_do, -- out std_logic_vector(15 downto 0);
- mem_di => mem_di, -- in std_logic_vector(15 downto 0);
-
- mem_wr => mem_wr, -- in std_logic; --write not read signal
- mem_val => mem_val, -- in std_logic;
- mem_ack => mem_ack -- out std_logic
- );
-
-
-
-USB: usb2mem
- port map(
- clk25 => sys_clk, -- in std_logic;
- reset_n => resetn, -- in std_logic;
- dongle_ver => dongle_ver,
- pcb_ver => pcb_ver, --: in std_logic_vector(15 downto 0);
- mode => mode,-- : in std_logic_vector(2 downto 0); --sel upper addr bits
- usb_buf_en => buf_oe_n, --: out std_logic;
- dev_present_n => ldev_present,--: out std_logic;
- -- mem Bus
- mem_busy_n=> fl_sts, --check flash status before starting new command on flash
- mem_idle => mem_idle,
- mem_addr => umem_addr, -- out std_logic_vector(23 downto 0);
- mem_do => umem_do, -- out std_logic_vector(15 downto 0);
- mem_di => mem_do, -- in std_logic_vector(15 downto 0); --from flash
- mem_wr => umem_wr, -- out std_logic;
- mem_val => umem_val, -- out std_logic;
- mem_ack => umem_ack, -- in std_logic; --from flash
- mem_cmd => umem_cmd, -- out std_logic;
- -- USB port
- usb_mode_en => usb_mode_en,
- usb_rd_n => usb_rd_n, -- out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
- usb_wr => usb_wr, -- out std_logic; -- write performed on edge \ of signal
- usb_txe_n => usb_txe_n, -- in std_logic; -- tx fifo empty (redy for new data if low)
- usb_rxf_n => usb_rxf_n, -- in std_logic; -- rx fifo empty (data redy if low)
- usb_bd => usb_bd -- inout std_logic_vector(7 downto 0) --bus data
- );
-
-
-DBG : pc_serializer
- port map ( --system signals
- sys_clk => sys_clk, -- in STD_LOGIC;
- resetn => resetn, -- in STD_LOGIC;
- --postcode data port
- dbg_data => dbg_data, -- in STD_LOGIC_VECTOR (7 downto 0);
- dbg_wr => dbg_wr, -- in STD_LOGIC; --write not read
- dbg_full => dbg_full,--: out STD_LOGIC; --write not read
- dbg_almost_full => dbg_almost_full,
- dbg_usedw => dbg_usedw,
-
- --debug USB port
- dbg_usb_mode_en=> dbg_usb_mode_en, -- in std_logic; -- enable this debug mode
- dbg_usb_wr => usb_wr, -- out std_logic; -- write performed on edge \ of signal
- dbg_usb_txe_n => usb_txe_n, -- in std_logic; -- tx fifo not full (redy for new data if low)
- dbg_usb_bd => usb_bd -- inout std_logic_vector(7 downto 0) --bus data
-);
-
-
---END MAIN DATAPATH CONNECTIONS
-
-end rtl;
-
-
-
+------------------------------------------------------------------
+-- Universal dongle board source code
+--
+-- Copyright (C) 2006 Artec Design
+--
+-- This source code is free hardware; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This source code is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+--
+--
+-- The complete text of the GNU Lesser General Public License can be found in
+-- the file 'lesser.txt'.
+
+
+-- Coding for seg_out(7:0) "01101101"
+--
+-- bit 0,A
+-- ----------
+-- | |
+-- | |
+-- 5,F| | 1,B
+-- | 6,G |
+-- ----------
+-- | |
+-- | |
+-- 4,E| | 2,C
+-- | 3,D |
+-- ----------
+-- # 7,H
+
+-- Revision history
+--
+-- Version 1.01
+-- 15 oct 2006 version code 86 01 jyrit
+-- Added IO write to address 0x0088 with commands F1 and F4 to
+-- enable switching dongle to 4Meg mode for external reads
+-- Changed USB interface to address all 4 Meg on any mode jumper configuration
+--
+-- Version 1.02
+-- 04 dec 2006 version code 86 02 jyrit
+-- Added listen only mode for mode pin configuration "00" to enable post code
+-- spy mode (does not respond to external reads).
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+use work.serial_usb_package.all;
+use work.dongle_arch.all;
+
+entity design_top is
+ port(
+ --system signals
+ sys_clk : in std_logic; --25 MHz clk
+ resetn : in std_logic;
+ hdr : inout std_logic_vector(15 downto 0);
+ hdr_b : inout std_logic_vector(15 downto 0);
+ --alt_clk : out std_logic;
+
+ mode : inout std_logic_vector(2 downto 0); --sel upper addr bits
+ --lpc slave interf
+ lad : inout std_logic_vector(3 downto 0);
+ lframe_n : in std_logic;
+ lreset_n : in std_logic;
+ lclk : in std_logic;
+ ldev_present : out std_logic;
+ lserirq : inout std_logic;
+ --led system
+ seg_out : out std_logic_vector(7 downto 0);
+ scn_seg : out std_logic_vector(3 downto 0);
+ scn_seg2 : out std_logic_vector(3 downto 0); --parallel line to get more current
+
+ led_green : out std_logic;
+ led_red : out std_logic;
+ --flash interface
+ fl_addr : out std_logic_vector(23 downto 0);
+ fl_ce_n : out std_logic; --chip select
+ fl_oe_n : out std_logic; --output enable for flash
+ fl_we_n : out std_logic; --write enable
+ fl_data : inout std_logic_vector(15 downto 0);
+ fl_rp_n : out std_logic; --reset signal
+ fl_sts : in std_logic; --status signal
+ fl_sts_en : out std_logic; --enable status signal wiht highZ out
+ -- PSRAM aditional signals to flash
+ ps_ram_en : out std_logic;
+ ps_clk : out std_logic; --PSRAM clock
+ ps_wait : in std_logic;
+ ps_addr_val : out std_logic; --active low
+ ps_confr_en : out std_logic;
+ ps_lsb_en : out std_logic;
+ ps_msb_en : out std_logic;
+ -- EEPROM signals
+-- ee_di : out std_logic;
+-- ee_do : in std_logic;
+-- ee_hold_n : out std_logic;
+-- ee_cs_n : out std_logic;
+-- ee_clk : out std_logic;
+-- ee_write : out std_logic;
+ -- PROG enable
+ buf_oe_n : out std_logic;
+ --USB parallel interface
+ usb_rd_n : out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
+ usb_wr : out std_logic; -- write performed on edge \ of signal
+ usb_txe_n : in std_logic; -- transmit enable (redy for new data if low)
+ usb_rxf_n : in std_logic; -- rx fifo has data if low
+ usb_bd : inout std_logic_vector(7 downto 0) --bus data
+ );
+end design_top;
+
+architecture rtl of design_top is
+ component led_sys --toplevel for led system
+ generic(
+ msn_hib : std_logic_vector(7 downto 0); --Most signif. of hi byte
+ lsn_hib : std_logic_vector(7 downto 0); --Least signif. of hi byte
+ msn_lob : std_logic_vector(7 downto 0); --Most signif. of hi byte
+ lsn_lob : std_logic_vector(7 downto 0) --Least signif. of hi byte
+ );
+ port(
+ clk : in std_logic;
+ reset_n : in std_logic;
+ led_data_i : in std_logic_vector(15 downto 0); --binary data in
+ seg_out : out std_logic_vector(7 downto 0); --one segment out
+ sel_out : out std_logic_vector(3 downto 0) --segment scanner with one bit low
+ );
+ end component;
+
+ component lpc_iow
+ port(
+ --system signals
+ lreset_n : in std_logic;
+ lclk : in std_logic;
+ lena_mem_r : in std_logic; --enable full adress range covering memory read block
+ lena_reads : in std_logic; --enable read capabilities
+ uart_addr : in std_logic_vector(15 downto 0); -- define UART address to listen to
+ --LPC bus from host
+ lad_i : in std_logic_vector(3 downto 0);
+ lad_o : out std_logic_vector(3 downto 0);
+ lad_oe : out std_logic;
+ lframe_n : in std_logic;
+ --memory interface
+ lpc_addr : out std_logic_vector(23 downto 0); --shared address
+ lpc_wr : out std_logic; --shared write not read
+ lpc_io : out std_logic; --io access not mem access select
+ lpc_uart : out std_logic; --uart mapped cycle coming
+ lpc_gpioled: out std_logic; --gpio led cycle coming
+ lpc_data_i : in std_logic_vector(7 downto 0);
+ lpc_data_o : out std_logic_vector(7 downto 0);
+ lpc_val : out std_logic;
+ lpc_ack : in std_logic
+ );
+ end component;
+
+ component flash_if
+ port(
+ clk : in std_logic;
+ reset_n : in std_logic;
+ mode : in std_logic_vector(2 downto 0); --sel upper addr bits
+ --flash Bus
+ fl_addr : out std_logic_vector(23 downto 0);
+ fl_ce_n : out std_logic; --chip select
+ fl_oe_n : out std_logic; --output enable for flash
+ fl_we_n : out std_logic; --write enable
+ fl_data : inout std_logic_vector(15 downto 0);
+ fl_rp_n : out std_logic; --reset signal
+ fl_byte_n : out std_logic; --hold in byte mode
+ fl_sts : in std_logic; --status signal
+ -- mem Bus
+ mem_addr : in std_logic_vector(23 downto 0);
+ mem_do : out std_logic_vector(15 downto 0);
+ mem_di : in std_logic_vector(15 downto 0);
+ mem_wr : in std_logic; --write not read signal
+ mem_val : in std_logic;
+ mem_ack : out std_logic
+ );
+ end component;
+
+ component usb2mem
+ port(
+ clk25 : in std_logic;
+ reset_n : in std_logic;
+ dongle_ver : in std_logic_vector(15 downto 0);
+ pcb_ver : in std_logic_vector(15 downto 0);
+ mode : in std_logic_vector(2 downto 0); --sel upper addr bits
+ usb_buf_en : out std_logic;
+ dev_present_n : out std_logic;
+ -- mem Bus
+ mem_busy_n : in std_logic;
+ mem_idle : out std_logic; -- '1' if controller is idle (flash is safe for LPC reads)
+ mem_addr : out std_logic_vector(23 downto 0);
+ mem_do : out std_logic_vector(15 downto 0);
+ mem_di : in std_logic_vector(15 downto 0);
+ mem_wr : out std_logic;
+ mem_val : out std_logic;
+ mem_ack : in std_logic;
+ mem_cmd : out std_logic;
+ -- USB port
+ usb_mode_en : in std_logic; -- enable this block
+ usb_rd_n : out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
+ usb_wr : out std_logic; -- write performed on edge \ of signal
+ usb_txe_n : in std_logic; -- tx fifo empty (redy for new data if low)
+ usb_rxf_n : in std_logic; -- rx fifo empty (data redy if low)
+ usb_bd_o : out std_logic_vector(7 downto 0); --bus data
+ usb_bd : in std_logic_vector(7 downto 0) --bus data
+ );
+ end component;
+
+ component pc_serializer
+ Port( --system signals
+ sys_clk : in STD_LOGIC;
+ resetn : in STD_LOGIC;
+ --postcode data port
+ dbg_data : in STD_LOGIC_VECTOR(7 downto 0);
+ dbg_wr : in STD_LOGIC; --write not read
+ dbg_full : out STD_LOGIC; --write not read
+ dbg_almost_full : out STD_LOGIC;
+ dbg_usedw : out STD_LOGIC_VECTOR(12 DOWNTO 0);
+ --debug USB port
+ dbg_usb_mode_en : in std_logic; -- enable this debug mode
+ dbg_usb_wr : out std_logic; -- write performed on edge \ of signal
+ dbg_usb_txe_n : in std_logic; -- tx fifo not full (redy for new data if low)
+ dbg_usb_bd : out std_logic_vector(7 downto 0) --bus data
+ );
+ end component;
+
+ component serial_usb
+ port(
+ clock : in std_logic;
+ reset_n : in std_logic;
+ --VCI Port
+ vci_in : in vci_slave_in;
+ vci_out : out vci_slave_out;
+ --FTDI fifo interface
+ uart_ena : in usbser_ctrl;
+ fifo_out : out usb_out;
+ fifo_in : in usb_in
+ );
+ end component;
+
+ component serirq
+ port (
+ clock : in std_logic;
+ reset_n : in std_logic;
+ slot_sel : in std_logic_vector(4 downto 0); --clk no of IRQ defined in Ser irq for PCI systems spec.
+ serirq : inout std_logic;
+ irq : in std_logic
+ );
+ end component;
+
+
+ --LED signals
+ signal data_to_disp : std_logic_vector(15 downto 0);
+
+ signal scn_seg_w : std_logic_vector(3 downto 0);
+ --END LED SIGNALS
+
+ --lpc signals
+ signal lad_i : std_logic_vector(3 downto 0);
+ signal lad_o : std_logic_vector(3 downto 0);
+ signal lad_oe : std_logic;
+
+ signal lpc_debug : std_logic_vector(31 downto 0);
+ signal lpc_debug_cnt : std_logic_vector(15 downto 0);
+ signal lpc_addr : std_logic_vector(23 downto 0); --shared address
+ signal lpc_data_o : std_logic_vector(7 downto 0);
+ signal lpc_data_i : std_logic_vector(7 downto 0);
+ signal lpc_wr : std_logic; --shared write not read
+ signal lpc_io : std_logic; --io cycle not mem cycle
+ signal lpc_uart : std_logic; --uart mapped cycle coming
+ signal lpc_gpioled : std_logic; --gpio led cycle coming
+ signal lpc_ack : std_logic;
+ signal lpc_val : std_logic;
+ signal lena_mem_r : std_logic; --enable full adress range covering memory read block
+ signal lena_reads : std_logic; --enable/disables all read capabilty to make the device post code capturer
+
+ signal c25_lpc_val : std_logic;
+ signal c25_lpc_io : std_logic;
+ signal c25_lpc_uart : std_logic;
+ signal c25_lpc_wr : std_logic; --shared write not read
+ signal c25_lpc_wr_long : std_logic; --for led debug data latching
+
+ signal c33_lpc_wr_long : std_logic; --for led debug data latching
+ signal c33_lpc_wr : std_logic; --for led debug data latching
+ signal c33_lpc_wr_wait : std_logic; --for led debug data latching
+ signal c33_lpc_wr_waitd : std_logic; --for led debug data latching
+ signal c33_wr_cnt : std_logic_vector(23 downto 0); --for led debug data latching
+ signal c33_led_ack : std_logic; --for led debug data latching
+
+
+ --End lpc signals
+
+ --Flash signals
+ signal mem_addr : std_logic_vector(23 downto 0);
+ signal mem_do : std_logic_vector(15 downto 0);
+ signal mem_di : std_logic_vector(15 downto 0);
+ signal mem_wr : std_logic; --write not read signal
+ signal mem_val : std_logic;
+ signal mem_ack : std_logic;
+
+ signal c33_mem_ack : std_logic; --sync signal
+
+
+ signal fl_ce_n_w : std_logic; --chip select
+ signal fl_oe_n_w : std_logic; --output enable for flash
+ signal fl_we_n_w : std_logic; --output enable for flash
+
+
+ --END flash signals
+
+ -- UART signals
+ signal uart_addr : std_logic_vector(15 downto 0); -- define UART address to listen to
+ signal uart_name : STD_LOGIC_VECTOR(7 downto 0);
+ signal clock : std_logic;
+ signal reset_n : std_logic;
+
+ signal pc_loop_en : std_logic;
+ --VCI Port
+ signal uart_vci_in : vci_slave_in;
+ signal uart_vci_out : vci_slave_out;
+ --FTDI fifo interface
+ signal uart_ena : usbser_ctrl;
+ signal uart_fifo_out : usb_out;
+ signal uart_fifo_in : usb_in;
+ signal c33_uart_ack : std_logic;
+ -- end UART
+
+ --USB signals
+ signal dbg_data : STD_LOGIC_VECTOR(7 downto 0);
+ signal c25_dbg_addr_d : STD_LOGIC_VECTOR(7 downto 0);
+ signal c33_dbg_addr_d : STD_LOGIC_VECTOR(7 downto 0);
+
+ signal dbg_wr : STD_LOGIC; --write not read
+ signal c25_dbg_wr : STD_LOGIC; --write not read
+ signal dbg_usb_wr : STD_LOGIC;
+ --signal dbg_full : STD_LOGIC; --write not read
+ signal dbg_almost_full : STD_LOGIC;
+ signal dbg_usedw : STD_LOGIC_VECTOR(12 DOWNTO 0);
+ signal dbg_usb_bd : STD_LOGIC_VECTOR(7 downto 0);
+
+ signal dbg_usb_mode_en : std_logic;
+ signal usb_mode_en : std_logic;
+ signal mem_usb_rd_n : std_logic;
+ signal mem_usb_wr : std_logic;
+ signal mem_usb_bd_o : STD_LOGIC_VECTOR(7 downto 0);
+
+ signal mem_idle : std_logic;
+ signal umem_addr : std_logic_vector(23 downto 0);
+ signal umem_do : std_logic_vector(15 downto 0);
+ signal umem_wr : std_logic;
+ signal umem_val : std_logic;
+ signal umem_ack : std_logic;
+ --signal umem_cmd : std_logic;
+ signal enable_4meg : std_logic;
+ signal enable_4meg_r : std_logic; --4 meg ena register
+
+ signal dongle_con_n : std_logic; -- set by device side/unset with IO write to enable/disalbe dongle memory
+
+ signal ldev_present_w : std_logic; --output from USB subsystem to show what command has been sent by PC
+
+ signal slot_sel : std_logic_vector(4 downto 0);
+
+ signal com_force : std_logic_vector(3 downto 0);
+ signal jmp_io_leds : std_logic_vector(7 downto 0);
+
+ signal c33_jmp_settings : std_logic_vector(7 downto 0);
+ signal jmp_settings : std_logic_vector(7 downto 0);
+ signal jmp_value : std_logic_vector(7 downto 0);
+ signal jmp_leds : std_logic_vector(7 downto 0);
+ signal jmp_cnt : std_logic_vector(7 downto 0);
+
+ constant dongle_ver : std_logic_vector(15 downto 0) := x"8623";
+ constant pcb_ver : std_logic_vector(15 downto 0) := x"0836"; -- proj. no and PCB ver in hexademical
+--END USB signals
+
+begin
+
+ --PSRAM static signals
+ ps_lsb_en <= '0';
+ ps_msb_en <= '0';
+ ps_addr_val <= '0'; --use async PSRAM access
+ ps_clk <= '0';
+ ps_confr_en <= '0';
+
+ ps_ram_en <= fl_ce_n_w when mode(2) = '1' else
+ '1';
+
+ --GPIO PINS START
+ fl_sts_en <= 'Z';
+
+ JMP_FETCH : process(sys_clk, resetn) --c33
+ begin
+ if resetn = '0' then
+ jmp_settings <= x"00";
+ jmp_cnt <= x"00";
+ jmp_leds <= x"FF";
+ elsif sys_clk'event and sys_clk = '1' then -- rising clock edge
+ jmp_cnt <= jmp_cnt + 1;
+ if jmp_cnt = x"FE" then
+ jmp_leds <= x"00"; --light leds
+ elsif jmp_cnt = x"00" then
+ jmp_settings <= jmp_value;
+ jmp_leds <= jmp_io_leds; --show last settings this is ok as leds are slow
+ end if;
+
+ end if;
+ end process JMP_FETCH;
+
+ hdr(14) <= jmp_leds(7);
+ hdr(12) <= jmp_leds(6);
+ hdr(10) <= jmp_leds(5);
+ hdr(8) <= jmp_leds(4);
+ hdr(6) <= jmp_leds(3);
+ hdr(4) <= jmp_leds(2);
+ hdr(2) <= jmp_leds(1);
+ hdr(0) <= jmp_leds(0);
+
+ jmp_value(0) <= hdr(1); --3,4
+ jmp_value(1) <= hdr(3); --5,6
+ jmp_value(2) <= hdr(5); --7,8
+ jmp_value(3) <= hdr(7); --9,10
+ jmp_value(4) <= hdr(9); --11,12
+ jmp_value(5) <= hdr(11);--13,14
+ jmp_value(6) <= hdr(13);
+ jmp_value(7) <= hdr(15);
+
+ --hdr(1) <= dongle_con_n; --commented out for firm rev 0x20
+
+ --hdr(1) <= fl_sts when resetn='1' else
+ -- '0';
+
+ --SETTING #0
+ --when jumper on then mem read and firmware read enabled else only firmware read
+ --hdr(0) <= '0'; --commented out for firm rev 0x20
+ lena_mem_r <= not jmp_settings(0); -- disabled if jumper is not on header pins 1-2
+
+ --SETTING #1
+ -- jumper on pins 5,6 then postcode only mode (no mem device)
+ --hdr(2) <= '0'; --create low pin for jumper pair 5-6 (this pin is 6 on J1 header) --commented out for firm rev 0x20
+ lena_reads <= jmp_settings(1) and mem_idle and(not dongle_con_n); -- disabled if jumper is on (jumper makes it a postcode only device) paired with hdr(2) pins 5,6 and when usb control is not accessing flash
+
+ --ldev_present_w is active low '1' menaing not present ;)
+ ldev_present <= '1' when lena_reads = '0' and ldev_present_w = '0' else --when jumper or IO disable and USB ena bit is default then look disconnected
+ '1' when ldev_present_w = '1' else --when dev present is removed from USB override jumper and LPC IO
+ '0';
+
+ --SETTING #2
+ -- when jumpers on pins 7,8| 9,10 | 11,12 > jmp_settings (2,3,4) (need inverting as on is '0')
+ -- off,off,off PC utility access enabled > 111
+ -- off,off,on UART on base address 0x3F8 > 110
+ -- off,on,off UART on base address 0x2F8 > 101
+ -- off,on,on UART on base address 0x3E8 > 100
+ -- on,on,on UART on base address 0x2E8 > 000
+ -- on,on,off pc side UART loop ena > 001
+ -- on,off,off post code capture mode enabled > 011
+
+ uart_addr <=x"03F8" when com_force(2 downto 0)="001" else
+ x"02F8" when com_force(2 downto 0)="010" else
+ x"03E8" when com_force(2 downto 0)="011" else
+ x"02E8" when com_force(2 downto 0)="100" else
+ x"03F8" when jmp_settings(4 downto 2)="011" else
+ x"02F8" when jmp_settings(4 downto 2)="101" else
+ x"03E8" when jmp_settings(4 downto 2)="001" else
+ x"02E8" when jmp_settings(4 downto 2)="000" else
+ x"0000"; --uart diabled as bit 3 is 0
+
+ slot_sel <= "01011" when com_force(2 downto 0)="010" or com_force(2 downto 0)="100" else
+ "01110" when com_force(2 downto 0)="001" or com_force(2 downto 0)="011" else
+ "01011" when jmp_settings(4 downto 2)="101" or jmp_settings(4 downto 2)="000" else
+ "01110" when jmp_settings(4 downto 2)="011" or jmp_settings(4 downto 2)="001" else
+ "00000";
+
+ uart_name<=x"C1" when com_force(2 downto 0)="001" else
+ x"C2" when com_force(2 downto 0)="010" else
+ x"C3" when com_force(2 downto 0)="011" else
+ x"C4" when com_force(2 downto 0)="100" else
+ x"C1" when jmp_settings(4 downto 2)="011" else
+ x"C2" when jmp_settings(4 downto 2)="101" else
+ x"C3" when jmp_settings(4 downto 2)="001" else
+ x"C4" when jmp_settings(4 downto 2)="000" else
+ x"00"; --uart diabled as bit 3 is 0
+
+ --SETTING #3
+ -- when jumper on pins 13, 14 mem window override to 4Meg mode (Used for intel atom boot) jmp_settings(5)
+ -- look at the LATCHled process enable_4meg signal
+
+
+ uart_ena.mode_en <= uart_addr(3); -- when bit3 is up in addr uart is enabled
+
+ dbg_usb_mode_en <= '1' when jmp_settings(4 downto 2)="110" else --post code logging
+ '0';
+
+ usb_mode_en <= '1' when jmp_settings(4 downto 2)="111" else --all off is pc mode
+ '0';
+
+
+
+ --GPIO PINS END
+
+
+ --LED SUBSYSTEM START
+ data_to_disp <= x"86" & lpc_debug(7 downto 0) when usb_mode_en = '1' and resetn = '1' else --x"C0DE"; -- ASSIGN data to be displayed (should be regitered)
+ uart_name&lpc_debug(7 downto 0) when uart_ena.mode_en='1' and resetn = '1' else
+ "000" & dbg_usedw when usb_mode_en = '0' and resetn = '1' else
+ dongle_ver; --show tx fifo state on leds when postcode capture mode
+
+
+ --########################################--
+ --VERSION CONSTATNS
+ --########################################--
+ led_red <= not enable_4meg;
+ led_green <= not mem_val;
+
+ LEDS : led_sys --toplevel for led system
+ generic map(
+ msn_hib => "10111111", -- not used "01111111",--8 --Most signif. of hi byte
+ lsn_hib => "10111111", -- not used "01111101",--6 --Least signif. of hi byte
+ msn_lob => "10111111", -- not used 0 --Most signif. of hi byte This is version code
+ --lsn_lob => "01001111"-- not used 3 --Least signif. of hi byte This is version code
+ --lsn_lob => "01100110"-- not used 4 --Least signif. of hi byte This is version code
+ --lsn_lob => "01101101"-- not used 5 --sync with dongle version const. Least signif. of hi byte This is version code
+ lsn_lob => "10111111" -- not used
+ )
+ port map(
+ clk => sys_clk, -- in std_logic;
+ reset_n => resetn, -- in std_logic;
+ led_data_i => data_to_disp, -- in std_logic_vector(15 downto 0); --binary data in
+ seg_out => seg_out, -- out std_logic_vector(7 downto 0); --one segment out
+ sel_out => scn_seg_w -- out std_logic_vector(3 downto 0) --segment scanner with one bit low
+ );
+
+ scn_seg <= scn_seg_w;
+ scn_seg2 <= scn_seg_w;
+
+ --LED SUBSYSTEM END
+
+
+ --MAIN DATAPATH CONNECTIONS
+ --LPC bus logic
+ lad_i <= lad;
+ lad <= lad_o when lad_oe = '1' else(others => 'Z');
+
+ --END LPC bus logic
+
+ LPCBUS : lpc_iow
+ port map(
+ --system signals
+ lreset_n => lreset_n, -- in std_logic;
+ lclk => lclk, -- in std_logic;
+ lena_mem_r => lena_mem_r, --: in std_logic; --enable full adress range covering memory read block
+ lena_reads => lena_reads, -- : in std_logic; --enable read capabilities, : in std_logic; --enable read capabilities
+ uart_addr => uart_addr,
+ --LPC bus from host
+ lad_i => lad_i, -- in std_logic_vector(3 downto 0);
+ lad_o => lad_o, -- out std_logic_vector(3 downto 0);
+ lad_oe => lad_oe, -- out std_logic;
+ lframe_n => lframe_n, -- in std_logic;
+ --memory interface
+ lpc_addr => lpc_addr, -- out std_logic_vector(23 downto 0); --shared address
+ lpc_wr => lpc_wr, -- out std_logic; --shared write not read
+ lpc_io => lpc_io, --: out std_logic; --io access not mem access select
+ lpc_uart => lpc_uart,
+ lpc_gpioled=> lpc_gpioled, --: out std_logic; --gpio led cycle coming
+ lpc_data_i => lpc_data_i, -- in std_logic_vector(7 downto 0);
+ lpc_data_o => lpc_data_o, -- out std_logic_vector(7 downto 0);
+ lpc_val => lpc_val, -- out std_logic;
+ lpc_ack => lpc_ack -- in std_logic
+ );
+
+ --memory data bus logic
+ mem_addr <= mode(1 downto 0) & "11" & lpc_addr(19 downto 0) when c25_lpc_val = '1' and enable_4meg = '0' else --use mode bist
+ mode(1 downto 0) & lpc_addr(21 downto 0) when c25_lpc_val = '1' and enable_4meg = '1' else --use mode bist
+ mode(1 downto 0) & umem_addr(21 downto 0) when umem_val = '1' else --use mode bist
+(others => 'Z');
+
+ mem_di <=(others => 'Z') when c25_lpc_val = '1' else
+ umem_do when umem_val = '1' else(others => 'Z');
+
+ mem_wr <= c25_lpc_wr when c25_lpc_val = '1' and c25_lpc_wr = '0' else --pass read olny
+ umem_wr when umem_val = '1' else
+ '0';
+
+ mem_val <= (c25_lpc_val and not c25_lpc_io) or umem_val;
+
+ umem_ack <= mem_ack when umem_val = '1' else
+ '0';
+
+ uart_vci_in.lpc_val <= c25_lpc_val when c25_lpc_uart='1' else
+ '0';
+ uart_vci_in.lpc_wr <= c25_lpc_wr; --can be connected as val is needed to do the cycle
+
+ uart_vci_in.lpc_addr <= x"000"&'0'&lpc_addr(2 downto 0); --these are stable when val is up so sync needed
+ uart_vci_in.lpc_data_o <= lpc_data_o; --these are stable when val is up so sync needed
+
+ lpc_data_i <= mem_do(7 downto 0) when lpc_addr(0) = '0' and lpc_io='0' else
+ mem_do(15 downto 8) when lpc_io='0' else
+ c33_jmp_settings when lpc_gpioled='1' and lpc_io='1' else -- IO read to 0x84 (jumper status)
+ uart_vci_out.lpc_data_i when lpc_uart='1' and lpc_io='1' else --IO read data for UART
+ (others=>'0');
+
+ lpc_ack <= c33_mem_ack when lpc_val = '1' and lpc_wr = '0' and lpc_io='0' else --all mem cycles
+ c33_uart_ack when lpc_val = '1' and lpc_io='1' and lpc_uart='1' else --we have UART bound IO cycle
+ c33_led_ack when lpc_val = '1' and lpc_io='1' and lpc_gpioled='1' else --we have IO 0x84 acking bound IO cycle this needs no wait so the ack can be looped back
+ (not dbg_almost_full) when lpc_val = '1' and lpc_wr = '1' and lpc_io='1' else --debug write to 80 and 88 IO cycle
+ '0';
+
+ SYNC1 : process(lclk, lreset_n) --c33
+ begin
+ if lclk'event and lclk = '1' then -- rising clock edge
+ c33_mem_ack <= mem_ack;
+ c33_uart_ack <= uart_vci_out.lpc_ack;
+ c33_led_ack<= lpc_val; --loop val back to ack for leds
+ end if;
+ end process SYNC1;
+
+ dbg_data <= lpc_debug(7 downto 0);
+ SYNC2 : process(sys_clk) --c25
+ begin
+ if sys_clk'event and sys_clk = '1' then -- rising clock edge
+ c25_lpc_val <= lpc_val; --syncro two clock domains
+ c25_lpc_io <= lpc_io;
+ c25_lpc_uart <= lpc_uart;
+ c25_lpc_uart <= lpc_uart;
+ c25_lpc_wr <= lpc_wr; --syncro two clock domains
+ c25_dbg_wr <= c33_lpc_wr; --delayed write
+ c25_dbg_addr_d <= c33_dbg_addr_d; --syncro two clock domains
+ if uart_ena.mode_en='0' and usb_mode_en = '0' and c25_dbg_addr_d = x"80" and c25_lpc_io='1' then --don't fill fifo in regular mode
+ dbg_wr <= c25_lpc_wr; --c33_lpc_wr_wait;--c33_lpc_wr_wait;
+ else
+ dbg_wr <= '0'; --write never rises when usb_mode_en = 1
+ end if;
+ end if;
+ end process SYNC2;
+
+ LATCHled : process(lclk, lreset_n) --c33
+ begin
+ if lreset_n = '0' then
+ lpc_debug(7 downto 0) <=(others => '0');
+ c33_dbg_addr_d <=(others => '0');
+ jmp_io_leds<=(others => '1');
+ com_force<=(others =>'0');
+ enable_4meg <= '0';
+ enable_4meg_r <= '0';
+ c33_lpc_wr <= '0';
+ dongle_con_n <= '0'; -- pin 3 in GPIO make it toggleable
+ elsif lclk'event and lclk = '1' then -- rising clock edge
+
+
+ if lpc_val = '1' and lpc_io='1' and lpc_gpioled='1' then
+ jmp_io_leds<=not lpc_data_o;
+ end if;
+ c33_jmp_settings<=not jmp_settings; --invert for better understanding jumper on is
+ c33_lpc_wr <= lpc_wr;
+ if c33_lpc_wr = '0' and lpc_wr = '1' and lpc_io='1' then
+ c33_dbg_addr_d <= lpc_addr(7 downto 0);
+ if lpc_addr(7 downto 0) = x"80" then
+ lpc_debug(7 downto 0) <= lpc_data_o;
+ end if;
+
+ if lpc_addr(7 downto 0) = x"88" and lpc_data_o = x"F4" then --Flash 4 Mega enable (LSN is first MSN is second)
+ enable_4meg_r <= '1';
+ elsif lpc_addr(7 downto 0) = x"88" and lpc_data_o = x"F1" then --Flash 1 Mega enalbe
+ enable_4meg_r <= '0';
+ elsif lpc_addr(7 downto 0) = x"88" and lpc_data_o = x"D1" then --Set Dongle not attached signal
+ dongle_con_n <= '1'; -- pin 3 in GPIO make it 1
+ elsif lpc_addr(7 downto 0) = x"88" and lpc_data_o = x"D0" then --Set Dongle attached signal
+ dongle_con_n <= '0'; -- pin 3 in GPIO make it 1
+ elsif lpc_addr(7 downto 0) = x"88" and lpc_data_o = x"C1" then --Set Dongle attached signal
+ com_force<=x"1";
+ elsif lpc_addr(7 downto 0) = x"88" and lpc_data_o = x"C2" then --Set Dongle attached signal
+ com_force<=x"2";
+ elsif lpc_addr(7 downto 0) = x"88" and lpc_data_o = x"C3" then --Set Dongle attached signal
+ com_force<=x"3";
+ elsif lpc_addr(7 downto 0) = x"88" and lpc_data_o = x"C4" then --Set Dongle attached signal
+ com_force<=x"4";
+ end if;
+ end if;
+ if jmp_settings(5)='0' then --0 is jumper on, meaning force 4 M mode
+ enable_4meg<='1';
+ else
+ enable_4meg<=enable_4meg_r;
+ end if;
+
+ end if;
+ end process LATCHled;
+
+ --END memory data bus logic
+ fl_ce_n <= fl_ce_n_w when mode(2) = '0' else
+ '1';
+ fl_oe_n <= fl_oe_n_w;
+ fl_we_n <= fl_we_n_w;
+
+ FLASH : flash_if
+ port map(
+ clk => sys_clk, -- in std_logic;
+ reset_n => resetn, -- in std_logic;
+ mode => mode, -- : in std_logic_vector(2 downto 0); --sel upper addr bits
+ --flash Bus
+ fl_addr => fl_addr, -- out std_logic_vector(23 downto 0);
+ fl_ce_n => fl_ce_n_w, -- out std_logic; --chip select
+ fl_oe_n => fl_oe_n_w, -- buffer std_logic; --output enable for flash
+ fl_we_n => fl_we_n_w, -- out std_logic; --write enable
+ fl_data => fl_data, -- inout std_logic_vector(15 downto 0);
+ fl_rp_n => fl_rp_n, -- out std_logic; --reset signal
+ --fl_byte_n => fl_byte_n, -- out std_logic; --hold in byte mode
+
+ fl_sts => fl_sts, -- in std_logic; --status signal
+ -- mem Bus
+ mem_addr => mem_addr, -- in std_logic_vector(23 downto 0);
+ mem_do => mem_do, -- out std_logic_vector(15 downto 0);
+ mem_di => mem_di, -- in std_logic_vector(15 downto 0);
+
+ mem_wr => mem_wr, -- in std_logic; --write not read signal
+ mem_val => mem_val, -- in std_logic;
+ mem_ack => mem_ack -- out std_logic
+ );
+
+ USB : usb2mem
+ port map(
+ clk25 => sys_clk, -- in std_logic;
+ reset_n => resetn, -- in std_logic;
+ dongle_ver => dongle_ver,
+ pcb_ver => pcb_ver, --: in std_logic_vector(15 downto 0);
+ mode => mode, -- : in std_logic_vector(2 downto 0); --sel upper addr bits
+ usb_buf_en => buf_oe_n, --: out std_logic;
+ dev_present_n => ldev_present_w, --: out std_logic;
+ -- mem Bus
+ mem_busy_n => fl_sts, --check flash status before starting new command on flash
+ mem_idle => mem_idle,
+ mem_addr => umem_addr, -- out std_logic_vector(23 downto 0);
+ mem_do => umem_do, -- out std_logic_vector(15 downto 0);
+ mem_di => mem_do, -- in std_logic_vector(15 downto 0); --from flash
+ mem_wr => umem_wr, -- out std_logic;
+ mem_val => umem_val, -- out std_logic;
+ mem_ack => umem_ack, -- in std_logic; --from flash
+ mem_cmd => open, -- out std_logic;
+ -- USB port
+ usb_mode_en => usb_mode_en,
+ usb_rd_n => mem_usb_rd_n, -- out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
+ usb_wr => mem_usb_wr, -- out std_logic; -- write performed on edge \ of signal
+ usb_txe_n => usb_txe_n, -- in std_logic; -- tx fifo empty (redy for new data if low)
+ usb_rxf_n => usb_rxf_n, -- in std_logic; -- rx fifo empty (data redy if low)
+ usb_bd_o => mem_usb_bd_o,
+ usb_bd => usb_bd -- in std_logic_vector(7 downto 0) --bus data
+ );
+
+ DBG : pc_serializer
+ port map( --system signals
+ sys_clk => sys_clk, -- in STD_LOGIC;
+ resetn => resetn, -- in STD_LOGIC;
+ --postcode data port
+ dbg_data => dbg_data, -- in STD_LOGIC_VECTOR (7 downto 0);
+ dbg_wr => dbg_wr, -- in STD_LOGIC; --write not read
+ dbg_full => open, --: out STD_LOGIC; --write not read
+ dbg_almost_full => dbg_almost_full,
+ dbg_usedw => dbg_usedw,
+
+ --debug USB port
+ dbg_usb_mode_en => dbg_usb_mode_en, -- in std_logic; -- enable this debug mode
+ dbg_usb_wr => dbg_usb_wr, -- out std_logic; -- write performed on edge \ of signal
+ dbg_usb_txe_n => usb_txe_n, -- in std_logic; -- tx fifo not full (redy for new data if low)
+ dbg_usb_bd => dbg_usb_bd -- out std_logic_vector(7 downto 0) --bus data
+ );
+
+ UART : serial_usb
+ port map (
+ clock => sys_clk, -- in std_logic;
+ reset_n => resetn, -- in std_logic;
+ --VCI Port
+ vci_in => uart_vci_in, -- in vci_slave_in;
+ vci_out => uart_vci_out, -- out vci_slave_out;
+ --FTDI fifo interface
+ uart_ena => uart_ena, -- in usbser_ctrl;
+ fifo_out => uart_fifo_out, -- out usb_out;
+ fifo_in => uart_fifo_in -- in usb_in
+ );
+
+ usb_rd_n <= mem_usb_rd_n when usb_mode_en='1' else --usb to mem reads fom fifo
+ uart_fifo_out.rx_oe_n when uart_ena.mode_en='1' else --UART read
+ '1'; --keep high
+
+ usb_wr <= uart_fifo_out.tx_wr when uart_ena.mode_en='1' else
+ mem_usb_wr when usb_mode_en='1' else
+ dbg_usb_wr when dbg_usb_mode_en='1' else
+ '0';
+
+ usb_bd <= uart_fifo_out.txdata when uart_ena.mode_en='1' and uart_fifo_out.tx_wr='1' else
+ dbg_usb_bd when dbg_usb_mode_en='1' and dbg_usb_wr='1' else
+ mem_usb_bd_o when usb_mode_en='1' and mem_usb_wr='1' else
+ (others=>'Z');
+
+
+ uart_fifo_in.rxdata <= usb_bd; --this can be in most of the time
+ uart_fifo_in.rx_full_n <= usb_rxf_n; --if low there is data
+ uart_fifo_in.tx_empty_n <= usb_txe_n; --if low data can be transmitted
+
+
+ irqgen : serirq
+ port map (
+ clock => lclk, -- in std_logic;
+ reset_n => lreset_n, -- in std_logic;
+ slot_sel => slot_sel, -- in std_logic_vector(4 downto 0); --clk no of IRQ defined in Ser irq for PCI systems spec.
+ serirq => lserirq, -- inout std_logic;
+ irq => uart_vci_out.lpc_irq -- in std_logic;
+ );
+
+--END MAIN DATAPATH CONNECTIONS
+
+end rtl;
+
+
+
Index: artec_dongle_ii_fpga/trunk/src/flash/flsh_if.vhd
===================================================================
--- artec_dongle_ii_fpga/trunk/src/flash/flsh_if.vhd (revision 8)
+++ artec_dongle_ii_fpga/trunk/src/flash/flsh_if.vhd (revision 9)
@@ -1,136 +1,136 @@
-------------------------------------------------------------------
--- Universal dongle board source code
---
--- Copyright (C) 2006 Artec Design
---
--- This source code is free hardware; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
---
--- This source code is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--- Lesser General Public License for more details.
---
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
---
---
--- The complete text of the GNU Lesser General Public License can be found in
--- the file 'lesser.txt'.
-
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-use IEEE.std_logic_arith.all;
-
-entity flash_if is
- port (
- clk : in std_logic;
- reset_n : in std_logic;
- mode : in std_logic_vector(2 downto 0); --sel upper addr bits
- --flash Bus
- fl_addr : out std_logic_vector(23 downto 0);
- fl_ce_n : out std_logic; --chip select (timing is very chip dependent)
- fl_oe_n : out std_logic; --output enable for flash (timing is very chip dependent)
- fl_we_n : out std_logic; --write enable (timing is very chip dependent)
- fl_data : inout std_logic_vector(15 downto 0);
- fl_rp_n : out std_logic; --reset signal
- fl_byte_n : out std_logic; --hold in byte mode
- fl_sts : in std_logic; --status signal
- -- mem Bus
- mem_addr : in std_logic_vector(23 downto 0);
- mem_do : out std_logic_vector(15 downto 0);
- mem_di : in std_logic_vector(15 downto 0);
-
- mem_wr : in std_logic; --write not read signal
- mem_val : in std_logic;
- mem_ack : out std_logic
- );
-end flash_if;
-
-
-architecture RTL of flash_if is
- type state_type is (RESETs,FLREADs,FLWRITEs,WAITs);
- signal CS : state_type;
- signal fl_cnt : std_logic_vector(3 downto 0);
- signal fl_oe_nd : std_logic; --output enable for flash
- signal mode_d : std_logic_vector(2 downto 0); --sel upper addr bits
-begin
-
-fl_rp_n <= reset_n; --make flash reset
-fl_addr <= mem_addr(23 downto 0);
-fl_byte_n <= '0'; --all byte accesses
-
-
-fl_oe_n<=fl_oe_nd;
-fl_data <= mem_di when fl_oe_nd ='1' else
- (others =>'Z');
-
-
-
-RD: process (clk, reset_n)
-begin -- process READ
- if reset_n='0' then
- fl_we_n <='1';
- fl_ce_n <='1';
- fl_oe_nd <='1';
- CS <= RESETs;
- fl_cnt <= (others=>'0');
- mem_do <= (others=>'0');
- mem_ack <='0';
- elsif clk'event and clk = '1' then -- rising clock edge
- mode_d <= mode;
- case CS is
- when RESETs =>
- mem_ack <='0';
- fl_ce_n <= (not mem_val); --chipselect 4 flash
- fl_we_n <= (not (mem_val and mem_wr)); --write enable 4 flash
- if mem_val='1' and mem_wr = '0' then --READ
- fl_oe_nd <='0';
- CS <= FLREADs;
- elsif mem_val='1' and mem_wr = '1' then --WRITE
- fl_oe_nd <='1';
- CS <= FLWRITEs;
- end if; --elsif mem_cmd
- --Lets set the cnt for flash and PSRAM separately
- if (mode_d(2)='0')then
- fl_cnt <= (others=>'0');
- else
- fl_cnt <= x"2"; --PSRAM cycle is 80 ns with 25MHz clock
- end if;
- when FLREADs =>
- fl_cnt <= fl_cnt + 1;
- if fl_cnt=x"3" then --3 cycles later
- mem_ack <='1';
- mem_do <= fl_data; --registered is nicer
- elsif fl_cnt=x"4" then --4 cycles later
- mem_ack <='0';
- fl_oe_nd <='1';
- CS <= WAITs;
- end if;
- when FLWRITEs =>
- fl_cnt <= fl_cnt + 1;
- if fl_cnt=x"3" then --3 cycles later
- mem_ack <='1';
- elsif fl_cnt=x"4" then --4 cycles later
- mem_ack <='0';
- CS <= WAITs;
- end if;
- when WAITs =>
- if mem_val='0' then -- wait untill val is removed
- CS <= RESETs;
- end if;
- end case;
-
- end if; --system
-end process RD;
-
-
-
-
-end RTL;
-
+------------------------------------------------------------------
+-- Universal dongle board source code
+--
+-- Copyright (C) 2006 Artec Design
+--
+-- This source code is free hardware; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This source code is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+--
+--
+-- The complete text of the GNU Lesser General Public License can be found in
+-- the file 'lesser.txt'.
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+entity flash_if is
+ port (
+ clk : in std_logic;
+ reset_n : in std_logic;
+ mode : in std_logic_vector(2 downto 0); --sel upper addr bits
+ --flash Bus
+ fl_addr : out std_logic_vector(23 downto 0);
+ fl_ce_n : out std_logic; --chip select (timing is very chip dependent)
+ fl_oe_n : out std_logic; --output enable for flash (timing is very chip dependent)
+ fl_we_n : out std_logic; --write enable (timing is very chip dependent)
+ fl_data : inout std_logic_vector(15 downto 0);
+ fl_rp_n : out std_logic; --reset signal
+ fl_byte_n : out std_logic; --hold in byte mode
+ fl_sts : in std_logic; --status signal
+ -- mem Bus
+ mem_addr : in std_logic_vector(23 downto 0);
+ mem_do : out std_logic_vector(15 downto 0);
+ mem_di : in std_logic_vector(15 downto 0);
+
+ mem_wr : in std_logic; --write not read signal
+ mem_val : in std_logic;
+ mem_ack : out std_logic
+ );
+end flash_if;
+
+
+architecture RTL of flash_if is
+ type state_type is (RESETs,FLREADs,FLWRITEs,WAITs);
+ signal CS : state_type;
+ signal fl_cnt : std_logic_vector(3 downto 0);
+ signal fl_oe_nd : std_logic; --output enable for flash
+ signal mode_d : std_logic_vector(2 downto 0); --sel upper addr bits
+begin
+
+fl_rp_n <= reset_n; --make flash reset
+fl_addr <= mem_addr(23 downto 0);
+fl_byte_n <= '0'; --all byte accesses
+
+
+fl_oe_n<=fl_oe_nd;
+fl_data <= mem_di when fl_oe_nd ='1' else
+ (others =>'Z');
+
+
+
+RD: process (clk, reset_n)
+begin -- process READ
+ if reset_n='0' then
+ fl_we_n <='1';
+ fl_ce_n <='1';
+ fl_oe_nd <='1';
+ CS <= RESETs;
+ fl_cnt <= (others=>'0');
+ mem_do <= (others=>'0');
+ mem_ack <='0';
+ elsif clk'event and clk = '1' then -- rising clock edge
+ mode_d <= mode;
+ case CS is
+ when RESETs =>
+ mem_ack <='0';
+ fl_ce_n <= (not mem_val); --chipselect 4 flash
+ fl_we_n <= (not (mem_val and mem_wr)); --write enable 4 flash
+ if mem_val='1' and mem_wr = '0' then --READ
+ fl_oe_nd <='0';
+ CS <= FLREADs;
+ elsif mem_val='1' and mem_wr = '1' then --WRITE
+ fl_oe_nd <='1';
+ CS <= FLWRITEs;
+ end if; --elsif mem_cmd
+ --Lets set the cnt for flash and PSRAM separately
+ if (mode_d(2)='0')then
+ fl_cnt <= (others=>'0');
+ else
+ fl_cnt <= x"2"; --PSRAM cycle is 80 ns with 25MHz clock
+ end if;
+ when FLREADs =>
+ fl_cnt <= fl_cnt + 1;
+ if fl_cnt=x"3" then --3 cycles later
+ mem_ack <='1';
+ mem_do <= fl_data; --registered is nicer
+ elsif fl_cnt=x"4" then --4 cycles later
+ mem_ack <='0';
+ fl_oe_nd <='1';
+ CS <= WAITs;
+ end if;
+ when FLWRITEs =>
+ fl_cnt <= fl_cnt + 1;
+ if fl_cnt=x"3" then --3 cycles later
+ mem_ack <='1';
+ elsif fl_cnt=x"4" then --4 cycles later
+ mem_ack <='0';
+ CS <= WAITs;
+ end if;
+ when WAITs =>
+ if mem_val='0' then -- wait untill val is removed
+ CS <= RESETs;
+ end if;
+ end case;
+
+ end if; --system
+end process RD;
+
+
+
+
+end RTL;
+