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URL https://opencores.org/ocsvn/cic_core_2/cic_core_2/trunk

Subversion Repositories cic_core_2

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Rev 8 → Rev 9

/cic_core_2/trunk/rtl/verilog/cic_d.sv
10,13 → 10,13
)
/*********************************************************************************************/
(
input clk,
input reset_n,
input clear,
input wire signed [INP_DW-1:0] inp_samp_data,
input inp_samp_str,
output wire signed [OUT_DW-1:0] out_samp_data,
output out_samp_str
input clk, ///< input clock
input reset_n, ///< input reset
input clear, ///< input clear integrator, set accumulator to 0
input wire signed [INP_DW-1:0] inp_samp_data, ///< input data
input inp_samp_str, ///< input data ready strobe
output wire signed [OUT_DW-1:0] out_samp_data, ///< output data
output out_samp_str ///< output data ready strobe
);
/*********************************************************************************************/
`include "cic_functions.vh"
23,25 → 23,20
/*********************************************************************************************/
localparam B_max = clog2_l((CIC_R * CIC_M) ** CIC_N) + INP_DW - 1;
/*********************************************************************************************/
 
genvar i;
generate
for (i = 0; i < CIC_N; i = i + 1) begin : int_stage
localparam B_jm1 = B_calc(i , CIC_N, CIC_R, CIC_M, INP_DW, OUT_DW);
localparam B_j = B_calc(i + 1, CIC_N, CIC_R, CIC_M, INP_DW, OUT_DW);
localparam F_sq_j = 0;
localparam idw_cur = B_max - B_jm1 + 1;
localparam odw_cur = B_max - B_j + 1;
localparam B_dw_prev = (i != 0) ? B_max - B_jm1 + 1 : 0;
wire signed [idw_cur - 1 : 0] int_in;
if ( i == 0 ) assign int_in = inp_samp_data;
else assign int_in = int_stage[i - 1].int_out;
wire signed [idw_cur - 1 : 0] int_inst_out;
localparam B_jm1 = B_calc(i , CIC_N, CIC_R, CIC_M, INP_DW, OUT_DW); ///< the number of bits to prune in previous stage
localparam B_j = B_calc(i + 1, CIC_N, CIC_R, CIC_M, INP_DW, OUT_DW); ///< the number of bits to prune in current stage
localparam idw_cur = B_max - B_jm1 + 1; ///< data width on the input
localparam odw_cur = B_max - B_j + 1; ///< data width on the output
wire signed [idw_cur - 1 : 0] int_in; ///< input data bus
if ( i == 0 ) assign int_in = inp_samp_data; ///< if it is the first stage, then takes data from input of CIC filter
else assign int_in = int_stage[i - 1].int_out; ///< otherwise, takes data from the previous stage of the filter
wire signed [odw_cur - 1 : 0] int_out;
assign int_out = int_inst_out[idw_cur - 1 -: odw_cur];
integrator #(
idw_cur,
idw_cur
odw_cur
)
int_inst(
.clk (clk),
49,7 → 44,7
.clear (clear) ,
.inp_samp_data (int_in),
.inp_samp_str (inp_samp_str),
.out_samp_data (int_inst_out)
.out_samp_data (int_out)
);
initial begin
//$display("i:%d integ idw=%2d odw=%2d B(%2d, %3d, %2d, %2d, %2d, %2d)=%2d, Bj-1=%2d, F_sq=%8d", i, idw_cur, odw_cur, i + 1, CIC_R, CIC_M, CIC_N, INP_DW, OUT_DW, B_j, B_jm1, F_sq_j);
58,8 → 53,9
end
endgenerate
/*********************************************************************************************/
localparam B_m = B_calc(CIC_N, CIC_N, CIC_R, CIC_M, INP_DW, OUT_DW);
localparam ds_dw = B_max - B_m + 1;
/// downsampler takes data from m-th stage
localparam B_m = B_calc(CIC_N, CIC_N, CIC_R, CIC_M, INP_DW, OUT_DW); ///< bits to prune on the m-th stage
localparam ds_dw = B_max - B_m + 1; ///< data width of the downsampler
wire signed [ds_dw - 1 : 0] ds_out_samp_data;
wire ds_out_samp_str;
/*********************************************************************************************/
87,8 → 83,8
reg [CIC_N : 0] comb_inp_str_d;
generate
wire summ_rdy_str;
if (SMALL_FOOTPRINT != 0) begin
always @(negedge reset_n or posedge clk)
if (SMALL_FOOTPRINT != 0) begin ///< generate comb for small footprint
always @(negedge reset_n or posedge clk) ///< shift register for strobe from datasampler, used to latch data from comb at N'th clock after downsamplers strobe
if (~reset_n) comb_inp_str_d <= '0;
else if (clear) comb_inp_str_d <= '0;
else comb_inp_str_d <= {comb_inp_str_d[CIC_N - 1 : 0], ds_out_samp_str};
101,7 → 97,6
for (j = 0; j < CIC_N; j = j + 1) begin : comb_stage
localparam B_m_j_m1 = B_calc(CIC_N + j , CIC_N, CIC_R, CIC_M, INP_DW, OUT_DW);
localparam B_m_j = B_calc(CIC_N + j + 1, CIC_N, CIC_R, CIC_M, INP_DW, OUT_DW);
localparam F_sq_j = 1;
localparam idw_cur = B_max - B_m_j_m1 + 1;
localparam odw_cur = B_max - B_m_j + 1;
wire signed [idw_cur - 1 : 0] comb_in;
129,7 → 124,7
if (SMALL_FOOTPRINT == 0) assign comb_chain_out_str = comb_stage[CIC_N - 1].comb_dv;
else assign comb_chain_out_str = comb_inp_str_d[CIC_N - 1];
initial begin
//$display("i:%d comb idw=%2d odw=%2d B(%2d, %3d, %2d, %2d, %2d, %2d)=%2d, ln(F_sq)=%4d, F_sq=%8d", j, idw_cur, odw_cur, CIC_N + j + 1, CIC_R, CIC_M, CIC_N, INP_DW, OUT_DW, B_m_j, $ln(F_sq_j), F_sq_j);
//$display("i:%d comb idw=%2d odw=%2d B(%2d, %3d, %2d, %2d, %2d, %2d)=%2d", j, idw_cur, odw_cur, CIC_N + j + 1, CIC_R, CIC_M, CIC_N, INP_DW, OUT_DW, B_m_j);
//if (j != 0) $display("odw_prev=%2d, comb_stage[j - 1].odw_cur=%2d", odw_prev, comb_stage[j - 1].odw_cur);
$display("i:%d comb idw=%d", j, idw_cur);
end
/cic_core_2/trunk/rtl/verilog/integrator.sv
9,16 → 9,20
input clear,
input wire signed [DATA_WIDTH_INP - 1:0] inp_samp_data,
input inp_samp_str,
output reg signed [DATA_WIDTH_OUT - 1:0] out_samp_data
output wire signed [DATA_WIDTH_OUT - 1:0] out_samp_data
);
/*********************************************************************************************/
wire signed [DATA_WIDTH_OUT - 1:0] sum;
assign #4 sum = out_samp_data + inp_samp_data; // delay for 18x18 multiplier of Cyclone V SE is 3.4 ns
localparam SUMMER_WIDTH = DATA_WIDTH_INP > DATA_WIDTH_OUT ? DATA_WIDTH_INP : DATA_WIDTH_OUT;
wire signed [SUMMER_WIDTH - 1:0] sum;
reg signed [SUMMER_WIDTH - 1:0] acc_reg;
assign #4 sum = acc_reg + inp_samp_data; // delay for 18x18 multiplier of Cyclone V SE is 3.4 ns
always @(posedge clk or negedge reset_n)
begin
if (!reset_n) out_samp_data <= '0;
else if (clear) out_samp_data <= '0;
else if (inp_samp_str) out_samp_data <= sum;
if (!reset_n) acc_reg <= '0;
else if (clear) acc_reg <= '0;
else if (inp_samp_str) acc_reg <= sum;
end
 
assign out_samp_data = acc_reg[SUMMER_WIDTH - 1 -: DATA_WIDTH_OUT];
/*********************************************************************************************/
endmodule

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