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/trunk/rtl/vhdl/fsm_execution_unit.vhd
1,8 → 1,8
-- VHDL Entity R6502_TC.FSM_Execution_Unit.symbol
--
-- Created:
-- by - eda.UNKNOWN (TEST)
-- at - 21:30:21 04.01.2009
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:42:53 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
10,55 → 10,55
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ENTITY FSM_Execution_Unit IS
PORT(
adr_nxt_pc_i : IN std_logic_vector (15 DOWNTO 0);
adr_pc_i : IN std_logic_vector (15 DOWNTO 0);
adr_sp_i : IN std_logic_vector (15 DOWNTO 0);
clk_clk_i : IN std_logic;
d_alu_i : IN std_logic_vector ( 7 DOWNTO 0 );
d_i : IN std_logic_vector ( 7 DOWNTO 0 );
d_regs_out_i : IN std_logic_vector ( 7 DOWNTO 0 );
irq_n_i : IN std_logic;
nmi_i : IN std_logic;
q_a_i : IN std_logic_vector ( 7 DOWNTO 0 );
q_x_i : IN std_logic_vector ( 7 DOWNTO 0 );
q_y_i : IN std_logic_vector ( 7 DOWNTO 0 );
rdy_i : IN std_logic;
reg_0flag_i : IN std_logic;
reg_1flag_i : IN std_logic;
reg_7flag_i : IN std_logic;
rst_rst_n_i : IN std_logic;
so_n_i : IN std_logic;
a_o : OUT std_logic_vector (15 DOWNTO 0);
adr_o : OUT std_logic_vector (15 DOWNTO 0);
ch_a_o : OUT std_logic_vector ( 7 DOWNTO 0 );
ch_b_o : OUT std_logic_vector ( 7 DOWNTO 0 );
d_o : OUT std_logic_vector ( 7 DOWNTO 0 );
d_regs_in_o : OUT std_logic_vector ( 7 DOWNTO 0 );
fetch_o : OUT std_logic;
ld_o : OUT std_logic_vector ( 1 DOWNTO 0 );
ld_pc_o : OUT std_logic;
ld_sp_o : OUT std_logic;
load_regs_o : OUT std_logic;
offset_o : OUT std_logic_vector ( 15 DOWNTO 0 );
rd_o : OUT std_logic;
sel_pc_as_o : OUT std_logic;
sel_pc_in_o : OUT std_logic;
sel_pc_val_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_rb_in_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_rb_out_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_reg_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_sp_as_o : OUT std_logic;
sel_sp_in_o : OUT std_logic;
sync_o : OUT std_logic;
wr_n_o : OUT std_logic;
wr_o : OUT std_logic
entity FSM_Execution_Unit is
port(
adr_nxt_pc_i : in std_logic_vector (15 downto 0);
adr_pc_i : in std_logic_vector (15 downto 0);
adr_sp_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic;
d_alu_i : in std_logic_vector ( 7 downto 0 );
d_i : in std_logic_vector ( 7 downto 0 );
d_regs_out_i : in std_logic_vector ( 7 downto 0 );
irq_n_i : in std_logic;
nmi_i : in std_logic;
q_a_i : in std_logic_vector ( 7 downto 0 );
q_x_i : in std_logic_vector ( 7 downto 0 );
q_y_i : in std_logic_vector ( 7 downto 0 );
rdy_i : in std_logic;
reg_0flag_i : in std_logic;
reg_1flag_i : in std_logic;
reg_7flag_i : in std_logic;
rst_rst_n_i : in std_logic;
so_n_i : in std_logic;
a_o : out std_logic_vector (15 downto 0);
adr_o : out std_logic_vector (15 downto 0);
ch_a_o : out std_logic_vector ( 7 downto 0 );
ch_b_o : out std_logic_vector ( 7 downto 0 );
d_o : out std_logic_vector ( 7 downto 0 );
d_regs_in_o : out std_logic_vector ( 7 downto 0 );
fetch_o : out std_logic;
ld_o : out std_logic_vector ( 1 downto 0 );
ld_pc_o : out std_logic;
ld_sp_o : out std_logic;
load_regs_o : out std_logic;
offset_o : out std_logic_vector ( 15 downto 0 );
rd_o : out std_logic;
sel_pc_as_o : out std_logic;
sel_pc_in_o : out std_logic;
sel_pc_val_o : out std_logic_vector ( 1 downto 0 );
sel_rb_in_o : out std_logic_vector ( 1 downto 0 );
sel_rb_out_o : out std_logic_vector ( 1 downto 0 );
sel_reg_o : out std_logic_vector ( 1 downto 0 );
sel_sp_as_o : out std_logic;
sel_sp_in_o : out std_logic;
sync_o : out std_logic;
wr_n_o : out std_logic;
wr_o : out std_logic
);
 
-- Declarations
 
END FSM_Execution_Unit ;
end FSM_Execution_Unit ;
 
-- Jens-D. Gutschmidt Project: R6502_TC
 
102,8 → 102,8
-- VHDL Architecture R6502_TC.FSM_Execution_Unit.fsm
--
-- Created:
-- by - eda.UNKNOWN (TEST)
-- at - 21:30:22 04.01.2009
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:42:55 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
111,215 → 111,215
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ARCHITECTURE fsm OF FSM_Execution_Unit IS
architecture fsm of FSM_Execution_Unit is
 
-- Architecture Declarations
SIGNAL reg_F : std_logic_vector( 7 DOWNTO 0 );
SIGNAL reg_PC : std_logic_vector(15 DOWNTO 0);
SIGNAL reg_PC1 : std_logic_vector( 15 DOWNTO 0 );
SIGNAL reg_sel_pc_as : std_logic;
SIGNAL reg_sel_pc_in : std_logic;
SIGNAL reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 );
SIGNAL reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 );
SIGNAL reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 );
SIGNAL reg_sel_reg : std_logic_vector( 1 DOWNTO 0 );
SIGNAL reg_sel_sp_as : std_logic;
SIGNAL reg_sel_sp_in : std_logic;
SIGNAL sig_D_OUT : std_logic_vector( 7 DOWNTO 0 );
SIGNAL sig_PC : std_logic_vector(15 DOWNTO 0);
SIGNAL sig_RD : std_logic;
SIGNAL sig_RWn : std_logic;
SIGNAL sig_SYNC : std_logic;
SIGNAL sig_WR : std_logic;
SIGNAL zw_ALU : std_logic_vector( 8 DOWNTO 0 );
SIGNAL zw_ALU1 : std_logic_vector( 8 DOWNTO 0 );
SIGNAL zw_ALU2 : std_logic_vector( 8 DOWNTO 0 );
SIGNAL zw_ALU3 : std_logic_vector( 8 DOWNTO 0 );
SIGNAL zw_ALU4 : std_logic_vector( 8 DOWNTO 0 );
SIGNAL zw_ALU5 : std_logic_vector( 8 DOWNTO 0 );
SIGNAL zw_ALU6 : std_logic_vector( 8 DOWNTO 0 );
SIGNAL zw_PC : std_logic_vector( 15 DOWNTO 0 );
SIGNAL zw_REG_ALU : std_logic_vector( 8 DOWNTO 0 );
SIGNAL zw_REG_NMI : std_logic;
SIGNAL zw_REG_OP : std_logic_vector( 7 DOWNTO 0 );
SIGNAL zw_REG_sig_PC : std_logic_vector(15 DOWNTO 0);
SIGNAL zw_b1 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL zw_b2 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL zw_b3 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL zw_b4 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL zw_so : std_logic;
SIGNAL zw_w1 : std_logic_vector( 15 DOWNTO 0 );
SIGNAL zw_w2 : std_logic_vector( 15 DOWNTO 0 );
SIGNAL zw_w3 : std_logic_vector( 15 DOWNTO 0 );
signal reg_F : std_logic_vector( 7 DOWNTO 0 );
signal reg_PC : std_logic_vector(15 DOWNTO 0);
signal reg_PC1 : std_logic_vector( 15 DOWNTO 0 );
signal reg_sel_pc_as : std_logic;
signal reg_sel_pc_in : std_logic;
signal reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_reg : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_sp_as : std_logic;
signal reg_sel_sp_in : std_logic;
signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 );
signal sig_PC : std_logic_vector(15 DOWNTO 0);
signal sig_RD : std_logic;
signal sig_RWn : std_logic;
signal sig_SYNC : std_logic;
signal sig_WR : std_logic;
signal zw_ALU : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU1 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU2 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU3 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU4 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU5 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU6 : std_logic_vector( 8 DOWNTO 0 );
signal zw_PC : std_logic_vector( 15 DOWNTO 0 );
signal zw_REG_ALU : std_logic_vector( 8 DOWNTO 0 );
signal zw_REG_NMI : std_logic;
signal zw_REG_OP : std_logic_vector( 7 DOWNTO 0 );
signal zw_REG_sig_PC : std_logic_vector(15 DOWNTO 0);
signal zw_b1 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b2 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b3 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b4 : std_logic_vector( 7 DOWNTO 0 );
signal zw_so : std_logic;
signal zw_w1 : std_logic_vector( 15 DOWNTO 0 );
signal zw_w2 : std_logic_vector( 15 DOWNTO 0 );
signal zw_w3 : std_logic_vector( 15 DOWNTO 0 );
 
SUBTYPE STATE_TYPE IS
std_logic_vector(7 DOWNTO 0);
subtype state_type is
std_logic_vector(7 downto 0);
-- State vector declaration
ATTRIBUTE state_vector : string;
ATTRIBUTE state_vector OF fsm : ARCHITECTURE IS "current_state";
attribute state_vector : string;
attribute state_vector of fsm : architecture is "current_state";
 
-- Hard encoding
CONSTANT FETCH : STATE_TYPE := "00000000";
CONSTANT s1 : STATE_TYPE := "00000001";
CONSTANT s2 : STATE_TYPE := "00000011";
CONSTANT s5 : STATE_TYPE := "00000010";
CONSTANT s3 : STATE_TYPE := "00000110";
CONSTANT s4 : STATE_TYPE := "00000111";
CONSTANT s12 : STATE_TYPE := "00000101";
CONSTANT s16 : STATE_TYPE := "00000100";
CONSTANT s17 : STATE_TYPE := "00001100";
CONSTANT s24 : STATE_TYPE := "00001101";
CONSTANT s25 : STATE_TYPE := "00001111";
CONSTANT s271 : STATE_TYPE := "00001110";
CONSTANT s273 : STATE_TYPE := "00001010";
CONSTANT s304 : STATE_TYPE := "00001011";
CONSTANT s307 : STATE_TYPE := "00001001";
CONSTANT s177 : STATE_TYPE := "00001000";
CONSTANT s180 : STATE_TYPE := "00011000";
CONSTANT s181 : STATE_TYPE := "00011001";
CONSTANT s182 : STATE_TYPE := "00011011";
CONSTANT s183 : STATE_TYPE := "00011010";
CONSTANT s184 : STATE_TYPE := "00011110";
CONSTANT s185 : STATE_TYPE := "00011111";
CONSTANT s186 : STATE_TYPE := "00011101";
CONSTANT s187 : STATE_TYPE := "00011100";
CONSTANT s188 : STATE_TYPE := "00010100";
CONSTANT s189 : STATE_TYPE := "00010101";
CONSTANT s190 : STATE_TYPE := "00010111";
CONSTANT s191 : STATE_TYPE := "00010110";
CONSTANT s192 : STATE_TYPE := "00010010";
CONSTANT s193 : STATE_TYPE := "00010011";
CONSTANT s377 : STATE_TYPE := "00010001";
CONSTANT s381 : STATE_TYPE := "00010000";
CONSTANT s378 : STATE_TYPE := "00110000";
CONSTANT s382 : STATE_TYPE := "00110001";
CONSTANT s379 : STATE_TYPE := "00110011";
CONSTANT s383 : STATE_TYPE := "00110010";
CONSTANT s384 : STATE_TYPE := "00110110";
CONSTANT s380 : STATE_TYPE := "00110111";
CONSTANT s385 : STATE_TYPE := "00110101";
CONSTANT s386 : STATE_TYPE := "00110100";
CONSTANT s387 : STATE_TYPE := "00111100";
CONSTANT s388 : STATE_TYPE := "00111101";
CONSTANT s389 : STATE_TYPE := "00111111";
CONSTANT s391 : STATE_TYPE := "00111110";
CONSTANT s392 : STATE_TYPE := "00111010";
CONSTANT s390 : STATE_TYPE := "00111011";
CONSTANT s393 : STATE_TYPE := "00111001";
CONSTANT s394 : STATE_TYPE := "00111000";
CONSTANT s395 : STATE_TYPE := "00101000";
CONSTANT s396 : STATE_TYPE := "00101001";
CONSTANT s397 : STATE_TYPE := "00101011";
CONSTANT s398 : STATE_TYPE := "00101010";
CONSTANT s399 : STATE_TYPE := "00101110";
CONSTANT s400 : STATE_TYPE := "00101111";
CONSTANT s401 : STATE_TYPE := "00101101";
CONSTANT s526 : STATE_TYPE := "00101100";
CONSTANT s527 : STATE_TYPE := "00100100";
CONSTANT s528 : STATE_TYPE := "00100101";
CONSTANT s529 : STATE_TYPE := "00100111";
CONSTANT s530 : STATE_TYPE := "00100110";
CONSTANT s531 : STATE_TYPE := "00100010";
CONSTANT s544 : STATE_TYPE := "00100011";
CONSTANT s545 : STATE_TYPE := "00100001";
CONSTANT s546 : STATE_TYPE := "00100000";
CONSTANT s547 : STATE_TYPE := "01100000";
CONSTANT s549 : STATE_TYPE := "01100001";
CONSTANT s550 : STATE_TYPE := "01100011";
CONSTANT s404 : STATE_TYPE := "01100010";
CONSTANT s556 : STATE_TYPE := "01100110";
CONSTANT s557 : STATE_TYPE := "01100111";
CONSTANT s579 : STATE_TYPE := "01100101";
CONSTANT s201 : STATE_TYPE := "01100100";
CONSTANT s202 : STATE_TYPE := "01101100";
CONSTANT s210 : STATE_TYPE := "01101101";
CONSTANT s211 : STATE_TYPE := "01101111";
CONSTANT s215 : STATE_TYPE := "01101110";
CONSTANT s217 : STATE_TYPE := "01101010";
CONSTANT s218 : STATE_TYPE := "01101011";
CONSTANT s222 : STATE_TYPE := "01101001";
CONSTANT s223 : STATE_TYPE := "01101000";
CONSTANT s224 : STATE_TYPE := "01111000";
CONSTANT s225 : STATE_TYPE := "01111001";
CONSTANT s226 : STATE_TYPE := "01111011";
CONSTANT s243 : STATE_TYPE := "01111010";
CONSTANT s244 : STATE_TYPE := "01111110";
CONSTANT s247 : STATE_TYPE := "01111111";
CONSTANT s344 : STATE_TYPE := "01111101";
CONSTANT s343 : STATE_TYPE := "01111100";
CONSTANT s250 : STATE_TYPE := "01110100";
CONSTANT s251 : STATE_TYPE := "01110101";
CONSTANT s351 : STATE_TYPE := "01110111";
CONSTANT s361 : STATE_TYPE := "01110110";
CONSTANT s360 : STATE_TYPE := "01110010";
CONSTANT s403 : STATE_TYPE := "01110011";
CONSTANT s406 : STATE_TYPE := "01110001";
CONSTANT s407 : STATE_TYPE := "01110000";
CONSTANT s409 : STATE_TYPE := "01010000";
CONSTANT s412 : STATE_TYPE := "01010001";
CONSTANT s413 : STATE_TYPE := "01010011";
CONSTANT s416 : STATE_TYPE := "01010010";
CONSTANT s418 : STATE_TYPE := "01010110";
CONSTANT s510 : STATE_TYPE := "01010111";
CONSTANT s553 : STATE_TYPE := "01010101";
CONSTANT s555 : STATE_TYPE := "01010100";
CONSTANT s558 : STATE_TYPE := "01011100";
CONSTANT s560 : STATE_TYPE := "01011101";
CONSTANT s561 : STATE_TYPE := "01011111";
CONSTANT s563 : STATE_TYPE := "01011110";
CONSTANT s564 : STATE_TYPE := "01011010";
CONSTANT s565 : STATE_TYPE := "01011011";
CONSTANT s566 : STATE_TYPE := "01011001";
CONSTANT s266 : STATE_TYPE := "01011000";
CONSTANT s301 : STATE_TYPE := "01001000";
CONSTANT s302 : STATE_TYPE := "01001001";
CONSTANT RES : STATE_TYPE := "01001011";
CONSTANT s511 : STATE_TYPE := "01001010";
CONSTANT s559 : STATE_TYPE := "01001110";
CONSTANT s562 : STATE_TYPE := "01001111";
CONSTANT s567 : STATE_TYPE := "01001101";
CONSTANT s568 : STATE_TYPE := "01001100";
CONSTANT s569 : STATE_TYPE := "01000100";
CONSTANT s570 : STATE_TYPE := "01000101";
CONSTANT s571 : STATE_TYPE := "01000111";
CONSTANT s572 : STATE_TYPE := "01000110";
CONSTANT s573 : STATE_TYPE := "01000010";
CONSTANT s574 : STATE_TYPE := "01000011";
CONSTANT s548 : STATE_TYPE := "01000001";
CONSTANT s551 : STATE_TYPE := "01000000";
CONSTANT s552 : STATE_TYPE := "11000000";
CONSTANT s575 : STATE_TYPE := "11000001";
CONSTANT s576 : STATE_TYPE := "11000011";
CONSTANT s577 : STATE_TYPE := "11000010";
CONSTANT s532 : STATE_TYPE := "11000110";
CONSTANT s533 : STATE_TYPE := "11000111";
CONSTANT s534 : STATE_TYPE := "11000101";
CONSTANT s535 : STATE_TYPE := "11000100";
CONSTANT s536 : STATE_TYPE := "11001100";
CONSTANT s537 : STATE_TYPE := "11001101";
constant FETCH : state_type := "00000000";
constant s1 : state_type := "00000001";
constant s2 : state_type := "00000011";
constant s5 : state_type := "00000010";
constant s3 : state_type := "00000110";
constant s4 : state_type := "00000111";
constant s12 : state_type := "00000101";
constant s16 : state_type := "00000100";
constant s17 : state_type := "00001100";
constant s24 : state_type := "00001101";
constant s25 : state_type := "00001111";
constant s271 : state_type := "00001110";
constant s273 : state_type := "00001010";
constant s304 : state_type := "00001011";
constant s307 : state_type := "00001001";
constant s177 : state_type := "00001000";
constant s180 : state_type := "00011000";
constant s181 : state_type := "00011001";
constant s182 : state_type := "00011011";
constant s183 : state_type := "00011010";
constant s184 : state_type := "00011110";
constant s185 : state_type := "00011111";
constant s186 : state_type := "00011101";
constant s187 : state_type := "00011100";
constant s188 : state_type := "00010100";
constant s189 : state_type := "00010101";
constant s190 : state_type := "00010111";
constant s191 : state_type := "00010110";
constant s192 : state_type := "00010010";
constant s193 : state_type := "00010011";
constant s377 : state_type := "00010001";
constant s381 : state_type := "00010000";
constant s378 : state_type := "00110000";
constant s382 : state_type := "00110001";
constant s379 : state_type := "00110011";
constant s383 : state_type := "00110010";
constant s384 : state_type := "00110110";
constant s380 : state_type := "00110111";
constant s385 : state_type := "00110101";
constant s386 : state_type := "00110100";
constant s387 : state_type := "00111100";
constant s388 : state_type := "00111101";
constant s389 : state_type := "00111111";
constant s391 : state_type := "00111110";
constant s392 : state_type := "00111010";
constant s390 : state_type := "00111011";
constant s393 : state_type := "00111001";
constant s394 : state_type := "00111000";
constant s395 : state_type := "00101000";
constant s396 : state_type := "00101001";
constant s397 : state_type := "00101011";
constant s398 : state_type := "00101010";
constant s399 : state_type := "00101110";
constant s400 : state_type := "00101111";
constant s401 : state_type := "00101101";
constant s526 : state_type := "00101100";
constant s527 : state_type := "00100100";
constant s528 : state_type := "00100101";
constant s529 : state_type := "00100111";
constant s530 : state_type := "00100110";
constant s531 : state_type := "00100010";
constant s544 : state_type := "00100011";
constant s545 : state_type := "00100001";
constant s546 : state_type := "00100000";
constant s547 : state_type := "01100000";
constant s549 : state_type := "01100001";
constant s550 : state_type := "01100011";
constant s404 : state_type := "01100010";
constant s556 : state_type := "01100110";
constant s557 : state_type := "01100111";
constant s579 : state_type := "01100101";
constant s201 : state_type := "01100100";
constant s202 : state_type := "01101100";
constant s210 : state_type := "01101101";
constant s211 : state_type := "01101111";
constant s215 : state_type := "01101110";
constant s217 : state_type := "01101010";
constant s218 : state_type := "01101011";
constant s222 : state_type := "01101001";
constant s223 : state_type := "01101000";
constant s224 : state_type := "01111000";
constant s225 : state_type := "01111001";
constant s226 : state_type := "01111011";
constant s243 : state_type := "01111010";
constant s244 : state_type := "01111110";
constant s247 : state_type := "01111111";
constant s344 : state_type := "01111101";
constant s343 : state_type := "01111100";
constant s250 : state_type := "01110100";
constant s251 : state_type := "01110101";
constant s351 : state_type := "01110111";
constant s361 : state_type := "01110110";
constant s360 : state_type := "01110010";
constant s403 : state_type := "01110011";
constant s406 : state_type := "01110001";
constant s407 : state_type := "01110000";
constant s409 : state_type := "01010000";
constant s412 : state_type := "01010001";
constant s413 : state_type := "01010011";
constant s416 : state_type := "01010010";
constant s418 : state_type := "01010110";
constant s510 : state_type := "01010111";
constant s553 : state_type := "01010101";
constant s555 : state_type := "01010100";
constant s558 : state_type := "01011100";
constant s560 : state_type := "01011101";
constant s561 : state_type := "01011111";
constant s563 : state_type := "01011110";
constant s564 : state_type := "01011010";
constant s565 : state_type := "01011011";
constant s566 : state_type := "01011001";
constant s266 : state_type := "01011000";
constant s301 : state_type := "01001000";
constant s302 : state_type := "01001001";
constant RES : state_type := "01001011";
constant s511 : state_type := "01001010";
constant s559 : state_type := "01001110";
constant s562 : state_type := "01001111";
constant s567 : state_type := "01001101";
constant s568 : state_type := "01001100";
constant s569 : state_type := "01000100";
constant s570 : state_type := "01000101";
constant s571 : state_type := "01000111";
constant s572 : state_type := "01000110";
constant s573 : state_type := "01000010";
constant s574 : state_type := "01000011";
constant s548 : state_type := "01000001";
constant s551 : state_type := "01000000";
constant s552 : state_type := "11000000";
constant s575 : state_type := "11000001";
constant s576 : state_type := "11000011";
constant s577 : state_type := "11000010";
constant s532 : state_type := "11000110";
constant s533 : state_type := "11000111";
constant s534 : state_type := "11000101";
constant s535 : state_type := "11000100";
constant s536 : state_type := "11001100";
constant s537 : state_type := "11001101";
 
-- Declare current and next state signals
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state : STATE_TYPE;
signal current_state : state_type;
signal next_state : state_type;
 
-- Declare any pre-registered internal signals
SIGNAL d_o_cld : std_logic_vector ( 7 DOWNTO 0 );
SIGNAL rd_o_cld : std_logic ;
SIGNAL sync_o_cld : std_logic ;
SIGNAL wr_n_o_cld : std_logic ;
SIGNAL wr_o_cld : std_logic ;
signal d_o_cld : std_logic_vector ( 7 downto 0 );
signal rd_o_cld : std_logic ;
signal sync_o_cld : std_logic ;
signal wr_n_o_cld : std_logic ;
signal wr_o_cld : std_logic ;
 
BEGIN
begin
 
-----------------------------------------------------------------
clocked_proc : PROCESS (
clocked_proc : process (
clk_clk_i,
rst_rst_n_i
)
-----------------------------------------------------------------
BEGIN
IF (rst_rst_n_i = '0') THEN
begin
if (rst_rst_n_i = '0') then
current_state <= RES;
-- Default Reset Values
d_o_cld <= X"00";
352,7 → 352,7
zw_w1 <= X"0000";
zw_w2 <= X"0000";
zw_w3 <= X"0000";
ELSIF (clk_clk_i'EVENT AND clk_clk_i = '1') THEN
elsif (clk_clk_i'event and clk_clk_i = '1') then
current_state <= next_state;
-- Default Assignment To Internals
reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0);
387,16 → 387,16
wr_o_cld <= sig_WR;
 
-- Combined Actions
CASE current_state IS
WHEN FETCH =>
case current_state is
when FETCH =>
zw_REG_OP <= d_i;
IF ((nmi_i = '1') AND (rdy_i = '1')) THEN
if ((nmi_i = '1') and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
zw_REG_NMI <= '0';
ELSIF ((irq_n_i = '0' and
reg_F(2) = '0') AND (rdy_i = '1')) THEN
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"69" or
elsif ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
403,17 → 403,17
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") AND (rdy_i = '1')) THEN
d_i = X"71") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
zw_b1(0) <= reg_F(7);
ELSIF ((d_i = X"06" or
elsif ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") AND (rdy_i = '1')) THEN
d_i = X"1E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"90" or
elsif ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
420,45 → 420,45
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") AND (rdy_i = '1')) THEN
d_i = X"70") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
zw_b3 <= adr_nxt_pc_i (15 downto 8);
ELSIF ((d_i = X"24" or
d_i = X"2C") AND (rdy_i = '1')) THEN
elsif ((d_i = X"24" or
d_i = X"2C") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN
elsif ((d_i = X"00") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"E0" or
elsif ((d_i = X"18") and (rdy_i = '1')) then
elsif ((d_i = X"D8") and (rdy_i = '1')) then
elsif ((d_i = X"58") and (rdy_i = '1')) then
elsif ((d_i = X"B8") and (rdy_i = '1')) then
elsif ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") AND (rdy_i = '1')) THEN
d_i = X"EC") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"C0" or
elsif ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") AND (rdy_i = '1')) THEN
d_i = X"CC") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"C6" or
elsif ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") AND (rdy_i = '1')) THEN
d_i = X"DE") and (rdy_i = '1')) then
zw_b4 <= X"FF";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN
elsif ((d_i = X"CA") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
zw_b4 <= X"FF";
ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN
elsif ((d_i = X"88") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
zw_b4 <= X"FF";
ELSIF ((d_i = X"49" or
elsif ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
489,33 → 489,33
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") AND (rdy_i = '1')) THEN
d_i = X"D1") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"E6" or
elsif ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") AND (rdy_i = '1')) THEN
d_i = X"FE") and (rdy_i = '1')) then
zw_b4 <= X"01";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN
elsif ((d_i = X"E8") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
zw_b4 <= X"01";
ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN
elsif ((d_i = X"C8") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
zw_b4 <= X"01";
ELSIF ((d_i = X"4C" or
d_i = X"6C") AND (rdy_i = '1')) THEN
elsif ((d_i = X"4C" or
d_i = X"6C") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN
elsif ((d_i = X"20") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"A9" or
elsif ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
522,62 → 522,62
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") AND (rdy_i = '1')) THEN
d_i = X"B1") and (rdy_i = '1')) then
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"A2" or
elsif ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") AND (rdy_i = '1')) THEN
d_i = X"BE") and (rdy_i = '1')) then
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"A0" or
elsif ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") AND (rdy_i = '1')) THEN
d_i = X"BC") and (rdy_i = '1')) then
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"46" or
elsif ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") AND (rdy_i = '1')) THEN
d_i = X"5E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN
elsif ((d_i = X"EA") and (rdy_i = '1')) then
elsif ((d_i = X"48") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN
elsif ((d_i = X"08") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN
elsif ((d_i = X"68") and (rdy_i = '1')) then
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN
elsif ((d_i = X"28") and (rdy_i = '1')) then
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
ELSIF ((d_i = X"26" or
elsif ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") AND (rdy_i = '1')) THEN
d_i = X"3E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"66" or
elsif ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") AND (rdy_i = '1')) THEN
d_i = X"7E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN
elsif ((d_i = X"40") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN
elsif ((d_i = X"60") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
ELSIF ((d_i = X"E9" or
elsif ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
584,88 → 584,88
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") AND (rdy_i = '1')) THEN
d_i = X"F1") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
zw_b1(0) <= reg_F(7);
ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"85" or
elsif ((d_i = X"38") and (rdy_i = '1')) then
elsif ((d_i = X"F8") and (rdy_i = '1')) then
elsif ((d_i = X"78") and (rdy_i = '1')) then
elsif ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91") AND (rdy_i = '1')) THEN
d_i = X"91") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"86" or
elsif ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") AND (rdy_i = '1')) THEN
d_i = X"8E") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"84" or
elsif ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") AND (rdy_i = '1')) THEN
d_i = X"8C") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN
elsif ((d_i = X"AA") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "01";
reg_sel_rb_in <= "00";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"0A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"4A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"2A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"6A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN
elsif ((d_i = X"A8") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "10";
reg_sel_rb_in <= "00";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN
elsif ((d_i = X"98") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
reg_sel_reg <= "00";
reg_sel_rb_in <= "01";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN
elsif ((d_i = X"BA") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"8A") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "00";
reg_sel_rb_in <= "10";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"9A") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "11";
reg_sel_rb_in <= "11";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
END IF;
WHEN s1 =>
IF (rdy_i = '1') THEN
end if;
when s1 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
672,9 → 672,9
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s2 =>
IF (rdy_i = '1') THEN
end if;
when s2 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= '1';
reg_sel_pc_in <= '0';
682,9 → 682,9
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s5 =>
IF (rdy_i = '1') THEN
end if;
when s5 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(3) <= '1';
reg_sel_pc_in <= '0';
692,10 → 692,10
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s3 =>
end if;
when s3 =>
sig_PC <= adr_pc_i;
IF (rdy_i = '1') THEN
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(2) <= '1';
reg_sel_pc_in <= '0';
703,10 → 703,10
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s4 =>
IF (rdy_i = '1' and
zw_REG_OP = X"9A") THEN
end if;
when s4 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
713,8 → 713,8
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"BA") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
723,7 → 723,7
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
732,9 → 732,9
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s12 =>
IF (rdy_i = '1') THEN
end if;
when s12 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= '0';
reg_sel_pc_in <= '0';
742,9 → 742,9
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s16 =>
IF (rdy_i = '1') THEN
end if;
when s16 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(3) <= '0';
reg_sel_pc_in <= '0';
752,9 → 752,9
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s17 =>
IF (rdy_i = '1') THEN
end if;
when s17 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(2) <= '0';
reg_sel_pc_in <= '0';
762,9 → 762,9
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s24 =>
IF (rdy_i = '1') THEN
end if;
when s24 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(6) <= '0';
reg_sel_pc_in <= '0';
772,9 → 772,9
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s25 =>
IF (rdy_i = '1') THEN
end if;
when s25 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
783,41 → 783,41
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s271 =>
IF (rdy_i = '1' and
zw_REG_OP = X"4C") THEN
end if;
when s271 =>
if (rdy_i = '1' and
zw_REG_OP = X"4C") then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"6C") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"6C") then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
zw_b1 <= d_i;
END IF;
WHEN s273 =>
IF (rdy_i = '1') THEN
end if;
when s273 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
zw_b2 <= d_i;
END IF;
WHEN s304 =>
IF (rdy_i = '1') THEN
end if;
when s304 =>
if (rdy_i = '1') then
sig_PC <= zw_b2 & adr_pc_i(7 downto 0);
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
END IF;
WHEN s307 =>
IF (rdy_i = '1') THEN
end if;
when s307 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
824,68 → 824,68
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s177 =>
IF (rdy_i = '1' and
end if;
when s177 =>
if (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) THEN
zw_REG_OP = X"84")) then
sig_PC <= X"00" & d_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) THEN
zw_REG_OP = X"94")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) THEN
zw_REG_OP = X"8C")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"9D") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"9D") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"99") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"91") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"81") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"96") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
END IF;
WHEN s180 =>
IF (rdy_i = '1') THEN
end if;
when s180 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s181 =>
IF (rdy_i = '1') THEN
end if;
when s181 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
END IF;
WHEN s182 =>
IF (rdy_i = '1') THEN
end if;
when s182 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s183 =>
IF (rdy_i = '1') THEN
end if;
when s183 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
END IF;
WHEN s184 =>
end if;
when s184 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
892,15 → 892,15
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s185 =>
IF (rdy_i = '1') THEN
when s185 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s186 =>
IF (rdy_i = '1') THEN
end if;
when s186 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s187 =>
end if;
when s187 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
907,17 → 907,17
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s188 =>
IF (rdy_i = '1') THEN
when s188 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
END IF;
WHEN s189 =>
IF (rdy_i = '1') THEN
end if;
when s189 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s190 =>
end if;
when s190 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
924,11 → 924,11
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s191 =>
when s191 =>
sig_PC <= zw_b3 & zw_b1;
WHEN s192 =>
when s192 =>
sig_PC <= d_i & zw_b1;
WHEN s193 =>
when s193 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
935,11 → 935,11
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s377 =>
IF (rdy_i = '1') THEN
when s377 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
END IF;
WHEN s381 =>
end if;
when s381 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
946,11 → 946,11
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s378 =>
IF (rdy_i = '1') THEN
when s378 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
END IF;
WHEN s382 =>
end if;
when s382 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
957,12 → 957,12
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s383 =>
IF (rdy_i = '1') THEN
when s383 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
END IF;
WHEN s384 =>
IF (rdy_i = '1') THEN
end if;
when s384 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
971,13 → 971,13
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s385 =>
IF (rdy_i = '1') THEN
end if;
when s385 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
END IF;
WHEN s386 =>
IF (rdy_i = '1') THEN
end if;
when s386 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F <= d_i;
reg_sel_pc_in <= '0';
985,30 → 985,30
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s387 =>
IF (rdy_i = '1') THEN
end if;
when s387 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
END IF;
WHEN s388 =>
IF (rdy_i = '1') THEN
end if;
when s388 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
END IF;
WHEN s389 =>
IF (rdy_i = '1') THEN
end if;
when s389 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
reg_F <= d_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
END IF;
WHEN s391 =>
IF (rdy_i = '1') THEN
end if;
when s391 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
END IF;
WHEN s392 =>
IF (rdy_i = '1') THEN
end if;
when s392 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
1015,29 → 1015,29
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s390 =>
IF (rdy_i = '1') THEN
end if;
when s390 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
END IF;
WHEN s393 =>
IF (rdy_i = '1') THEN
end if;
when s393 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
END IF;
WHEN s394 =>
IF (rdy_i = '1') THEN
end if;
when s394 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
END IF;
WHEN s395 =>
IF (rdy_i = '1') THEN
end if;
when s395 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
END IF;
WHEN s396 =>
IF (rdy_i = '1') THEN
end if;
when s396 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
1044,21 → 1044,21
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s397 =>
IF (rdy_i = '1') THEN
end if;
when s397 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
END IF;
WHEN s399 =>
end if;
when s399 =>
sig_PC <= adr_sp_i;
WHEN s400 =>
when s400 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
WHEN s401 =>
IF (rdy_i = '1') THEN
when s401 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1 (7 downto 0);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
1065,19 → 1065,19
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s526 =>
IF (rdy_i = '1') THEN
end if;
when s526 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
END IF;
WHEN s527 =>
end if;
when s527 =>
sig_PC <= adr_sp_i;
WHEN s528 =>
when s528 =>
sig_PC <= adr_sp_i;
WHEN s529 =>
when s529 =>
sig_PC <= X"FFFE";
WHEN s530 =>
IF (rdy_i = '1') THEN
when s530 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_F(2) <= '1';
reg_sel_pc_in <= '0';
1085,34 → 1085,34
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s531 =>
IF (rdy_i = '1') THEN
end if;
when s531 =>
if (rdy_i = '1') then
sig_PC <= X"FFFF";
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
END IF;
WHEN s544 =>
end if;
when s544 =>
sig_PC <= adr_sp_i;
WHEN s545 =>
when s545 =>
sig_PC <= adr_sp_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
WHEN s546 =>
when s546 =>
sig_PC <= adr_pc_i;
WHEN s547 =>
IF (rdy_i = '1') THEN
when s547 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
zw_w1 (7 downto 0) <= d_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
END IF;
WHEN s549 =>
IF (rdy_i = '1') THEN
end if;
when s549 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_w1 (7 downto 0);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
1119,14 → 1119,14
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s550 =>
end if;
when s550 =>
sig_PC <= adr_sp_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
WHEN s404 =>
IF (rdy_i = '1') THEN
when s404 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(7);
reg_F(7) <= reg_7flag_i;
1136,9 → 1136,9
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s556 =>
IF (rdy_i = '1') THEN
end if;
when s556 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(0);
reg_F(7) <= reg_7flag_i;
1148,9 → 1148,9
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s557 =>
IF (rdy_i = '1') THEN
end if;
when s557 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(7);
reg_F(0) <= q_a_i(7);
1161,9 → 1161,9
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s579 =>
IF (rdy_i = '1') THEN
end if;
when s579 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(0);
reg_F(7) <= reg_7flag_i;
1173,20 → 1173,20
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s201 =>
IF (rdy_i = '1' and
end if;
when s201 =>
if (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
sig_PC <= X"00" & d_i;
ELSIF ((rdy_i = '1' and
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
1195,12 → 1195,12
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1' and
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
1209,12 → 1209,12
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1' and
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
1223,15 → 1223,15
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1' and
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
1243,9 → 1243,9
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
1254,15 → 1254,15
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) THEN
zw_REG_OP = X"D5")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
1271,93 → 1271,93
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) THEN
zw_REG_OP = X"CC")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) THEN
zw_REG_OP = X"DD")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) THEN
zw_REG_OP = X"D9")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) THEN
zw_REG_OP = X"D1")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) THEN
zw_REG_OP = X"C1")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"B6") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
END IF;
WHEN s202 =>
IF (rdy_i = '1') THEN
end if;
when s202 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
END IF;
WHEN s210 =>
IF (rdy_i = '1') THEN
end if;
when s210 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s211 =>
IF (rdy_i = '1') THEN
end if;
when s211 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s215 =>
IF (rdy_i = '1') THEN
end if;
when s215 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
END IF;
WHEN s217 =>
IF (rdy_i = '1') THEN
end if;
when s217 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s218 =>
IF (rdy_i = '1') THEN
end if;
when s218 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s222 =>
IF (rdy_i = '1') THEN
end if;
when s222 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
END IF;
WHEN s223 =>
IF (rdy_i = '1') THEN
end if;
when s223 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s224 =>
IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
end if;
when s224 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
1366,10 → 1366,10
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
1378,10 → 1378,10
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
1390,13 → 1390,13
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
1408,7 → 1408,7
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
1417,13 → 1417,13
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s225 =>
IF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
end if;
when s225 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
1432,11 → 1432,11
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
1445,11 → 1445,11
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
1458,14 → 1458,14
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
1477,8 → 1477,8
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0') THEN
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
1487,53 → 1487,53
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
END IF;
WHEN s226 =>
IF (rdy_i = '1' and
end if;
when s226 =>
if (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) THEN
zw_REG_OP = X"E6")) then
sig_PC <= X"00" & d_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) THEN
zw_REG_OP = X"F6")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) THEN
zw_REG_OP = X"EE")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) THEN
zw_REG_OP = X"FE")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
END IF;
WHEN s243 =>
IF (rdy_i = '1') THEN
end if;
when s243 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
END IF;
WHEN s244 =>
IF (rdy_i = '1') THEN
end if;
when s244 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s247 =>
IF (rdy_i = '1') THEN
end if;
when s247 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s344 =>
IF (rdy_i = '1') THEN
end if;
when s344 =>
if (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
END IF;
WHEN s343 =>
IF (rdy_i = '1') THEN
end if;
when s343 =>
if (rdy_i = '1') then
zw_b1 <= d_alu_i;
END IF;
WHEN s251 =>
end if;
when s251 =>
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
1542,17 → 1542,17
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s351 =>
IF (rdy_i = '1' and
zw_REG_OP = X"24") THEN
when s351 =>
if (rdy_i = '1' and
zw_REG_OP = X"24") then
sig_PC <= X"00" & d_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"2C") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
END IF;
WHEN s361 =>
IF (rdy_i = '1') THEN
end if;
when s361 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= d_i(7);
reg_F(6) <= d_i(6);
1562,89 → 1562,89
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s360 =>
IF (rdy_i = '1') THEN
end if;
when s360 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
END IF;
WHEN s403 =>
IF (rdy_i = '1' and
end if;
when s403 =>
if (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) THEN
zw_REG_OP = X"5E")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) THEN
zw_REG_OP = X"46")) then
sig_PC <= X"00" & d_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) THEN
zw_REG_OP = X"56")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) THEN
zw_REG_OP = X"4E")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
END IF;
WHEN s406 =>
IF (rdy_i = '1') THEN
end if;
when s406 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
END IF;
WHEN s407 =>
IF (rdy_i = '1') THEN
end if;
when s407 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s409 =>
IF (rdy_i = '1') THEN
end if;
when s409 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s412 =>
IF (rdy_i = '1') THEN
end if;
when s412 =>
if (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
END IF;
WHEN s416 =>
IF (rdy_i = '1' and
end if;
when s416 =>
if (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) THEN
zw_REG_OP = X"1E")) then
zw_b1 <= d_i(6 downto 0) & '0';
zw_b2(0) <= d_i(7);
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) THEN
zw_REG_OP = X"5E")) then
zw_b1 <= '0' & d_i(7 downto 1);
zw_b2(0) <= d_i(0);
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) THEN
zw_REG_OP = X"3E")) then
zw_b1 <= d_i(6 downto 0) & reg_F(0);
zw_b2(0) <= d_i(7);
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) THEN
zw_REG_OP = X"7E")) then
zw_b1 <= reg_F(0) & d_i(7 downto 1);
zw_b2(0) <= d_i(0);
END IF;
WHEN s418 =>
end if;
when s418 =>
sig_PC <= adr_pc_i;
reg_F(0) <= zw_b2(0);
reg_F(7) <= reg_7flag_i;
1654,13 → 1654,13
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s510 =>
IF (rdy_i = '1' and
zw_REG_OP = X"65") THEN
when s510 =>
if (rdy_i = '1' and
zw_REG_OP = X"65") then
sig_PC <= X"00" & d_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') THEN
reg_F(3) = '0') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
1674,35 → 1674,35
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"75") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"6D") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"7D") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"79") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"71") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"61") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') THEN
reg_F(3) = '1') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
1716,39 → 1716,39
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s553 =>
IF (rdy_i = '1') THEN
end if;
when s553 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
END IF;
WHEN s555 =>
IF (rdy_i = '1') THEN
end if;
when s555 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s558 =>
IF (rdy_i = '1') THEN
end if;
when s558 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
END IF;
WHEN s560 =>
IF (rdy_i = '1') THEN
end if;
when s560 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s561 =>
IF (rdy_i = '1') THEN
end if;
when s561 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s563 =>
IF (rdy_i = '1') THEN
end if;
when s563 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
END IF;
WHEN s564 =>
IF (rdy_i = '1' AND
end if;
when s564 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') THEN
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
1762,9 → 1762,9
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' AND
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') THEN
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
1778,12 → 1778,12
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
END IF;
WHEN s565 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
end if;
when s565 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
1797,8 → 1797,8
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
elsif (rdy_i = '1' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
1812,14 → 1812,14
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s566 =>
IF (rdy_i = '1') THEN
end if;
when s566 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s266 =>
IF (rdy_i = '1' and (
end if;
when s266 =>
if (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
1827,7 → 1827,7
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN
(reg_F(6) = '0' and zw_REG_OP = X"70"))) then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
1834,16 → 1834,16
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "10";
zw_b2 <= d_i;
END IF;
WHEN s301 =>
IF (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN
end if;
when s301 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
1850,11 → 1850,11
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0);
END IF;
WHEN s302 =>
IF (rdy_i = '1') THEN
end if;
when s302 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
1861,8 → 1861,8
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN RES =>
end if;
when RES =>
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_pc_as <= '0';
1872,13 → 1872,13
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s511 =>
IF (rdy_i = '1' and
zw_REG_OP = X"E5") THEN
when s511 =>
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
sig_PC <= X"00" & d_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') THEN
reg_F(3) = '0') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
1892,35 → 1892,35
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F5") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"ED") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"FD") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F9") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F1") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E1") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') THEN
reg_F(3) = '1') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
1934,49 → 1934,49
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s559 =>
IF (rdy_i = '1') THEN
end if;
when s559 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
END IF;
WHEN s562 =>
IF (rdy_i = '1') THEN
end if;
when s562 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s567 =>
IF (rdy_i = '1') THEN
end if;
when s567 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s568 =>
IF (rdy_i = '1') THEN
end if;
when s568 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
END IF;
WHEN s569 =>
IF (rdy_i = '1') THEN
end if;
when s569 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s570 =>
IF (rdy_i = '1') THEN
end if;
when s570 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s571 =>
IF (rdy_i = '1') THEN
end if;
when s571 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s572 =>
IF (rdy_i = '1') THEN
end if;
when s572 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
END IF;
WHEN s573 =>
IF (rdy_i = '1' AND
end if;
when s573 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') THEN
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
1990,9 → 1990,9
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' AND
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') THEN
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
2006,12 → 2006,12
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
END IF;
WHEN s574 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
end if;
when s574 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
2025,8 → 2025,8
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
elsif (rdy_i = '1' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
2040,24 → 2040,24
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s548 =>
IF (rdy_i = '1') THEN
end if;
when s548 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
END IF;
WHEN s551 =>
end if;
when s551 =>
sig_PC <= adr_sp_i;
WHEN s552 =>
when s552 =>
sig_PC <= adr_sp_i;
WHEN s575 =>
IF (rdy_i = '1') THEN
when s575 =>
if (rdy_i = '1') then
sig_PC <= X"FFFF";
zw_b1 <= d_i;
END IF;
WHEN s576 =>
end if;
when s576 =>
sig_PC <= X"FFFE";
WHEN s577 =>
IF (rdy_i = '1') THEN
when s577 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_F(2) <= '1';
reg_sel_pc_in <= '0';
2065,27 → 2065,27
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s532 =>
IF (rdy_i = '1') THEN
end if;
when s532 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
END IF;
WHEN s533 =>
end if;
when s533 =>
sig_PC <= adr_sp_i;
WHEN s534 =>
when s534 =>
sig_PC <= adr_sp_i;
WHEN s535 =>
IF (rdy_i = '1') THEN
when s535 =>
if (rdy_i = '1') then
sig_PC <= X"FFFB";
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
END IF;
WHEN s536 =>
end if;
when s536 =>
sig_PC <= X"FFFA";
WHEN s537 =>
IF (rdy_i = '1') THEN
when s537 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
2092,15 → 2092,15
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END PROCESS clocked_proc;
end if;
when others =>
null;
end case;
end if;
end process clocked_proc;
-----------------------------------------------------------------
nextstate_proc : PROCESS (
nextstate_proc : process (
adr_nxt_pc_i,
current_state,
d_i,
2113,15 → 2113,15
zw_b3
)
-----------------------------------------------------------------
BEGIN
CASE current_state IS
WHEN FETCH =>
IF ((nmi_i = '1') AND (rdy_i = '1')) THEN
begin
case current_state is
when FETCH =>
if ((nmi_i = '1') and (rdy_i = '1')) then
next_state <= s532;
ELSIF ((irq_n_i = '0' and
reg_F(2) = '0') AND (rdy_i = '1')) THEN
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
next_state <= s548;
ELSIF ((d_i = X"69" or
elsif ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
2128,14 → 2128,14
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") AND (rdy_i = '1')) THEN
d_i = X"71") and (rdy_i = '1')) then
next_state <= s510;
ELSIF ((d_i = X"06" or
elsif ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") AND (rdy_i = '1')) THEN
d_i = X"1E") and (rdy_i = '1')) then
next_state <= s403;
ELSIF ((d_i = X"90" or
elsif ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
2142,39 → 2142,39
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") AND (rdy_i = '1')) THEN
d_i = X"70") and (rdy_i = '1')) then
next_state <= s266;
ELSIF ((d_i = X"24" or
d_i = X"2C") AND (rdy_i = '1')) THEN
elsif ((d_i = X"24" or
d_i = X"2C") and (rdy_i = '1')) then
next_state <= s351;
ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN
elsif ((d_i = X"00") and (rdy_i = '1')) then
next_state <= s526;
ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN
elsif ((d_i = X"18") and (rdy_i = '1')) then
next_state <= s12;
ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN
elsif ((d_i = X"D8") and (rdy_i = '1')) then
next_state <= s16;
ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN
elsif ((d_i = X"58") and (rdy_i = '1')) then
next_state <= s17;
ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN
elsif ((d_i = X"B8") and (rdy_i = '1')) then
next_state <= s24;
ELSIF ((d_i = X"E0" or
elsif ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") AND (rdy_i = '1')) THEN
d_i = X"EC") and (rdy_i = '1')) then
next_state <= s201;
ELSIF ((d_i = X"C0" or
elsif ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") AND (rdy_i = '1')) THEN
d_i = X"CC") and (rdy_i = '1')) then
next_state <= s201;
ELSIF ((d_i = X"C6" or
elsif ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") AND (rdy_i = '1')) THEN
d_i = X"DE") and (rdy_i = '1')) then
next_state <= s226;
ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN
elsif ((d_i = X"CA") and (rdy_i = '1')) then
next_state <= s25;
ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN
elsif ((d_i = X"88") and (rdy_i = '1')) then
next_state <= s25;
ELSIF ((d_i = X"49" or
elsif ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
2205,23 → 2205,23
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") AND (rdy_i = '1')) THEN
d_i = X"D1") and (rdy_i = '1')) then
next_state <= s201;
ELSIF ((d_i = X"E6" or
elsif ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") AND (rdy_i = '1')) THEN
d_i = X"FE") and (rdy_i = '1')) then
next_state <= s226;
ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN
elsif ((d_i = X"E8") and (rdy_i = '1')) then
next_state <= s25;
ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN
elsif ((d_i = X"C8") and (rdy_i = '1')) then
next_state <= s25;
ELSIF ((d_i = X"4C" or
d_i = X"6C") AND (rdy_i = '1')) THEN
elsif ((d_i = X"4C" or
d_i = X"6C") and (rdy_i = '1')) then
next_state <= s271;
ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN
elsif ((d_i = X"20") and (rdy_i = '1')) then
next_state <= s397;
ELSIF ((d_i = X"A9" or
elsif ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
2228,50 → 2228,50
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") AND (rdy_i = '1')) THEN
d_i = X"B1") and (rdy_i = '1')) then
next_state <= s201;
ELSIF ((d_i = X"A2" or
elsif ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") AND (rdy_i = '1')) THEN
d_i = X"BE") and (rdy_i = '1')) then
next_state <= s201;
ELSIF ((d_i = X"A0" or
elsif ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") AND (rdy_i = '1')) THEN
d_i = X"BC") and (rdy_i = '1')) then
next_state <= s201;
ELSIF ((d_i = X"46" or
elsif ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") AND (rdy_i = '1')) THEN
d_i = X"5E") and (rdy_i = '1')) then
next_state <= s403;
ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN
elsif ((d_i = X"EA") and (rdy_i = '1')) then
next_state <= s1;
ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN
elsif ((d_i = X"48") and (rdy_i = '1')) then
next_state <= s377;
ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN
elsif ((d_i = X"08") and (rdy_i = '1')) then
next_state <= s378;
ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN
elsif ((d_i = X"68") and (rdy_i = '1')) then
next_state <= s379;
ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN
elsif ((d_i = X"28") and (rdy_i = '1')) then
next_state <= s380;
ELSIF ((d_i = X"26" or
elsif ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") AND (rdy_i = '1')) THEN
d_i = X"3E") and (rdy_i = '1')) then
next_state <= s403;
ELSIF ((d_i = X"66" or
elsif ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") AND (rdy_i = '1')) THEN
d_i = X"7E") and (rdy_i = '1')) then
next_state <= s403;
ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN
elsif ((d_i = X"40") and (rdy_i = '1')) then
next_state <= s387;
ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN
elsif ((d_i = X"60") and (rdy_i = '1')) then
next_state <= s390;
ELSIF ((d_i = X"E9" or
elsif ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
2278,494 → 2278,494
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") AND (rdy_i = '1')) THEN
d_i = X"F1") and (rdy_i = '1')) then
next_state <= s511;
ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN
elsif ((d_i = X"38") and (rdy_i = '1')) then
next_state <= s2;
ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN
elsif ((d_i = X"F8") and (rdy_i = '1')) then
next_state <= s5;
ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN
elsif ((d_i = X"78") and (rdy_i = '1')) then
next_state <= s3;
ELSIF ((d_i = X"85" or
elsif ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91") AND (rdy_i = '1')) THEN
d_i = X"91") and (rdy_i = '1')) then
next_state <= s177;
ELSIF ((d_i = X"86" or
elsif ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") AND (rdy_i = '1')) THEN
d_i = X"8E") and (rdy_i = '1')) then
next_state <= s177;
ELSIF ((d_i = X"84" or
elsif ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") AND (rdy_i = '1')) THEN
d_i = X"8C") and (rdy_i = '1')) then
next_state <= s177;
ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN
elsif ((d_i = X"AA") and (rdy_i = '1')) then
next_state <= s4;
ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"0A") and (rdy_i = '1')) then
next_state <= s404;
ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"4A") and (rdy_i = '1')) then
next_state <= s556;
ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"2A") and (rdy_i = '1')) then
next_state <= s557;
ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"6A") and (rdy_i = '1')) then
next_state <= s579;
ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN
elsif ((d_i = X"A8") and (rdy_i = '1')) then
next_state <= s4;
ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN
elsif ((d_i = X"98") and (rdy_i = '1')) then
next_state <= s4;
ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN
elsif ((d_i = X"BA") and (rdy_i = '1')) then
next_state <= s4;
ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"8A") and (rdy_i = '1')) then
next_state <= s4;
ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"9A") and (rdy_i = '1')) then
next_state <= s4;
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
next_state <= s1;
ELSE
else
next_state <= FETCH;
END IF;
WHEN s1 =>
IF (rdy_i = '1') THEN
end if;
when s1 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s1;
END IF;
WHEN s2 =>
IF (rdy_i = '1') THEN
end if;
when s2 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s2;
END IF;
WHEN s5 =>
IF (rdy_i = '1') THEN
end if;
when s5 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s5;
END IF;
WHEN s3 =>
IF (rdy_i = '1') THEN
end if;
when s3 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s3;
END IF;
WHEN s4 =>
IF (rdy_i = '1' and
zw_REG_OP = X"9A") THEN
end if;
when s4 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
next_state <= FETCH;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"BA") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s4;
END IF;
WHEN s12 =>
IF (rdy_i = '1') THEN
end if;
when s12 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s12;
END IF;
WHEN s16 =>
IF (rdy_i = '1') THEN
end if;
when s16 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s16;
END IF;
WHEN s17 =>
IF (rdy_i = '1') THEN
end if;
when s17 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s17;
END IF;
WHEN s24 =>
IF (rdy_i = '1') THEN
end if;
when s24 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s24;
END IF;
WHEN s25 =>
IF (rdy_i = '1') THEN
end if;
when s25 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s25;
END IF;
WHEN s271 =>
IF (rdy_i = '1' and
zw_REG_OP = X"4C") THEN
end if;
when s271 =>
if (rdy_i = '1' and
zw_REG_OP = X"4C") then
next_state <= s307;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"6C") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"6C") then
next_state <= s273;
ELSE
else
next_state <= s271;
END IF;
WHEN s273 =>
IF (rdy_i = '1') THEN
end if;
when s273 =>
if (rdy_i = '1') then
next_state <= s304;
ELSE
else
next_state <= s273;
END IF;
WHEN s304 =>
IF (rdy_i = '1') THEN
end if;
when s304 =>
if (rdy_i = '1') then
next_state <= s307;
ELSE
else
next_state <= s304;
END IF;
WHEN s307 =>
IF (rdy_i = '1') THEN
end if;
when s307 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s307;
END IF;
WHEN s177 =>
IF (rdy_i = '1' and
end if;
when s177 =>
if (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) THEN
zw_REG_OP = X"84")) then
next_state <= s184;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) THEN
zw_REG_OP = X"94")) then
next_state <= s185;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) THEN
zw_REG_OP = X"8C")) then
next_state <= s183;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"9D") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"9D") then
next_state <= s182;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"99") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
next_state <= s180;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"91") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
next_state <= s181;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"81") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
next_state <= s186;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"96") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
next_state <= s185;
ELSE
else
next_state <= s177;
END IF;
WHEN s180 =>
IF (rdy_i = '1') THEN
end if;
when s180 =>
if (rdy_i = '1') then
next_state <= s191;
ELSE
else
next_state <= s180;
END IF;
WHEN s181 =>
IF (rdy_i = '1') THEN
end if;
when s181 =>
if (rdy_i = '1') then
next_state <= s189;
ELSE
else
next_state <= s181;
END IF;
WHEN s182 =>
IF (rdy_i = '1') THEN
end if;
when s182 =>
if (rdy_i = '1') then
next_state <= s191;
ELSE
else
next_state <= s182;
END IF;
WHEN s183 =>
IF (rdy_i = '1') THEN
end if;
when s183 =>
if (rdy_i = '1') then
next_state <= s187;
ELSE
else
next_state <= s183;
END IF;
WHEN s184 =>
end if;
when s184 =>
next_state <= FETCH;
WHEN s185 =>
IF (rdy_i = '1') THEN
when s185 =>
if (rdy_i = '1') then
next_state <= s190;
ELSE
else
next_state <= s185;
END IF;
WHEN s186 =>
IF (rdy_i = '1') THEN
end if;
when s186 =>
if (rdy_i = '1') then
next_state <= s188;
ELSE
else
next_state <= s186;
END IF;
WHEN s187 =>
end if;
when s187 =>
next_state <= FETCH;
WHEN s188 =>
IF (rdy_i = '1') THEN
when s188 =>
if (rdy_i = '1') then
next_state <= s192;
ELSE
else
next_state <= s188;
END IF;
WHEN s189 =>
IF (rdy_i = '1') THEN
end if;
when s189 =>
if (rdy_i = '1') then
next_state <= s191;
ELSE
else
next_state <= s189;
END IF;
WHEN s190 =>
end if;
when s190 =>
next_state <= FETCH;
WHEN s191 =>
when s191 =>
next_state <= s193;
WHEN s192 =>
when s192 =>
next_state <= s193;
WHEN s193 =>
when s193 =>
next_state <= FETCH;
WHEN s377 =>
IF (rdy_i = '1') THEN
when s377 =>
if (rdy_i = '1') then
next_state <= s381;
ELSE
else
next_state <= s377;
END IF;
WHEN s381 =>
end if;
when s381 =>
next_state <= FETCH;
WHEN s378 =>
IF (rdy_i = '1') THEN
when s378 =>
if (rdy_i = '1') then
next_state <= s382;
ELSE
else
next_state <= s378;
END IF;
WHEN s382 =>
end if;
when s382 =>
next_state <= FETCH;
WHEN s379 =>
IF (rdy_i = '1') THEN
when s379 =>
if (rdy_i = '1') then
next_state <= s383;
ELSE
else
next_state <= s379;
END IF;
WHEN s383 =>
IF (rdy_i = '1') THEN
end if;
when s383 =>
if (rdy_i = '1') then
next_state <= s384;
ELSE
else
next_state <= s383;
END IF;
WHEN s384 =>
IF (rdy_i = '1') THEN
end if;
when s384 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s384;
END IF;
WHEN s380 =>
IF (rdy_i = '1') THEN
end if;
when s380 =>
if (rdy_i = '1') then
next_state <= s385;
ELSE
else
next_state <= s380;
END IF;
WHEN s385 =>
IF (rdy_i = '1') THEN
end if;
when s385 =>
if (rdy_i = '1') then
next_state <= s386;
ELSE
else
next_state <= s385;
END IF;
WHEN s386 =>
IF (rdy_i = '1') THEN
end if;
when s386 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s386;
END IF;
WHEN s387 =>
IF (rdy_i = '1') THEN
end if;
when s387 =>
if (rdy_i = '1') then
next_state <= s388;
ELSE
else
next_state <= s387;
END IF;
WHEN s388 =>
IF (rdy_i = '1') THEN
end if;
when s388 =>
if (rdy_i = '1') then
next_state <= s389;
ELSE
else
next_state <= s388;
END IF;
WHEN s389 =>
IF (rdy_i = '1') THEN
end if;
when s389 =>
if (rdy_i = '1') then
next_state <= s391;
ELSE
else
next_state <= s389;
END IF;
WHEN s391 =>
IF (rdy_i = '1') THEN
end if;
when s391 =>
if (rdy_i = '1') then
next_state <= s392;
ELSE
else
next_state <= s391;
END IF;
WHEN s392 =>
IF (rdy_i = '1') THEN
end if;
when s392 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s392;
END IF;
WHEN s390 =>
IF (rdy_i = '1') THEN
end if;
when s390 =>
if (rdy_i = '1') then
next_state <= s393;
ELSE
else
next_state <= s390;
END IF;
WHEN s393 =>
IF (rdy_i = '1') THEN
end if;
when s393 =>
if (rdy_i = '1') then
next_state <= s394;
ELSE
else
next_state <= s393;
END IF;
WHEN s394 =>
IF (rdy_i = '1') THEN
end if;
when s394 =>
if (rdy_i = '1') then
next_state <= s395;
ELSE
else
next_state <= s394;
END IF;
WHEN s395 =>
IF (rdy_i = '1') THEN
end if;
when s395 =>
if (rdy_i = '1') then
next_state <= s396;
ELSE
else
next_state <= s395;
END IF;
WHEN s396 =>
IF (rdy_i = '1') THEN
end if;
when s396 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s396;
END IF;
WHEN s397 =>
IF (rdy_i = '1') THEN
end if;
when s397 =>
if (rdy_i = '1') then
next_state <= s398;
ELSE
else
next_state <= s397;
END IF;
WHEN s398 =>
IF (rdy_i = '1') THEN
end if;
when s398 =>
if (rdy_i = '1') then
next_state <= s399;
ELSE
else
next_state <= s398;
END IF;
WHEN s399 =>
end if;
when s399 =>
next_state <= s400;
WHEN s400 =>
when s400 =>
next_state <= s401;
WHEN s401 =>
IF (rdy_i = '1') THEN
when s401 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s401;
END IF;
WHEN s526 =>
IF (rdy_i = '1') THEN
end if;
when s526 =>
if (rdy_i = '1') then
next_state <= s527;
ELSE
else
next_state <= s526;
END IF;
WHEN s527 =>
end if;
when s527 =>
next_state <= s528;
WHEN s528 =>
when s528 =>
next_state <= s529;
WHEN s529 =>
when s529 =>
next_state <= s531;
WHEN s530 =>
IF (rdy_i = '1') THEN
when s530 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s530;
END IF;
WHEN s531 =>
IF (rdy_i = '1') THEN
end if;
when s531 =>
if (rdy_i = '1') then
next_state <= s530;
ELSE
else
next_state <= s531;
END IF;
WHEN s544 =>
end if;
when s544 =>
next_state <= s550;
WHEN s545 =>
when s545 =>
next_state <= s546;
WHEN s546 =>
when s546 =>
next_state <= s547;
WHEN s547 =>
IF (rdy_i = '1') THEN
when s547 =>
if (rdy_i = '1') then
next_state <= s549;
ELSE
else
next_state <= s547;
END IF;
WHEN s549 =>
IF (rdy_i = '1') THEN
end if;
when s549 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s549;
END IF;
WHEN s550 =>
end if;
when s550 =>
next_state <= s545;
WHEN s404 =>
IF (rdy_i = '1') THEN
when s404 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s404;
END IF;
WHEN s556 =>
IF (rdy_i = '1') THEN
end if;
when s556 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s556;
END IF;
WHEN s557 =>
IF (rdy_i = '1') THEN
end if;
when s557 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s557;
END IF;
WHEN s579 =>
IF (rdy_i = '1') THEN
end if;
when s579 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s579;
END IF;
WHEN s201 =>
IF (rdy_i = '1' and
end if;
when s201 =>
if (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
next_state <= s224;
ELSIF ((rdy_i = '1' and
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
next_state <= FETCH;
ELSIF ((rdy_i = '1' and
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
next_state <= FETCH;
ELSIF ((rdy_i = '1' and
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
next_state <= FETCH;
ELSIF ((rdy_i = '1' and
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
next_state <= FETCH;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
next_state <= FETCH;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) THEN
zw_REG_OP = X"D5")) then
next_state <= s217;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
2774,426 → 2774,426
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) THEN
zw_REG_OP = X"CC")) then
next_state <= s202;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) THEN
zw_REG_OP = X"DD")) then
next_state <= s210;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) THEN
zw_REG_OP = X"D9")) then
next_state <= s211;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) THEN
zw_REG_OP = X"D1")) then
next_state <= s215;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) THEN
zw_REG_OP = X"C1")) then
next_state <= s218;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"B6") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
next_state <= s217;
ELSE
else
next_state <= s201;
END IF;
WHEN s202 =>
IF (rdy_i = '1') THEN
end if;
when s202 =>
if (rdy_i = '1') then
next_state <= s224;
ELSE
else
next_state <= s202;
END IF;
WHEN s210 =>
IF (rdy_i = '1') THEN
end if;
when s210 =>
if (rdy_i = '1') then
next_state <= s225;
ELSE
else
next_state <= s210;
END IF;
WHEN s211 =>
IF (rdy_i = '1') THEN
end if;
when s211 =>
if (rdy_i = '1') then
next_state <= s225;
ELSE
else
next_state <= s211;
END IF;
WHEN s215 =>
IF (rdy_i = '1') THEN
end if;
when s215 =>
if (rdy_i = '1') then
next_state <= s223;
ELSE
else
next_state <= s215;
END IF;
WHEN s217 =>
IF (rdy_i = '1') THEN
end if;
when s217 =>
if (rdy_i = '1') then
next_state <= s224;
ELSE
else
next_state <= s217;
END IF;
WHEN s218 =>
IF (rdy_i = '1') THEN
end if;
when s218 =>
if (rdy_i = '1') then
next_state <= s222;
ELSE
else
next_state <= s218;
END IF;
WHEN s222 =>
IF (rdy_i = '1') THEN
end if;
when s222 =>
if (rdy_i = '1') then
next_state <= s202;
ELSE
else
next_state <= s222;
END IF;
WHEN s223 =>
IF (rdy_i = '1') THEN
end if;
when s223 =>
if (rdy_i = '1') then
next_state <= s225;
ELSE
else
next_state <= s223;
END IF;
WHEN s224 =>
IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
end if;
when s224 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
next_state <= FETCH;
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
next_state <= FETCH;
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
next_state <= FETCH;
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s224;
END IF;
WHEN s225 =>
IF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
end if;
when s225 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
next_state <= FETCH;
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
next_state <= FETCH;
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
next_state <= FETCH;
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
next_state <= FETCH;
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0') THEN
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
next_state <= s224;
ELSE
else
next_state <= s225;
END IF;
WHEN s226 =>
IF (rdy_i = '1' and
end if;
when s226 =>
if (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) THEN
zw_REG_OP = X"E6")) then
next_state <= s343;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) THEN
zw_REG_OP = X"F6")) then
next_state <= s247;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) THEN
zw_REG_OP = X"EE")) then
next_state <= s243;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) THEN
zw_REG_OP = X"FE")) then
next_state <= s244;
ELSE
else
next_state <= s226;
END IF;
WHEN s243 =>
IF (rdy_i = '1') THEN
end if;
when s243 =>
if (rdy_i = '1') then
next_state <= s343;
ELSE
else
next_state <= s243;
END IF;
WHEN s244 =>
IF (rdy_i = '1') THEN
end if;
when s244 =>
if (rdy_i = '1') then
next_state <= s344;
ELSE
else
next_state <= s244;
END IF;
WHEN s247 =>
IF (rdy_i = '1') THEN
end if;
when s247 =>
if (rdy_i = '1') then
next_state <= s343;
ELSE
else
next_state <= s247;
END IF;
WHEN s344 =>
IF (rdy_i = '1') THEN
end if;
when s344 =>
if (rdy_i = '1') then
next_state <= s343;
ELSE
else
next_state <= s344;
END IF;
WHEN s343 =>
IF (rdy_i = '1') THEN
end if;
when s343 =>
if (rdy_i = '1') then
next_state <= s250;
ELSE
else
next_state <= s343;
END IF;
WHEN s250 =>
IF (rdy_i = '1') THEN
end if;
when s250 =>
if (rdy_i = '1') then
next_state <= s251;
ELSE
else
next_state <= s250;
END IF;
WHEN s251 =>
end if;
when s251 =>
next_state <= FETCH;
WHEN s351 =>
IF (rdy_i = '1' and
zw_REG_OP = X"24") THEN
when s351 =>
if (rdy_i = '1' and
zw_REG_OP = X"24") then
next_state <= s361;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"2C") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
next_state <= s360;
ELSE
else
next_state <= s351;
END IF;
WHEN s361 =>
IF (rdy_i = '1') THEN
end if;
when s361 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s361;
END IF;
WHEN s360 =>
IF (rdy_i = '1') THEN
end if;
when s360 =>
if (rdy_i = '1') then
next_state <= s361;
ELSE
else
next_state <= s360;
END IF;
WHEN s403 =>
IF (rdy_i = '1' and
end if;
when s403 =>
if (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) THEN
zw_REG_OP = X"5E")) then
next_state <= s407;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) THEN
zw_REG_OP = X"46")) then
next_state <= s413;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) THEN
zw_REG_OP = X"56")) then
next_state <= s409;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) THEN
zw_REG_OP = X"4E")) then
next_state <= s406;
ELSE
else
next_state <= s403;
END IF;
WHEN s406 =>
IF (rdy_i = '1') THEN
end if;
when s406 =>
if (rdy_i = '1') then
next_state <= s413;
ELSE
else
next_state <= s406;
END IF;
WHEN s407 =>
IF (rdy_i = '1') THEN
end if;
when s407 =>
if (rdy_i = '1') then
next_state <= s412;
ELSE
else
next_state <= s407;
END IF;
WHEN s409 =>
IF (rdy_i = '1') THEN
end if;
when s409 =>
if (rdy_i = '1') then
next_state <= s413;
ELSE
else
next_state <= s409;
END IF;
WHEN s412 =>
IF (rdy_i = '1') THEN
end if;
when s412 =>
if (rdy_i = '1') then
next_state <= s413;
ELSE
else
next_state <= s412;
END IF;
WHEN s413 =>
IF (rdy_i = '1') THEN
end if;
when s413 =>
if (rdy_i = '1') then
next_state <= s416;
ELSE
else
next_state <= s413;
END IF;
WHEN s416 =>
IF (rdy_i = '1' and
end if;
when s416 =>
if (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) THEN
zw_REG_OP = X"1E")) then
next_state <= s418;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) THEN
zw_REG_OP = X"5E")) then
next_state <= s418;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) THEN
zw_REG_OP = X"3E")) then
next_state <= s418;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) THEN
zw_REG_OP = X"7E")) then
next_state <= s418;
ELSE
else
next_state <= s416;
END IF;
WHEN s418 =>
end if;
when s418 =>
next_state <= FETCH;
WHEN s510 =>
IF (rdy_i = '1' and
zw_REG_OP = X"65") THEN
when s510 =>
if (rdy_i = '1' and
zw_REG_OP = X"65") then
next_state <= s565;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') THEN
reg_F(3) = '0') then
next_state <= FETCH;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"75") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
next_state <= s560;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"6D") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
next_state <= s553;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"7D") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
next_state <= s555;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"79") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
next_state <= s555;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"71") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
next_state <= s558;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"61") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
next_state <= s561;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') THEN
reg_F(3) = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s510;
END IF;
WHEN s553 =>
IF (rdy_i = '1') THEN
end if;
when s553 =>
if (rdy_i = '1') then
next_state <= s565;
ELSE
else
next_state <= s553;
END IF;
WHEN s555 =>
IF (rdy_i = '1') THEN
end if;
when s555 =>
if (rdy_i = '1') then
next_state <= s564;
ELSE
else
next_state <= s555;
END IF;
WHEN s558 =>
IF (rdy_i = '1') THEN
end if;
when s558 =>
if (rdy_i = '1') then
next_state <= s566;
ELSE
else
next_state <= s558;
END IF;
WHEN s560 =>
IF (rdy_i = '1') THEN
end if;
when s560 =>
if (rdy_i = '1') then
next_state <= s565;
ELSE
else
next_state <= s560;
END IF;
WHEN s561 =>
IF (rdy_i = '1') THEN
end if;
when s561 =>
if (rdy_i = '1') then
next_state <= s563;
ELSE
else
next_state <= s561;
END IF;
WHEN s563 =>
IF (rdy_i = '1') THEN
end if;
when s563 =>
if (rdy_i = '1') then
next_state <= s553;
ELSE
else
next_state <= s563;
END IF;
WHEN s564 =>
IF (rdy_i = '1' AND
end if;
when s564 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') THEN
reg_F(3) = '0') then
next_state <= FETCH;
ELSIF (rdy_i = '1' AND
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') THEN
reg_F(3) = '1') then
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
next_state <= s565;
ELSE
else
next_state <= s564;
END IF;
WHEN s565 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
end if;
when s565 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
next_state <= FETCH;
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
elsif (rdy_i = '1' and
reg_F(3) = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s565;
END IF;
WHEN s566 =>
IF (rdy_i = '1') THEN
end if;
when s566 =>
if (rdy_i = '1') then
next_state <= s564;
ELSE
else
next_state <= s566;
END IF;
WHEN s266 =>
IF (rdy_i = '1' and (
end if;
when s266 =>
if (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
3201,190 → 3201,190
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN
(reg_F(6) = '0' and zw_REG_OP = X"70"))) then
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
next_state <= s301;
ELSE
else
next_state <= s266;
END IF;
WHEN s301 =>
IF (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN
end if;
when s301 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
next_state <= s302;
ELSE
else
next_state <= s301;
END IF;
WHEN s302 =>
IF (rdy_i = '1') THEN
end if;
when s302 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s302;
END IF;
WHEN RES =>
end if;
when RES =>
next_state <= s544;
WHEN s511 =>
IF (rdy_i = '1' and
zw_REG_OP = X"E5") THEN
when s511 =>
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
next_state <= s574;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') THEN
reg_F(3) = '0') then
next_state <= FETCH;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F5") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
next_state <= s569;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"ED") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
next_state <= s559;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"FD") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
next_state <= s562;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F9") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
next_state <= s567;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F1") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
next_state <= s568;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E1") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
next_state <= s570;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') THEN
reg_F(3) = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s511;
END IF;
WHEN s559 =>
IF (rdy_i = '1') THEN
end if;
when s559 =>
if (rdy_i = '1') then
next_state <= s574;
ELSE
else
next_state <= s559;
END IF;
WHEN s562 =>
IF (rdy_i = '1') THEN
end if;
when s562 =>
if (rdy_i = '1') then
next_state <= s573;
ELSE
else
next_state <= s562;
END IF;
WHEN s567 =>
IF (rdy_i = '1') THEN
end if;
when s567 =>
if (rdy_i = '1') then
next_state <= s573;
ELSE
else
next_state <= s567;
END IF;
WHEN s568 =>
IF (rdy_i = '1') THEN
end if;
when s568 =>
if (rdy_i = '1') then
next_state <= s571;
ELSE
else
next_state <= s568;
END IF;
WHEN s569 =>
IF (rdy_i = '1') THEN
end if;
when s569 =>
if (rdy_i = '1') then
next_state <= s574;
ELSE
else
next_state <= s569;
END IF;
WHEN s570 =>
IF (rdy_i = '1') THEN
end if;
when s570 =>
if (rdy_i = '1') then
next_state <= s572;
ELSE
else
next_state <= s570;
END IF;
WHEN s571 =>
IF (rdy_i = '1') THEN
end if;
when s571 =>
if (rdy_i = '1') then
next_state <= s573;
ELSE
else
next_state <= s571;
END IF;
WHEN s572 =>
IF (rdy_i = '1') THEN
end if;
when s572 =>
if (rdy_i = '1') then
next_state <= s559;
ELSE
else
next_state <= s572;
END IF;
WHEN s573 =>
IF (rdy_i = '1' AND
end if;
when s573 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') THEN
reg_F(3) = '0') then
next_state <= FETCH;
ELSIF (rdy_i = '1' AND
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') THEN
reg_F(3) = '1') then
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
next_state <= s574;
ELSE
else
next_state <= s573;
END IF;
WHEN s574 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
end if;
when s574 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
next_state <= FETCH;
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
elsif (rdy_i = '1' and
reg_F(3) = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s574;
END IF;
WHEN s548 =>
IF (rdy_i = '1') THEN
end if;
when s548 =>
if (rdy_i = '1') then
next_state <= s551;
ELSE
else
next_state <= s548;
END IF;
WHEN s551 =>
end if;
when s551 =>
next_state <= s552;
WHEN s552 =>
when s552 =>
next_state <= s576;
WHEN s575 =>
IF (rdy_i = '1') THEN
when s575 =>
if (rdy_i = '1') then
next_state <= s577;
ELSE
else
next_state <= s575;
END IF;
WHEN s576 =>
end if;
when s576 =>
next_state <= s575;
WHEN s577 =>
IF (rdy_i = '1') THEN
when s577 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s577;
END IF;
WHEN s532 =>
IF (rdy_i = '1') THEN
end if;
when s532 =>
if (rdy_i = '1') then
next_state <= s533;
ELSE
else
next_state <= s532;
END IF;
WHEN s533 =>
end if;
when s533 =>
next_state <= s534;
WHEN s534 =>
when s534 =>
next_state <= s536;
WHEN s535 =>
IF (rdy_i = '1') THEN
when s535 =>
if (rdy_i = '1') then
next_state <= s537;
ELSE
else
next_state <= s535;
END IF;
WHEN s536 =>
end if;
when s536 =>
next_state <= s535;
WHEN s537 =>
IF (rdy_i = '1') THEN
when s537 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
else
next_state <= s537;
END IF;
WHEN OTHERS =>
end if;
when others =>
next_state <= RES;
END CASE;
END PROCESS nextstate_proc;
end case;
end process nextstate_proc;
-----------------------------------------------------------------
output_proc : PROCESS (
output_proc : process (
adr_nxt_pc_i,
adr_pc_i,
adr_sp_i,
3423,7 → 3423,7
zw_w1
)
-----------------------------------------------------------------
BEGIN
begin
-- Default Assignment
a_o <= sig_PC;
adr_o <= X"0000";
3459,19 → 3459,19
zw_ALU6 <= '0' & X"00";
 
-- Combined Actions
CASE current_state IS
WHEN FETCH =>
case current_state is
when FETCH =>
sig_RWn <= '1';
sig_RD <= '1';
sig_SYNC <= NOT (rdy_i);
IF ((nmi_i = '1') AND (rdy_i = '1')) THEN
if ((nmi_i = '1') and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((irq_n_i = '0' and
reg_F(2) = '0') AND (rdy_i = '1')) THEN
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"69" or
elsif ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
3478,16 → 3478,16
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") AND (rdy_i = '1')) THEN
d_i = X"71") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"06" or
elsif ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") AND (rdy_i = '1')) THEN
d_i = X"1E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"90" or
elsif ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
3494,51 → 3494,51
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") AND (rdy_i = '1')) THEN
d_i = X"70") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"24" or
d_i = X"2C") AND (rdy_i = '1')) THEN
elsif ((d_i = X"24" or
d_i = X"2C") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN
elsif ((d_i = X"00") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN
elsif ((d_i = X"18") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN
elsif ((d_i = X"D8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN
elsif ((d_i = X"58") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN
elsif ((d_i = X"B8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"E0" or
elsif ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") AND (rdy_i = '1')) THEN
d_i = X"EC") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"C0" or
elsif ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") AND (rdy_i = '1')) THEN
d_i = X"CC") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"C6" or
elsif ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") AND (rdy_i = '1')) THEN
d_i = X"DE") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN
elsif ((d_i = X"CA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN
elsif ((d_i = X"88") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"49" or
elsif ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
3569,29 → 3569,29
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") AND (rdy_i = '1')) THEN
d_i = X"D1") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"E6" or
elsif ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") AND (rdy_i = '1')) THEN
d_i = X"FE") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN
elsif ((d_i = X"E8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN
elsif ((d_i = X"C8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"4C" or
d_i = X"6C") AND (rdy_i = '1')) THEN
elsif ((d_i = X"4C" or
d_i = X"6C") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN
elsif ((d_i = X"20") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"A9" or
elsif ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
3598,63 → 3598,63
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") AND (rdy_i = '1')) THEN
d_i = X"B1") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"A2" or
elsif ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") AND (rdy_i = '1')) THEN
d_i = X"BE") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"A0" or
elsif ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") AND (rdy_i = '1')) THEN
d_i = X"BC") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"46" or
elsif ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") AND (rdy_i = '1')) THEN
d_i = X"5E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN
elsif ((d_i = X"EA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN
elsif ((d_i = X"48") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN
elsif ((d_i = X"08") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN
elsif ((d_i = X"68") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN
elsif ((d_i = X"28") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"26" or
elsif ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") AND (rdy_i = '1')) THEN
d_i = X"3E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"66" or
elsif ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") AND (rdy_i = '1')) THEN
d_i = X"7E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN
elsif ((d_i = X"40") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN
elsif ((d_i = X"60") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"E9" or
elsif ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
3661,107 → 3661,107
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") AND (rdy_i = '1')) THEN
d_i = X"F1") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN
elsif ((d_i = X"38") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN
elsif ((d_i = X"F8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN
elsif ((d_i = X"78") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"85" or
elsif ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91") AND (rdy_i = '1')) THEN
d_i = X"91") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"86" or
elsif ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") AND (rdy_i = '1')) THEN
d_i = X"8E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"84" or
elsif ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") AND (rdy_i = '1')) THEN
d_i = X"8C") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN
elsif ((d_i = X"AA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"0A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"4A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"2A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"6A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN
elsif ((d_i = X"A8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN
elsif ((d_i = X"98") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN
elsif ((d_i = X"BA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"8A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"9A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s1 =>
IF (rdy_i = '1') THEN
end if;
when s1 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s2 =>
IF (rdy_i = '1') THEN
end if;
when s2 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s5 =>
IF (rdy_i = '1') THEN
end if;
when s5 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s3 =>
IF (rdy_i = '1') THEN
end if;
when s3 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s4 =>
IF (rdy_i = '1' and
zw_REG_OP = X"9A") THEN
end if;
when s4 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
adr_o <= X"01" & d_regs_out_i;
ld_o <= "11";
ld_sp_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"BA") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
d_regs_in_o <= adr_sp_i (7 downto 0);
ch_a_o <= adr_sp_i (7 downto 0);
ch_b_o <= X"00";
3768,35 → 3768,35
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
ch_a_o <= d_regs_out_i;
ch_b_o <= X"00";
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s12 =>
IF (rdy_i = '1') THEN
end if;
when s12 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s16 =>
IF (rdy_i = '1') THEN
end if;
when s16 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s17 =>
IF (rdy_i = '1') THEN
end if;
when s17 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s24 =>
IF (rdy_i = '1') THEN
end if;
when s24 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s25 =>
IF (rdy_i = '1') THEN
end if;
when s25 =>
if (rdy_i = '1') then
d_regs_in_o <= d_alu_i;
ch_a_o <= d_regs_out_i;
ch_b_o <= zw_b4;
3803,26 → 3803,26
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s273 =>
IF (rdy_i = '1') THEN
end if;
when s273 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s307 =>
IF (rdy_i = '1') THEN
end if;
when s307 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s177 =>
IF (rdy_i = '1' and
end if;
when s177 =>
if (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) THEN
zw_REG_OP = X"84")) then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
3829,65 → 3829,65
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) THEN
zw_REG_OP = X"94")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) THEN
zw_REG_OP = X"8C")) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"9D") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"9D") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"99") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"91") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
ch_a_o <= d_i;
ch_b_o <= X"01";
ELSIF (rdy_i = '1' and
zw_REG_OP = X"81") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"96") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
END IF;
WHEN s180 =>
IF (rdy_i = '1') THEN
end if;
when s180 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s181 =>
IF (rdy_i = '1') THEN
end if;
when s181 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
END IF;
WHEN s182 =>
end if;
when s182 =>
sig_RWn <= '1';
sig_RD <= '1';
IF (rdy_i = '1') THEN
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s183 =>
IF (rdy_i = '1') THEN
end if;
when s183 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
3894,12 → 3894,12
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s184 =>
end if;
when s184 =>
sig_SYNC <= '1';
fetch_o <= '1';
WHEN s185 =>
IF (rdy_i = '1') THEN
when s185 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
3906,31 → 3906,31
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s187 =>
end if;
when s187 =>
sig_SYNC <= '1';
fetch_o <= '1';
WHEN s188 =>
IF (rdy_i = '1') THEN
when s188 =>
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
END IF;
WHEN s189 =>
IF (rdy_i = '1') THEN
end if;
when s189 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s190 =>
end if;
when s190 =>
sig_SYNC <= '1';
fetch_o <= '1';
WHEN s191 =>
when s191 =>
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
WHEN s192 =>
when s192 =>
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
3937,11 → 3937,11
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
WHEN s193 =>
when s193 =>
sig_SYNC <= '1';
fetch_o <= '1';
WHEN s377 =>
IF (rdy_i = '1') THEN
when s377 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
3948,12 → 3948,12
sig_D_OUT <= q_a_i;
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s381 =>
end if;
when s381 =>
sig_SYNC <= '1';
fetch_o <= '1';
WHEN s378 =>
IF (rdy_i = '1') THEN
when s378 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
3960,17 → 3960,17
sig_D_OUT <= reg_F;
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s382 =>
end if;
when s382 =>
sig_SYNC <= '1';
fetch_o <= '1';
WHEN s379 =>
IF (rdy_i = '1') THEN
when s379 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s384 =>
IF (rdy_i = '1') THEN
end if;
when s384 =>
if (rdy_i = '1') then
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
3977,75 → 3977,75
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s380 =>
IF (rdy_i = '1') THEN
end if;
when s380 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s386 =>
IF (rdy_i = '1') THEN
end if;
when s386 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s387 =>
IF (rdy_i = '1') THEN
end if;
when s387 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s388 =>
IF (rdy_i = '1') THEN
end if;
when s388 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s389 =>
IF (rdy_i = '1') THEN
end if;
when s389 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s392 =>
IF (rdy_i = '1') THEN
end if;
when s392 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s390 =>
IF (rdy_i = '1') THEN
end if;
when s390 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s393 =>
IF (rdy_i = '1') THEN
end if;
when s393 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s395 =>
IF (rdy_i = '1') THEN
end if;
when s395 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s396 =>
IF (rdy_i = '1') THEN
end if;
when s396 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s397 =>
IF (rdy_i = '1') THEN
end if;
when s397 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
END IF;
WHEN s398 =>
IF (rdy_i = '1') THEN
end if;
when s398 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
END IF;
WHEN s399 =>
end if;
when s399 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
4052,16 → 4052,16
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
WHEN s401 =>
IF (rdy_i = '1') THEN
when s401 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s526 =>
IF (rdy_i = '1') THEN
end if;
when s526 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
4069,8 → 4069,8
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
END IF;
WHEN s527 =>
end if;
when s527 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
4077,7 → 4077,7
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
WHEN s528 =>
when s528 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
4084,37 → 4084,37
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F OR X"10";
WHEN s530 =>
IF (rdy_i = '1') THEN
when s530 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s544 =>
end if;
when s544 =>
ld_o <= "11";
ld_sp_o <= '1';
WHEN s545 =>
when s545 =>
adr_o <= X"FFFB";
ld_o <= "11";
ld_pc_o <= '1';
WHEN s546 =>
when s546 =>
ld_o <= "11";
ld_pc_o <= '1';
WHEN s549 =>
IF (rdy_i = '1') THEN
when s549 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_w1 (7 downto 0);
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s550 =>
end if;
when s550 =>
ld_o <= "11";
ld_sp_o <= '1';
WHEN s404 =>
IF (rdy_i = '1') THEN
when s404 =>
if (rdy_i = '1') then
ch_a_o <= q_a_i (6 downto 0) & '0';
ch_b_o <= X"00";
d_regs_in_o <= q_a_i (6 downto 0) & '0';
4121,9 → 4121,9
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s556 =>
IF (rdy_i = '1') THEN
end if;
when s556 =>
if (rdy_i = '1') then
ch_a_o <= '0' & q_a_i (7 downto 1);
ch_b_o <= X"00";
d_regs_in_o <= '0' & q_a_i (7 downto 1);
4130,9 → 4130,9
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s557 =>
IF (rdy_i = '1') THEN
end if;
when s557 =>
if (rdy_i = '1') then
ch_a_o <= q_a_i (6 downto 0) & reg_F(0);
ch_b_o <= X"00";
d_regs_in_o <= q_a_i (6 downto 0) & reg_F(0);
4139,9 → 4139,9
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s579 =>
IF (rdy_i = '1') THEN
end if;
when s579 =>
if (rdy_i = '1') then
ch_a_o <= reg_F(0) & q_a_i (7 downto 1);
ch_b_o <= X"00";
d_regs_in_o <= reg_F(0) & q_a_i (7 downto 1);
4148,21 → 4148,21
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s201 =>
IF (rdy_i = '1' and
end if;
when s201 =>
if (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((rdy_i = '1' and
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i OR q_a_i;
4171,12 → 4171,12
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF ((rdy_i = '1' and
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i XOR q_a_i;
4185,12 → 4185,12
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF ((rdy_i = '1' and
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i AND q_a_i;
4199,23 → 4199,23
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF ((rdy_i = '1' and
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
ld_o <= "11";
ld_pc_o <= '1';
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i;
4224,15 → 4224,15
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) THEN
zw_REG_OP = X"D5")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
4241,98 → 4241,98
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) THEN
zw_REG_OP = X"CC")) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) THEN
zw_REG_OP = X"DD")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) THEN
zw_REG_OP = X"D9")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) THEN
zw_REG_OP = X"D1")) then
ch_a_o <= d_i;
ch_b_o <= X"01";
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) THEN
zw_REG_OP = X"C1")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"B6") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
END IF;
WHEN s202 =>
IF (rdy_i = '1') THEN
end if;
when s202 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s210 =>
IF (rdy_i = '1') THEN
end if;
when s210 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s211 =>
IF (rdy_i = '1') THEN
end if;
when s211 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s215 =>
IF (rdy_i = '1') THEN
end if;
when s215 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
END IF;
WHEN s217 =>
IF (rdy_i = '1') THEN
end if;
when s217 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s222 =>
IF (rdy_i = '1') THEN
end if;
when s222 =>
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
END IF;
WHEN s223 =>
IF (rdy_i = '1') THEN
end if;
when s223 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s224 =>
IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
end if;
when s224 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
4339,10 → 4339,10
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
4349,10 → 4349,10
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
4359,17 → 4359,17
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
4376,13 → 4376,13
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s225 =>
IF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
end if;
when s225 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
4389,11 → 4389,11
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
4400,11 → 4400,11
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
4411,19 → 4411,19
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0') THEN
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
4430,187 → 4430,187
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s226 =>
IF (rdy_i = '1' and
end if;
when s226 =>
if (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) THEN
zw_REG_OP = X"E6")) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) THEN
zw_REG_OP = X"F6")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) THEN
zw_REG_OP = X"EE")) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) THEN
zw_REG_OP = X"FE")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
END IF;
WHEN s243 =>
IF (rdy_i = '1') THEN
end if;
when s243 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s244 =>
IF (rdy_i = '1') THEN
end if;
when s244 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s247 =>
IF (rdy_i = '1') THEN
end if;
when s247 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s343 =>
IF (rdy_i = '1') THEN
end if;
when s343 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= zw_b4;
END IF;
WHEN s250 =>
IF (rdy_i = '1') THEN
end if;
when s250 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= zw_b1;
END IF;
WHEN s251 =>
end if;
when s251 =>
ch_a_o <= zw_b1;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
WHEN s351 =>
IF (rdy_i = '1' and
zw_REG_OP = X"24") THEN
when s351 =>
if (rdy_i = '1' and
zw_REG_OP = X"24") then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"2C") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s361 =>
IF (rdy_i = '1') THEN
end if;
when s361 =>
if (rdy_i = '1') then
ch_a_o <= q_a_i AND d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s360 =>
IF (rdy_i = '1') THEN
end if;
when s360 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s403 =>
IF (rdy_i = '1' and
end if;
when s403 =>
if (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) THEN
zw_REG_OP = X"5E")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) THEN
zw_REG_OP = X"46")) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) THEN
zw_REG_OP = X"56")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) THEN
zw_REG_OP = X"4E")) then
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s406 =>
IF (rdy_i = '1') THEN
end if;
when s406 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s407 =>
IF (rdy_i = '1') THEN
end if;
when s407 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s409 =>
IF (rdy_i = '1') THEN
end if;
when s409 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s416 =>
IF (rdy_i = '1' and
end if;
when s416 =>
if (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) THEN
zw_REG_OP = X"1E")) then
sig_D_OUT <= d_i(6 downto 0) & '0';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) THEN
zw_REG_OP = X"5E")) then
sig_D_OUT <= '0' & d_i(7 downto 1);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) THEN
zw_REG_OP = X"3E")) then
sig_D_OUT <= d_i(6 downto 0) & reg_F(0);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) THEN
zw_REG_OP = X"7E")) then
sig_D_OUT <= reg_F(0) & d_i(7 downto 1);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
END IF;
WHEN s418 =>
end if;
when s418 =>
ch_a_o <= zw_b1;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
WHEN s510 =>
IF (rdy_i = '1' and
zw_REG_OP = X"65") THEN
when s510 =>
if (rdy_i = '1' and
zw_REG_OP = X"65") then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') THEN
reg_F(3) = '0') then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
4618,37 → 4618,37
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"75") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"6D") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"7D") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"79") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"71") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
ch_a_o <= d_i;
ch_b_o <= X"01";
ELSIF (rdy_i = '1' and
zw_REG_OP = X"61") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') THEN
reg_F(3) = '1') then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
4668,46 → 4668,46
('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s553 =>
IF (rdy_i = '1') THEN
end if;
when s553 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s555 =>
IF (rdy_i = '1') THEN
end if;
when s555 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s558 =>
IF (rdy_i = '1') THEN
end if;
when s558 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
END IF;
WHEN s560 =>
IF (rdy_i = '1') THEN
end if;
when s560 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s563 =>
IF (rdy_i = '1') THEN
end if;
when s563 =>
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
END IF;
WHEN s564 =>
IF (rdy_i = '1' AND
end if;
when s564 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') THEN
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1' AND
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') THEN
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(7 downto 5));
4725,17 → 4725,17
('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s565 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
end if;
when s565 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
elsif (rdy_i = '1' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(7 downto 5));
4753,16 → 4753,16
('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s566 =>
IF (rdy_i = '1') THEN
end if;
when s566 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s266 =>
IF (rdy_i = '1' and (
end if;
when s266 =>
if (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
4770,18 → 4770,18
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN
(reg_F(6) = '0' and zw_REG_OP = X"70"))) then
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s301 =>
IF (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN
end if;
when s301 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
ld_o <= "11";
4788,18 → 4788,18
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s302 =>
IF (rdy_i = '1') THEN
end if;
when s302 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN RES =>
end if;
when RES =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
4808,14 → 4808,14
ld_sp_o <= '1';
sig_RWn <= '1';
sig_RD <= '1';
WHEN s511 =>
IF (rdy_i = '1' and
zw_REG_OP = X"E5") THEN
when s511 =>
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') THEN
reg_F(3) = '0') then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
4823,37 → 4823,37
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F5") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"ED") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"FD") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F9") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F1") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
ch_a_o <= d_i;
ch_b_o <= X"01";
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E1") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') THEN
reg_F(3) = '1') then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
4877,60 → 4877,60
('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s559 =>
IF (rdy_i = '1') THEN
end if;
when s559 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s562 =>
IF (rdy_i = '1') THEN
end if;
when s562 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s567 =>
IF (rdy_i = '1') THEN
end if;
when s567 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s568 =>
IF (rdy_i = '1') THEN
end if;
when s568 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
END IF;
WHEN s569 =>
IF (rdy_i = '1') THEN
end if;
when s569 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s571 =>
IF (rdy_i = '1') THEN
end if;
when s571 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s572 =>
IF (rdy_i = '1') THEN
end if;
when s572 =>
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
END IF;
WHEN s573 =>
IF (rdy_i = '1' AND
end if;
when s573 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') THEN
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1' AND
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') THEN
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) +
4952,17 → 4952,17
('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s574 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
end if;
when s574 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
elsif (rdy_i = '1' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) +
4984,9 → 4984,9
('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s548 =>
IF (rdy_i = '1') THEN
end if;
when s548 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
4994,8 → 4994,8
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
END IF;
WHEN s551 =>
end if;
when s551 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
5002,7 → 5002,7
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
WHEN s552 =>
when s552 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
5009,13 → 5009,13
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F;
WHEN s577 =>
IF (rdy_i = '1') THEN
when s577 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s532 =>
IF (rdy_i = '1') THEN
end if;
when s532 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
5023,8 → 5023,8
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
END IF;
WHEN s533 =>
end if;
when s533 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
5031,7 → 5031,7
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
WHEN s534 =>
when s534 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
5038,18 → 5038,18
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F;
WHEN s537 =>
IF (rdy_i = '1') THEN
when s537 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS output_proc;
end if;
when others =>
null;
end case;
end process output_proc;
-- Concurrent Statements
-- Clocked output assignments
5058,4 → 5058,4
sync_o <= sync_o_cld;
wr_n_o <= wr_n_o_cld;
wr_o <= wr_o_cld;
END fsm;
end fsm;

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