Subversion Repositories djpeg

/djpeg/trunk/testbench/convbtoh File deleted \ No newline at end of file

djpeg/trunk/testbench/convbtoh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: djpeg/trunk/testbench/convsim =================================================================== --- djpeg/trunk/testbench/convsim (revision 8) +++ djpeg/trunk/testbench/convsim (nonexistent) @@ -1,22 +0,0 @@ -ELF



Є44 (44€4€àà
��

€€ü -ü -
ü -üšüš(
,
››ÈÈ(
(�(� Qåtd/lib/ld-linux.so.2
GNU  
 - -;ˆ4‹
@~
.r
GFvŸ
NÎ
\ñˆ¤
a2gìŠU[

 _Jv_RegisterClasses__gmon_start__libc.so.6fgetsperrorfeofmallocstrtolfclosefwriteexitfopen_IO_stdin_used__libc_start_mainfreeGLIBC_2.1GLIBC_2.0

$ii -�ii -—Ø›è›
ì›ð›ô›ø›ü›œœœ œ -œœU‰åƒìè
è`
è«ÉÃÿ5à›ÿ%ä›ÿ%è›héàÿÿÿÿ%ì›héÐÿÿÿÿ%ð›héÀÿÿÿÿ%ô›hé°ÿÿÿÿ%ø›h é ÿÿÿÿ%ü›h(é�ÿÿÿÿ%œh0é€ÿÿÿÿ%œh8épÿÿÿÿ%œh@é`ÿÿÿÿ%œhHéPÿÿÿÿ%œhPé@ÿÿÿÿ%œhXé0ÿÿÿ1í^‰áƒäðPTRh8Šh@ŠQVht…ègÿÿÿô��U‰åSƒìè[�ÃÜ‹“üÿÿÿ…Òtè¢ÿÿÿX[ÉÃ������U‰åƒì€=$œtëƒÀ£ œÿÒ¡ œ‹…ÒuëÆ$œ
ÉÃ�U‰åƒì¡›…Àt¸…Àt Ç$›ÿÐÉÃ��L$ƒäðÿqüU‰åQ�ìd
‰�¨þÿÿ‹•¨þÿÿ‹BƒÀ‹ÇD$ðŠ‰$èìþÿÿ‰Eàƒ}àuÇ$èWþÿÿÇ$è«þÿÿ‹�¨þÿÿ‹AƒÀ‹ÇD$óŠ‰$è­þÿÿ‰Eäƒ}äuÇ$èþÿÿÇ$èlþÿÿ‹Eà‰D$ÇD$
�…Üþÿÿ‰$èþÿÿÇD$ -ÇD$�…Üþÿÿ‰$è
þÿÿ‰Eè‹Eà‰D$ÇD$
�…Üþÿÿ‰$èÑýÿÿÇD$ -ÇD$�…Üþÿÿ‰$èÃýÿÿ‰Eì‹Eì‰Â¯Uè‰Ð
À
Љ$è‰ýÿÿ‰EôÆ…ØþÿÿBÆ…ÙþÿÿM‹Eä‰D$ÇD$
ÇD$�…Øþÿÿ‰$èÓýÿÿ‹Eè‰Â¯Uì‰Ð
À
ЃÀ6Á舅Ûþÿÿ‹Eè‰Â¯Uì‰Ð
À
ЃÀ6Á舅Úþÿÿ‹Eè‰Â¯Uì‰Ð
À
ЃÀ6Á舅Ùþÿÿ‹Eè‰Â¯Uì‰Ð
À
ЃÀ6ˆ…Øþÿÿ‹Eä‰D$ÇD$
ÇD$�…Øþÿÿ‰$èEýÿÿÆ…ÙþÿÿÆ…Øþÿÿ‹Eä‰D$ÇD$
ÇD$�…Øþÿÿ‰$èýÿÿ‹Eä‰D$ÇD$
ÇD$�…Øþÿÿ‰$èíüÿÿÆ…ÛþÿÿÆ…ÚþÿÿÆ…ÙþÿÿÆ…Øþÿÿ6‹Eä‰D$ÇD$
ÇD$�…Øþÿÿ‰$è¬üÿÿÇ…°þÿÿ(‹E艅´þÿÿ‹E쉅¸þÿÿfÇ…¼þÿÿ
fÇ…¾þÿÿÇ…Àþÿÿ‹Eè‰Â¯Uì‰Ð
À
Љ…ÄþÿÿÇ…Èþÿÿ,
Ç…Ìþÿÿ,
Ç…ÐþÿÿÇ…Ôþÿÿ‹Eä‰D$ÇD$(ÇD$
�…°þÿÿ‰$èüÿÿÇEøé#
‹Eè¯Eì;Eø†&
‹Eà‰D$ÇD$
�…Üþÿÿ‰$èiûÿÿÇD$ÇD$�…Üþÿÿ‰$è[ûÿÿ‰Eð‹Eøº÷uè‰Â‹Eì‰Á)щʉÐ
À
Ѓè‰Á¯Mè‹Eøº÷uè‰Ð
À
�
‰ÂUô‹Eðˆ‹Eøº÷uè‰Â‹Eì‰Á)щʉÐ
À
Ѓè‰Á¯Mè‹Eøº÷uè‰Ð
À
�
Eô�P
‹EðÁ舋Eøº÷uè‰Â‹Eì‰Á)щʉÐ
À
Ѓè‰Á¯Mè‹Eøº÷uè‰Ð
À
�
Eô�P‹EðÁ舃Eø
‹Eà‰$è8úÿÿ…À„Êþÿÿ‹Eè‰Â¯Uì‰Ð
À�‹Eä‰D$‰T$ÇD$
‹Eô‰$è¢úÿÿ‹Eà‰$èWúÿÿ‹Eä‰$èLúÿÿ‹Eô‰$èaúÿÿ¸�Äd
Y]�aüÃU‰åÉÃ�vU‰åWVSƒìè[�ÃŽè†ùÿÿ�ƒ ÿÿÿ�“ ÿÿÿ)ÐÁø‰Eðt1ÿ‰ÖPÿuÿuÿuÿGƒÆƒÄ9}ðuè�eô[^_ÉÃ������������U‰åSƒì¡üšƒøÿt1ÛÿЋƒøšƒëƒøÿuðƒÄ[]Ã���U‰åSƒìè[�Ãè<úÿÿY[ÉÃ
rbwbÿÿÿÿÿÿÿÿ
$àƒ -ÌŠH�ˆ‚˜� -¡Ü›`€ƒxƒþÿÿoHƒÿÿÿo
ðÿÿo*ƒ›„„.„>„N„^„n„~„Ž„ž„®„¾„›GCC: (GNU) 4.1.0 20060304 (Red Hat 4.1.0-2)GCC: (GNU) 4.1.0 20060304 (Red Hat 4.1.0-2)GCC: (GNU) 4.1.0 20060304 (Red Hat 4.1.0-3)GCC: (GNU) 4.1.0 20060304 (Red Hat 4.1.0-3)GCC: (GNU) 4.1.0 20060304 (Red Hat 4.1.0-3)GCC: (GNU) 4.1.0 20060304 (Red Hat 4.1.0-2).symtab.strtab.shstrtab.interp.note.ABI-tag.hash.dynsym.dynstr.gnu.version.gnu.version_r.rel.dyn.rel.plt.init.text.fini.rodata.eh_frame.ctors.dtors.jcr.dynamic.got.got.plt.data.bss.comment
�

#(�(
1H�H
P7˜�˜
ð
?ˆ‚ˆ¡
Gÿÿÿo*ƒ*TþÿÿoHƒH0
c xƒxl €ƒ€`u
àƒàp
øƒøÐ{
ЄÐü�
ÌŠÌ -‡
èŠè -�
øŠø -™
üšü - 
ݤ
›¬›Èµ
؛غ
Ü›Ü<Ã
œÉ$œ$Î
$

2 -×

lð4 \Ù
�
(�H�˜�ˆ‚*ƒHƒxƒ€ƒ àƒ -øƒЄÌŠ -èŠøŠüš›››Ø›Ü›œ$œ
ô„ñÿüš
*›
8›
E$œ

T œ
[ …qP…ñÿ}›
Š›
—øŠ
¥›
± ŠÇñÿÑ›
Úüšñÿëüšñÿþüšñÿ
üšñÿ#
Ü›
9
üšñÿL
üšñÿb
ˆr
èŠy
‹
‹
œ˜
8Š¨
àƒ -®
~
À
ЄÇ
r
Ø
Fê
@ŠTú
$œñÿt…ÄŸ
(œ 3ÌŠ -9Î
Kñ[$œñÿb¤
r(œñÿw2ˆìŠ—[
©œ¶ Ê call_gmon_startcrtstuff.c__CTOR_LIST____DTOR_LIST____JCR_LIST__completed.5751p.5749__do_global_dtors_auxframe_dummy__CTOR_END____DTOR_END____FRAME_END____JCR_END____do_global_ctors_auxconvsim.c_DYNAMIC__fini_array_end__fini_array_start__init_array_end__preinit_array_end_GLOBAL_OFFSET_TABLE___init_array_start__preinit_array_startfeof@@GLIBC_2.0_fp_hwperror@@GLIBC_2.0__dso_handle__libc_csu_fini_initmalloc@@GLIBC_2.0_startfgets@@GLIBC_2.0strtol@@GLIBC_2.0__libc_csu_init__bss_startmain__libc_start_main@@GLIBC_2.0data_start_finifclose@@GLIBC_2.1exit@@GLIBC_2.0_edatafree@@GLIBC_2.0_endfopen@@GLIBC_2.1_IO_stdin_usedfwrite@@GLIBC_2.0__data_start_Jv_RegisterClasses__gmon_start__ \ No newline at end of file

djpeg/trunk/testbench/convsim Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: djpeg/trunk/testbench/convbtoh.c =================================================================== --- djpeg/trunk/testbench/convbtoh.c (revision 8) +++ djpeg/trunk/testbench/convbtoh.c (nonexistent) @@ -1,31 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -#include -#include - -////////////////////////////////////////////////////////////////////////////// -// ƒ�ƒCƒ“ŠÖ�” -////////////////////////////////////////////////////////////////////////////// -int main(int argc, char *argv[]) -{ - unsigned char buff[4]; - char data[256]; - FILE *rfp,*wfp; - - if((rfp = fopen(argv[1],"rb")) == NULL){ - perror(0); - exit(0); - } - if((wfp = fopen(argv[2],"wb")) == NULL){ - perror(0); - exit(0); - } - while(!feof(rfp)){ - fread(buff,1,4,rfp); - sprintf(data,"%02X%02X%02X%02X\n",buff[3],buff[2],buff[1],buff[0]); - fwrite(data,1,9,wfp); - } - fclose(rfp); - fclose(wfp); - - return 0; -}

djpeg/trunk/testbench/convbtoh.c Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: djpeg/trunk/testbench/convsim.c =================================================================== --- djpeg/trunk/testbench/convsim.c (revision 8) +++ djpeg/trunk/testbench/convsim.c (nonexistent) @@ -1,108 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -#include -#include - -typedef unsigned short WORD; -typedef unsigned long DWORD; -typedef long LONG; - -typedef struct tagBITMAPINFOHEADER{ - DWORD biSize; - LONG biWidth; - LONG biHeight; - WORD biPlanes; - WORD biBitCount; - DWORD biCompression; - DWORD biSizeImage; - LONG biXPelsPerMeter; - LONG biYPelsPerMeter; - DWORD biClrUsed; - DWORD biClrImportant; -} BITMAPINFOHEADER, *PBITMAPINFOHEADER; - -////////////////////////////////////////////////////////////////////////////// -// ƒ�ƒCƒ“ŠÖ�” -////////////////////////////////////////////////////////////////////////////// -int main(int argc, char *argv[]) -{ - unsigned char buff[4]; - char data[256]; - FILE *rfp,*wfp; - - unsigned long width; - unsigned long height; - unsigned long bitdata; - unsigned char tbuff[4]; - BITMAPINFOHEADER lpBi; - - unsigned char *image; - unsigned int i; - - if((rfp = fopen(argv[1],"rb")) == NULL){ - perror(0); - exit(0); - } - - if((wfp = fopen(argv[2],"wb")) == NULL){ - perror(0); - exit(0); - } - - - fgets(data,256,rfp); - width = (unsigned int)strtol(data,NULL,10); - fgets(data,256,rfp); - height = (unsigned int)strtol(data,NULL,10); - - image = (unsigned char *)malloc(height*width*3); - - // ƒtƒ@ƒCƒ‹ƒwƒbƒ_‚Ì�Ý’è - tbuff[0] = 'B'; - tbuff[1] = 'M'; - fwrite(tbuff,2,1,wfp); - tbuff[3] = ((14 +40 +width * height * 3) >> 24) & 0xff; - tbuff[2] = ((14 +40 +width * height * 3) >> 16) & 0xff; - tbuff[1] = ((14 +40 +width * height * 3) >> 8) & 0xff; - tbuff[0] = ((14 +40 +width * height * 3) >> 0) & 0xff; - fwrite(tbuff,4,1,wfp); - tbuff[1] = 0; - tbuff[0] = 0; - fwrite(tbuff,2,1,wfp); - fwrite(tbuff,2,1,wfp); - tbuff[3] = 0; - tbuff[2] = 0; - tbuff[1] = 0; - tbuff[0] = 54; - fwrite(tbuff,4,1,wfp); - - // ƒCƒ“ƒtƒHƒ��[ƒVƒ‡ƒ“‚Ì�Ý’è - lpBi.biSize = 40; - lpBi.biWidth = width; - lpBi.biHeight = height; - lpBi.biPlanes = 1; - lpBi.biBitCount = 3*8; - lpBi.biCompression = 0; - lpBi.biSizeImage = width*height*3; - lpBi.biXPelsPerMeter = 300; - lpBi.biYPelsPerMeter = 300; - lpBi.biClrUsed = 0; - lpBi.biClrImportant = 0; - fwrite(&lpBi,1,40,wfp); - - i = 0; - while(!feof(rfp)){ - if(i>=width*height) break; - fgets(data,256,rfp); - bitdata=strtol(data,NULL,16); - image[((height-i/width-1)*width*3)+(i%width)*3+0] = (bitdata >> 0) & 0xff; - image[((height-i/width-1)*width*3)+(i%width)*3+1] = (bitdata >> 8) & 0xff; - image[((height-i/width-1)*width*3)+(i%width)*3+2] = (bitdata >> 16) & 0xff; - i++; - } - fwrite(image,1,width*height*3,wfp); - fclose(rfp); - fclose(wfp); - free(image); - - return 0; -}

djpeg/trunk/testbench/convsim.c Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: djpeg/trunk/c_model/djpeg.c =================================================================== --- djpeg/trunk/c_model/djpeg.c (revision 8) +++ djpeg/trunk/c_model/djpeg.c (revision 9) @@ -78,7 +78,7 @@ // b: ƒoƒCƒgƒJƒEƒ“ƒg(1ƒhƒbƒg•Ó‚è‚̃oƒCƒg�”) ////////////////////////////////////////////////////////////////////////////// void BmpSave(unsigned char *file,unsigned char *buff, - unsigned int x,unsigned int y,unsigned int b){ + unsigned int x,unsigned int y,unsigned int b){ BITMAPFILEHEADER lpBf; BITMAPINFOHEADER lpBi; unsigned char tbuff[4]; @@ -409,17 +409,17 @@ count ++; }else{ if(ZeroCount == 0x0 && DataCount == 0x0){ - // AC�¬•ª‚ÅEOB•„�†‚ª—ˆ‚½�ê�‡‚Í�I—¹‚·‚é - break; + // AC�¬•ª‚ÅEOB•„�†‚ª—ˆ‚½�ê�‡‚Í�I—¹‚·‚é + break; }else if(ZeroCount ==0xF && DataCount == 0x0){ - // ZRL•„�†‚ª—ˆ‚½�ê�‡�A15ŒÂ‚̃[ƒ�ƒf�[ƒ^‚Æ‚Ý‚È‚· - count += 15; + // ZRL•„�†‚ª—ˆ‚½�ê�‡�A15ŒÂ‚̃[ƒ�ƒf�[ƒ^‚Æ‚Ý‚È‚· + count += 15; }else{ - count += ZeroCount; - // ‹t—ÊŽq‰»�{ƒWƒOƒUƒO - BlockData[zigzag_table[count]] = DataCode * TableDQT[tabledqt][count]; - count ++; + count += ZeroCount; + // ‹t—ÊŽq‰»�{ƒWƒOƒUƒO + BlockData[zigzag_table[count]] = DataCode * TableDQT[tabledqt][count]; } + count ++; } } } @@ -661,8 +661,8 @@ rgb[i*3+2] = r; /* printf("[RGB]%3d: %3x,%3x,%3x = %2x,%2x,%2x\n",i, - y[i]&0x1FF,cr[p]&0x1FF,cb[p]&0x1FF, - rgb[i*3+2],rgb[i*3+1],rgb[i*3+0]); + y[i]&0x1FF,cr[p]&0x1FF,cb[p]&0x1FF, + rgb[i*3+2],rgb[i*3+1],rgb[i*3+0]); */ } } @@ -680,16 +680,16 @@ Decode411(buff,BlockY,BlockCb,BlockCr); // 4:1:1‚̃fƒR�[ƒh DecodeYUV(BlockY,BlockCb,BlockCr,rgb); // YUV�¨RGB•ÏŠ· for(i=0;i<256;i++){ - if((x*16+(i%16)> 8: - (Phase5Count == 3'd2)?Phase4R1r >> 8: - (Phase5Count == 3'd3)?Phase3Reg[4]: - 32'd0; - - reg signed [31:0] Phase5R0r; - reg signed [31:0] Phase5R1r; - - always @(posedge clk or negedge rst) begin - if(!rst) begin - Phase5R0r <= 0; - Phase5R1r <= 0; - end else begin - Phase5R0r <= Phase5R0w + Phase5R1w; - Phase5R1r <= Phase5R0w - Phase5R1w; - end - end - - assign DataOutEnable = Phase5EnableD == 1'b1 & Phase5CountD[2] == 1'b0; - assign DataOutPage = Phase5PageD; - assign DataOutCount = Phase5CountD[1:0]; - - assign Data0Out = Phase5R0r[30:15]; - assign Data1Out = Phase5R1r[30:15]; - -endmodule // jpeg_idcty Index: djpeg/trunk/src/jpeg_idctx.v =================================================================== --- djpeg/trunk/src/jpeg_idctx.v (revision 8) +++ djpeg/trunk/src/jpeg_idctx.v (nonexistent) @@ -1,1241 +0,0 @@ -//--------------------------------------------------------------------------- -// File Name : jpeg_idctx.v -// Module Name : jpeg_idctx -// Description : iDCT-X -// Project : JPEG Decoder -// Belong to : -// Author : H.Ishihara -// E-Mail : hidemi@sweetcafe.jp -// HomePage : http://www.sweetcafe.jp/ -// Date : 2006/10/01 -// Rev. : 1.1 -//--------------------------------------------------------------------------- -// Rev. Date Description -//--------------------------------------------------------------------------- -// 1.01 2006/09/01 1st Release -//--------------------------------------------------------------------------- -// $Id: -//--------------------------------------------------------------------------- -`timescale 1ps / 1ps - -module jpeg_idctx - ( - rst, - clk, - - DataInEnable, - DataInSel, - Data00In, - Data01In, - Data02In, - Data03In, - Data04In, - Data05In, - Data06In, - Data07In, - Data08In, - Data09In, - Data10In, - Data11In, - Data12In, - Data13In, - Data14In, - Data15In, - Data16In, - Data17In, - Data18In, - Data19In, - Data20In, - Data21In, - Data22In, - Data23In, - Data24In, - Data25In, - Data26In, - Data27In, - Data28In, - Data29In, - Data30In, - Data31In, - Data32In, - Data33In, - Data34In, - Data35In, - Data36In, - Data37In, - Data38In, - Data39In, - Data40In, - Data41In, - Data42In, - Data43In, - Data44In, - Data45In, - Data46In, - Data47In, - Data48In, - Data49In, - Data50In, - Data51In, - Data52In, - Data53In, - Data54In, - Data55In, - Data56In, - Data57In, - Data58In, - Data59In, - Data60In, - Data61In, - Data62In, - Data63In, - DataInIdle, - DataInRelease, - - DataOutIdle, - DataOutEnable, - DataOutPage, - DataOutCount, - Data0Out, - Data1Out - ); - - input clk; - input rst; - - input DataInEnable; - output DataInSel; - input [15:0] Data00In; - input [15:0] Data01In; - input [15:0] Data02In; - input [15:0] Data03In; - input [15:0] Data04In; - input [15:0] Data05In; - input [15:0] Data06In; - input [15:0] Data07In; - input [15:0] Data08In; - input [15:0] Data09In; - input [15:0] Data10In; - input [15:0] Data11In; - input [15:0] Data12In; - input [15:0] Data13In; - input [15:0] Data14In; - input [15:0] Data15In; - input [15:0] Data16In; - input [15:0] Data17In; - input [15:0] Data18In; - input [15:0] Data19In; - input [15:0] Data20In; - input [15:0] Data21In; - input [15:0] Data22In; - input [15:0] Data23In; - input [15:0] Data24In; - input [15:0] Data25In; - input [15:0] Data26In; - input [15:0] Data27In; - input [15:0] Data28In; - input [15:0] Data29In; - input [15:0] Data30In; - input [15:0] Data31In; - input [15:0] Data32In; - input [15:0] Data33In; - input [15:0] Data34In; - input [15:0] Data35In; - input [15:0] Data36In; - input [15:0] Data37In; - input [15:0] Data38In; - input [15:0] Data39In; - input [15:0] Data40In; - input [15:0] Data41In; - input [15:0] Data42In; - input [15:0] Data43In; - input [15:0] Data44In; - input [15:0] Data45In; - input [15:0] Data46In; - input [15:0] Data47In; - input [15:0] Data48In; - input [15:0] Data49In; - input [15:0] Data50In; - input [15:0] Data51In; - input [15:0] Data52In; - input [15:0] Data53In; - input [15:0] Data54In; - input [15:0] Data55In; - input [15:0] Data56In; - input [15:0] Data57In; - input [15:0] Data58In; - input [15:0] Data59In; - input [15:0] Data60In; - input [15:0] Data61In; - input [15:0] Data62In; - input [15:0] Data63In; - output DataInIdle; - output DataInRelease; - - input DataOutIdle; - output DataOutEnable; - output [2:0] DataOutPage; - output [1:0] DataOutCount; - output [15:0] Data0Out; - output [15:0] Data1Out; - - //------------------------------------------------------------------------- - // Phase1 - //------------------------------------------------------------------------- - reg Phase1Enable; - reg [2:0] Phase1Page; - reg [2:0] Phase1Count; - //reg Phase1EnableD; - //reg [2:0] Phase1PageD; - //reg [2:0] Phase1CountD; - reg DataInBank; - - always @(posedge clk or negedge rst) begin - if(!rst) begin - Phase1Enable <= 1'b0; - Phase1Page <= 3'd0; - Phase1Count <= 3'd0; - //Phase1EnableD <= 1'b0; - //Phase1PageD <= 3'd0; - //Phase1CountD <= 3'd0; - DataInBank <= 1'b0; - end else begin - if(Phase1Enable == 1'b0) begin - if(DataInEnable == 1'b1) begin - Phase1Enable <= 1'b1; - Phase1Page <= 3'd0; - Phase1Count <= 3'd0; - end - end else begin - if(Phase1Count == 3'd6) begin - if(Phase1Page == 3'd7) begin - Phase1Enable <= 1'b0; - Phase1Page <= 3'd0; - DataInBank <= ~DataInBank; - end else begin - Phase1Page <= Phase1Page + 3'd1; - end - Phase1Count <= 3'd0; - end else begin - Phase1Count <= Phase1Count + 3'd1; - end // else: !if(Phase1Count == 3'd6) - end // else: !if(Phase1Enable == 1'b0) - //Phase1EnableD <= Phase1Enable; - //Phase1PageD <= Phase1Page; - //Phase1CountD <= Phase1Count; - end // else: !if(!rst) - end // always @ (posedge clk or negedge rst) - - assign DataInSel = DataInBank; - assign DataInIdle = Phase1Enable == 1'b0 & DataOutIdle == 1'b1; - assign DataInRelease = Phase1Enable == 1'b1 & Phase1Count == 3'd6 & Phase1Page == 3'd7; - - wire signed [15:0] Phase1R0w; - wire signed [15:0] Phase1R1w; - wire signed [15:0] Phase1C0w; - wire signed [15:0] Phase1C1w; - wire signed [15:0] Phase1C2w; - wire signed [15:0] Phase1C3w; - -/* - always @(*) begin - case(Phase1Page) - 3'd0:begin - case(Phase1Count) - 3'd0: begin - Phase1R0w <= Data00In; - Phase1R1w <= Data04In; - end - 3'd1: begin - Phase1R0w <= Data02In; - Phase1R1w <= Data06In; - end - 3'd2: begin - Phase1R0w <= Data01In; - Phase1R1w <= Data07In; - end - 3'd3: begin - Phase1R0w <= Data05In; - Phase1R1w <= Data03In; - end - endcase // case(Phase1Count) - end // case: 3'd0 - 3'd1:begin - case(Phase1Count) - 3'd0: begin - Phase1R0w <= Data08In; - Phase1R1w <= Data12In; - end - 3'd1: begin - Phase1R0w <= Data10In; - Phase1R1w <= Data14In; - end - 3'd2: begin - Phase1R0w <= Data09In; - Phase1R1w <= Data15In; - end - 3'd3: begin - Phase1R0w <= Data13In; - Phase1R1w <= Data11In; - end - endcase // case(Phase1Count) - end // case: 3'd1 - 3'd2:begin - case(Phase1Count) - 3'd0: begin - Phase1R0w <= Data16In; - Phase1R1w <= Data20In; - end - 3'd1: begin - Phase1R0w <= Data18In; - Phase1R1w <= Data22In; - end - 3'd2: begin - Phase1R0w <= Data17In; - Phase1R1w <= Data23In; - end - 3'd3: begin - Phase1R0w <= Data21In; - Phase1R1w <= Data19In; - end - endcase // case(Phase1Count) - end // case: 3'd2 - 3'd3:begin - case(Phase1Count) - 3'd0: begin - Phase1R0w <= Data24In; - Phase1R1w <= Data28In; - end - 3'd1: begin - Phase1R0w <= Data26In; - Phase1R1w <= Data30In; - end - 3'd2: begin - Phase1R0w <= Data25In; - Phase1R1w <= Data31In; - end - 3'd3: begin - Phase1R0w <= Data29In; - Phase1R1w <= Data27In; - end - endcase // case(Phase1Count) - end // case: 3'd3 - 3'd4:begin - case(Phase1Count) - 3'd0: begin - Phase1R0w <= Data32In; - Phase1R1w <= Data36In; - end - 3'd1: begin - Phase1R0w <= Data34In; - Phase1R1w <= Data38In; - end - 3'd2: begin - Phase1R0w <= Data33In; - Phase1R1w <= Data39In; - end - 3'd3: begin - Phase1R0w <= Data37In; - Phase1R1w <= Data35In; - end - endcase // case(Phase1Count) - end // case: 3'd4 - 3'd5:begin - case(Phase1Count) - 3'd0: begin - Phase1R0w <= Data40In; - Phase1R1w <= Data44In; - end - 3'd1: begin - Phase1R0w <= Data42In; - Phase1R1w <= Data46In; - end - 3'd2: begin - Phase1R0w <= Data41In; - Phase1R1w <= Data47In; - end - 3'd3: begin - Phase1R0w <= Data45In; - Phase1R1w <= Data43In; - end - endcase // case(Phase1Count) - end // case: 3'd5 - 3'd6:begin - case(Phase1Count) - 3'd0: begin - Phase1R0w <= Data48In; - Phase1R1w <= Data52In; - end - 3'd1: begin - Phase1R0w <= Data50In; - Phase1R1w <= Data54In; - end - 3'd2: begin - Phase1R0w <= Data49In; - Phase1R1w <= Data55In; - end - 3'd3: begin - Phase1R0w <= Data53In; - Phase1R1w <= Data51In; - end - endcase // case(Phase1Count) - end // case: 3'd6 - 3'd7:begin - case(Phase1Count) - 3'd0: begin - Phase1R0w <= Data56In; - Phase1R1w <= Data60In; - end - 3'd1: begin - Phase1R0w <= Data58In; - Phase1R1w <= Data62In; - end - 3'd2: begin - Phase1R0w <= Data57In; - Phase1R1w <= Data63In; - end - 3'd3: begin - Phase1R0w <= Data61In; - Phase1R1w <= Data59In; - end - endcase // case(Phase1Count) - end // case: 3'd7 - endcase // case(Phase1Page) - end // always @ (*) -*/ - function [15:0] Phase1R0wSel; - input [2:0] Phase1Page; - input [2:0] Phase1Count; - input [15:0] Data00In; - input [15:0] Data01In; - input [15:0] Data02In; - input [15:0] Data03In; - input [15:0] Data04In; - input [15:0] Data05In; - input [15:0] Data06In; - input [15:0] Data07In; - input [15:0] Data08In; - input [15:0] Data09In; - input [15:0] Data10In; - input [15:0] Data11In; - input [15:0] Data12In; - input [15:0] Data13In; - input [15:0] Data14In; - input [15:0] Data15In; - input [15:0] Data16In; - input [15:0] Data17In; - input [15:0] Data18In; - input [15:0] Data19In; - input [15:0] Data20In; - input [15:0] Data21In; - input [15:0] Data22In; - input [15:0] Data23In; - input [15:0] Data24In; - input [15:0] Data25In; - input [15:0] Data26In; - input [15:0] Data27In; - input [15:0] Data28In; - input [15:0] Data29In; - input [15:0] Data30In; - input [15:0] Data31In; - input [15:0] Data32In; - input [15:0] Data33In; - input [15:0] Data34In; - input [15:0] Data35In; - input [15:0] Data36In; - input [15:0] Data37In; - input [15:0] Data38In; - input [15:0] Data39In; - input [15:0] Data40In; - input [15:0] Data41In; - input [15:0] Data42In; - input [15:0] Data43In; - input [15:0] Data44In; - input [15:0] Data45In; - input [15:0] Data46In; - input [15:0] Data47In; - input [15:0] Data48In; - input [15:0] Data49In; - input [15:0] Data50In; - input [15:0] Data51In; - input [15:0] Data52In; - input [15:0] Data53In; - input [15:0] Data54In; - input [15:0] Data55In; - input [15:0] Data56In; - input [15:0] Data57In; - input [15:0] Data58In; - input [15:0] Data59In; - input [15:0] Data60In; - input [15:0] Data61In; - input [15:0] Data62In; - input [15:0] Data63In; - begin - case(Phase1Page) - 3'd0:begin - case(Phase1Count) - 3'd0: begin - Phase1R0wSel = Data00In; - end - 3'd1: begin - Phase1R0wSel = Data02In; - end - 3'd2: begin - Phase1R0wSel = Data01In; - end - 3'd3: begin - Phase1R0wSel = Data05In; - end - endcase // case(Phase1Count) - end // case: 3'd0 - 3'd1:begin - case(Phase1Count) - 3'd0: begin - Phase1R0wSel = Data08In; - end - 3'd1: begin - Phase1R0wSel = Data10In; - end - 3'd2: begin - Phase1R0wSel = Data09In; - end - 3'd3: begin - Phase1R0wSel = Data13In; - end - endcase // case(Phase1Count) - end // case: 3'd1 - 3'd2:begin - case(Phase1Count) - 3'd0: begin - Phase1R0wSel = Data16In; - end - 3'd1: begin - Phase1R0wSel = Data18In; - end - 3'd2: begin - Phase1R0wSel = Data17In; - end - 3'd3: begin - Phase1R0wSel = Data21In; - end - endcase // case(Phase1Count) - end // case: 3'd2 - 3'd3:begin - case(Phase1Count) - 3'd0: begin - Phase1R0wSel = Data24In; - end - 3'd1: begin - Phase1R0wSel = Data26In; - end - 3'd2: begin - Phase1R0wSel = Data25In; - end - 3'd3: begin - Phase1R0wSel = Data29In; - end - endcase // case(Phase1Count) - end // case: 3'd3 - 3'd4:begin - case(Phase1Count) - 3'd0: begin - Phase1R0wSel = Data32In; - end - 3'd1: begin - Phase1R0wSel = Data34In; - end - 3'd2: begin - Phase1R0wSel = Data33In; - end - 3'd3: begin - Phase1R0wSel = Data37In; - end - endcase // case(Phase1Count) - end // case: 3'd4 - 3'd5:begin - case(Phase1Count) - 3'd0: begin - Phase1R0wSel = Data40In; - end - 3'd1: begin - Phase1R0wSel = Data42In; - end - 3'd2: begin - Phase1R0wSel = Data41In; - end - 3'd3: begin - Phase1R0wSel = Data45In; - end - endcase // case(Phase1Count) - end // case: 3'd5 - 3'd6:begin - case(Phase1Count) - 3'd0: begin - Phase1R0wSel = Data48In; - end - 3'd1: begin - Phase1R0wSel = Data50In; - end - 3'd2: begin - Phase1R0wSel = Data49In; - end - 3'd3: begin - Phase1R0wSel = Data53In; - end - endcase // case(Phase1Count) - end // case: 3'd6 - 3'd7:begin - case(Phase1Count) - 3'd0: begin - Phase1R0wSel = Data56In; - end - 3'd1: begin - Phase1R0wSel = Data58In; - end - 3'd2: begin - Phase1R0wSel = Data57In; - end - 3'd3: begin - Phase1R0wSel = Data61In; - end - endcase // case(Phase1Count) - end // case: 3'd7 - endcase // case(Phase1Page) - end - endfunction - function [15:0] Phase1R1wSel; - input [2:0] Phase1Page; - input [2:0] Phase1Count; - input [15:0] Data00In; - input [15:0] Data01In; - input [15:0] Data02In; - input [15:0] Data03In; - input [15:0] Data04In; - input [15:0] Data05In; - input [15:0] Data06In; - input [15:0] Data07In; - input [15:0] Data08In; - input [15:0] Data09In; - input [15:0] Data10In; - input [15:0] Data11In; - input [15:0] Data12In; - input [15:0] Data13In; - input [15:0] Data14In; - input [15:0] Data15In; - input [15:0] Data16In; - input [15:0] Data17In; - input [15:0] Data18In; - input [15:0] Data19In; - input [15:0] Data20In; - input [15:0] Data21In; - input [15:0] Data22In; - input [15:0] Data23In; - input [15:0] Data24In; - input [15:0] Data25In; - input [15:0] Data26In; - input [15:0] Data27In; - input [15:0] Data28In; - input [15:0] Data29In; - input [15:0] Data30In; - input [15:0] Data31In; - input [15:0] Data32In; - input [15:0] Data33In; - input [15:0] Data34In; - input [15:0] Data35In; - input [15:0] Data36In; - input [15:0] Data37In; - input [15:0] Data38In; - input [15:0] Data39In; - input [15:0] Data40In; - input [15:0] Data41In; - input [15:0] Data42In; - input [15:0] Data43In; - input [15:0] Data44In; - input [15:0] Data45In; - input [15:0] Data46In; - input [15:0] Data47In; - input [15:0] Data48In; - input [15:0] Data49In; - input [15:0] Data50In; - input [15:0] Data51In; - input [15:0] Data52In; - input [15:0] Data53In; - input [15:0] Data54In; - input [15:0] Data55In; - input [15:0] Data56In; - input [15:0] Data57In; - input [15:0] Data58In; - input [15:0] Data59In; - input [15:0] Data60In; - input [15:0] Data61In; - input [15:0] Data62In; - input [15:0] Data63In; - begin - case(Phase1Page) - 3'd0:begin - case(Phase1Count) - 3'd0: begin - Phase1R1wSel = Data04In; - end - 3'd1: begin - Phase1R1wSel = Data06In; - end - 3'd2: begin - Phase1R1wSel = Data07In; - end - 3'd3: begin - Phase1R1wSel = Data03In; - end - endcase // case(Phase1Count) - end // case: 3'd0 - 3'd1:begin - case(Phase1Count) - 3'd0: begin - Phase1R1wSel = Data12In; - end - 3'd1: begin - Phase1R1wSel = Data14In; - end - 3'd2: begin - Phase1R1wSel = Data15In; - end - 3'd3: begin - Phase1R1wSel = Data11In; - end - endcase // case(Phase1Count) - end // case: 3'd1 - 3'd2:begin - case(Phase1Count) - 3'd0: begin - Phase1R1wSel = Data20In; - end - 3'd1: begin - Phase1R1wSel = Data22In; - end - 3'd2: begin - Phase1R1wSel = Data23In; - end - 3'd3: begin - Phase1R1wSel = Data19In; - end - endcase // case(Phase1Count) - end // case: 3'd2 - 3'd3:begin - case(Phase1Count) - 3'd0: begin - Phase1R1wSel = Data28In; - end - 3'd1: begin - Phase1R1wSel = Data30In; - end - 3'd2: begin - Phase1R1wSel = Data31In; - end - 3'd3: begin - Phase1R1wSel = Data27In; - end - endcase // case(Phase1Count) - end // case: 3'd3 - 3'd4:begin - case(Phase1Count) - 3'd0: begin - Phase1R1wSel = Data36In; - end - 3'd1: begin - Phase1R1wSel = Data38In; - end - 3'd2: begin - Phase1R1wSel = Data39In; - end - 3'd3: begin - Phase1R1wSel = Data35In; - end - endcase // case(Phase1Count) - end // case: 3'd4 - 3'd5:begin - case(Phase1Count) - 3'd0: begin - Phase1R1wSel = Data44In; - end - 3'd1: begin - Phase1R1wSel = Data46In; - end - 3'd2: begin - Phase1R1wSel = Data47In; - end - 3'd3: begin - Phase1R1wSel = Data43In; - end - endcase // case(Phase1Count) - end // case: 3'd5 - 3'd6:begin - case(Phase1Count) - 3'd0: begin - Phase1R1wSel = Data52In; - end - 3'd1: begin - Phase1R1wSel = Data54In; - end - 3'd2: begin - Phase1R1wSel = Data55In; - end - 3'd3: begin - Phase1R1wSel = Data51In; - end - endcase // case(Phase1Count) - end // case: 3'd6 - 3'd7:begin - case(Phase1Count) - 3'd0: begin - Phase1R1wSel = Data60In; - end - 3'd1: begin - Phase1R1wSel = Data62In; - end - 3'd2: begin - Phase1R1wSel = Data63In; - end - 3'd3: begin - Phase1R1wSel = Data59In; - end - endcase // case(Phase1Count) - end // case: 3'd7 - endcase // case(Phase1Page) - end - endfunction - - assign Phase1R0w = Phase1R0wSel(Phase1Page, Phase1Count, - Data00In, Data01In, Data02In, Data03In, Data04In, Data05In, Data06In, Data07In, Data08In, Data09In, - Data10In, Data11In, Data12In, Data13In, Data14In, Data15In, Data16In, Data17In, Data18In, Data19In, - Data20In, Data21In, Data22In, Data23In, Data24In, Data25In, Data26In, Data27In, Data28In, Data29In, - Data30In, Data31In, Data32In, Data33In, Data34In, Data35In, Data36In, Data37In, Data38In, Data39In, - Data40In, Data41In, Data42In, Data43In, Data44In, Data45In, Data46In, Data47In, Data48In, Data49In, - Data50In, Data51In, Data52In, Data53In, Data54In, Data55In, Data56In, Data57In, Data58In, Data59In, - Data60In, Data61In, Data62In, Data63In - ); - assign Phase1R1w = Phase1R1wSel(Phase1Page, Phase1Count, - Data00In, Data01In, Data02In, Data03In, Data04In, Data05In, Data06In, Data07In, Data08In, Data09In, - Data10In, Data11In, Data12In, Data13In, Data14In, Data15In, Data16In, Data17In, Data18In, Data19In, - Data20In, Data21In, Data22In, Data23In, Data24In, Data25In, Data26In, Data27In, Data28In, Data29In, - Data30In, Data31In, Data32In, Data33In, Data34In, Data35In, Data36In, Data37In, Data38In, Data39In, - Data40In, Data41In, Data42In, Data43In, Data44In, Data45In, Data46In, Data47In, Data48In, Data49In, - Data50In, Data51In, Data52In, Data53In, Data54In, Data55In, Data56In, Data57In, Data58In, Data59In, - Data60In, Data61In, Data62In, Data63In - ); -/* - always @(*) begin - case(Phase1Count) - 3'd0: begin - Phase1C0w <= 16'd2896; // C4_16 - Phase1C1w <= 16'd2896; // C4_16 - Phase1C2w <= 16'd2896; // C4_16 - Phase1C3w <= 16'd2896; // C4_16 - end - 3'd1: begin - Phase1C0w <= 16'd3784; // C2_16 - Phase1C1w <= 16'd1567; // C6_16 - Phase1C2w <= 16'd1567; // C6_16 - Phase1C3w <= 16'd3784; // C2_16 - end - 3'd2: begin - Phase1C0w <= 16'd4017; // C1_16 - Phase1C1w <= 16'd799; // C7_16 - Phase1C2w <= 16'd799; // C7_16 - Phase1C3w <= 16'd4017; // C1_16 - end - 3'd3: begin - Phase1C0w <= 16'd2276; // C5_16 - Phase1C1w <= 16'd3406; // C3_16 - Phase1C2w <= 16'd3406; // C3_16 - Phase1C3w <= 16'd2276; // C5_16 - end - endcase // case(Phase1Count) - end // always @ (*) -*/ - function [15:0] Phase1C0wSel; - input [2:0] Phase1Count; - begin - case(Phase1Count) - 3'd0: begin - Phase1C0wSel = 16'd2896; // C4_16 - end - 3'd1: begin - Phase1C0wSel = 16'd3784; // C2_16 - end - 3'd2: begin - Phase1C0wSel = 16'd4017; // C1_16 - end - 3'd3: begin - Phase1C0wSel = 16'd2276; // C5_16 - end - endcase // case(Phase1Count) - end - endfunction - - function [15:0] Phase1C1wSel; - input [2:0] Phase1Count; - begin - case(Phase1Count) - 3'd0: begin - Phase1C1wSel = 16'd2896; // C4_16 - end - 3'd1: begin - Phase1C1wSel = 16'd1567; // C6_16 - end - 3'd2: begin - Phase1C1wSel = 16'd799; // C7_16 - end - 3'd3: begin - Phase1C1wSel = 16'd3406; // C3_16 - end - endcase // case(Phase1Count) - end - endfunction - - function [15:0] Phase1C2wSel; - input [2:0] Phase1Count; - begin - case(Phase1Count) - 3'd0: begin - Phase1C2wSel = 16'd2896; // C4_16 - end - 3'd1: begin - Phase1C2wSel = 16'd1567; // C6_16 - end - 3'd2: begin - Phase1C2wSel = 16'd799; // C7_16 - end - 3'd3: begin - Phase1C2wSel = 16'd3406; // C3_16 - end - endcase // case(Phase1Count) - end - endfunction - - function [15:0] Phase1C3wSel; - input [2:0] Phase1Count; - begin - case(Phase1Count) - 3'd0: begin - Phase1C3wSel = 16'd2896; // C4_16 - end - 3'd1: begin - Phase1C3wSel = 16'd3784; // C2_16 - end - 3'd2: begin - Phase1C3wSel = 16'd4017; // C1_16 - end - 3'd3: begin - Phase1C3wSel = 16'd2276; // C5_16 - end - endcase // case(Phase1Count) - end - endfunction - - assign Phase1C0w = Phase1C0wSel(Phase1Count); - assign Phase1C1w = Phase1C1wSel(Phase1Count); - assign Phase1C2w = Phase1C2wSel(Phase1Count); - assign Phase1C3w = Phase1C3wSel(Phase1Count); - - reg signed [31:0] Phase1R0r; - reg signed [31:0] Phase1R1r; - reg signed [31:0] Phase1R2r; - reg signed [31:0] Phase1R3r; - - always @(posedge clk or negedge rst) begin - if(!rst) begin - Phase1R0r <= 0; - Phase1R1r <= 0; - Phase1R2r <= 0; - Phase1R3r <= 0; - end else begin - Phase1R0r <= Phase1R0w * Phase1C0w; - Phase1R1r <= Phase1R1w * Phase1C1w; - Phase1R2r <= Phase1R0w * Phase1C2w; - Phase1R3r <= Phase1R1w * Phase1C3w; - end // else: !if(!rst) - end // always @ (posedge clk or negedge rst) - - //------------------------------------------------------------------------- - // Phase2 - // R0: s0,s3,s7,s6 - // R1: s1,s2,s4,s5 - //------------------------------------------------------------------------- - reg Phase2Enable; - reg signed [2:0] Phase2Page; - reg signed [2:0] Phase2Count; - reg Phase2EnableD; - reg signed [2:0] Phase2PageD; - reg signed [2:0] Phase2CountD; - - always @(posedge clk or negedge rst) begin - if(!rst) begin - Phase2Enable <= 1'b0; - Phase2Page <= 3'd0; - Phase2Count <= 3'd0; - Phase2EnableD <= 1'b0; - Phase2PageD <= 3'd0; - Phase2CountD <= 3'd0; - end else begin - Phase2Enable <= Phase1Enable; - Phase2Page <= Phase1Page; - Phase2Count <= Phase1Count; - Phase2EnableD <= Phase2Enable; - Phase2PageD <= Phase2Page; - Phase2CountD <= Phase2Count; - end // else: !if(!rst) - end // always @ (posedge clk or negedge rst) - - wire signed [31:0] Phase2A0w; - wire signed [31:0] Phase2A1w; -/* - always @(*) begin - Phase2A0w <= Phase1R0r + Phase1R1r; - Phase2A1w <= Phase1R2r - Phase1R3r; - end -*/ - assign Phase2A0w = Phase1R0r + Phase1R1r; - assign Phase2A1w = Phase1R2r - Phase1R3r; - - reg signed [31:0] Phase2Reg [0:7]; - - always @(posedge clk or negedge rst) begin - if(!rst) begin - Phase2Reg[0] <= 0; - Phase2Reg[1] <= 0; - Phase2Reg[2] <= 0; - Phase2Reg[3] <= 0; - Phase2Reg[4] <= 0; - Phase2Reg[5] <= 0; - Phase2Reg[6] <= 0; - Phase2Reg[7] <= 0; - end else begin - case(Phase2Count) - 3'd0: begin - Phase2Reg[0] <= Phase2A0w; - Phase2Reg[1] <= Phase2A1w; - end - 3'd1: begin - Phase2Reg[3] <= Phase2A0w; - Phase2Reg[2] <= Phase2A1w; - end - 3'd2: begin - Phase2Reg[7] <= Phase2A0w; - Phase2Reg[4] <= Phase2A1w; - end - 3'd3: begin - Phase2Reg[6] <= Phase2A0w; - Phase2Reg[5] <= Phase2A1w; - end - endcase // case(Phase2Count) - end // else: !if(!rst) - end // always @ (posedge clk or negedge rst) - - //------------------------------------------------------------------------- - // Phase3 - // R0: t0,t1,t4,t7 - // R1: t3,t2,t5,t6 - //------------------------------------------------------------------------- - reg Phase3Enable; - reg [2:0] Phase3Page; - reg [2:0] Phase3Count; - reg Phase3EnableD; - reg [2:0] Phase3PageD; - reg [2:0] Phase3CountD; - - always @(posedge clk or negedge rst) begin - if(!rst) begin - Phase3Enable <= 1'b0; - Phase3Page <= 3'd0; - Phase3Count <= 3'd0; - Phase3EnableD <= 1'b0; - Phase3PageD <= 3'd0; - Phase3CountD <= 3'd0; - end else begin - Phase3Enable <= Phase2EnableD; - Phase3Page <= Phase2PageD; - Phase3Count <= Phase2CountD; - Phase3EnableD <= Phase3Enable; - Phase3PageD <= Phase3Page; - Phase3CountD <= Phase3Count; - end // else: !if(!rst) - end // always @ (posedge clk or negedge rst) - - //reg signed [31:0] Phase3R0w; - //reg signed [31:0] Phase3R1w; - wire signed [31:0] Phase3R0w; - wire signed [31:0] Phase3R1w; - - assign Phase3R0w = (Phase3Count == 3'd0)?Phase2Reg[0]: - (Phase3Count == 3'd1)?Phase2Reg[1]: - (Phase3Count == 3'd2)?Phase2Reg[4]: - (Phase3Count == 3'd3)?Phase2Reg[7]: - 32'd0; - assign Phase3R1w = (Phase3Count == 3'd0)?Phase2Reg[3]: - (Phase3Count == 3'd1)?Phase2Reg[2]: - (Phase3Count == 3'd2)?Phase2Reg[5]: - (Phase3Count == 3'd3)?Phase2Reg[6]: - 32'd0; - - - - wire signed [31:0] Phase3A0w; - wire signed [31:0] Phase3A1w; -/* - always @(*) begin - Phase3A0w <= Phase3R0w + Phase3R1w; - Phase3A1w <= Phase3R0w - Phase3R1w; - end -*/ - assign Phase3A0w = Phase3R0w + Phase3R1w; - assign Phase3A1w = Phase3R0w - Phase3R1w; - - reg signed [31:0] Phase3Reg [0:7]; - - always @(posedge clk or negedge rst) begin - if(!rst) begin - Phase3Reg[0] <= 0; - Phase3Reg[1] <= 0; - Phase3Reg[2] <= 0; - Phase3Reg[3] <= 0; - Phase3Reg[4] <= 0; - Phase3Reg[5] <= 0; - Phase3Reg[6] <= 0; - Phase3Reg[7] <= 0; - end else begin - case(Phase3Count) - 3'd0: begin - Phase3Reg[0] <= Phase3A0w; - Phase3Reg[3] <= Phase3A1w; - end - 3'd1: begin - Phase3Reg[1] <= Phase3A0w; - Phase3Reg[2] <= Phase3A1w; - end - 3'd2: begin - Phase3Reg[4] <= Phase3A0w; - Phase3Reg[5] <= Phase3A1w; - end - 3'd3: begin - Phase3Reg[7] <= Phase3A0w; - Phase3Reg[6] <= Phase3A1w; - end - endcase // case(Phase3Count) - end // else: !if(!rst) - end // always @ (posedge clk or negedge rst) - - //------------------------------------------------------------------------- - // Phase4 - // R0: s6 - // R1: s5 - //------------------------------------------------------------------------- - reg Phase4Enable; - reg [2:0] Phase4Page; - reg [2:0] Phase4Count; - reg Phase4EnableD; - reg [2:0] Phase4PageD; - reg [2:0] Phase4CountD; - - always @(posedge clk or negedge rst) begin - if(!rst) begin - Phase4Enable <= 1'b0; - Phase4Page <= 3'd0; - Phase4Count <= 3'd0; - Phase4EnableD <= 1'b0; - Phase4PageD <= 3'd0; - Phase4CountD <= 3'd0; - end else begin - Phase4Enable <= Phase3EnableD; - Phase4Page <= Phase3PageD; - Phase4Count <= Phase3CountD; - Phase4EnableD <= Phase4Enable; - Phase4PageD <= Phase4Page; - Phase4CountD <= Phase4Count; - end // else: !if(!rst) - end // always @ (posedge clk or negedge rst) - - reg signed [42:0] Phase4R0r; - reg signed [42:0] Phase4R1r; - - wire signed [8:0] C_181; - assign C_181 = 9'h0B5; - - always @(posedge clk or negedge rst) begin - if(!rst) begin - Phase4R0r <= 0; - Phase4R1r <= 0; - end else begin - case(Phase4Count) - 3'd2: begin - Phase4R0r <= (Phase3Reg[6] + Phase3Reg[5]) * C_181; - Phase4R1r <= (Phase3Reg[6] - Phase3Reg[5]) * C_181; - end - endcase // case(Phase4Count) - end // else: !if(!rst) - end // always @ (posedge clk or negedge rst) - - //------------------------------------------------------------------------- - // Phase5 - // R0: B0,B1,B2,B3 - // R1: B7,B6,B5,B4 - //------------------------------------------------------------------------- - reg Phase5Enable; - reg [2:0] Phase5Page; - reg [2:0] Phase5Count; - reg Phase5EnableD; - reg [2:0] Phase5PageD; - reg [2:0] Phase5CountD; - - always @(posedge clk or negedge rst) begin - if(!rst) begin - Phase5Enable <= 1'b0; - Phase5Page <= 3'd0; - Phase5Count <= 3'd0; - Phase5EnableD <= 1'b0; - Phase5PageD <= 3'd0; - Phase5CountD <= 3'd0; - end else begin - Phase5Enable <= Phase4EnableD; - Phase5Page <= Phase4PageD; - Phase5Count <= Phase4CountD; - Phase5EnableD <= Phase5Enable; - Phase5PageD <= Phase5Page; - Phase5CountD <= Phase5Count; - end // else: !if(!rst) - end // always @ (posedge clk or negedge rst) - - wire signed [31:0] Phase5R0w; - wire signed [31:0] Phase5R1w; - assign Phase5R0w = (Phase5Count == 3'd0)?Phase3Reg[0]: - (Phase5Count == 3'd1)?Phase3Reg[1]: - (Phase5Count == 3'd2)?Phase3Reg[2]: - (Phase5Count == 3'd3)?Phase3Reg[3]: - 32'd0; - assign Phase5R1w = (Phase5Count == 3'd0)?Phase3Reg[7]: - (Phase5Count == 3'd1)?Phase4R0r >> 8: - (Phase5Count == 3'd2)?Phase4R1r >> 8: - (Phase5Count == 3'd3)?Phase3Reg[4]: - 32'd0; - - - reg signed [31:0] Phase5R0r; - reg signed [31:0] Phase5R1r; - - always @(posedge clk or negedge rst) begin - if(!rst) begin - Phase5R0r <= 0; - Phase5R1r <= 0; - end else begin - Phase5R0r <= Phase5R0w + Phase5R1w; - Phase5R1r <= Phase5R0w - Phase5R1w; - end - end - - assign DataOutEnable = Phase5EnableD == 1'b1 & Phase5CountD[2] == 1'b0; - assign DataOutPage = Phase5PageD; - assign DataOutCount = Phase5CountD[1:0]; - - assign Data0Out = Phase5R0r[26:11]; - assign Data1Out = Phase5R1r[26:11]; - -endmodule // jpeg_idctx Index: djpeg/trunk/src/jpeg_haffuman.v =================================================================== --- djpeg/trunk/src/jpeg_haffuman.v (revision 8) +++ djpeg/trunk/src/jpeg_haffuman.v (nonexistent) @@ -1,404 +0,0 @@ -//--------------------------------------------------------------------------- -// File Name : jpeg_haffuman.v -// Module Name : jpeg_haffuman -// Description : Haffuam top module -// Project : JPEG Decoder -// Belong to : -// Author : H.Ishihara -// E-Mail : hidemi@sweetcafe.jp -// HomePage : http://www.sweetcafe.jp/ -// Date : 2006/10/01 -// Rev. : 1.1 -//--------------------------------------------------------------------------- -// Rev. Date Description -//--------------------------------------------------------------------------- -// 1.01 2006/10/01 1st Release -//--------------------------------------------------------------------------- -// $Id: -//--------------------------------------------------------------------------- -`timescale 1ps / 1ps - -module jpeg_haffuman - ( - rst, - clk, - - // DQT Table - DqtInEnable, - DqtInColor, - DqtInCount, - DqtInData, - - // DHT Table - DhtInEnable, - DhtInColor, - DhtInCount, - DhtInData, - - // Haffuman Table - HaffumanTableEnable, // Table Data In Enable - HaffumanTableColor, // Haffuman Table Color Number - HaffumanTableCount, // Table Number - HaffumanTableCode, // Haffuman Table Code - HaffumanTableStart, // Haffuman Table Start Number - - // Haffuman Decode - DataInRun, // Data In Start - DataInEnable, // Data In Enable - DataIn, // Data In - - DecodeUseBit, // Used Data Bit - DecodeUseWidth, // Used Data Width - - // Data Out - DataOutIdle, - DataOutEnable, - DataOutColor, - DataOutSel, - Data00Reg, - Data01Reg, - Data02Reg, - Data03Reg, - Data04Reg, - Data05Reg, - Data06Reg, - Data07Reg, - Data08Reg, - Data09Reg, - Data10Reg, - Data11Reg, - Data12Reg, - Data13Reg, - Data14Reg, - Data15Reg, - Data16Reg, - Data17Reg, - Data18Reg, - Data19Reg, - Data20Reg, - Data21Reg, - Data22Reg, - Data23Reg, - Data24Reg, - Data25Reg, - Data26Reg, - Data27Reg, - Data28Reg, - Data29Reg, - Data30Reg, - Data31Reg, - Data32Reg, - Data33Reg, - Data34Reg, - Data35Reg, - Data36Reg, - Data37Reg, - Data38Reg, - Data39Reg, - Data40Reg, - Data41Reg, - Data42Reg, - Data43Reg, - Data44Reg, - Data45Reg, - Data46Reg, - Data47Reg, - Data48Reg, - Data49Reg, - Data50Reg, - Data51Reg, - Data52Reg, - Data53Reg, - Data54Reg, - Data55Reg, - Data56Reg, - Data57Reg, - Data58Reg, - Data59Reg, - Data60Reg, - Data61Reg, - Data62Reg, - Data63Reg, - DataOutRelease - - ); - - input rst; - input clk; - - // DQT Table - input DqtInEnable; - input DqtInColor; - input [5:0] DqtInCount; - input [7:0] DqtInData; - - // DHT Table - input DhtInEnable; - input [1:0] DhtInColor; - input [7:0] DhtInCount; - input [7:0] DhtInData; - - input HaffumanTableEnable; // Table Data In Enable - input [1:0] HaffumanTableColor; - input [3:0] HaffumanTableCount; // Table Number - input [15:0] HaffumanTableCode; // Haffuman Table Data - input [7:0] HaffumanTableStart; // Haffuman Table Start Number - - input DataInRun; - input DataInEnable; // Data In Enable - input [31:0] DataIn; // Data In - - output DecodeUseBit; - output [6:0] DecodeUseWidth; - - // Data Out - input DataOutIdle; - output DataOutEnable; - output [2:0] DataOutColor; - input DataOutSel; - output [15:0] Data00Reg; - output [15:0] Data01Reg; - output [15:0] Data02Reg; - output [15:0] Data03Reg; - output [15:0] Data04Reg; - output [15:0] Data05Reg; - output [15:0] Data06Reg; - output [15:0] Data07Reg; - output [15:0] Data08Reg; - output [15:0] Data09Reg; - output [15:0] Data10Reg; - output [15:0] Data11Reg; - output [15:0] Data12Reg; - output [15:0] Data13Reg; - output [15:0] Data14Reg; - output [15:0] Data15Reg; - output [15:0] Data16Reg; - output [15:0] Data17Reg; - output [15:0] Data18Reg; - output [15:0] Data19Reg; - output [15:0] Data20Reg; - output [15:0] Data21Reg; - output [15:0] Data22Reg; - output [15:0] Data23Reg; - output [15:0] Data24Reg; - output [15:0] Data25Reg; - output [15:0] Data26Reg; - output [15:0] Data27Reg; - output [15:0] Data28Reg; - output [15:0] Data29Reg; - output [15:0] Data30Reg; - output [15:0] Data31Reg; - output [15:0] Data32Reg; - output [15:0] Data33Reg; - output [15:0] Data34Reg; - output [15:0] Data35Reg; - output [15:0] Data36Reg; - output [15:0] Data37Reg; - output [15:0] Data38Reg; - output [15:0] Data39Reg; - output [15:0] Data40Reg; - output [15:0] Data41Reg; - output [15:0] Data42Reg; - output [15:0] Data43Reg; - output [15:0] Data44Reg; - output [15:0] Data45Reg; - output [15:0] Data46Reg; - output [15:0] Data47Reg; - output [15:0] Data48Reg; - output [15:0] Data49Reg; - output [15:0] Data50Reg; - output [15:0] Data51Reg; - output [15:0] Data52Reg; - output [15:0] Data53Reg; - output [15:0] Data54Reg; - output [15:0] Data55Reg; - output [15:0] Data56Reg; - output [15:0] Data57Reg; - output [15:0] Data58Reg; - output [15:0] Data59Reg; - output [15:0] Data60Reg; - output [15:0] Data61Reg; - output [15:0] Data62Reg; - output [15:0] Data63Reg; - input DataOutRelease; - - wire HmDqtColor; - wire [5:0] HmDqtNumber; - wire [7:0] HmDqtData; - - // DQT Table - jpeg_dqt u_jpeg_dqt( - .rst(rst), - .clk(clk), - - .DataInEnable ( DqtInEnable ), - .DataInColor ( DqtInColor ), - .DataInCount ( DqtInCount[5:0] ), - .DataIn ( DqtInData ), - - .TableColor ( HmDqtColor ), - .TableNumber ( HmDqtNumber ), - .TableData ( HmDqtData ) - ); - - wire [1:0] HmDhtColor; - wire [7:0] HmDhtNumber; - wire [3:0] HmDhtZero; - wire [3:0] HmDhtWidth; - - jpeg_dht u_jpeg_dht( - .rst(rst), - .clk(clk), - - .DataInEnable ( DhtInEnable ), - .DataInColor ( DhtInColor ), - .DataInCount ( DhtInCount ), - .DataIn ( DhtInData ), - - .ColorNumber ( HmDhtColor ), - .TableNumber ( HmDhtNumber ), - .ZeroTable ( HmDhtZero ), - .WidhtTable ( HmDhtWidth ) - ); - - //wire [2:0] HmDecColor; - wire [5:0] HmDecCount; - wire [15:0] HmDecData; - - wire HmOutEnable; - wire [2:0] HmOutColor; - - jpeg_hm_decode u_jpeg_hm_decode( - .rst(rst), - .clk(clk), - - // Haffuman Table - .HaffumanTableEnable ( HaffumanTableEnable ), - .HaffumanTableColor ( HaffumanTableColor ), - .HaffumanTableCount ( HaffumanTableCount ), - .HaffumanTableCode ( HaffumanTableCode ), - .HaffumanTableStart ( HaffumanTableStart ), - - // Haffuman Decode - .DataInRun ( DataInRun ), - .DataInEnable ( DataInEnable ), - .DataIn ( DataIn ), - - // Haffuman Table List - .DhtColor ( HmDhtColor ), - .DhtNumber ( HmDhtNumber ), - .DhtZero ( HmDhtZero ), - .DhtWidth ( HmDhtWidth ), - - // DQT Table - .DqtColor ( HmDqtColor ), - .DqtNumber ( HmDqtNumber ), - .DqtData ( HmDqtData ), - - .DataOutIdle ( HmOutIdle ), - .DataOutEnable ( HmOutEnable ), - .DataOutColor ( HmOutColor ), - - // Output decode data - .DecodeUseBit ( DecodeUseBit ), - .DecodeUseWidth ( DecodeUseWidth ), - - .DecodeEnable ( HmDecEnable ), - .DecodeColor ( ), - .DecodeCount ( HmDecCount ), - .DecodeZero ( ), - .DecodeCode ( HmDecData ) - ); - - wire BankARelease; - wire BankBRelease; - - assign BankARelease = DataOutSel == 1'b0 & DataOutRelease; - assign BankBRelease = DataOutSel == 1'b1 & DataOutRelease; - - - jpeg_ziguzagu u_jpeg_ziguzagu( - .rst(rst), - .clk(clk), - - .DataInEnable ( HmDecEnable ), - .DataInAddress ( HmDecCount ), - .DataInColor ( HmOutColor ), - .DataInIdle ( HmOutIdle ), - .DataIn ( HmDecData ), - - .HaffumanEndEnable(HmOutEnable), - - .DataOutEnable( DataOutEnable), - .DataOutColor ( DataOutColor), - .DataOutSel(DataOutSel), - .Data00Reg( Data00Reg ), - .Data01Reg( Data01Reg ), - .Data02Reg( Data02Reg ), - .Data03Reg( Data03Reg ), - .Data04Reg( Data04Reg ), - .Data05Reg( Data05Reg ), - .Data06Reg( Data06Reg ), - .Data07Reg( Data07Reg ), - .Data08Reg( Data08Reg ), - .Data09Reg( Data09Reg ), - .Data10Reg( Data10Reg ), - .Data11Reg( Data11Reg ), - .Data12Reg( Data12Reg ), - .Data13Reg( Data13Reg ), - .Data14Reg( Data14Reg ), - .Data15Reg( Data15Reg ), - .Data16Reg( Data16Reg ), - .Data17Reg( Data17Reg ), - .Data18Reg( Data18Reg ), - .Data19Reg( Data19Reg ), - .Data20Reg( Data20Reg ), - .Data21Reg( Data21Reg ), - .Data22Reg( Data22Reg ), - .Data23Reg( Data23Reg ), - .Data24Reg( Data24Reg ), - .Data25Reg( Data25Reg ), - .Data26Reg( Data26Reg ), - .Data27Reg( Data27Reg ), - .Data28Reg( Data28Reg ), - .Data29Reg( Data29Reg ), - .Data30Reg( Data30Reg ), - .Data31Reg( Data31Reg ), - .Data32Reg( Data32Reg ), - .Data33Reg( Data33Reg ), - .Data34Reg( Data34Reg ), - .Data35Reg( Data35Reg ), - .Data36Reg( Data36Reg ), - .Data37Reg( Data37Reg ), - .Data38Reg( Data38Reg ), - .Data39Reg( Data39Reg ), - .Data40Reg( Data40Reg ), - .Data41Reg( Data41Reg ), - .Data42Reg( Data42Reg ), - .Data43Reg( Data43Reg ), - .Data44Reg( Data44Reg ), - .Data45Reg( Data45Reg ), - .Data46Reg( Data46Reg ), - .Data47Reg( Data47Reg ), - .Data48Reg( Data48Reg ), - .Data49Reg( Data49Reg ), - .Data50Reg( Data50Reg ), - .Data51Reg( Data51Reg ), - .Data52Reg( Data52Reg ), - .Data53Reg( Data53Reg ), - .Data54Reg( Data54Reg ), - .Data55Reg( Data55Reg ), - .Data56Reg( Data56Reg ), - .Data57Reg( Data57Reg ), - .Data58Reg( Data58Reg ), - .Data59Reg( Data59Reg ), - .Data60Reg( Data60Reg ), - .Data61Reg( Data61Reg ), - .Data62Reg( Data62Reg ), - .Data63Reg( Data63Reg ), - - .BankARelease(BankARelease), - .BankBRelease(BankBRelease) - ); - -endmodule // jpeg_haffuman Index: djpeg/trunk/src/jpeg_regdata.v =================================================================== --- djpeg/trunk/src/jpeg_regdata.v (revision 8) +++ djpeg/trunk/src/jpeg_regdata.v (revision 9) @@ -1,209 +1,260 @@ //--------------------------------------------------------------------------- // File Name : jpeg_regdata.v // Module Name : jpeg_regdata -// Description : get Data -// Project : JPEG Decoder +// Description : Get Data +// Project : JPEG Decoder // Belong to : -// Author : H.Ishihara -// E-Mail : hidemi@sweetcafe.jp -// HomePage : http://www.sweetcafe.jp/ -// Date : 2007/04/11 -// Rev. : 1.03 +// Author : H.Ishihara +// E-Mail : hidemi@sweetcafe.jp +// HomePage : http://www.sweetcafe.jp/ +// Date : 2008/02/27 +// Rev. : 2.00 //--------------------------------------------------------------------------- -// Rev. Date Description +// Rev. Date Description //--------------------------------------------------------------------------- // 1.01 2006/10/01 1st Release // 1.02 2006/10/04 Remove a RegEnd register. -// When reset, clear on OutEnable,PreEnable,DataOut registers. -// Remove some comments. +// When reset, clear on OutEnable,PreEnable,DataOut registers. +// Remove some comments. // 1.03 2007/04/11 Don't OutEnable, ImageEnable == 1 and DataOut == 0xFFD9XXXX // Stop ReadEnable with DataEnd(after 0xFFD9 of ImageData) +// 1.04 2007/10/16 Modify (RegData[31:0] == 0xFF00FF00) process +// not convert 0xFF00 -> 0xFF after convert [7:0] == 0xFF +// 2.00 2008/02/27 Modify RegValid, when ImageEnable == 1 then RegWidth > 64 +// when ImageEnable == 0 then RegWidth > 32 +// Add SliceData Pattern //--------------------------------------------------------------------------- -// $Id: -//--------------------------------------------------------------------------- `timescale 1ps / 1ps module jpeg_regdata( - rst, - clk, - - // Read Data - DataIn, // - DataInEnable, // Data Enable - DataInRead, // Data Read - - // DataOut - DataOut, // Data Out - DataOutEnable, // Data Out Enable - - // - ImageEnable, - ProcessIdle, - - // UseData - UseBit, // Used data bit - UseWidth, // Used data bit width - UseByte, // Used data byte - UseWord // Used data word - ); - - input rst; - input clk; - - input [31:0] DataIn; - input DataInEnable; - output DataInRead; - - output [31:0] DataOut; - output DataOutEnable; - - input ImageEnable; - input ProcessIdle; - - input UseBit; - input [6:0] UseWidth; - input UseByte; - input UseWord; - - wire RegValid; - reg [95:0] RegData; - reg [7:0] RegWidth; - - reg DataEnd; - - assign RegValid = RegWidth > 64; - assign DataInRead = RegValid == 1'b0 & DataInEnable == 1'b1; - - always @(posedge clk or negedge rst) begin - if(!rst) begin - RegData <= 96'd0; - RegWidth <= 8'h00; + rst, + clk, + + // Read Data + DataIn, // + DataInEnable, // Data Enable + DataInRead, // Data Read + + // DataOut + DataOut, // Data Out + DataOutEnable, // Data Out Enable + + // + ImageEnable, + ProcessIdle, + + // UseData + UseBit, // Used data bit + UseWidth, // Used data bit width + UseByte, // Used data byte + UseWord // Used data word +); + + input rst; + input clk; + + input [31:0] DataIn; + input DataInEnable; + output DataInRead; + + output [31:0] DataOut; + output DataOutEnable; + + input ImageEnable; + input ProcessIdle; + + input UseBit; + input [6:0] UseWidth; + input UseByte; + input UseWord; + + wire RegValid; + reg [95:0] RegData; + reg [6:0] RegWidth; + reg CheckMode; + reg DataEnd; + + assign RegValid = (ImageEnable)?(RegWidth > 7'd64):(RegWidth > 7'd32); + assign DataInRead = ((RegValid == 1'b0) & (DataInEnable == 1'b1) & (DataEnd == 1'b0)); + + always @(posedge clk or negedge rst) begin + if(!rst) begin + RegData <= 96'd0; + RegWidth <= 7'd0; + CheckMode <= 1'b0; + end else begin + if(DataEnd == 1'b1 & ProcessIdle == 1'b1) begin + RegData <= 96'd0; + RegWidth <= 7'd0; + CheckMode <= 1'b0; + end else if(RegValid == 1'b0 & (DataInEnable == 1'b1 | DataEnd == 1'b1)) begin + if(ImageEnable == 1'b1) begin + if(RegData[39: 8] == 32'hFF00FF00 & CheckMode != 1'b1) begin + RegWidth <= RegWidth + 7'd16; + RegData[95:64] <= {8'h00,RegData[71:48]}; + RegData[63:32] <= {RegData[47:40],16'hFFFF,RegData[7:0]}; + CheckMode <= 1'b0; + end else if(RegData[39:24] == 16'hFF00 & RegData[15: 0] == 16'hFF00 & CheckMode != 1'b1) begin + RegWidth <= RegWidth + 7'd16; + RegData[95:64] <= {8'h00,RegData[71:48]}; + RegData[63:32] <= {RegData[47:40],8'hFF,RegData[23:16],8'hFF}; + CheckMode <= 1'b1; + end else if(RegData[31: 0] == 32'hFF00FF00) begin + RegWidth <= RegWidth + 7'd16; + RegData[95:64] <= {16'h0000,RegData[63:48]}; + RegData[63:32] <= {RegData[47:32],16'hFFFF}; + CheckMode <= 1'b1; + end else if(RegData[39:24] == 16'hFF00 & CheckMode != 1'b1) begin + RegWidth <= RegWidth + 7'd24; + RegData[95:64] <= {RegData[71:40]}; + RegData[63:32] <= {8'hFF,RegData[23:0]}; + CheckMode <= 1'b0; + end else if(RegData[31:16] == 16'hFF00) begin + RegWidth <= RegWidth + 7'd24; + RegData[95:64] <= {RegData[71:40]}; + RegData[63:32] <= {RegData[39:32],8'hFF,RegData[15:0]}; + CheckMode <= 1'b0; + end else if(RegData[23: 8] == 16'hFF00) begin + RegWidth <= RegWidth + 7'd24; + RegData[95:64] <= {RegData[71:40]}; + RegData[63:32] <= {RegData[39:32],RegData[31:24],8'hFF,RegData[7:0]}; + CheckMode <= 1'b0; + end else if(RegData[15: 0] == 16'hFF00) begin + RegWidth <= RegWidth + 7'd24; + RegData[95:64] <= {RegData[71:40]}; + RegData[63:32] <= {RegData[39:32],RegData[31:16],8'hFF}; + CheckMode <= 1'b1; + end else begin + RegWidth <= RegWidth + 7'd32; + RegData[95:64] <= RegData[63:32]; + RegData[63:32] <= RegData[31:0]; + CheckMode <= 1'b0; + end end else begin - if(RegValid == 1'b0 & (DataInEnable == 1'b1 | DataEnd == 1'b1)) begin - if(ImageEnable == 1'b1) begin - if(RegData[39: 8] == 32'hFF00FF00) begin - RegWidth <= RegWidth + 16; - RegData[95:64] <= {8'h00,RegData[71:48]}; - RegData[63:32] <= {RegData[47:40],16'hFFFF,RegData[7:0]}; - end else if(RegData[39:24] == 16'hFF00 & - RegData[15: 0] == 16'hFF00) begin - RegWidth <= RegWidth + 16; - RegData[95:64] <= {8'h00,RegData[71:48]}; - RegData[63:32] <= {RegData[47:40],8'hFF,RegData[23:16],8'hFF}; - end else if(RegData[31: 0] == 32'hFF00FF00) begin - RegWidth <= RegWidth + 16; - RegData[95:64] <= {16'h0000,RegData[71:56]}; - RegData[63:32] <= {RegData[55:40],16'hFFFF}; - end else if(RegData[39:24] == 16'hFF00) begin - RegWidth <= RegWidth + 24; - RegData[95:64] <= {RegData[71:40]}; - RegData[63:32] <= {8'hFF,RegData[23:0]}; - end else if(RegData[31:16] == 16'hFF00) begin - RegWidth <= RegWidth + 24; - RegData[95:64] <= {RegData[71:40]}; - RegData[63:32] <= {RegData[39:32],8'hFF,RegData[15:0]}; - end else if(RegData[23: 8] == 16'hFF00) begin - RegWidth <= RegWidth + 24; - RegData[95:64] <= {RegData[71:40]}; - RegData[63:32] <= {RegData[39:32],RegData[31:24],8'hFF,RegData[7:0]}; - end else if(RegData[15: 0] == 16'hFF00) begin - RegWidth <= RegWidth + 24; - RegData[95:64] <= {RegData[71:40]}; - RegData[63:32] <= {RegData[39:32],RegData[31:16],8'hFF}; - end else begin - RegWidth <= RegWidth + 32; - RegData[95:64] <= RegData[63:32]; - RegData[63:32] <= RegData[31:0]; - end - end else begin - RegWidth <= RegWidth + 32; - RegData[95:64] <= RegData[63:32]; - RegData[63:32] <= RegData[31:0]; - end - RegData[31: 0] <= {DataIn[7:0],DataIn[15:8],DataIn[23:16],DataIn[31:24]}; - end else if(UseBit == 1'b1) begin - RegWidth <= RegWidth - UseWidth; - end else if(UseByte == 1'b1) begin - RegWidth <= RegWidth - 8; - end else if(UseWord == 1'b1) begin - RegWidth <= RegWidth - 16; - end + RegWidth <= RegWidth + 7'd32; + RegData[95:64] <= RegData[63:32]; + RegData[63:32] <= RegData[31:0]; + CheckMode <= 1'b0; end + RegData[31: 0] <= {DataIn[7:0],DataIn[15:8],DataIn[23:16],DataIn[31:24]}; + end else if(UseBit == 1'b1) begin + RegWidth <= RegWidth - UseWidth; + end else if(UseByte == 1'b1) begin + RegWidth <= RegWidth - 7'd8; + end else if(UseWord == 1'b1) begin + RegWidth <= RegWidth - 7'd16; + end end - - always @(posedge clk or negedge rst) begin - if(!rst) begin - DataEnd <= 1'b0; - end else begin - if(ProcessIdle) begin - DataEnd <= 1'b0; - end else if(ImageEnable == 1'b1 & (RegData[39:24] == 16'hFFD9 | RegData[31:16] == 16'hFFD9 | RegData[23: 8] == 16'hFFD9 | RegData[15: 0] == 16'hFFD9)) begin - DataEnd <= 1'b1; - end - end + end + + // PickUp with End of Jpeg Data + always @(posedge clk or negedge rst) begin + if(!rst) begin + DataEnd <= 1'b0; + end else begin + if(ProcessIdle) begin + DataEnd <= 1'b0; + end else if(ImageEnable == 1'b1 & ((RegData[39:24] == 16'hFFD9 & CheckMode != 1'b1) | RegData[31:16] == 16'hFFD9 | RegData[23: 8] == 16'hFFD9 | RegData[15: 0] == 16'hFFD9)) begin + DataEnd <= 1'b1; + end end + end + + function [31:0] SliceData; + input [95:0] RegData; + input [7:0] RegWidth; + + case(RegWidth) + //8'd33: SliceData = RegData[32: 1]; + //8'd34: SliceData = RegData[33: 2]; + //8'd35: SliceData = RegData[34: 3]; + //8'd36: SliceData = RegData[35: 4]; + //8'd37: SliceData = RegData[36: 5]; + //8'd38: SliceData = RegData[37: 6]; + //8'd39: SliceData = RegData[38: 7]; + 8'd40: SliceData = RegData[39: 8]; + //8'd41: SliceData = RegData[40: 9]; + //8'd42: SliceData = RegData[41:10]; + //8'd43: SliceData = RegData[42:11]; + //8'd44: SliceData = RegData[43:12]; + //8'd45: SliceData = RegData[44:13]; + //8'd46: SliceData = RegData[45:14]; + //8'd47: SliceData = RegData[46:15]; + 8'd48: SliceData = RegData[47:16]; + //8'd49: SliceData = RegData[48:17]; + //8'd50: SliceData = RegData[49:18]; + //8'd51: SliceData = RegData[50:19]; + //8'd52: SliceData = RegData[51:20]; + //8'd53: SliceData = RegData[52:21]; + //8'd54: SliceData = RegData[53:22]; + //8'd55: SliceData = RegData[54:23]; + 8'd56: SliceData = RegData[55:24]; + //8'd57: SliceData = RegData[56:25]; + //8'd58: SliceData = RegData[57:26]; + //8'd59: SliceData = RegData[58:27]; + //8'd60: SliceData = RegData[59:28]; + //8'd61: SliceData = RegData[60:29]; + //8'd62: SliceData = RegData[61:30]; + //8'd63: SliceData = RegData[62:31]; + 8'd64: SliceData = RegData[63:32]; + 8'd65: SliceData = RegData[64:33]; + 8'd66: SliceData = RegData[65:34]; + 8'd67: SliceData = RegData[66:35]; + 8'd68: SliceData = RegData[67:36]; + 8'd69: SliceData = RegData[68:37]; + 8'd70: SliceData = RegData[69:38]; + 8'd71: SliceData = RegData[70:39]; + 8'd72: SliceData = RegData[71:40]; + 8'd73: SliceData = RegData[72:41]; + 8'd74: SliceData = RegData[73:42]; + 8'd75: SliceData = RegData[74:43]; + 8'd76: SliceData = RegData[75:44]; + 8'd77: SliceData = RegData[76:45]; + 8'd78: SliceData = RegData[77:46]; + 8'd79: SliceData = RegData[78:47]; + 8'd80: SliceData = RegData[79:48]; + 8'd81: SliceData = RegData[80:49]; + 8'd82: SliceData = RegData[81:50]; + 8'd83: SliceData = RegData[82:51]; + 8'd84: SliceData = RegData[83:52]; + 8'd85: SliceData = RegData[84:53]; + 8'd86: SliceData = RegData[85:54]; + 8'd87: SliceData = RegData[86:55]; + 8'd88: SliceData = RegData[87:56]; + 8'd89: SliceData = RegData[88:57]; + 8'd90: SliceData = RegData[89:58]; + 8'd91: SliceData = RegData[90:59]; + 8'd92: SliceData = RegData[91:60]; + 8'd93: SliceData = RegData[92:61]; + 8'd94: SliceData = RegData[93:62]; + 8'd95: SliceData = RegData[94:63]; + 8'd96: SliceData = RegData[95:64]; + default: SliceData = 32'h00000000; + endcase + endfunction - function [31:0] SliceData; - input [95:0] RegData; - input [7:0] RegWidth; + reg OutEnable; + reg PreEnable; + reg [31:0] DataOut; - case(RegWidth) - 8'd65: SliceData = RegData[64:33]; - 8'd66: SliceData = RegData[65:34]; - 8'd67: SliceData = RegData[66:35]; - 8'd68: SliceData = RegData[67:36]; - 8'd69: SliceData = RegData[68:37]; - 8'd70: SliceData = RegData[69:38]; - 8'd71: SliceData = RegData[70:39]; - 8'd72: SliceData = RegData[71:40]; - 8'd73: SliceData = RegData[72:41]; - 8'd74: SliceData = RegData[73:42]; - 8'd75: SliceData = RegData[74:43]; - 8'd76: SliceData = RegData[75:44]; - 8'd77: SliceData = RegData[76:45]; - 8'd78: SliceData = RegData[77:46]; - 8'd79: SliceData = RegData[78:47]; - 8'd80: SliceData = RegData[79:48]; - 8'd81: SliceData = RegData[80:49]; - 8'd82: SliceData = RegData[81:50]; - 8'd83: SliceData = RegData[82:51]; - 8'd84: SliceData = RegData[83:52]; - 8'd85: SliceData = RegData[84:53]; - 8'd86: SliceData = RegData[85:54]; - 8'd87: SliceData = RegData[86:55]; - 8'd88: SliceData = RegData[87:56]; - 8'd89: SliceData = RegData[88:57]; - 8'd90: SliceData = RegData[89:58]; - 8'd91: SliceData = RegData[90:59]; - 8'd92: SliceData = RegData[91:60]; - 8'd93: SliceData = RegData[92:61]; - 8'd94: SliceData = RegData[93:62]; - 8'd95: SliceData = RegData[94:63]; - 8'd96: SliceData = RegData[95:64]; - default: SliceData = 32'h00000000; - endcase - endfunction - - reg OutEnable; - reg PreEnable; - - reg [31:0] DataOut; - - always @(posedge clk or negedge rst) begin - if(!rst) begin - OutEnable <= 1'b0; - PreEnable <= 1'b0; - DataOut <= 32'h00000000; - end else begin - OutEnable <= RegWidth >64; - PreEnable <= (UseBit == 1'b1 | UseByte == 1'b1 | UseWord == 1'b1); - DataOut <= SliceData(RegData,RegWidth); - end + always @(posedge clk or negedge rst) begin + if(!rst) begin + OutEnable <= 1'b0; + PreEnable <= 1'b0; + DataOut <= 32'h00000000; + end else begin + if(DataEnd == 1'b1 & ProcessIdle == 1'b1) begin + OutEnable <= 1'b0; + PreEnable <= 1'b0; + DataOut <= 32'h00000000; + end else begin + OutEnable <= RegValid; + PreEnable <= (UseBit == 1'b1 | UseByte == 1'b1 | UseWord == 1'b1); + DataOut <= SliceData(RegData,RegWidth); + end end + end + + assign DataOutEnable = (PreEnable == 1'b0)?OutEnable:1'b0; - assign DataOutEnable = (PreEnable == 1'b0)?OutEnable:1'b0; - endmodule - - - \ No newline at end of file

/djpeg/trunk/src/jpeg_hm_decode.v

/djpeg/trunk/src/jpeg_dqt.v

/djpeg/trunk/src/jpeg_decode_fsm.v