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Rev 8 → Rev 9
/trunk/ham_7_4_enc/bench/ham_7_4_enc_wb_tb.v
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/trunk/ham_7_4_enc/rtl/verilog/ham_7_4_enc_wb.v
7,14 → 7,14
//// soneryesil@opencores.org //// |
//// burakokcan@opencores.org //// |
//// //// |
//// D/L from: http://www.opencores.org/cores/ham_7_4_enc/ //// |
//// D/L from: http://www.opencores.org/cores/hamming/ //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2004 Soner Yesil & Burak Okcan //// |
//// soneryesil@opencores.org //// |
//// burakokcan@opencores.org //// |
//// //// |
//// burakokcan@opencores.org //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
53,44 → 53,43
C=M*G, |
|
where |
# M is the 4-bit message M=[m1 m2 m3 m4] |
# G is the generator matrix |
M is the 4-bit message M=[m1 m2 m3 m4] |
G is the generator matrix |
|
1110000 |
G = 1001100 |
G = 1001100 |
0101010 |
1101001 |
# and C is the corresponding codeword C=[c1 c2 c3 c4 c5 c6 c7]; |
and C is the corresponding codeword C=[c1 c2 c3 c4 c5 c6 c7]; |
|
|
2.Functionality: |
================ |
|
WISHBONE SIGNALS |
---------------- |
|
CLK_I : Posedge clock. |
RST_I : Active HIGH synchronous reset. |
RST_I : Active HIGH synchronous reset. |
|
#Slave part: |
#Slave signals: |
|
STB_I : Active HIGH. |
DAT_I[7:0] : Message input, valid when STB_I and CYC_I are HIGH. DAT_I[7:4] is ignored. |
ADR_I[3:0] : Active when ADR_I is equal to the parameter "ham_enc_adr_in". |
DAT_I[7:0] : Message input, valid when STB_I, CYC_I and WE_I are HIGH. DAT_I[7:4] is ignored. |
DAT_O[7:0] : Codeword. Can be monitored by a master module when WE_I is LOW. DAT_O[7] is stuck at 0. |
ADR_I : Not Used |
ACK_O : Acknowledge signal: Ready for new data when ACK_O is HIGH. |
WE_I : Active HIGH. |
WE_I : Encoding is performed when WE_I is HIGH. |
CYC_I : Active HIGH. |
|
NON-WISHBONE SIGNALS |
-------------------- |
|
#master part: |
CODEWORD[7:0] : Codeword. Can be monitored by a master module when WE_I is LOW. DAT_O[7] is stuck at 0. |
DV_OUT : Indicates valid codeword when HIGH. |
|
STB_O : Active High. |
DAT_O[7:0] : Valid when STB_O is HIGH. DAT_O[7] is stuck at 0. |
ADR_O[3:0] : Stuck at parameter "ham_enc_adr_out". |
ACK_I : Acknowledge signal: Ready for new data transmission. |
WE_O : Active HIGH. |
CYC_O : Active HIGH. |
|
|
*/ |
/////////////////////////////////// |
////////////////////////////////////////////// |
|
module ham_7_4_enc ( |
CLK_I, |
99,44 → 98,34
STB_I, |
DAT_I, |
ADR_I, |
ACK_O, |
WE_I, |
CYC_I, |
|
STB_O, |
ACK_O, |
DAT_O, |
ADR_O, |
ACK_I, |
WE_O, |
CYC_O); |
|
CODEWORD, |
DV_OUT); |
|
input CLK_I, RST_I; |
input STB_I, WE_I, CYC_I; |
input [7:0] DAT_I; |
input [3:0] ADR_I; |
output ACK_O; |
input ADR_I; |
|
output STB_O, WE_O, CYC_O; |
output [7:0] DAT_O; |
output [3:0] ADR_O; |
input ACK_I; |
output ACK_O; |
output [7:0] CODEWORD; |
output DV_OUT; |
|
|
reg DV_OUT; |
reg [7:0] DAT_O; |
reg ACK_I_reg; |
reg STB_O, CYC_O; |
|
assign ACK_O = ACK_I; |
assign ADR_O = ham_enc_adr_out; |
assign WE_O = 1; |
|
///////////////////////////////////////////////// |
assign CODEWORD = DAT_O; |
assign ACK_O = STB_I; |
|
parameter ham_enc_adr_in = 4'b1111; |
parameter ham_enc_adr_out = 4'b1010; |
//////////////////////////////////////////////// |
|
///////////////////////////////////////////////// |
|
always@(posedge CLK_I) |
|
if (RST_I) |
143,57 → 132,26
|
DAT_O <= 0; |
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else if (ADR_I==ham_enc_adr_in) |
begin |
else |
if ( (STB_I) && (WE_I) && (CYC_I) ) |
begin |
DAT_O[0] <= DAT_I[3] ^ DAT_I[2] ^ DAT_I[0]; |
DAT_O[1] <= DAT_I[3] ^ DAT_I[1] ^ DAT_I[0]; |
DAT_O[2] <= DAT_I[3]; |
DAT_O[6] <= DAT_I[3] ^ DAT_I[2] ^ DAT_I[0]; |
DAT_O[5] <= DAT_I[3] ^ DAT_I[1] ^ DAT_I[0]; |
DAT_O[4] <= DAT_I[3]; |
DAT_O[3] <= DAT_I[2] ^ DAT_I[1] ^ DAT_I[0]; |
DAT_O[4] <= DAT_I[2]; |
DAT_O[5] <= DAT_I[1]; |
DAT_O[6] <= DAT_I[0]; |
DAT_O[2] <= DAT_I[2]; |
DAT_O[1] <= DAT_I[1]; |
DAT_O[0] <= DAT_I[0]; |
end |
end |
///////////////////////////////////////////////// |
|
always@(posedge CLK_I) |
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ACK_I_reg <= ACK_I; |
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///////////////////////////////////////////////// |
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always@(posedge CLK_I) |
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if (RST_I) |
CYC_O <= 0; |
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else if (ADR_I==ham_enc_adr_in) |
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CYC_O <= CYC_I; |
|
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///////////////////////////////////////////////// |
always@(posedge CLK_I) |
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if (RST_I) |
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STB_O <= 0; |
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else if (ADR_I==ham_enc_adr_in) |
begin |
if ( (ACK_I)&&(!ACK_I_reg) ) |
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STB_O <= 0; |
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else |
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STB_O <= STB_I; |
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end |
///////////////////////////////////////////////// |
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DV_OUT<=0; |
else |
DV_OUT<=STB_I; |
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endmodule |
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|