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/trunk/CODE/MEM_PKG.VHD
0,0 → 1,197
-------------------------------------------------------------------------------
-- Title : Memory Package
-- Project : Memory Cores
-------------------------------------------------------------------------------
-- File : mem_pkg.vhd
-- Author : Jamil Khatib <khatib@ieee.org>
-- Organization: OpenIPCore Project
-- Created : 2000/02/29
-- Last update: 2001/03/20
-- Platform :
-- Simulators : Modelsim 5.2EE / Windows98, NC-Sim/Linux
-- Synthesizers: Leonardo / Windows98
-- Target : Flex10K
-- Dependency : ieee.std_logic_1164
-- utility.tools_pkg
-------------------------------------------------------------------------------
-- Description: Memory Package
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it under the terms of the Openip General Public
-- License as it is going to be published by the OpenIPCore Organization and
-- any coming versions of this license.
-- You can check the draft license at
-- http://www.openip.org/oc/license.html
 
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 29th Feb 2000
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Created
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 2
-- Version : 0.2
-- Date : 29th Mar 2000
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Memory components are added.
--
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 3
-- Version : 0.3
-- Date : 12 Jan 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Memory components updated
--
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 4
-- Version : 0.31
-- Date : 11 March 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : FIFO component added
--
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 5
-- Version : 0.5
-- Date : 16 April 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : WISHBONE components added
--
-------------------------------------------------------------------------------
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2001/04/16 20:14:35 jamil
-- WishBone components added
--
-- Revision 1.3 2001/03/20 19:39:32 jamil
-- tools pkg bug fixed
--
-- Revision 1.2 2001/03/11 21:22:55 jamil
-- FIFO component added
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
library utility;
use utility.tools_pkg.all;
 
package mem_pkg is
 
constant ADD_WIDTH : integer := 8; -- Address width
constant WIDTH : integer := 4; -- Data width
-------------------------------------------------------------------------------
component dpmem_ent
generic (
USE_RESET : boolean;
USE_CS : boolean;
DEFAULT_OUT : std_logic;
CLK_DOMAIN : integer;
ADD_WIDTH : integer;
WIDTH : integer);
port (
W_clk : in std_logic;
R_clk : in std_logic;
reset : in std_logic;
W_add : in std_logic_vector(add_width -1 downto 0);
R_add : in std_logic_vector(add_width -1 downto 0);
Data_In : in std_logic_vector(WIDTH - 1 downto 0);
Data_Out : out std_logic_vector(WIDTH -1 downto 0);
WR : in std_logic;
RE : in std_logic);
end component;
-------------------------------------------------------------------------------
COMPONENT wb_dpmem
GENERIC (
ADD_WIDTH : INTEGER;
WIDTH : INTEGER;
CLK_DOMAIN : INTEGER);
PORT (
CLK_I_1 : IN STD_LOGIC;
CLK_I_2 : IN STD_LOGIC;
ADR_I_1 : IN STD_LOGIC_VECTOR(ADD_WIDTH-1 DOWNTO 0);
ADR_I_2 : IN STD_LOGIC_VECTOR(ADD_WIDTH-1 DOWNTO 0);
DAT_O : OUT STD_LOGIC_VECTOR(WIDTH -1 DOWNTO 0);
DAT_I : IN STD_LOGIC_VECTOR(WIDTH -1 DOWNTO 0);
WE_I_1 : IN STD_LOGIC;
WE_I_2 : IN STD_LOGIC;
ACK_O_1 : OUT STD_LOGIC;
ACK_O_2 : OUT STD_LOGIC;
STB_I_1 : IN STD_LOGIC;
STB_I_2 : IN STD_LOGIC);
END COMPONENT;
-------------------------------------------------------------------------------
component Spmem_ent
generic (
USE_RESET : boolean;
USE_CS : boolean;
DEFAULT_OUT : std_logic;
OPTION : integer;
ADD_WIDTH : integer;
WIDTH : integer);
port (
cs : std_logic;
clk : in std_logic;
reset : in std_logic;
add : in std_logic_vector(add_width -1 downto 0);
Data_In : in std_logic_vector(WIDTH -1 downto 0);
Data_Out : out std_logic_vector(WIDTH -1 downto 0);
WR : in std_logic);
end component;
 
-------------------------------------------------------------------------------
COMPONENT WB_spmem
GENERIC (
ADD_WIDTH : INTEGER;
WIDTH : INTEGER;
OPTION : INTEGER);
PORT (
DAT_O : OUT STD_LOGIC_VECTOR(ADD_WIDTH -1 DOWNTO 0);
DAT_I : IN STD_LOGIC_VECTOR(WIDTH -1 DOWNTO 0);
CLK_I : IN STD_LOGIC;
ADR_I : IN STD_LOGIC_VECTOR(ADD_WIDTH -1 DOWNTO 0);
STB_I : IN STD_LOGIC;
WE_I : IN STD_LOGIC;
ACK_O : OUT STD_LOGIC);
END COMPONENT;
-------------------------------------------------------------------------------
component FIFO_ent
generic (
ARCH : integer;
USE_CS : boolean;
DEFAULT_OUT : std_logic;
CLK_DOMAIN : integer;
MEM_CORE : integer;
BLOCK_SIZE : integer;
WIDTH : integer;
DEPTH : integer);
port (
rst_n : in std_logic;
Rclk : in std_logic;
Wclk : in std_logic;
cs : in std_logic;
Din : in std_logic_vector(WIDTH-1 downto 0);
Dout : out std_logic_vector(WIDTH-1 downto 0);
Re : in std_logic;
wr : in std_logic;
UsedCount : out std_logic_vector(log2(DEPTH)-1 downto 0);
RFull : out std_logic;
RHalf_full : out std_logic;
REmpty : out std_logic;
WFull : out std_logic;
WHalf_full : out std_logic;
WEmpty : out std_logic);
end component;
 
end mem_pkg;
 
-------------------------------------------------------------------------------
/trunk/CODE/SPMEM.VHD
0,0 → 1,378
-------------------------------------------------------------------------------
-- Title : Single port RAM
-- Project : Memory Cores
-------------------------------------------------------------------------------
-- File : spmem.vhd
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 1999/5/14
-- Last update : 2000/12/19
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers: Leonardo/WindowsNT
-- Target :
-- Dependency : ieee.std_logic_1164,ieee.std_logic_unsigned
-------------------------------------------------------------------------------
-- Description: Single Port memory
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
 
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 12 May 1999
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Created
-- Known bugs :
-- To Optimze :
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 2
-- Version : 0.2
-- Date : 19 Dec 2000
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : General review
-- Two versions are now available with reset and without
-- Default output can can be defined
-- Known bugs :
-- To Optimze :
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 3
-- Version : 0.3
-- Date : 5 Jan 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Registered Read Address feature is added to make use of
-- Altera's FPGAs memory bits
-- This feature was added from Richard Herveille's
-- contribution and his memory core
-- Known bugs :
-- To Optimze :
-------------------------------------------------------------------------------
 
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- Single port Memory core with reset
-- To make use of on FPGA memory bits do not use the RESET option
-- For Altera's FPGA you have to use also OPTION := 1
 
entity Spmem_ent is
generic ( USE_RESET : boolean := false; -- use system reset
USE_CS : boolean := false; -- use chip select signal
DEFAULT_OUT : std_logic := '1'; -- Default output
OPTION : integer := 1; -- 1: Registered read Address(suitable
-- for Altera's FPGAs
-- 0: non registered read address
ADD_WIDTH : integer := 3;
WIDTH : integer := 8);
 
port (
cs : std_logic; -- chip select
clk : in std_logic; -- write clock
reset : in std_logic; -- System Reset
add : in std_logic_vector(add_width -1 downto 0); -- Address
Data_In : in std_logic_vector(WIDTH -1 downto 0); -- input data
Data_Out : out std_logic_vector(WIDTH -1 downto 0); -- Output Data
WR : in std_logic); -- Read Write Enable
end Spmem_ent;
 
 
 
-------------------------------------------------------------------------------
-- This Architecture was tested on the ModelSim 5.2EE
-- The test vectors for model sim is included in vectors.do file
 
 
architecture spmem_beh of Spmem_ent is
 
 
 
type data_array is array (integer range <>) of std_logic_vector(WIDTH-1 downto 0);
-- Memory Type
signal data : data_array(0 to (2** add_width-1) ); -- Local data
 
 
-- FLEX/APEX devices require address to be registered with inclock for read operations
-- This signal is used only when OPTION = 1
signal regA : std_logic_vector( (add_width -1) downto 0);
procedure init_mem(signal memory_cell : inout data_array ) is
begin
 
for i in 0 to (2** add_width-1) loop
memory_cell(i) <= (others => '0');
end loop;
 
end init_mem;
 
begin -- spmem_beh
-------------------------------------------------------------------------------
-- Non Registered Read Address
-------------------------------------------------------------------------------
NON_REG : if OPTION = 0 generate
-------------------------------------------------------------------------------
-- Clocked Process with Reset
-------------------------------------------------------------------------------
Reset_ENABLED : if USE_RESET = true generate
-------------------------------------------------------------------------------
CS_ENABLED : if USE_CS = true generate
process (clk, reset)
 
begin -- PROCESS
-- activities triggered by asynchronous reset (active low)
 
if reset = '0' then
data_out <= (others => DEFAULT_OUT);
init_mem ( data);
 
-- activities triggered by rising edge of clock
elsif clk'event and clk = '1' then
if CS = '1' then
if WR = '0' then
data(conv_integer(add)) <= data_in;
data_out <= (others => DEFAULT_OUT);
else
data_out <= data(conv_integer(add));
end if;
else
data_out <= (others => DEFAULT_OUT);
end if;
 
end if;
 
end process;
end generate CS_ENABLED;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
CS_DISABLED : if USE_CS = false generate
process (clk, reset)
 
 
begin -- PROCESS
-- activities triggered by asynchronous reset (active low)
 
if reset = '0' then
data_out <= (others => DEFAULT_OUT);
init_mem ( data);
 
-- activities triggered by rising edge of clock
elsif clk'event and clk = '1' then
if WR = '0' then
data(conv_integer(add)) <= data_in;
data_out <= (others => DEFAULT_OUT);
else
data_out <= data(conv_integer(add));
end if;
 
end if;
 
end process;
end generate CS_DISABLED;
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate Reset_ENABLED;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Clocked Process without Reset
-------------------------------------------------------------------------------
Reset_DISABLED : if USE_RESET = false generate
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
CS_ENABLED : if USE_CS = true generate
process (clk)
begin -- PROCESS
 
-- activities triggered by rising edge of clock
if clk'event and clk = '1' then
if cs = '1' then
if WR = '0' then
data(conv_integer(add)) <= data_in;
data_out <= (others => DEFAULT_OUT);
else
data_out <= data(conv_integer(add));
end if;
else
data_out <= (others => DEFAULT_OUT);
end if;
 
 
end if;
 
end process;
end generate CS_ENABLED;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
CS_DISABLED : if USE_CS = false generate
process (clk)
begin -- PROCESS
 
-- activities triggered by rising edge of clock
if clk'event and clk = '1' then
if WR = '0' then
data(conv_integer(add)) <= data_in;
data_out <= (others => DEFAULT_OUT);
else
data_out <= data(conv_integer(add));
end if;
 
end if;
 
end process;
end generate CS_DISABLED;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate Reset_DISABLED;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate NON_REG;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
REG: if OPTION = 1 generate
-------------------------------------------------------------------------------
-- Clocked Process with Reset
-------------------------------------------------------------------------------
Reset_ENABLED : if USE_RESET = true generate
-------------------------------------------------------------------------------
CS_ENABLED : if USE_CS = true generate
process (clk, reset)
 
begin -- PROCESS
-- activities triggered by asynchronous reset (active low)
 
if reset = '0' then
data_out <= (others => DEFAULT_OUT);
init_mem ( data);
 
-- activities triggered by rising edge of clock
elsif clk'event and clk = '1' then
 
regA <= add;
if CS = '1' then
if WR = '0' then
data(conv_integer(add)) <= data_in;
data_out <= (others => DEFAULT_OUT);
else
data_out <= data(conv_integer(regA));
end if;
else
data_out <= (others => DEFAULT_OUT);
end if;
 
end if;
 
end process;
end generate CS_ENABLED;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
CS_DISABLED : if USE_CS = false generate
process (clk, reset)
 
 
begin -- PROCESS
-- activities triggered by asynchronous reset (active low)
 
if reset = '0' then
data_out <= (others => DEFAULT_OUT);
init_mem ( data);
 
-- activities triggered by rising edge of clock
elsif clk'event and clk = '1' then
regA <= add;
if WR = '0' then
data(conv_integer(add)) <= data_in;
data_out <= (others => DEFAULT_OUT);
else
data_out <= data(conv_integer(regA));
end if;
 
end if;
 
end process;
end generate CS_DISABLED;
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate Reset_ENABLED;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Clocked Process without Reset
-------------------------------------------------------------------------------
Reset_DISABLED : if USE_RESET = false generate
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
CS_ENABLED : if USE_CS = true generate
process (clk)
begin -- PROCESS
 
-- activities triggered by rising edge of clock
if clk'event and clk = '1' then
 
regA <= add;
if cs = '1' then
if WR = '0' then
data(conv_integer(add)) <= data_in;
data_out <= (others => DEFAULT_OUT);
else
data_out <= data(conv_integer(regA));
end if;
else
data_out <= (others => DEFAULT_OUT);
end if;
 
 
end if;
 
end process;
end generate CS_ENABLED;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
CS_DISABLED : if USE_CS = false generate
process (clk)
begin -- PROCESS
 
-- activities triggered by rising edge of clock
if clk'event and clk = '1' then
regA <= add;
if WR = '0' then
data(conv_integer(add)) <= data_in;
data_out <= (others => DEFAULT_OUT);
else
data_out <= data(conv_integer(regA));
end if;
 
end if;
 
end process;
end generate CS_DISABLED;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate Reset_DISABLED;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate REG;
 
end spmem_beh;
-------------------------------------------------------------------------------
/trunk/CODE/tools_pkg.vhd
0,0 → 1,367
-------------------------------------------------------------------------------
-- Title : Tools Package
-- Project : Utility library
-------------------------------------------------------------------------------
-- File : tools.vhd
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 2000/11/02
-- Last update : 2000/11/02
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers:
-- Target :
-- Dependency : ieee.std_logic_1164
-- ieee.std_logic_arith
-- ieee.std_logic_unsigned
--
-------------------------------------------------------------------------------
-- Description: This package contains set of usefull functions and procedures
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
 
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 2nd Nov 2000
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Created
--
---------- Revisions :
-- Revision Number : 2
-- Version : 0.2
-- Date : 14 Nov 2000
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Shift functions and int_2_slv are added
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
 
package tools_pkg is
-------------------------------------------------------------------------------
-- Types
 
-- Memory arraye type of std_logic_vector
-- type std_memory_array_typ is array (integer range <>) of std_logic_vector(5 downto 0); --integer range <>);
 
-- Memory arraye type of std_ulogic_vector
-- type stdu_memory_array_typ is array (integer range <>) of std_ulogic_vector(integer range <>);
 
-- Sign magnitude numbers based on std_logic_vector (The msb represents the sign)
type SIGN_MAG_typ is array (natural range <>) of std_logic;
 
 
-----------------------------------------------------------------------------
-- Functions
 
 
function Log2( input : integer ) return integer; -- log2 functions
 
function slv_2_int ( SLV : std_logic_vector) return integer; --
--std_logic_vector
--to integer
 
function "+"(A, B : SIGN_MAG_typ) return SIGN_MAG_typ; -- sign_magnitude addition
 
function "-"(A, B : SIGN_MAG_typ) return SIGN_MAG_typ; -- sign_magnitude
-- subtraction (
-- based on
-- complement operations)
function LeftShift (
InReg : std_logic_vector; -- Input Register
ShSize : std_logic_vector) -- Shift Size
return std_logic_vector;
 
 
function RightShift (
InReg : std_logic_vector; -- Input register
ShSize : std_logic_vector) -- Shift Size
return std_logic_vector;
 
function int_2_slv (val, SIZE : integer) return std_logic_vector;
 
-----------------------------------------------------------------------------
end tools_pkg;
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
package body tools_pkg is
 
-----------------------------------------------------------------------------
function Log2(
input : integer ) -- input number
return integer is
variable temp, log : integer;
begin
 
assert input /= 0
report "Error : function missuse : log2(zero)"
severity failure;
temp := input;
log := 0;
while (temp /= 0) loop
temp := temp/2;
log := log+1;
end loop;
return log;
end log2;
-------------------------------------------------------------------------------
 
-- function LOG2(COUNT:INTEGER) return INTEGER is -- COUNT should be >0 variable TEMP:INTEGER;
-- variable TEMP : integer;
-- variable cnt : integer;
-- begin
-- cnt := COUNT;
--
-- TEMP:=0;
-- while COUNT>1 loop
-- TEMP:=TEMP+1;
-- cnt:=cnt/2;
-- end loop;
-- return TEMP;
-- end log2;
-------------------------------------------------------------------------------
function slv_2_int (
SLV : std_logic_vector) -- std_logic_vector to convert
return integer is
 
variable Result : integer := 0; -- conversion result
 
begin
for i in SLV'range loop
Result := Result * 2; -- shift the variable to left
case SLV(i) is
when '1' | 'H' => Result := Result + 1;
when '0' | 'L' => Result := Result + 0;
when others => null;
end case;
end loop;
 
return Result;
end;
-------------------------------------------------------------------------------
function "+"(A, B : SIGN_MAG_typ) return SIGN_MAG_typ is
variable VA, VB, VR : unsigned(A'length - 1 downto 0);
-- include the overflow bit
 
variable SA, SB, SR : std_logic;
variable TMP, RES : SIGN_MAG_typ(A'length - 1 downto 0);
 
variable casevar : std_logic_vector(1 downto 0);
variable std_tmp : std_logic_vector(A'length - 1 downto 0) := (others => '0');
 
begin
 
assert A'length = B'length
report "Error : length mismatch"
severity failure;
 
 
TMP := A;
SA := TMP(A'length - 1);
VA := '0' & unsigned(TMP(A'length - 2 downto 0));
TMP := B;
SB := TMP(B'length - 1);
VB := '0' & unsigned(TMP(B'length - 2 downto 0));
 
casevar := SA & SB;
case casevar is
when "00" |"11" =>
 
VR := VA + VB;
SR := SA;
 
when "01" =>
 
VR := VA - VB;
SR := VR(VR'length - 1);
 
if SR = '1' then
std_tmp(VR'length -2 downto 0) := std_logic_vector(VR(VR'length -2 downto 0));
std_tmp := not std_tmp;
 
VR(VR'length -2 downto 0) := unsigned(std_tmp(VR'length -2 downto 0));
 
VR(VR'length -2 downto 0) := VR(VR'length -2 downto 0) +1;
 
end if;
 
 
when "10" =>
VR := VB - VA;
SR := VR(VR'length - 1);
 
if SR = '1' then
std_tmp(VR'length -2 downto 0) := std_logic_vector(VR(VR'length -2 downto 0));
std_tmp := not std_tmp;
 
VR(VR'length -2 downto 0) := unsigned(std_tmp(VR'length -2 downto 0));
 
VR(VR'length -2 downto 0) := VR(VR'length -2 downto 0) +1;
 
end if;
 
when others => null;
end case;
 
 
RES := SIGN_MAG_typ(SR & VR(VR'length -2 downto 0));
 
return RES;
end "+";
 
-------------------------------------------------------------------------------
-- function "+"(A, B: SIGN_MAG) return SIGN_MAG is
-- variable VA, VB, VR: UNSIGNED(A'length - 2 downto 0);
-- variable SA, SB, SR: STD_LOGIC;
-- variable TMP, RES: SIGN_MAG(A'length - 1 downto 0);
--begin
-- assert A'length = B'length
-- report "Error"
-- severity FAILURE;
-- TMP := A;
-- SA := TMP(A'length - 1);
-- VA := UNSIGNED(TMP(A'length - 2 downto 0));
-- TMP := B;
-- SB := TMP(B'length - 1);
-- VB := UNSIGNED(TMP(B'length - 2 downto 0));
-- if (SA = SB) then
-- VR := VA + VB;
-- SR := SA;
-- elsif (VA >= VB) then
-- VR := VA - VB;
-- SR := SA;
-- else
-- VR := VB - VA;
-- SR := SB;
-- end if;
-- RES := SIGN_MAG(SR & VR);
-- return RES;
--end "+";
-------------------------------------------------------------------------------
function "-"(A, B : SIGN_MAG_typ) return SIGN_MAG_typ is
variable TMP : SIGN_MAG_typ(A'length - 1 downto 0);
begin
assert A'length = B'length
report "Error : length mismach"
severity failure;
TMP := B;
TMP(B'length - 1) := not TMP(B'length - 1);
return A + TMP;
end "-";
 
-------------------------------------------------------------------------------
-- purpose: combinational left shift register
function LeftShift (
InReg : std_logic_vector; -- Input Register
ShSize : std_logic_vector) -- Shift Size
return std_logic_vector is
 
constant REGSIZE : integer := InReg'length; -- Register Size
variable VarReg : std_logic_vector(InReg'length -1 downto 0);
-- Local storage for shifter
constant SHIFTSIZE : integer := log2(InReg'length); -- Shift size
begin
 
VarReg := inReg;
 
for i in 0 to SHIFTSIZE -2 loop
 
 
if ShSize(i) = '1' then
 
VarReg(REGSIZE -1 downto 0) := VarReg( (REGSIZE-(2**i)-1) downto 0) & ((2**i)-1 downto 0 => '0');
 
end if;
 
end loop; -- i
 
if ShSize(SHIFTSIZE-1) = '1' then
VarReg := (others => '0');
end if;
 
return VarReg;
 
end LeftShift;
 
-------------------------------------------------------------------------------
-- purpose: combinational Right shift register
function RightShift (
InReg : std_logic_vector; -- Input register
ShSize : std_logic_vector) -- Shift Size
return std_logic_vector is
 
constant REGSIZE : integer := InReg'length; -- Register Size
variable VarReg : std_logic_vector(InReg'length -1 downto 0);
-- Local storage for shifter
constant SHIFTSIZE : integer := log2(InReg'length); -- Shift size
 
begin -- RightShift
 
 
 
 
VarReg := inReg;
 
for i in 0 to SHIFTSIZE -2 loop
 
 
if ShSize(i) = '1' then
 
VarReg(REGSIZE -1 downto 0) := (REGSIZE-1 downto REGSIZE-(2**i) => '0') & VarReg(REGSIZE -1 downto (2**i));
 
end if;
 
end loop; -- i
 
if ShSize(SHIFTSIZE-1) = '1' then
VarReg := (others => '0');
end if;
 
return VarReg;
 
 
end RightShift;
-------------------------------------------------------------------------------
-- purpose: Integer to Std_logic_vector conversion
function int_2_slv (val, SIZE : integer) return std_logic_vector is
variable result : std_logic_vector(SIZE-1 downto 0);
variable l_val : integer := val;
begin
 
assert SIZE > 1
report "Error : function missuse : in_2_slv(val, negative size)"
severity failure;
 
for i in 0 to result'length-1 loop
 
if (l_val mod 2) = 0 then
 
result(i) := '0';
 
else
result(i) := '1';
 
end if;
 
l_val := l_val/2;
 
end loop;
 
return result;
 
end int_2_slv;
-------------------------------------------------------------------------------
end tools_pkg;
/trunk/CODE/LIBS/hdlc_components_pkg.vhd
6,7 → 6,7
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 2000/12/30
-- Last update: 2001/01/26
-- Last update: 2001/04/27
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers:
49,12 → 49,153
-- Desccription : TX componentes added
--
-------------------------------------------------------------------------------
 
-- Revision Number : 4
-- Version : 0.4
-- Date : 22 March 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Tx Top components added
--
-------------------------------------------------------------------------------
-- Revision Number : 5
-- Version : 0.5
-- Date : 9 April 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Rx Top components added
--
-------------------------------------------------------------------------------
-- $Log: not supported by cvs2svn $
-- Revision 1.11 2001/04/27 18:21:59 jamil
-- After Prelimenray simulation
--
-- Revision 1.10 2001/04/22 20:08:16 jamil
-- Top level simulation
--
-- Revision 1.7 2001/04/14 15:23:34 jamil
-- Rx Components added
--
-- Revision 1.6 2001/03/22 21:58:46 jamil
-- Top Tx Components added
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
 
package hdlc_components_pkg is
 
component hdlc_ent
generic (
FCS_TYPE : integer;
ADD_WIDTH : integer);
port (
Txclk : in std_logic;
RxClk : in std_logic;
Tx : out std_logic;
Rx : in std_logic;
TxEN : in std_logic;
RxEn : in std_logic;
RST_I : in std_logic;
CLK_I : in std_logic;
ADR_I : in std_logic_vector(2 downto 0);
DAT_O : out std_logic_vector(31 downto 0);
DAT_I : in std_logic_vector(31 downto 0);
WE_I : in std_logic;
STB_I : in std_logic;
ACK_O : out std_logic;
CYC_I : in std_logic;
RTY_O : out std_logic;
TAG0_O : out std_logic;
TAG1_O : out std_logic);
end component;
 
 
constant ADD_WIDTH : integer := 7; -- Internal Buffers address width
component WB_IF_ent
generic (
ADD_WIDTH : integer);
port (
CLK_I : in std_logic;
RST_I : in std_logic;
ACK_O : out std_logic;
ADR_I : in std_logic_vector(2 downto 0);
CYC_I : in std_logic;
DAT_I : in std_logic_vector(31 downto 0);
DAT_O : out std_logic_vector(31 downto 0);
RTY_O : out std_logic;
STB_I : in std_logic;
WE_I : in std_logic;
TAG0_O : out std_logic;
TAG1_O : out std_logic;
TxEnable : out std_logic;
TxDone : in std_logic;
TxDataInBuff : out std_logic_vector(7 downto 0);
Txwr : out std_logic;
TxAborted : in std_logic;
TxAbort : out std_logic;
TxOverflow : in std_logic;
TxFCSen : out std_logic;
RxFrameSize : in std_logic_vector(ADD_WIDTH-1 downto 0);
RxRdy : in std_logic;
RxDataBuffOut : in std_logic_vector(7 downto 0);
RxOverflow : in std_logic;
RxFrameError : in std_logic;
RxFCSErr : in std_logic;
RxRd : out std_logic;
RxAbort : in std_logic);
end component;
 
component txSynch_ent
port (
rst_n : in std_logic;
clk_D1 : in std_logic;
clk_D2 : in std_logic;
rdy_D1 : in std_logic;
rdy_D2 : out std_logic;
ack : out std_logic;
TXD_D1 : out std_logic_vector(7 downto 0);
TXD_D2 : in std_logic_vector(7 downto 0);
ValidFrame_D1 : out std_logic;
ValidFrame_D2 : in std_logic;
AbortedTrans_D1 : in std_logic;
AbortedTrans_D2 : out std_logic;
AbortFrame_D1 : out std_logic;
AbortFrame_D2 : in std_logic;
WriteByte_D1 : out std_logic;
WriteByte_D2 : in std_logic);
end component;
 
component Txfcs_ent
generic (
FCS_TYPE : integer);
port (
TxClk : in std_logic;
rst_n : in std_logic;
FCSen : in std_logic;
ValidFrame : out std_logic;
WriteByte : out std_logic;
rdy : in std_logic;
ack : in std_logic;
TxData : out std_logic_vector(7 downto 0);
TxDataAvail : in std_logic;
RdBuff : out std_logic;
TxDataBuff : in std_logic_vector(7 downto 0));
end component;
 
component TxBuff_ent
generic (
ADD_WIDTH : integer);
port (
TxClk : in std_logic;
rst_n : in std_logic;
RdBuff : in std_logic;
Wr : in std_logic;
TxDataAvail : out std_logic;
TxEnable : in std_logic;
TxDone : out std_logic;
TxDataOutBuff : out std_logic_vector(7 downto 0);
TxDataInBuff : in std_logic_vector(7 downto 0);
Full : out std_logic);
end component;
 
component TxChannel_ent
port (
TxClk : in std_logic;
128,6 → 269,7
 
component ZeroDetect_ent
port (
ValidFrame : in std_logic; --New
Readbyte : in std_logic;
aval : out std_logic;
enable : in std_logic;
165,4 → 307,57
RxEn : in std_logic);
end component;
 
component RxSynch_ent
port (
rst_n : in std_logic;
clk_D1 : in std_logic;
clk_D2 : in std_logic;
rdy_D1 : in std_logic;
rdy_D2 : out std_logic;
RXD_D1 : in std_logic_vector(7 downto 0);
RXD_D2 : out std_logic_vector(7 downto 0);
ValidFrame_D1 : in std_logic;
ValidFrame_D2 : out std_logic;
AbortSignal_D1 : in std_logic;
AbortSignal_D2 : out std_logic;
FrameError_D1 : in std_logic;
FrameError_D2 : out std_logic;
ReadByte_D1 : out std_logic;
ReadByte_D2 : in std_logic);
end component;
 
component RxFCS_ent
generic (
FCS_TYPE : integer);
port (
clk : in std_logic;
rst_n : in std_logic;
RxD : in std_logic_vector(7 downto 0);
ValidFrame : in std_logic;
rdy : in std_logic;
Readbyte : out std_logic;
DataBuff : out std_logic_vector(7 downto 0);
WrBuff : out std_logic;
EOF : out std_logic;
FCSen : in std_logic;
FCSerr : out std_logic);
end component;
 
component RxBuff_ent
generic (
FCS_TYPE : integer;
ADD_WIDTH : integer);
port (
Clk : in std_logic;
rst_n : in std_logic;
DataBuff : in std_logic_vector(7 downto 0);
EOF : in std_logic;
WrBuff : in std_logic;
FrameSize : out std_logic_vector(ADD_WIDTH-1 downto 0);
RxRdy : out std_logic;
RxDataBuffOut : out std_logic_vector(7 downto 0);
Overflow : out std_logic;
Rd : in std_logic);
end component;
 
end hdlc_components_pkg;
/trunk/CODE/LIBS/PCK_CRC16_D8.vhd
0,0 → 1,84
-----------------------------------------------------------------------
-- File: PCK_CRC16_D8.vhd
-- Date: Wed Feb 7 08:06:05 2001
--
-- Copyright (C) 1999 Easics NV.
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains the original copyright notice
-- and the associated disclaimer.
--
-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
--
-- Purpose: VHDL package containing a synthesizable CRC function
-- * polynomial: (0 5 12 16)
-- * data width: 8
--
-- Info: jand@easics.be (Jan Decaluwe)
-- http://www.easics.com
-----------------------------------------------------------------------
 
 
library IEEE;
use IEEE.std_logic_1164.all;
 
package PCK_CRC16_D8 is
 
-- polynomial: (0 5 12 16)
-- data width: 8
-- convention: the first serial data bit is D(7)
function nextCRC16_D8
( Data: std_logic_vector(7 downto 0);
CRC: std_logic_vector(15 downto 0) )
return std_logic_vector;
 
end PCK_CRC16_D8;
 
library IEEE;
use IEEE.std_logic_1164.all;
 
package body PCK_CRC16_D8 is
 
-- polynomial: (0 5 12 16)
-- data width: 8
-- convention: the first serial data bit is D(7)
function nextCRC16_D8
( Data: std_logic_vector(7 downto 0);
CRC: std_logic_vector(15 downto 0) )
return std_logic_vector is
 
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(15 downto 0);
variable NewCRC: std_logic_vector(15 downto 0);
 
begin
 
D := Data;
C := CRC;
 
NewCRC(0) := D(4) xor D(0) xor C(8) xor C(12);
NewCRC(1) := D(5) xor D(1) xor C(9) xor C(13);
NewCRC(2) := D(6) xor D(2) xor C(10) xor C(14);
NewCRC(3) := D(7) xor D(3) xor C(11) xor C(15);
NewCRC(4) := D(4) xor C(12);
NewCRC(5) := D(5) xor D(4) xor D(0) xor C(8) xor C(12) xor C(13);
NewCRC(6) := D(6) xor D(5) xor D(1) xor C(9) xor C(13) xor C(14);
NewCRC(7) := D(7) xor D(6) xor D(2) xor C(10) xor C(14) xor C(15);
NewCRC(8) := D(7) xor D(3) xor C(0) xor C(11) xor C(15);
NewCRC(9) := D(4) xor C(1) xor C(12);
NewCRC(10) := D(5) xor C(2) xor C(13);
NewCRC(11) := D(6) xor C(3) xor C(14);
NewCRC(12) := D(7) xor D(4) xor D(0) xor C(4) xor C(8) xor C(12) xor
C(15);
NewCRC(13) := D(5) xor D(1) xor C(5) xor C(9) xor C(13);
NewCRC(14) := D(6) xor D(2) xor C(6) xor C(10) xor C(14);
NewCRC(15) := D(7) xor D(3) xor C(7) xor C(11) xor C(15);
 
return NewCRC;
 
end nextCRC16_D8;
 
end PCK_CRC16_D8;
 
/trunk/CODE/RX/CORE/RxChannel.vhd
6,7 → 6,7
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 2000/12/30
-- Last update: 2001/01/12
-- Last update: 2001/04/27
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers:
41,12 → 41,19
-- Desccription : RXEN bug fixed
--
-------------------------------------------------------------------------------
 
-- Revisions :
-- Revision Number : 3
-- Version : 0.3
-- Date : 27 April 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : FrameAvailable port added to Zero_detect
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
LIBRARY hdlc;
use hdlc.hdlc_components_pkg.all;
 
use work.hdlc_components_pkg.all;
 
entity RxChannel_ent is
 
port (
74,9 → 81,13
signal initzero_i : std_logic; -- Init Zero detect block
signal rxen_i : std_logic; -- RXenable internal
 
-- New
signal ValidFrame_i : std_logic; -- Internal Valid Frame
begin -- RxChannel_beh
 
-------------------------------------------------------------------------------
ValidFrame <= ValidFrame_i;
 
Controller : rxcont_ent
port map (
86,7 → 97,7
AbortedFrame => AbortSignal,
Abort => Abort_i,
FlagDetect => FlagDetect_i,
ValidFrame => ValidFrame,
ValidFrame => ValidFrame_i, --New
FrameError => FrameError,
aval => aval_i,
initzero => initzero_i,
94,6 → 105,7
-------------------------------------------------------------------------------
zero_backend : ZeroDetect_ent
port map (
ValidFrame => ValidFrame_i, --New
Readbyte => Readbyte,
aval => aval_i,
enable => enable_i,
/trunk/CODE/RX/CORE/Zero_detect.vhd
6,7 → 6,7
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 2000/12/28
-- Last update: 2001/01/12
-- Last update: 2001/04/27
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers: FPGA express 3
44,7 → 44,14
-- for low speed backend interface
-- (flow control is used to manage this problem)
-------------------------------------------------------------------------------
 
-- Revisions :
-- Revision Number : 3
-- Version : 0.3
-- Date : 27 April 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Available and enable bugs fixed
-- ToOptimize :
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
 
51,10 → 58,11
entity ZeroDetect_ent is
 
port (
Readbyte : in std_logic; -- Back end read byte
aval : out std_logic; -- can get more data (connected to flow
ValidFrame : in std_logic; -- Valid Frame strobe
Readbyte : in std_logic; -- Back end read byte
aval : out std_logic; -- can get more data (connected to flow
-- controller
enable : in std_logic; -- enable (Driven by flow controller)
enable : in std_logic; -- enable (Driven by flow controller)
 
rdy : out std_logic; -- data ready
rst : in std_logic; -- system reset
192,8 → 200,16
 
end if; -- readbyte
 
rdy <= rdy_var;
aval <= not status;
rdy <= rdy_var;
 
if ValidFrame = '0' then
aval <= '1';
else
 
aval <= not status;
end if;
 
 
end if; -- clk
 
 
/trunk/CODE/RX/CORE/Rxcont.vhd
6,7 → 6,7
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 2000/12/30
-- Last update: 2001/01/10
-- Last update: 2001/04/27
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers:
33,7 → 33,15
-- ToOptimize :
-- Bugs :
-------------------------------------------------------------------------------
 
-- Revisions :
-- Revision Number : 2
-- Version : 0.2
-- Date : 27 April 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Enable and Available Bugs fixed
-- ToOptimize :
-- Bugs :
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
 
139,7 → 147,7
if counter = 5 then
 
enable <= '0';
counter := 0;
counter := 0;
FrameError <= '1';
 
else

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