URL
https://opencores.org/ocsvn/lwrisc/lwrisc/trunk
Subversion Repositories lwrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 8 to Rev 9
- ↔ Reverse comparison
Rev 8 → Rev 9
/trunk/SIM/work/_info
0,0 → 1,3
m255 |
cModel Technology |
dC:\Modeltech_5.8e\examples |
/trunk/SYN/rev_1/ClaiRISC_core_rm.tcl
0,0 → 1,13
set_global_assignment -name ROOT "|ClaiRISC_core" -remove |
set_global_assignment -name FAMILY -remove |
set_global_assignment -section_id clk_setting -name DUTY_CYCLE "50.00" -remove |
set_instance_assignment -entity ClaiRISC_core -to clk -name GLOBAL_SIGNAL ON -remove |
set_instance_assignment -entity ClaiRISC_core -to clk -name USE_CLOCK_SETTINGS clk_setting -remove |
set_global_assignment -section_id clk_setting -name FMAX_REQUIREMENT "120.7MHZ" -remove |
set_global_assignment -name TAO_FILE "myresults.tao" -remove |
set_global_assignment -name SOURCES_PER_DESTINATION_INCLUDE_COUNT "1000" -remove |
set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON -remove |
set_global_assignment -name REMOVE_DUPLICATE_LOGIC "OFF" -remove |
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS "OFF" -remove |
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS "ON" -remove |
set_global_assignment -name EDA_RESYNTHESIS_TOOL "AMPLIFY" -remove |
/trunk/SYN/rev_1/ClaiRISC_core.vqm
0,0 → 1,6625
// |
// Written by Synplify |
// Synplify 8.1.0, Build 539R. |
// Mon Mar 10 17:23:16 2008 |
// |
// Source file index table: |
// Object locations will have the form <file>:<line> |
// file 0 "noname" |
// file 1 "\c:\program files\synplicity\fpga_81\lib\altera\altera.v " |
// file 2 "\c:\program files\synplicity\fpga_81\lib\altera\cyclone.v " |
// file 3 "\c:\program files\synplicity\fpga_81\lib\altera\altera_mf.v " |
// file 4 "\c:\program files\synplicity\fpga_81\lib\altera\altera_lpm.v " |
// file 5 "\d:\lwrisc\rtl\sim_rom.v " |
// file 6 "\d:\lwrisc\rtl\test.v " |
// file 7 "\d:\lwrisc\rtl\mem_man.v " |
// file 8 "\d:\lwrisc\rtl\clairisc_def.h " |
// file 9 "\d:\lwrisc\rtl\memory.v " |
// file 10 "\d:\lwrisc\rtl\rom_set.h " |
// file 11 "\d:\lwrisc\rtl\risc_core.v " |
// file 12 "\d:\lwrisc\rtl\altera\rom512x12.v " |
// file 13 "\d:\lwrisc\rtl\altera\rom1024x12.v " |
// file 14 "\d:\lwrisc\rtl\altera\rom2048x12.v " |
// file 15 "\d:\lwrisc\rtl\altera\ram128x8.v " |
// file 16 "\d:\lwrisc\rtl\altera\rom32x12.v " |
// file 17 "\d:\lwrisc\rtl\altera\rom64x12.v " |
// file 18 "\d:\lwrisc\rtl\altera\rom128x12.v " |
// file 19 "\d:\lwrisc\rtl\altera\rom256x12.v " |
|
// VQM4.1+ |
module altsyncram_Z1 ( |
wren_a, |
data_a, |
address_a, |
address_b, |
clock0, |
q_a, |
q_b |
); |
input wren_a ; |
input [7:0] data_a ; |
input [6:0] address_a ; |
input [6:0] address_b ; |
input clock0 ; |
output [7:0] q_a ; |
output [7:0] q_b ; |
altsyncram U1 ( |
.wren_a(wren_a), |
.data_a(data_a), |
.address_a(address_a), |
.address_b(address_b), |
.clock0(clock0), |
.q_a(q_a), |
.q_b(q_b) |
); |
defparam U1.intended_device_family = "Cyclone"; |
defparam U1.read_during_write_mode_mixed_ports = "DONT_CARE"; |
defparam U1.operation_mode = "DUAL_PORT"; |
defparam U1.address_aclr_b = "NONE"; |
defparam U1.outdata_aclr_b = "NONE"; |
defparam U1.outdata_reg_b = "UNREGISTERED"; |
defparam U1.address_reg_b = "CLOCK0"; |
defparam U1.numwords_b = 128; |
defparam U1.widthad_b = 7; |
defparam U1.width_b = 8; |
defparam U1.width_byteena_a = 1; |
defparam U1.wrcontrol_aclr_a = "NONE"; |
defparam U1.indata_aclr_a = "NONE"; |
defparam U1.address_aclr_a = "NONE"; |
defparam U1.numwords_a = 128; |
defparam U1.widthad_a = 7; |
defparam U1.width_a = 8; |
endmodule /* altsyncram_Z1 */ |
|
// VQM4.1+ |
module ram128x8 ( |
alt_ram_q_7, |
alt_ram_q_6, |
alt_ram_q_5, |
alt_ram_q_4, |
alt_ram_q_3, |
alt_ram_q_2, |
alt_ram_q_1, |
alt_ram_q_0, |
w_ins_4, |
w_ins_3, |
w_ins_2, |
w_ins_1, |
w_ins_0, |
fsr_1, |
fsr_0, |
w_ek_r_4, |
w_ek_r_3, |
w_ek_r_2, |
w_ek_r_1, |
w_ek_r_0, |
w_alu_res_1_6_2, |
w_alu_res_1_6_1, |
w_alu_res_1_6_0, |
w_alu_res_1_3_0, |
w_alu_res_1_1_0, |
w_alu_res_1_0_2, |
w_alu_res_1_0_1, |
w_alu_res_1_0_0, |
clk_c, |
w_mem_wr_r |
); |
output alt_ram_q_7 ; |
output alt_ram_q_6 ; |
output alt_ram_q_5 ; |
output alt_ram_q_4 ; |
output alt_ram_q_3 ; |
output alt_ram_q_2 ; |
output alt_ram_q_1 ; |
output alt_ram_q_0 ; |
input w_ins_4 ; |
input w_ins_3 ; |
input w_ins_2 ; |
input w_ins_1 ; |
input w_ins_0 ; |
input fsr_1 ; |
input fsr_0 ; |
input w_ek_r_4 ; |
input w_ek_r_3 ; |
input w_ek_r_2 ; |
input w_ek_r_1 ; |
input w_ek_r_0 ; |
input w_alu_res_1_6_2 ; |
input w_alu_res_1_6_1 ; |
input w_alu_res_1_6_0 ; |
input w_alu_res_1_3_0 ; |
input w_alu_res_1_1_0 ; |
input w_alu_res_1_0_2 ; |
input w_alu_res_1_0_1 ; |
input w_alu_res_1_0_0 ; |
input clk_c ; |
input w_mem_wr_r ; |
wire alt_ram_q_7 ; |
wire alt_ram_q_6 ; |
wire alt_ram_q_5 ; |
wire alt_ram_q_4 ; |
wire alt_ram_q_3 ; |
wire alt_ram_q_2 ; |
wire alt_ram_q_1 ; |
wire alt_ram_q_0 ; |
wire w_ins_4 ; |
wire w_ins_3 ; |
wire w_ins_2 ; |
wire w_ins_1 ; |
wire w_ins_0 ; |
wire fsr_1 ; |
wire fsr_0 ; |
wire w_ek_r_4 ; |
wire w_ek_r_3 ; |
wire w_ek_r_2 ; |
wire w_ek_r_1 ; |
wire w_ek_r_0 ; |
wire w_alu_res_1_6_2 ; |
wire w_alu_res_1_6_1 ; |
wire w_alu_res_1_6_0 ; |
wire w_alu_res_1_3_0 ; |
wire w_alu_res_1_1_0 ; |
wire w_alu_res_1_0_2 ; |
wire w_alu_res_1_0_1 ; |
wire w_alu_res_1_0_0 ; |
wire clk_c ; |
wire w_mem_wr_r ; |
wire [7:0] q_a; |
wire NC0 ; |
wire NC1 ; |
wire NC2 ; |
wire NC3 ; |
wire NC4 ; |
wire NC5 ; |
wire NC6 ; |
wire NC7 ; |
wire NC8 ; |
wire NC9 ; |
wire NC10 ; |
wire NC11 ; |
wire NC12 ; |
wire NC13 ; |
wire NC14 ; |
wire NC15 ; |
wire NC16 ; |
wire NC17 ; |
wire NC18 ; |
wire GND ; |
wire VCC ; |
assign VCC = 1'b1; |
assign GND = 1'b0; |
// @15:162 |
altsyncram_Z1 altsyncram_component_Z ( |
.wren_a(w_mem_wr_r), |
.data_a({w_alu_res_1_6_2, w_alu_res_1_6_1, w_alu_res_1_6_0, w_alu_res_1_3_0, |
w_alu_res_1_1_0, w_alu_res_1_0_2, w_alu_res_1_0_1, w_alu_res_1_0_0}), |
.address_a({fsr_1, fsr_0, w_ek_r_4, w_ek_r_3, w_ek_r_2, w_ek_r_1, w_ek_r_0}), |
.address_b({fsr_1, fsr_0, w_ins_4, w_ins_3, w_ins_2, w_ins_1, w_ins_0}), |
.clock0(clk_c), |
.q_a({q_a[7], q_a[6], q_a[5], q_a[4], q_a[3], q_a[2], q_a[1], q_a[0]}), |
.q_b({alt_ram_q_7, alt_ram_q_6, alt_ram_q_5, alt_ram_q_4, alt_ram_q_3, |
alt_ram_q_2, alt_ram_q_1, alt_ram_q_0}) |
); |
endmodule /* ram128x8 */ |
|
// VQM4.1+ |
module wb_mem_man ( |
w_ins_0, |
w_ins_1, |
w_ins_2, |
w_ins_3, |
w_ins_4, |
out0_0, |
out0_1, |
out0_2, |
out0_3, |
out0_4, |
out0_5, |
out0_6, |
out0_7, |
out1_0, |
out1_1, |
out1_2, |
out1_3, |
out1_4, |
out1_5, |
out1_6, |
out1_7, |
w_alu_res_1_1_0, |
w_alu_res_1_3_0, |
w_alu_res_1_6_0, |
w_alu_res_1_6_1, |
w_alu_res_1_6_2, |
in0_c_0, |
in0_c_1, |
in0_c_2, |
in0_c_3, |
in0_c_4, |
in0_c_5, |
in0_c_6, |
in0_c_7, |
w_alu_res_1_0_1, |
w_alu_res_1_0_2, |
w_alu_res_1_0_0, |
w_alu_res_1_0_a2_1_0, |
w_alu_res_1_0_a2_1_1, |
dout_4, |
dout_7, |
dout_5, |
dout_3, |
dout_2, |
dout_6, |
dout_0, |
dout_1, |
w_alu_res_1_0_a2_2_0_0, |
w_alu_res_1_0_a2_2_0_1, |
w_alu_res_1_0_0_0, |
w_alu_res_1_0_a2_0_0, |
w_alu_res_1_0_a2_0_1, |
w_alu_res_1_0_a2_0_2, |
w_alu_res_1_1_a_0, |
w_alu_res_1_1_1_0, |
w_alu_res_1_3_a_0, |
w_alu_res_1_3_1_0, |
w_alu_res_1_6_a_2, |
w_alu_res_1_6_a_0, |
w_alu_res_1_6_a_1, |
w_alu_res_1_6_1_2, |
w_alu_res_1_6_1_0, |
w_alu_res_1_6_1_1, |
in1_c_7, |
in1_c_6, |
in1_c_5, |
in1_c_4, |
in1_c_3, |
in1_c_2, |
in1_c_1, |
in1_c_0, |
w_ek_r_4, |
w_ek_r_3, |
w_ek_r_2, |
w_ek_r_1, |
w_ek_r_0, |
write_out0_0_a3_0_o2, |
rst_c, |
un11_w_alu_res_carry_7, |
w_c_2mem_i_a2_0_0, |
N_796, |
w_c_wr_r, |
w_z_0_a2, |
w_z_wr_r, |
G_287, |
G_279, |
G_271, |
rst_i_i, |
un11_w_alu_res_add7, |
un11_w_alu_res_add3, |
un11_w_alu_res_add4, |
un11_w_alu_res_add5, |
un11_w_alu_res_add6, |
w_c_2mem_i_a3, |
w_mem_wr_r, |
clk_c |
); |
input w_ins_0 ; |
input w_ins_1 ; |
input w_ins_2 ; |
input w_ins_3 ; |
input w_ins_4 ; |
output out0_0 ; |
output out0_1 ; |
output out0_2 ; |
output out0_3 ; |
output out0_4 ; |
output out0_5 ; |
output out0_6 ; |
output out0_7 ; |
output out1_0 ; |
output out1_1 ; |
output out1_2 ; |
output out1_3 ; |
output out1_4 ; |
output out1_5 ; |
output out1_6 ; |
output out1_7 ; |
input w_alu_res_1_1_0 ; |
input w_alu_res_1_3_0 ; |
input w_alu_res_1_6_0 ; |
input w_alu_res_1_6_1 ; |
input w_alu_res_1_6_2 ; |
input in0_c_0 ; |
input in0_c_1 ; |
input in0_c_2 ; |
input in0_c_3 ; |
input in0_c_4 ; |
input in0_c_5 ; |
input in0_c_6 ; |
input in0_c_7 ; |
input w_alu_res_1_0_1 ; |
input w_alu_res_1_0_2 ; |
output w_alu_res_1_0_0 ; |
input w_alu_res_1_0_a2_1_0 ; |
input w_alu_res_1_0_a2_1_1 ; |
output dout_4 ; |
output dout_7 ; |
output dout_5 ; |
output dout_3 ; |
output dout_2 ; |
output dout_6 ; |
output dout_0 ; |
output dout_1 ; |
input w_alu_res_1_0_a2_2_0_0 ; |
input w_alu_res_1_0_a2_2_0_1 ; |
input w_alu_res_1_0_0_0 ; |
input w_alu_res_1_0_a2_0_0 ; |
input w_alu_res_1_0_a2_0_1 ; |
input w_alu_res_1_0_a2_0_2 ; |
input w_alu_res_1_1_a_0 ; |
input w_alu_res_1_1_1_0 ; |
input w_alu_res_1_3_a_0 ; |
input w_alu_res_1_3_1_0 ; |
input w_alu_res_1_6_a_2 ; |
input w_alu_res_1_6_a_0 ; |
input w_alu_res_1_6_a_1 ; |
input w_alu_res_1_6_1_2 ; |
input w_alu_res_1_6_1_0 ; |
input w_alu_res_1_6_1_1 ; |
input in1_c_7 ; |
input in1_c_6 ; |
input in1_c_5 ; |
input in1_c_4 ; |
input in1_c_3 ; |
input in1_c_2 ; |
input in1_c_1 ; |
input in1_c_0 ; |
input w_ek_r_4 ; |
input w_ek_r_3 ; |
input w_ek_r_2 ; |
input w_ek_r_1 ; |
input w_ek_r_0 ; |
output write_out0_0_a3_0_o2 ; |
input rst_c ; |
input un11_w_alu_res_carry_7 ; |
input w_c_2mem_i_a2_0_0 ; |
input N_796 ; |
input w_c_wr_r ; |
input w_z_0_a2 ; |
input w_z_wr_r ; |
input G_287 ; |
input G_279 ; |
input G_271 ; |
input rst_i_i ; |
input un11_w_alu_res_add7 ; |
input un11_w_alu_res_add3 ; |
input un11_w_alu_res_add4 ; |
input un11_w_alu_res_add5 ; |
input un11_w_alu_res_add6 ; |
input w_c_2mem_i_a3 ; |
input w_mem_wr_r ; |
input clk_c ; |
wire w_ins_0 ; |
wire w_ins_1 ; |
wire w_ins_2 ; |
wire w_ins_3 ; |
wire w_ins_4 ; |
wire out0_0 ; |
wire out0_1 ; |
wire out0_2 ; |
wire out0_3 ; |
wire out0_4 ; |
wire out0_5 ; |
wire out0_6 ; |
wire out0_7 ; |
wire out1_0 ; |
wire out1_1 ; |
wire out1_2 ; |
wire out1_3 ; |
wire out1_4 ; |
wire out1_5 ; |
wire out1_6 ; |
wire out1_7 ; |
wire w_alu_res_1_1_0 ; |
wire w_alu_res_1_3_0 ; |
wire w_alu_res_1_6_0 ; |
wire w_alu_res_1_6_1 ; |
wire w_alu_res_1_6_2 ; |
wire in0_c_0 ; |
wire in0_c_1 ; |
wire in0_c_2 ; |
wire in0_c_3 ; |
wire in0_c_4 ; |
wire in0_c_5 ; |
wire in0_c_6 ; |
wire in0_c_7 ; |
wire w_alu_res_1_0_1 ; |
wire w_alu_res_1_0_2 ; |
wire w_alu_res_1_0_0 ; |
wire w_alu_res_1_0_a2_1_0 ; |
wire w_alu_res_1_0_a2_1_1 ; |
wire dout_4 ; |
wire dout_7 ; |
wire dout_5 ; |
wire dout_3 ; |
wire dout_2 ; |
wire dout_6 ; |
wire dout_0 ; |
wire dout_1 ; |
wire w_alu_res_1_0_a2_2_0_0 ; |
wire w_alu_res_1_0_a2_2_0_1 ; |
wire w_alu_res_1_0_0_0 ; |
wire w_alu_res_1_0_a2_0_0 ; |
wire w_alu_res_1_0_a2_0_1 ; |
wire w_alu_res_1_0_a2_0_2 ; |
wire w_alu_res_1_1_a_0 ; |
wire w_alu_res_1_1_1_0 ; |
wire w_alu_res_1_3_a_0 ; |
wire w_alu_res_1_3_1_0 ; |
wire w_alu_res_1_6_a_2 ; |
wire w_alu_res_1_6_a_0 ; |
wire w_alu_res_1_6_a_1 ; |
wire w_alu_res_1_6_1_2 ; |
wire w_alu_res_1_6_1_0 ; |
wire w_alu_res_1_6_1_1 ; |
wire in1_c_7 ; |
wire in1_c_6 ; |
wire in1_c_5 ; |
wire in1_c_4 ; |
wire in1_c_3 ; |
wire in1_c_2 ; |
wire in1_c_1 ; |
wire in1_c_0 ; |
wire w_ek_r_4 ; |
wire w_ek_r_3 ; |
wire w_ek_r_2 ; |
wire w_ek_r_1 ; |
wire w_ek_r_0 ; |
wire write_out0_0_a3_0_o2 ; |
wire rst_c ; |
wire un11_w_alu_res_carry_7 ; |
wire w_c_2mem_i_a2_0_0 ; |
wire N_796 ; |
wire w_c_wr_r ; |
wire w_z_0_a2 ; |
wire w_z_wr_r ; |
wire G_287 ; |
wire G_279 ; |
wire G_271 ; |
wire rst_i_i ; |
wire un11_w_alu_res_add7 ; |
wire un11_w_alu_res_add3 ; |
wire un11_w_alu_res_add4 ; |
wire un11_w_alu_res_add5 ; |
wire un11_w_alu_res_add6 ; |
wire w_c_2mem_i_a3 ; |
wire w_mem_wr_r ; |
wire clk_c ; |
wire [4:0] wr_addr_r; |
wire [7:0] dout_1_Z; |
wire [7:0] reg_in0; |
wire [6:0] din_r; |
wire [7:0] status; |
wire [6:6] status_0_0_0_a2_1; |
wire [6:6] status_0_0_0_a2_2; |
wire [2:2] status_0_i_0_a; |
wire [0:0] status_6; |
wire [7:0] fsr; |
wire [0:0] status_6_a; |
wire [7:0] alt_ram_q; |
wire [6:0] dout_a; |
wire [7:0] dout_3_Z; |
wire [7:0] dout_3_a; |
wire ram_q_a ; |
wire VCC ; |
wire dout10 ; |
wire ram_q ; |
wire un1_ram_q_NE_2 ; |
wire un1_ram_q_NE_2_a ; |
wire dout_sn_m5_e_0_a2 ; |
wire dout_sn_m5_e_0_a2_a ; |
wire dout10_2 ; |
wire dout8 ; |
wire dout_sn_m6_0_a2 ; |
wire dout7_1 ; |
wire N_64 ; |
wire N_63 ; |
wire GND ; |
wire rst_i_i_i ; |
//@1:1 |
assign VCC = 1'b1; |
assign GND = 1'b0; |
// @7:36 |
cyclone_lcell wr_en_r_Z ( |
.combout(ram_q_a), |
.clk(clk_c), |
.dataa(wr_addr_r[0]), |
.datab(w_ek_r_0), |
.datac(w_mem_wr_r), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(VCC), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam wr_en_r_Z.operation_mode="normal"; |
defparam wr_en_r_Z.output_mode="comb_only"; |
defparam wr_en_r_Z.lut_mask="6f6f"; |
defparam wr_en_r_Z.synch_mode="on"; |
defparam wr_en_r_Z.sum_lutc_input="qfbk"; |
// @7:109 |
cyclone_lcell reg_in1_0__Z ( |
.combout(dout_1_Z[0]), |
.clk(clk_c), |
.dataa(reg_in0[0]), |
.datab(dout10), |
.datac(in1_c_0), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(VCC), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam reg_in1_0__Z.operation_mode="normal"; |
defparam reg_in1_0__Z.output_mode="comb_only"; |
defparam reg_in1_0__Z.lut_mask="e2e2"; |
defparam reg_in1_0__Z.synch_mode="on"; |
defparam reg_in1_0__Z.sum_lutc_input="qfbk"; |
// @7:109 |
cyclone_lcell reg_in1_1__Z ( |
.combout(dout_1_Z[1]), |
.clk(clk_c), |
.dataa(reg_in0[1]), |
.datab(dout10), |
.datac(in1_c_1), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(VCC), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam reg_in1_1__Z.operation_mode="normal"; |
defparam reg_in1_1__Z.output_mode="comb_only"; |
defparam reg_in1_1__Z.lut_mask="e2e2"; |
defparam reg_in1_1__Z.synch_mode="on"; |
defparam reg_in1_1__Z.sum_lutc_input="qfbk"; |
// @7:109 |
cyclone_lcell reg_in1_2__Z ( |
.combout(dout_1_Z[2]), |
.clk(clk_c), |
.dataa(reg_in0[2]), |
.datab(dout10), |
.datac(in1_c_2), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(VCC), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam reg_in1_2__Z.operation_mode="normal"; |
defparam reg_in1_2__Z.output_mode="comb_only"; |
defparam reg_in1_2__Z.lut_mask="e2e2"; |
defparam reg_in1_2__Z.synch_mode="on"; |
defparam reg_in1_2__Z.sum_lutc_input="qfbk"; |
// @7:109 |
cyclone_lcell reg_in1_3__Z ( |
.combout(dout_1_Z[3]), |
.clk(clk_c), |
.dataa(reg_in0[3]), |
.datab(dout10), |
.datac(in1_c_3), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(VCC), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam reg_in1_3__Z.operation_mode="normal"; |
defparam reg_in1_3__Z.output_mode="comb_only"; |
defparam reg_in1_3__Z.lut_mask="e2e2"; |
defparam reg_in1_3__Z.synch_mode="on"; |
defparam reg_in1_3__Z.sum_lutc_input="qfbk"; |
// @7:109 |
cyclone_lcell reg_in1_4__Z ( |
.combout(dout_1_Z[4]), |
.clk(clk_c), |
.dataa(reg_in0[4]), |
.datab(dout10), |
.datac(in1_c_4), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(VCC), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam reg_in1_4__Z.operation_mode="normal"; |
defparam reg_in1_4__Z.output_mode="comb_only"; |
defparam reg_in1_4__Z.lut_mask="e2e2"; |
defparam reg_in1_4__Z.synch_mode="on"; |
defparam reg_in1_4__Z.sum_lutc_input="qfbk"; |
// @7:109 |
cyclone_lcell reg_in1_5__Z ( |
.combout(dout_1_Z[5]), |
.clk(clk_c), |
.dataa(reg_in0[5]), |
.datab(dout10), |
.datac(in1_c_5), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(VCC), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam reg_in1_5__Z.operation_mode="normal"; |
defparam reg_in1_5__Z.output_mode="comb_only"; |
defparam reg_in1_5__Z.lut_mask="e2e2"; |
defparam reg_in1_5__Z.synch_mode="on"; |
defparam reg_in1_5__Z.sum_lutc_input="qfbk"; |
// @7:109 |
cyclone_lcell reg_in1_6__Z ( |
.combout(dout_1_Z[6]), |
.clk(clk_c), |
.dataa(reg_in0[6]), |
.datab(dout10), |
.datac(in1_c_6), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(VCC), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam reg_in1_6__Z.operation_mode="normal"; |
defparam reg_in1_6__Z.output_mode="comb_only"; |
defparam reg_in1_6__Z.lut_mask="e2e2"; |
defparam reg_in1_6__Z.synch_mode="on"; |
defparam reg_in1_6__Z.sum_lutc_input="qfbk"; |
// @7:109 |
cyclone_lcell reg_in1_7__Z ( |
.combout(dout_1_Z[7]), |
.clk(clk_c), |
.dataa(reg_in0[7]), |
.datab(dout10), |
.datac(in1_c_7), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(VCC), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam reg_in1_7__Z.operation_mode="normal"; |
defparam reg_in1_7__Z.output_mode="comb_only"; |
defparam reg_in1_7__Z.lut_mask="e2e2"; |
defparam reg_in1_7__Z.synch_mode="on"; |
defparam reg_in1_7__Z.sum_lutc_input="qfbk"; |
// @7:36 |
cyclone_lcell wr_addr_r_1__Z ( |
.combout(ram_q), |
.clk(clk_c), |
.dataa(w_ek_r_1), |
.datab(ram_q_a), |
.datac(w_ek_r_1), |
.datad(un1_ram_q_NE_2), |
.aclr(GND), |
.sclr(GND), |
.sload(VCC), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam wr_addr_r_1__Z.operation_mode="normal"; |
defparam wr_addr_r_1__Z.output_mode="comb_only"; |
defparam wr_addr_r_1__Z.lut_mask="0021"; |
defparam wr_addr_r_1__Z.synch_mode="on"; |
defparam wr_addr_r_1__Z.sum_lutc_input="qfbk"; |
// @7:36 |
cyclone_lcell wr_addr_r_2__Z ( |
.combout(un1_ram_q_NE_2), |
.clk(clk_c), |
.dataa(w_ek_r_2), |
.datab(un1_ram_q_NE_2_a), |
.datac(w_ek_r_2), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(VCC), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam wr_addr_r_2__Z.operation_mode="normal"; |
defparam wr_addr_r_2__Z.output_mode="comb_only"; |
defparam wr_addr_r_2__Z.lut_mask="dede"; |
defparam wr_addr_r_2__Z.synch_mode="on"; |
defparam wr_addr_r_2__Z.sum_lutc_input="qfbk"; |
// @7:36 |
cyclone_lcell wr_addr_r_3__Z ( |
.combout(un1_ram_q_NE_2_a), |
.clk(clk_c), |
.dataa(wr_addr_r[4]), |
.datab(w_ek_r_3), |
.datac(w_ek_r_3), |
.datad(w_ek_r_4), |
.aclr(GND), |
.sclr(GND), |
.sload(VCC), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam wr_addr_r_3__Z.operation_mode="normal"; |
defparam wr_addr_r_3__Z.output_mode="comb_only"; |
defparam wr_addr_r_3__Z.lut_mask="7dbe"; |
defparam wr_addr_r_3__Z.synch_mode="on"; |
defparam wr_addr_r_3__Z.sum_lutc_input="qfbk"; |
// @7:36 |
cyclone_lcell din_r_6__Z ( |
.regout(din_r[6]), |
.clk(clk_c), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add6), |
.datac(w_alu_res_1_6_1_1), |
.datad(w_alu_res_1_6_a_1), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam din_r_6__Z.operation_mode="normal"; |
defparam din_r_6__Z.output_mode="reg_only"; |
defparam din_r_6__Z.lut_mask="f8ff"; |
defparam din_r_6__Z.synch_mode="off"; |
defparam din_r_6__Z.sum_lutc_input="datac"; |
// @7:36 |
cyclone_lcell din_r_5__Z ( |
.regout(din_r[5]), |
.clk(clk_c), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add5), |
.datac(w_alu_res_1_6_1_0), |
.datad(w_alu_res_1_6_a_0), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam din_r_5__Z.operation_mode="normal"; |
defparam din_r_5__Z.output_mode="reg_only"; |
defparam din_r_5__Z.lut_mask="f8ff"; |
defparam din_r_5__Z.synch_mode="off"; |
defparam din_r_5__Z.sum_lutc_input="datac"; |
// @7:36 |
cyclone_lcell din_r_4__Z ( |
.regout(din_r[4]), |
.clk(clk_c), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add4), |
.datac(w_alu_res_1_3_1_0), |
.datad(w_alu_res_1_3_a_0), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam din_r_4__Z.operation_mode="normal"; |
defparam din_r_4__Z.output_mode="reg_only"; |
defparam din_r_4__Z.lut_mask="f8ff"; |
defparam din_r_4__Z.synch_mode="off"; |
defparam din_r_4__Z.sum_lutc_input="datac"; |
// @7:36 |
cyclone_lcell din_r_3__Z ( |
.regout(din_r[3]), |
.clk(clk_c), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add3), |
.datac(w_alu_res_1_1_1_0), |
.datad(w_alu_res_1_1_a_0), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam din_r_3__Z.operation_mode="normal"; |
defparam din_r_3__Z.output_mode="reg_only"; |
defparam din_r_3__Z.lut_mask="f8ff"; |
defparam din_r_3__Z.synch_mode="off"; |
defparam din_r_3__Z.sum_lutc_input="datac"; |
// @7:36 |
cyclone_lcell din_r_2__Z ( |
.regout(din_r[2]), |
.clk(clk_c), |
.dataa(VCC), |
.datab(VCC), |
.datac(w_alu_res_1_0_a2_0_2), |
.datad(w_alu_res_1_0_0_0), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam din_r_2__Z.operation_mode="normal"; |
defparam din_r_2__Z.output_mode="reg_only"; |
defparam din_r_2__Z.lut_mask="fff0"; |
defparam din_r_2__Z.synch_mode="off"; |
defparam din_r_2__Z.sum_lutc_input="datac"; |
// @7:36 |
cyclone_lcell din_r_1__Z ( |
.regout(din_r[1]), |
.clk(clk_c), |
.dataa(w_alu_res_1_0_a2_2_0_1), |
.datab(dout_1), |
.datac(w_alu_res_1_0_a2_1_1), |
.datad(w_alu_res_1_0_a2_0_1), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam din_r_1__Z.operation_mode="normal"; |
defparam din_r_1__Z.output_mode="reg_only"; |
defparam din_r_1__Z.lut_mask="fff8"; |
defparam din_r_1__Z.synch_mode="off"; |
defparam din_r_1__Z.sum_lutc_input="datac"; |
// @7:36 |
cyclone_lcell din_r_0__Z ( |
.combout(w_alu_res_1_0_0), |
.regout(din_r[0]), |
.clk(clk_c), |
.dataa(w_alu_res_1_0_a2_2_0_0), |
.datab(dout_0), |
.datac(w_alu_res_1_0_a2_0_0), |
.datad(w_alu_res_1_0_a2_1_0), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam din_r_0__Z.operation_mode="normal"; |
defparam din_r_0__Z.output_mode="reg_and_comb"; |
defparam din_r_0__Z.lut_mask="fff8"; |
defparam din_r_0__Z.synch_mode="off"; |
defparam din_r_0__Z.sum_lutc_input="datac"; |
// @7:36 |
cyclone_lcell wr_addr_r_4__Z ( |
.regout(wr_addr_r[4]), |
.clk(clk_c), |
.dataa(VCC), |
.datab(VCC), |
.datac(VCC), |
.datad(w_ek_r_4), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam wr_addr_r_4__Z.operation_mode="normal"; |
defparam wr_addr_r_4__Z.output_mode="reg_only"; |
defparam wr_addr_r_4__Z.lut_mask="ff00"; |
defparam wr_addr_r_4__Z.synch_mode="off"; |
defparam wr_addr_r_4__Z.sum_lutc_input="datac"; |
// @7:36 |
cyclone_lcell wr_addr_r_0__Z ( |
.regout(wr_addr_r[0]), |
.clk(clk_c), |
.dataa(VCC), |
.datab(VCC), |
.datac(VCC), |
.datad(w_ek_r_0), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam wr_addr_r_0__Z.operation_mode="normal"; |
defparam wr_addr_r_0__Z.output_mode="reg_only"; |
defparam wr_addr_r_0__Z.lut_mask="ff00"; |
defparam wr_addr_r_0__Z.synch_mode="off"; |
defparam wr_addr_r_0__Z.sum_lutc_input="datac"; |
// @7:108 |
cyclone_lcell reg_in0_7__Z ( |
.regout(reg_in0[7]), |
.clk(clk_c), |
.dataa(VCC), |
.datab(VCC), |
.datac(VCC), |
.datad(in0_c_7), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam reg_in0_7__Z.operation_mode="normal"; |
defparam reg_in0_7__Z.output_mode="reg_only"; |
defparam reg_in0_7__Z.lut_mask="ff00"; |
defparam reg_in0_7__Z.synch_mode="off"; |
defparam reg_in0_7__Z.sum_lutc_input="datac"; |
// @7:108 |
cyclone_lcell reg_in0_6__Z ( |
.regout(reg_in0[6]), |
.clk(clk_c), |
.dataa(VCC), |
.datab(VCC), |
.datac(VCC), |
.datad(in0_c_6), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam reg_in0_6__Z.operation_mode="normal"; |
defparam reg_in0_6__Z.output_mode="reg_only"; |
defparam reg_in0_6__Z.lut_mask="ff00"; |
defparam reg_in0_6__Z.synch_mode="off"; |
defparam reg_in0_6__Z.sum_lutc_input="datac"; |
// @7:108 |
cyclone_lcell reg_in0_5__Z ( |
.regout(reg_in0[5]), |
.clk(clk_c), |
.dataa(VCC), |
.datab(VCC), |
.datac(VCC), |
.datad(in0_c_5), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam reg_in0_5__Z.operation_mode="normal"; |
defparam reg_in0_5__Z.output_mode="reg_only"; |
defparam reg_in0_5__Z.lut_mask="ff00"; |
defparam reg_in0_5__Z.synch_mode="off"; |
defparam reg_in0_5__Z.sum_lutc_input="datac"; |
// @7:108 |
cyclone_lcell reg_in0_4__Z ( |
.regout(reg_in0[4]), |
.clk(clk_c), |
.dataa(VCC), |
.datab(VCC), |
.datac(VCC), |
.datad(in0_c_4), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam reg_in0_4__Z.operation_mode="normal"; |
defparam reg_in0_4__Z.output_mode="reg_only"; |
defparam reg_in0_4__Z.lut_mask="ff00"; |
defparam reg_in0_4__Z.synch_mode="off"; |
defparam reg_in0_4__Z.sum_lutc_input="datac"; |
// @7:108 |
cyclone_lcell reg_in0_3__Z ( |
.regout(reg_in0[3]), |
.clk(clk_c), |
.dataa(VCC), |
.datab(VCC), |
.datac(VCC), |
.datad(in0_c_3), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam reg_in0_3__Z.operation_mode="normal"; |
defparam reg_in0_3__Z.output_mode="reg_only"; |
defparam reg_in0_3__Z.lut_mask="ff00"; |
defparam reg_in0_3__Z.synch_mode="off"; |
defparam reg_in0_3__Z.sum_lutc_input="datac"; |
// @7:108 |
cyclone_lcell reg_in0_2__Z ( |
.regout(reg_in0[2]), |
.clk(clk_c), |
.dataa(VCC), |
.datab(VCC), |
.datac(VCC), |
.datad(in0_c_2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam reg_in0_2__Z.operation_mode="normal"; |
defparam reg_in0_2__Z.output_mode="reg_only"; |
defparam reg_in0_2__Z.lut_mask="ff00"; |
defparam reg_in0_2__Z.synch_mode="off"; |
defparam reg_in0_2__Z.sum_lutc_input="datac"; |
// @7:108 |
cyclone_lcell reg_in0_1__Z ( |
.regout(reg_in0[1]), |
.clk(clk_c), |
.dataa(VCC), |
.datab(VCC), |
.datac(VCC), |
.datad(in0_c_1), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam reg_in0_1__Z.operation_mode="normal"; |
defparam reg_in0_1__Z.output_mode="reg_only"; |
defparam reg_in0_1__Z.lut_mask="ff00"; |
defparam reg_in0_1__Z.synch_mode="off"; |
defparam reg_in0_1__Z.sum_lutc_input="datac"; |
// @7:108 |
cyclone_lcell reg_in0_0__Z ( |
.regout(reg_in0[0]), |
.clk(clk_c), |
.dataa(VCC), |
.datab(VCC), |
.datac(VCC), |
.datad(in0_c_0), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam reg_in0_0__Z.operation_mode="normal"; |
defparam reg_in0_0__Z.output_mode="reg_only"; |
defparam reg_in0_0__Z.lut_mask="ff00"; |
defparam reg_in0_0__Z.synch_mode="off"; |
defparam reg_in0_0__Z.sum_lutc_input="datac"; |
// @7:72 |
cyclone_lcell status_7__Z ( |
.regout(status[7]), |
.clk(clk_c), |
.dataa(status[7]), |
.datab(status_0_0_0_a2_1[6]), |
.datac(status_0_0_0_a2_2[6]), |
.datad(w_alu_res_1_6_2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam status_7__Z.operation_mode="normal"; |
defparam status_7__Z.output_mode="reg_only"; |
defparam status_7__Z.lut_mask="eca0"; |
defparam status_7__Z.synch_mode="off"; |
defparam status_7__Z.sum_lutc_input="datac"; |
// @7:72 |
cyclone_lcell status_6__Z ( |
.regout(status[6]), |
.clk(clk_c), |
.dataa(status[6]), |
.datab(status_0_0_0_a2_1[6]), |
.datac(status_0_0_0_a2_2[6]), |
.datad(w_alu_res_1_6_1), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam status_6__Z.operation_mode="normal"; |
defparam status_6__Z.output_mode="reg_only"; |
defparam status_6__Z.lut_mask="eca0"; |
defparam status_6__Z.synch_mode="off"; |
defparam status_6__Z.sum_lutc_input="datac"; |
// @7:72 |
cyclone_lcell status_5__Z ( |
.regout(status[5]), |
.clk(clk_c), |
.dataa(status[5]), |
.datab(status_0_0_0_a2_1[6]), |
.datac(status_0_0_0_a2_2[6]), |
.datad(w_alu_res_1_6_0), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam status_5__Z.operation_mode="normal"; |
defparam status_5__Z.output_mode="reg_only"; |
defparam status_5__Z.lut_mask="af23"; |
defparam status_5__Z.synch_mode="off"; |
defparam status_5__Z.sum_lutc_input="datac"; |
// @7:72 |
cyclone_lcell status_4__Z ( |
.regout(status[4]), |
.clk(clk_c), |
.dataa(status[4]), |
.datab(status_0_0_0_a2_1[6]), |
.datac(status_0_0_0_a2_2[6]), |
.datad(w_alu_res_1_3_0), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam status_4__Z.operation_mode="normal"; |
defparam status_4__Z.output_mode="reg_only"; |
defparam status_4__Z.lut_mask="af23"; |
defparam status_4__Z.synch_mode="off"; |
defparam status_4__Z.sum_lutc_input="datac"; |
// @7:72 |
cyclone_lcell status_3__Z ( |
.regout(status[3]), |
.clk(clk_c), |
.dataa(status[3]), |
.datab(status_0_0_0_a2_1[6]), |
.datac(status_0_0_0_a2_2[6]), |
.datad(w_alu_res_1_1_0), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam status_3__Z.operation_mode="normal"; |
defparam status_3__Z.output_mode="reg_only"; |
defparam status_3__Z.lut_mask="af23"; |
defparam status_3__Z.synch_mode="off"; |
defparam status_3__Z.sum_lutc_input="datac"; |
// @7:72 |
cyclone_lcell status_2__Z ( |
.regout(status[2]), |
.clk(clk_c), |
.dataa(status_0_0_0_a2_2[6]), |
.datab(status_0_0_0_a2_1[6]), |
.datac(w_alu_res_1_0_2), |
.datad(status_0_i_0_a[2]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam status_2__Z.operation_mode="normal"; |
defparam status_2__Z.output_mode="reg_only"; |
defparam status_2__Z.lut_mask="51f3"; |
defparam status_2__Z.synch_mode="off"; |
defparam status_2__Z.sum_lutc_input="datac"; |
// @7:72 |
cyclone_lcell status_1__Z ( |
.regout(status[1]), |
.clk(clk_c), |
.dataa(status[1]), |
.datab(status_0_0_0_a2_1[6]), |
.datac(status_0_0_0_a2_2[6]), |
.datad(w_alu_res_1_0_1), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam status_1__Z.operation_mode="normal"; |
defparam status_1__Z.output_mode="reg_only"; |
defparam status_1__Z.lut_mask="af23"; |
defparam status_1__Z.synch_mode="off"; |
defparam status_1__Z.sum_lutc_input="datac"; |
// @7:72 |
cyclone_lcell status_0__Z ( |
.regout(status[0]), |
.clk(clk_c), |
.dataa(status_0_0_0_a2_1[6]), |
.datab(status_0_0_0_a2_2[6]), |
.datac(w_alu_res_1_0_0), |
.datad(status_6[0]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam status_0__Z.operation_mode="normal"; |
defparam status_0__Z.output_mode="reg_only"; |
defparam status_0__Z.lut_mask="f531"; |
defparam status_0__Z.synch_mode="off"; |
defparam status_0__Z.sum_lutc_input="datac"; |
// @7:121 |
cyclone_lcell out1_7__Z ( |
.regout(out1_7), |
.clk(clk_c), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add7), |
.datac(w_alu_res_1_6_1_2), |
.datad(w_alu_res_1_6_a_2), |
.aclr(GND), |
.sclr(rst_i_i_i), |
.sload(GND), |
.ena(G_271), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam out1_7__Z.operation_mode="normal"; |
defparam out1_7__Z.output_mode="reg_only"; |
defparam out1_7__Z.lut_mask="f8ff"; |
defparam out1_7__Z.synch_mode="on"; |
defparam out1_7__Z.sum_lutc_input="datac"; |
// @7:121 |
cyclone_lcell out1_6__Z ( |
.regout(out1_6), |
.clk(clk_c), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add6), |
.datac(w_alu_res_1_6_1_1), |
.datad(w_alu_res_1_6_a_1), |
.aclr(GND), |
.sclr(rst_i_i_i), |
.sload(GND), |
.ena(G_271), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam out1_6__Z.operation_mode="normal"; |
defparam out1_6__Z.output_mode="reg_only"; |
defparam out1_6__Z.lut_mask="f8ff"; |
defparam out1_6__Z.synch_mode="on"; |
defparam out1_6__Z.sum_lutc_input="datac"; |
// @7:121 |
cyclone_lcell out1_5__Z ( |
.regout(out1_5), |
.clk(clk_c), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add5), |
.datac(w_alu_res_1_6_1_0), |
.datad(w_alu_res_1_6_a_0), |
.aclr(GND), |
.sclr(rst_i_i_i), |
.sload(GND), |
.ena(G_271), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam out1_5__Z.operation_mode="normal"; |
defparam out1_5__Z.output_mode="reg_only"; |
defparam out1_5__Z.lut_mask="f8ff"; |
defparam out1_5__Z.synch_mode="on"; |
defparam out1_5__Z.sum_lutc_input="datac"; |
// @7:121 |
cyclone_lcell out1_4__Z ( |
.regout(out1_4), |
.clk(clk_c), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add4), |
.datac(w_alu_res_1_3_1_0), |
.datad(w_alu_res_1_3_a_0), |
.aclr(GND), |
.sclr(rst_i_i_i), |
.sload(GND), |
.ena(G_271), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam out1_4__Z.operation_mode="normal"; |
defparam out1_4__Z.output_mode="reg_only"; |
defparam out1_4__Z.lut_mask="f8ff"; |
defparam out1_4__Z.synch_mode="on"; |
defparam out1_4__Z.sum_lutc_input="datac"; |
// @7:121 |
cyclone_lcell out1_3__Z ( |
.regout(out1_3), |
.clk(clk_c), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add3), |
.datac(w_alu_res_1_1_1_0), |
.datad(w_alu_res_1_1_a_0), |
.aclr(GND), |
.sclr(rst_i_i_i), |
.sload(GND), |
.ena(G_271), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam out1_3__Z.operation_mode="normal"; |
defparam out1_3__Z.output_mode="reg_only"; |
defparam out1_3__Z.lut_mask="f8ff"; |
defparam out1_3__Z.synch_mode="on"; |
defparam out1_3__Z.sum_lutc_input="datac"; |
// @7:121 |
cyclone_lcell out1_2__Z ( |
.regout(out1_2), |
.clk(clk_c), |
.dataa(VCC), |
.datab(VCC), |
.datac(w_alu_res_1_0_a2_0_2), |
.datad(w_alu_res_1_0_0_0), |
.aclr(GND), |
.sclr(rst_i_i_i), |
.sload(GND), |
.ena(G_271), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam out1_2__Z.operation_mode="normal"; |
defparam out1_2__Z.output_mode="reg_only"; |
defparam out1_2__Z.lut_mask="fff0"; |
defparam out1_2__Z.synch_mode="on"; |
defparam out1_2__Z.sum_lutc_input="datac"; |
// @7:121 |
cyclone_lcell out1_1__Z ( |
.regout(out1_1), |
.clk(clk_c), |
.dataa(w_alu_res_1_0_a2_2_0_1), |
.datab(dout_1), |
.datac(w_alu_res_1_0_a2_1_1), |
.datad(w_alu_res_1_0_a2_0_1), |
.aclr(GND), |
.sclr(rst_i_i_i), |
.sload(GND), |
.ena(G_271), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam out1_1__Z.operation_mode="normal"; |
defparam out1_1__Z.output_mode="reg_only"; |
defparam out1_1__Z.lut_mask="fff8"; |
defparam out1_1__Z.synch_mode="on"; |
defparam out1_1__Z.sum_lutc_input="datac"; |
// @7:121 |
cyclone_lcell out1_0__Z ( |
.regout(out1_0), |
.clk(clk_c), |
.dataa(w_alu_res_1_0_a2_2_0_0), |
.datab(dout_0), |
.datac(w_alu_res_1_0_a2_1_0), |
.datad(w_alu_res_1_0_a2_0_0), |
.aclr(GND), |
.sclr(rst_i_i_i), |
.sload(GND), |
.ena(G_271), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam out1_0__Z.operation_mode="normal"; |
defparam out1_0__Z.output_mode="reg_only"; |
defparam out1_0__Z.lut_mask="fff8"; |
defparam out1_0__Z.synch_mode="on"; |
defparam out1_0__Z.sum_lutc_input="datac"; |
// @7:113 |
cyclone_lcell out0_7__Z ( |
.regout(out0_7), |
.clk(clk_c), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add7), |
.datac(w_alu_res_1_6_1_2), |
.datad(w_alu_res_1_6_a_2), |
.aclr(GND), |
.sclr(rst_i_i_i), |
.sload(GND), |
.ena(G_279), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam out0_7__Z.operation_mode="normal"; |
defparam out0_7__Z.output_mode="reg_only"; |
defparam out0_7__Z.lut_mask="f8ff"; |
defparam out0_7__Z.synch_mode="on"; |
defparam out0_7__Z.sum_lutc_input="datac"; |
// @7:113 |
cyclone_lcell out0_6__Z ( |
.regout(out0_6), |
.clk(clk_c), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add6), |
.datac(w_alu_res_1_6_1_1), |
.datad(w_alu_res_1_6_a_1), |
.aclr(GND), |
.sclr(rst_i_i_i), |
.sload(GND), |
.ena(G_279), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam out0_6__Z.operation_mode="normal"; |
defparam out0_6__Z.output_mode="reg_only"; |
defparam out0_6__Z.lut_mask="f8ff"; |
defparam out0_6__Z.synch_mode="on"; |
defparam out0_6__Z.sum_lutc_input="datac"; |
// @7:113 |
cyclone_lcell out0_5__Z ( |
.regout(out0_5), |
.clk(clk_c), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add5), |
.datac(w_alu_res_1_6_1_0), |
.datad(w_alu_res_1_6_a_0), |
.aclr(GND), |
.sclr(rst_i_i_i), |
.sload(GND), |
.ena(G_279), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam out0_5__Z.operation_mode="normal"; |
defparam out0_5__Z.output_mode="reg_only"; |
defparam out0_5__Z.lut_mask="f8ff"; |
defparam out0_5__Z.synch_mode="on"; |
defparam out0_5__Z.sum_lutc_input="datac"; |
// @7:113 |
cyclone_lcell out0_4__Z ( |
.regout(out0_4), |
.clk(clk_c), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add4), |
.datac(w_alu_res_1_3_1_0), |
.datad(w_alu_res_1_3_a_0), |
.aclr(GND), |
.sclr(rst_i_i_i), |
.sload(GND), |
.ena(G_279), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam out0_4__Z.operation_mode="normal"; |
defparam out0_4__Z.output_mode="reg_only"; |
defparam out0_4__Z.lut_mask="f8ff"; |
defparam out0_4__Z.synch_mode="on"; |
defparam out0_4__Z.sum_lutc_input="datac"; |
// @7:113 |
cyclone_lcell out0_3__Z ( |
.regout(out0_3), |
.clk(clk_c), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add3), |
.datac(w_alu_res_1_1_1_0), |
.datad(w_alu_res_1_1_a_0), |
.aclr(GND), |
.sclr(rst_i_i_i), |
.sload(GND), |
.ena(G_279), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam out0_3__Z.operation_mode="normal"; |
defparam out0_3__Z.output_mode="reg_only"; |
defparam out0_3__Z.lut_mask="f8ff"; |
defparam out0_3__Z.synch_mode="on"; |
defparam out0_3__Z.sum_lutc_input="datac"; |
// @7:113 |
cyclone_lcell out0_2__Z ( |
.regout(out0_2), |
.clk(clk_c), |
.dataa(VCC), |
.datab(VCC), |
.datac(w_alu_res_1_0_a2_0_2), |
.datad(w_alu_res_1_0_0_0), |
.aclr(GND), |
.sclr(rst_i_i_i), |
.sload(GND), |
.ena(G_279), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam out0_2__Z.operation_mode="normal"; |
defparam out0_2__Z.output_mode="reg_only"; |
defparam out0_2__Z.lut_mask="fff0"; |
defparam out0_2__Z.synch_mode="on"; |
defparam out0_2__Z.sum_lutc_input="datac"; |
// @7:113 |
cyclone_lcell out0_1__Z ( |
.regout(out0_1), |
.clk(clk_c), |
.dataa(w_alu_res_1_0_a2_2_0_1), |
.datab(dout_1), |
.datac(w_alu_res_1_0_a2_1_1), |
.datad(w_alu_res_1_0_a2_0_1), |
.aclr(GND), |
.sclr(rst_i_i_i), |
.sload(GND), |
.ena(G_279), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam out0_1__Z.operation_mode="normal"; |
defparam out0_1__Z.output_mode="reg_only"; |
defparam out0_1__Z.lut_mask="fff8"; |
defparam out0_1__Z.synch_mode="on"; |
defparam out0_1__Z.sum_lutc_input="datac"; |
// @7:113 |
cyclone_lcell out0_0__Z ( |
.regout(out0_0), |
.clk(clk_c), |
.dataa(w_alu_res_1_0_a2_2_0_0), |
.datab(dout_0), |
.datac(w_alu_res_1_0_a2_1_0), |
.datad(w_alu_res_1_0_a2_0_0), |
.aclr(GND), |
.sclr(rst_i_i_i), |
.sload(GND), |
.ena(G_279), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam out0_0__Z.operation_mode="normal"; |
defparam out0_0__Z.output_mode="reg_only"; |
defparam out0_0__Z.lut_mask="fff8"; |
defparam out0_0__Z.synch_mode="on"; |
defparam out0_0__Z.sum_lutc_input="datac"; |
// @7:100 |
cyclone_lcell fsr_7__Z ( |
.regout(fsr[7]), |
.clk(clk_c), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add7), |
.datac(w_alu_res_1_6_1_2), |
.datad(w_alu_res_1_6_a_2), |
.aclr(GND), |
.sclr(rst_i_i_i), |
.sload(GND), |
.ena(G_287), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam fsr_7__Z.operation_mode="normal"; |
defparam fsr_7__Z.output_mode="reg_only"; |
defparam fsr_7__Z.lut_mask="f8ff"; |
defparam fsr_7__Z.synch_mode="on"; |
defparam fsr_7__Z.sum_lutc_input="datac"; |
// @7:100 |
cyclone_lcell fsr_6__Z ( |
.regout(fsr[6]), |
.clk(clk_c), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add6), |
.datac(w_alu_res_1_6_1_1), |
.datad(w_alu_res_1_6_a_1), |
.aclr(GND), |
.sclr(rst_i_i_i), |
.sload(GND), |
.ena(G_287), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam fsr_6__Z.operation_mode="normal"; |
defparam fsr_6__Z.output_mode="reg_only"; |
defparam fsr_6__Z.lut_mask="f8ff"; |
defparam fsr_6__Z.synch_mode="on"; |
defparam fsr_6__Z.sum_lutc_input="datac"; |
// @7:100 |
cyclone_lcell fsr_5__Z ( |
.regout(fsr[5]), |
.clk(clk_c), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add5), |
.datac(w_alu_res_1_6_1_0), |
.datad(w_alu_res_1_6_a_0), |
.aclr(GND), |
.sclr(rst_i_i_i), |
.sload(GND), |
.ena(G_287), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam fsr_5__Z.operation_mode="normal"; |
defparam fsr_5__Z.output_mode="reg_only"; |
defparam fsr_5__Z.lut_mask="f8ff"; |
defparam fsr_5__Z.synch_mode="on"; |
defparam fsr_5__Z.sum_lutc_input="datac"; |
// @7:100 |
cyclone_lcell fsr_4__Z ( |
.regout(fsr[4]), |
.clk(clk_c), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add4), |
.datac(w_alu_res_1_3_1_0), |
.datad(w_alu_res_1_3_a_0), |
.aclr(GND), |
.sclr(rst_i_i_i), |
.sload(GND), |
.ena(G_287), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam fsr_4__Z.operation_mode="normal"; |
defparam fsr_4__Z.output_mode="reg_only"; |
defparam fsr_4__Z.lut_mask="f8ff"; |
defparam fsr_4__Z.synch_mode="on"; |
defparam fsr_4__Z.sum_lutc_input="datac"; |
// @7:100 |
cyclone_lcell fsr_3__Z ( |
.regout(fsr[3]), |
.clk(clk_c), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add3), |
.datac(w_alu_res_1_1_1_0), |
.datad(w_alu_res_1_1_a_0), |
.aclr(GND), |
.sclr(rst_i_i_i), |
.sload(GND), |
.ena(G_287), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam fsr_3__Z.operation_mode="normal"; |
defparam fsr_3__Z.output_mode="reg_only"; |
defparam fsr_3__Z.lut_mask="f8ff"; |
defparam fsr_3__Z.synch_mode="on"; |
defparam fsr_3__Z.sum_lutc_input="datac"; |
// @7:100 |
cyclone_lcell fsr_2__Z ( |
.regout(fsr[2]), |
.clk(clk_c), |
.dataa(VCC), |
.datab(VCC), |
.datac(w_alu_res_1_0_a2_0_2), |
.datad(w_alu_res_1_0_0_0), |
.aclr(GND), |
.sclr(rst_i_i_i), |
.sload(GND), |
.ena(G_287), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam fsr_2__Z.operation_mode="normal"; |
defparam fsr_2__Z.output_mode="reg_only"; |
defparam fsr_2__Z.lut_mask="fff0"; |
defparam fsr_2__Z.synch_mode="on"; |
defparam fsr_2__Z.sum_lutc_input="datac"; |
// @7:100 |
cyclone_lcell fsr_1__Z ( |
.regout(fsr[1]), |
.clk(clk_c), |
.dataa(w_alu_res_1_0_a2_2_0_1), |
.datab(dout_1), |
.datac(w_alu_res_1_0_a2_1_1), |
.datad(w_alu_res_1_0_a2_0_1), |
.aclr(GND), |
.sclr(rst_i_i_i), |
.sload(GND), |
.ena(G_287), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam fsr_1__Z.operation_mode="normal"; |
defparam fsr_1__Z.output_mode="reg_only"; |
defparam fsr_1__Z.lut_mask="fff8"; |
defparam fsr_1__Z.synch_mode="on"; |
defparam fsr_1__Z.sum_lutc_input="datac"; |
// @7:100 |
cyclone_lcell fsr_0__Z ( |
.regout(fsr[0]), |
.clk(clk_c), |
.dataa(w_alu_res_1_0_a2_2_0_0), |
.datab(dout_0), |
.datac(w_alu_res_1_0_a2_1_0), |
.datad(w_alu_res_1_0_a2_0_0), |
.aclr(GND), |
.sclr(rst_i_i_i), |
.sload(GND), |
.ena(G_287), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam fsr_0__Z.operation_mode="normal"; |
defparam fsr_0__Z.output_mode="reg_only"; |
defparam fsr_0__Z.lut_mask="fff8"; |
defparam fsr_0__Z.synch_mode="on"; |
defparam fsr_0__Z.sum_lutc_input="datac"; |
// @7:72 |
cyclone_lcell status_0_i_0_a_2_ ( |
.combout(status_0_i_0_a[2]), |
.dataa(VCC), |
.datab(status[2]), |
.datac(w_z_wr_r), |
.datad(w_z_0_a2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam status_0_i_0_a_2_.operation_mode="normal"; |
defparam status_0_i_0_a_2_.output_mode="comb_only"; |
defparam status_0_i_0_a_2_.lut_mask="03f3"; |
defparam status_0_i_0_a_2_.synch_mode="off"; |
defparam status_0_i_0_a_2_.sum_lutc_input="datac"; |
// @7:79 |
cyclone_lcell status_6_0_ ( |
.combout(status_6[0]), |
.dataa(status[0]), |
.datab(w_c_wr_r), |
.datac(status_6_a[0]), |
.datad(N_796), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam status_6_0_.operation_mode="normal"; |
defparam status_6_0_.output_mode="comb_only"; |
defparam status_6_0_.lut_mask="22e2"; |
defparam status_6_0_.synch_mode="off"; |
defparam status_6_0_.sum_lutc_input="datac"; |
// @7:79 |
cyclone_lcell status_6_a_0_ ( |
.combout(status_6_a[0]), |
.dataa(VCC), |
.datab(w_c_2mem_i_a2_0_0), |
.datac(w_c_2mem_i_a3), |
.datad(un11_w_alu_res_carry_7), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam status_6_a_0_.operation_mode="normal"; |
defparam status_6_a_0_.output_mode="comb_only"; |
defparam status_6_a_0_.lut_mask="330f"; |
defparam status_6_a_0_.synch_mode="off"; |
defparam status_6_a_0_.sum_lutc_input="datac"; |
// @7:72 |
cyclone_lcell status_0_0_0_a2_1_6_ ( |
.combout(status_0_0_0_a2_1[6]), |
.dataa(rst_c), |
.datab(w_ek_r_2), |
.datac(w_ek_r_0), |
.datad(write_out0_0_a3_0_o2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam status_0_0_0_a2_1_6_.operation_mode="normal"; |
defparam status_0_0_0_a2_1_6_.output_mode="comb_only"; |
defparam status_0_0_0_a2_1_6_.lut_mask="0010"; |
defparam status_0_0_0_a2_1_6_.synch_mode="off"; |
defparam status_0_0_0_a2_1_6_.sum_lutc_input="datac"; |
// @7:72 |
cyclone_lcell status_0_0_0_a2_2_6_ ( |
.combout(status_0_0_0_a2_2[6]), |
.dataa(rst_c), |
.datab(w_ek_r_2), |
.datac(w_ek_r_0), |
.datad(write_out0_0_a3_0_o2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam status_0_0_0_a2_2_6_.operation_mode="normal"; |
defparam status_0_0_0_a2_2_6_.output_mode="comb_only"; |
defparam status_0_0_0_a2_2_6_.lut_mask="5545"; |
defparam status_0_0_0_a2_2_6_.synch_mode="off"; |
defparam status_0_0_0_a2_2_6_.sum_lutc_input="datac"; |
// @7:68 |
cyclone_lcell dout_sn_m5_e_0_a2_cZ ( |
.combout(dout_sn_m5_e_0_a2), |
.dataa(w_ek_r_3), |
.datab(w_ek_r_2), |
.datac(dout_sn_m5_e_0_a2_a), |
.datad(dout10), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_sn_m5_e_0_a2_cZ.operation_mode="normal"; |
defparam dout_sn_m5_e_0_a2_cZ.output_mode="comb_only"; |
defparam dout_sn_m5_e_0_a2_cZ.lut_mask="00bf"; |
defparam dout_sn_m5_e_0_a2_cZ.synch_mode="off"; |
defparam dout_sn_m5_e_0_a2_cZ.sum_lutc_input="datac"; |
// @7:68 |
cyclone_lcell dout_sn_m5_e_0_a2_a_cZ ( |
.combout(dout_sn_m5_e_0_a2_a), |
.dataa(VCC), |
.datab(w_ek_r_4), |
.datac(w_ek_r_1), |
.datad(w_ek_r_0), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_sn_m5_e_0_a2_a_cZ.operation_mode="normal"; |
defparam dout_sn_m5_e_0_a2_a_cZ.output_mode="comb_only"; |
defparam dout_sn_m5_e_0_a2_a_cZ.lut_mask="0300"; |
defparam dout_sn_m5_e_0_a2_a_cZ.synch_mode="off"; |
defparam dout_sn_m5_e_0_a2_a_cZ.sum_lutc_input="datac"; |
// @7:133 |
cyclone_lcell dout10_cZ ( |
.combout(dout10), |
.dataa(w_ek_r_4), |
.datab(w_ek_r_1), |
.datac(w_ek_r_0), |
.datad(dout10_2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout10_cZ.operation_mode="normal"; |
defparam dout10_cZ.output_mode="comb_only"; |
defparam dout10_cZ.lut_mask="1000"; |
defparam dout10_cZ.synch_mode="off"; |
defparam dout10_cZ.sum_lutc_input="datac"; |
// @7:131 |
cyclone_lcell dout8_cZ ( |
.combout(dout8), |
.dataa(w_ek_r_4), |
.datab(w_ek_r_1), |
.datac(w_ek_r_0), |
.datad(dout10_2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout8_cZ.operation_mode="normal"; |
defparam dout8_cZ.output_mode="comb_only"; |
defparam dout8_cZ.lut_mask="4000"; |
defparam dout8_cZ.synch_mode="off"; |
defparam dout8_cZ.sum_lutc_input="datac"; |
// @7:68 |
cyclone_lcell dout_sn_m6_0_a2_cZ ( |
.combout(dout_sn_m6_0_a2), |
.dataa(w_ek_r_4), |
.datab(dout7_1), |
.datac(dout8), |
.datad(dout_sn_m5_e_0_a2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_sn_m6_0_a2_cZ.operation_mode="normal"; |
defparam dout_sn_m6_0_a2_cZ.output_mode="comb_only"; |
defparam dout_sn_m6_0_a2_cZ.lut_mask="0b00"; |
defparam dout_sn_m6_0_a2_cZ.synch_mode="off"; |
defparam dout_sn_m6_0_a2_cZ.sum_lutc_input="datac"; |
// @7:112 |
cyclone_lcell write_out0_0_a3_0_o2_cZ ( |
.combout(write_out0_0_a3_0_o2), |
.dataa(w_mem_wr_r), |
.datab(w_ek_r_3), |
.datac(w_ek_r_4), |
.datad(w_ek_r_1), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam write_out0_0_a3_0_o2_cZ.operation_mode="normal"; |
defparam write_out0_0_a3_0_o2_cZ.output_mode="comb_only"; |
defparam write_out0_0_a3_0_o2_cZ.lut_mask="fdff"; |
defparam write_out0_0_a3_0_o2_cZ.synch_mode="off"; |
defparam write_out0_0_a3_0_o2_cZ.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_6_ ( |
.combout(dout_6), |
.dataa(ram_q), |
.datab(alt_ram_q[6]), |
.datac(dout_sn_m6_0_a2), |
.datad(dout_a[6]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_6_.operation_mode="normal"; |
defparam dout_6_.output_mode="comb_only"; |
defparam dout_6_.lut_mask="40ef"; |
defparam dout_6_.synch_mode="off"; |
defparam dout_6_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_a_6_ ( |
.combout(dout_a[6]), |
.dataa(VCC), |
.datab(din_r[6]), |
.datac(dout_3_Z[6]), |
.datad(dout_sn_m6_0_a2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_a_6_.operation_mode="normal"; |
defparam dout_a_6_.output_mode="comb_only"; |
defparam dout_a_6_.lut_mask="330f"; |
defparam dout_a_6_.synch_mode="off"; |
defparam dout_a_6_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_1_ ( |
.combout(dout_1), |
.dataa(ram_q), |
.datab(alt_ram_q[1]), |
.datac(dout_sn_m6_0_a2), |
.datad(dout_a[1]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_1_.operation_mode="normal"; |
defparam dout_1_.output_mode="comb_only"; |
defparam dout_1_.lut_mask="40ef"; |
defparam dout_1_.synch_mode="off"; |
defparam dout_1_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_a_1_ ( |
.combout(dout_a[1]), |
.dataa(VCC), |
.datab(din_r[1]), |
.datac(dout_3_Z[1]), |
.datad(dout_sn_m6_0_a2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_a_1_.operation_mode="normal"; |
defparam dout_a_1_.output_mode="comb_only"; |
defparam dout_a_1_.lut_mask="330f"; |
defparam dout_a_1_.synch_mode="off"; |
defparam dout_a_1_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_2_ ( |
.combout(dout_2), |
.dataa(ram_q), |
.datab(alt_ram_q[2]), |
.datac(dout_sn_m6_0_a2), |
.datad(dout_a[2]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_2_.operation_mode="normal"; |
defparam dout_2_.output_mode="comb_only"; |
defparam dout_2_.lut_mask="40ef"; |
defparam dout_2_.synch_mode="off"; |
defparam dout_2_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_a_2_ ( |
.combout(dout_a[2]), |
.dataa(VCC), |
.datab(din_r[2]), |
.datac(dout_3_Z[2]), |
.datad(dout_sn_m6_0_a2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_a_2_.operation_mode="normal"; |
defparam dout_a_2_.output_mode="comb_only"; |
defparam dout_a_2_.lut_mask="330f"; |
defparam dout_a_2_.synch_mode="off"; |
defparam dout_a_2_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_3_ ( |
.combout(dout_3), |
.dataa(ram_q), |
.datab(alt_ram_q[3]), |
.datac(dout_sn_m6_0_a2), |
.datad(dout_a[3]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_3_.operation_mode="normal"; |
defparam dout_3_.output_mode="comb_only"; |
defparam dout_3_.lut_mask="40ef"; |
defparam dout_3_.synch_mode="off"; |
defparam dout_3_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_a_3_ ( |
.combout(dout_a[3]), |
.dataa(VCC), |
.datab(din_r[3]), |
.datac(dout_3_Z[3]), |
.datad(dout_sn_m6_0_a2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_a_3_.operation_mode="normal"; |
defparam dout_a_3_.output_mode="comb_only"; |
defparam dout_a_3_.lut_mask="330f"; |
defparam dout_a_3_.synch_mode="off"; |
defparam dout_a_3_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_5_ ( |
.combout(dout_5), |
.dataa(ram_q), |
.datab(alt_ram_q[5]), |
.datac(dout_sn_m6_0_a2), |
.datad(dout_a[5]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_5_.operation_mode="normal"; |
defparam dout_5_.output_mode="comb_only"; |
defparam dout_5_.lut_mask="40ef"; |
defparam dout_5_.synch_mode="off"; |
defparam dout_5_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_a_5_ ( |
.combout(dout_a[5]), |
.dataa(VCC), |
.datab(din_r[5]), |
.datac(dout_3_Z[5]), |
.datad(dout_sn_m6_0_a2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_a_5_.operation_mode="normal"; |
defparam dout_a_5_.output_mode="comb_only"; |
defparam dout_a_5_.lut_mask="330f"; |
defparam dout_a_5_.synch_mode="off"; |
defparam dout_a_5_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_0_ ( |
.combout(dout_0), |
.dataa(ram_q), |
.datab(alt_ram_q[0]), |
.datac(dout_sn_m6_0_a2), |
.datad(dout_a[0]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_0_.operation_mode="normal"; |
defparam dout_0_.output_mode="comb_only"; |
defparam dout_0_.lut_mask="40ef"; |
defparam dout_0_.synch_mode="off"; |
defparam dout_0_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_a_0_ ( |
.combout(dout_a[0]), |
.dataa(VCC), |
.datab(din_r[0]), |
.datac(dout_3_Z[0]), |
.datad(dout_sn_m6_0_a2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_a_0_.operation_mode="normal"; |
defparam dout_a_0_.output_mode="comb_only"; |
defparam dout_a_0_.lut_mask="330f"; |
defparam dout_a_0_.synch_mode="off"; |
defparam dout_a_0_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_7_ ( |
.combout(dout_7), |
.dataa(ram_q), |
.datab(dout_3_Z[7]), |
.datac(alt_ram_q[7]), |
.datad(dout_sn_m6_0_a2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_7_.operation_mode="normal"; |
defparam dout_7_.output_mode="comb_only"; |
defparam dout_7_.lut_mask="50cc"; |
defparam dout_7_.synch_mode="off"; |
defparam dout_7_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_4_ ( |
.combout(dout_4), |
.dataa(ram_q), |
.datab(alt_ram_q[4]), |
.datac(dout_sn_m6_0_a2), |
.datad(dout_a[4]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_4_.operation_mode="normal"; |
defparam dout_4_.output_mode="comb_only"; |
defparam dout_4_.lut_mask="40ef"; |
defparam dout_4_.synch_mode="off"; |
defparam dout_4_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_a_4_ ( |
.combout(dout_a[4]), |
.dataa(VCC), |
.datab(din_r[4]), |
.datac(dout_3_Z[4]), |
.datad(dout_sn_m6_0_a2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_a_4_.operation_mode="normal"; |
defparam dout_a_4_.output_mode="comb_only"; |
defparam dout_a_4_.lut_mask="330f"; |
defparam dout_a_4_.synch_mode="off"; |
defparam dout_a_4_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_3_6_ ( |
.combout(dout_3_Z[6]), |
.dataa(VCC), |
.datab(dout_3_a[6]), |
.datac(dout_1_Z[6]), |
.datad(dout_sn_m5_e_0_a2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_3_6_.operation_mode="normal"; |
defparam dout_3_6_.output_mode="comb_only"; |
defparam dout_3_6_.lut_mask="33f0"; |
defparam dout_3_6_.synch_mode="off"; |
defparam dout_3_6_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_3_a_6_ ( |
.combout(dout_3_a[6]), |
.dataa(VCC), |
.datab(fsr[6]), |
.datac(status[6]), |
.datad(dout8), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_3_a_6_.operation_mode="normal"; |
defparam dout_3_a_6_.output_mode="comb_only"; |
defparam dout_3_a_6_.lut_mask="0f33"; |
defparam dout_3_a_6_.synch_mode="off"; |
defparam dout_3_a_6_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_3_1_ ( |
.combout(dout_3_Z[1]), |
.dataa(VCC), |
.datab(dout_3_a[1]), |
.datac(dout_1_Z[1]), |
.datad(dout_sn_m5_e_0_a2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_3_1_.operation_mode="normal"; |
defparam dout_3_1_.output_mode="comb_only"; |
defparam dout_3_1_.lut_mask="33f0"; |
defparam dout_3_1_.synch_mode="off"; |
defparam dout_3_1_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_3_a_1_ ( |
.combout(dout_3_a[1]), |
.dataa(VCC), |
.datab(status[1]), |
.datac(fsr[1]), |
.datad(dout7_1), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_3_a_1_.operation_mode="normal"; |
defparam dout_3_a_1_.output_mode="comb_only"; |
defparam dout_3_a_1_.lut_mask="0f33"; |
defparam dout_3_a_1_.synch_mode="off"; |
defparam dout_3_a_1_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_3_2_ ( |
.combout(dout_3_Z[2]), |
.dataa(VCC), |
.datab(dout_3_a[2]), |
.datac(dout_1_Z[2]), |
.datad(dout_sn_m5_e_0_a2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_3_2_.operation_mode="normal"; |
defparam dout_3_2_.output_mode="comb_only"; |
defparam dout_3_2_.lut_mask="33f0"; |
defparam dout_3_2_.synch_mode="off"; |
defparam dout_3_2_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_3_a_2_ ( |
.combout(dout_3_a[2]), |
.dataa(VCC), |
.datab(status[2]), |
.datac(fsr[2]), |
.datad(dout7_1), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_3_a_2_.operation_mode="normal"; |
defparam dout_3_a_2_.output_mode="comb_only"; |
defparam dout_3_a_2_.lut_mask="0f33"; |
defparam dout_3_a_2_.synch_mode="off"; |
defparam dout_3_a_2_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_3_3_ ( |
.combout(dout_3_Z[3]), |
.dataa(VCC), |
.datab(dout_3_a[3]), |
.datac(dout_1_Z[3]), |
.datad(dout_sn_m5_e_0_a2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_3_3_.operation_mode="normal"; |
defparam dout_3_3_.output_mode="comb_only"; |
defparam dout_3_3_.lut_mask="33f0"; |
defparam dout_3_3_.synch_mode="off"; |
defparam dout_3_3_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_3_a_3_ ( |
.combout(dout_3_a[3]), |
.dataa(VCC), |
.datab(status[3]), |
.datac(fsr[3]), |
.datad(dout7_1), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_3_a_3_.operation_mode="normal"; |
defparam dout_3_a_3_.output_mode="comb_only"; |
defparam dout_3_a_3_.lut_mask="0f33"; |
defparam dout_3_a_3_.synch_mode="off"; |
defparam dout_3_a_3_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_3_5_ ( |
.combout(dout_3_Z[5]), |
.dataa(VCC), |
.datab(dout_3_a[5]), |
.datac(dout_1_Z[5]), |
.datad(dout_sn_m5_e_0_a2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_3_5_.operation_mode="normal"; |
defparam dout_3_5_.output_mode="comb_only"; |
defparam dout_3_5_.lut_mask="33f0"; |
defparam dout_3_5_.synch_mode="off"; |
defparam dout_3_5_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_3_a_5_ ( |
.combout(dout_3_a[5]), |
.dataa(VCC), |
.datab(status[5]), |
.datac(fsr[5]), |
.datad(dout7_1), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_3_a_5_.operation_mode="normal"; |
defparam dout_3_a_5_.output_mode="comb_only"; |
defparam dout_3_a_5_.lut_mask="0f33"; |
defparam dout_3_a_5_.synch_mode="off"; |
defparam dout_3_a_5_.sum_lutc_input="datac"; |
// @7:130 |
cyclone_lcell dout7_1_cZ ( |
.combout(dout7_1), |
.dataa(w_ek_r_3), |
.datab(w_ek_r_1), |
.datac(w_ek_r_2), |
.datad(w_ek_r_0), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout7_1_cZ.operation_mode="normal"; |
defparam dout7_1_cZ.output_mode="comb_only"; |
defparam dout7_1_cZ.lut_mask="0010"; |
defparam dout7_1_cZ.synch_mode="off"; |
defparam dout7_1_cZ.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_3_0_ ( |
.combout(dout_3_Z[0]), |
.dataa(VCC), |
.datab(dout_3_a[0]), |
.datac(dout_1_Z[0]), |
.datad(dout_sn_m5_e_0_a2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_3_0_.operation_mode="normal"; |
defparam dout_3_0_.output_mode="comb_only"; |
defparam dout_3_0_.lut_mask="33f0"; |
defparam dout_3_0_.synch_mode="off"; |
defparam dout_3_0_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_3_a_0_ ( |
.combout(dout_3_a[0]), |
.dataa(VCC), |
.datab(fsr[0]), |
.datac(status[0]), |
.datad(dout8), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_3_a_0_.operation_mode="normal"; |
defparam dout_3_a_0_.output_mode="comb_only"; |
defparam dout_3_a_0_.lut_mask="0f33"; |
defparam dout_3_a_0_.synch_mode="off"; |
defparam dout_3_a_0_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_3_7_ ( |
.combout(dout_3_Z[7]), |
.dataa(VCC), |
.datab(dout_3_a[7]), |
.datac(dout_1_Z[7]), |
.datad(dout_sn_m5_e_0_a2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_3_7_.operation_mode="normal"; |
defparam dout_3_7_.output_mode="comb_only"; |
defparam dout_3_7_.lut_mask="33f0"; |
defparam dout_3_7_.synch_mode="off"; |
defparam dout_3_7_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_3_a_7_ ( |
.combout(dout_3_a[7]), |
.dataa(VCC), |
.datab(fsr[7]), |
.datac(status[7]), |
.datad(dout8), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_3_a_7_.operation_mode="normal"; |
defparam dout_3_a_7_.output_mode="comb_only"; |
defparam dout_3_a_7_.lut_mask="0f33"; |
defparam dout_3_a_7_.synch_mode="off"; |
defparam dout_3_a_7_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_3_4_ ( |
.combout(dout_3_Z[4]), |
.dataa(VCC), |
.datab(dout_3_a[4]), |
.datac(dout_1_Z[4]), |
.datad(dout_sn_m5_e_0_a2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_3_4_.operation_mode="normal"; |
defparam dout_3_4_.output_mode="comb_only"; |
defparam dout_3_4_.lut_mask="33f0"; |
defparam dout_3_4_.synch_mode="off"; |
defparam dout_3_4_.sum_lutc_input="datac"; |
// @7:129 |
cyclone_lcell dout_3_a_4_ ( |
.combout(dout_3_a[4]), |
.dataa(VCC), |
.datab(fsr[4]), |
.datac(status[4]), |
.datad(dout8), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout_3_a_4_.operation_mode="normal"; |
defparam dout_3_a_4_.output_mode="comb_only"; |
defparam dout_3_a_4_.lut_mask="0f33"; |
defparam dout_3_a_4_.synch_mode="off"; |
defparam dout_3_a_4_.sum_lutc_input="datac"; |
// @7:133 |
cyclone_lcell dout10_2_cZ ( |
.combout(dout10_2), |
.dataa(VCC), |
.datab(VCC), |
.datac(w_ek_r_3), |
.datad(w_ek_r_2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam dout10_2_cZ.operation_mode="normal"; |
defparam dout10_2_cZ.output_mode="comb_only"; |
defparam dout10_2_cZ.lut_mask="000f"; |
defparam dout10_2_cZ.synch_mode="off"; |
defparam dout10_2_cZ.sum_lutc_input="datac"; |
//@7:133 |
//@7:133 |
// @7:58 |
ram128x8 i_reg_file ( |
.alt_ram_q_7(alt_ram_q[7]), |
.alt_ram_q_6(alt_ram_q[6]), |
.alt_ram_q_5(alt_ram_q[5]), |
.alt_ram_q_4(alt_ram_q[4]), |
.alt_ram_q_3(alt_ram_q[3]), |
.alt_ram_q_2(alt_ram_q[2]), |
.alt_ram_q_1(alt_ram_q[1]), |
.alt_ram_q_0(alt_ram_q[0]), |
.w_ins_4(w_ins_4), |
.w_ins_3(w_ins_3), |
.w_ins_2(w_ins_2), |
.w_ins_1(w_ins_1), |
.w_ins_0(w_ins_0), |
.fsr_1(fsr[6]), |
.fsr_0(fsr[5]), |
.w_ek_r_4(w_ek_r_4), |
.w_ek_r_3(w_ek_r_3), |
.w_ek_r_2(w_ek_r_2), |
.w_ek_r_1(w_ek_r_1), |
.w_ek_r_0(w_ek_r_0), |
.w_alu_res_1_6_2(w_alu_res_1_6_2), |
.w_alu_res_1_6_1(w_alu_res_1_6_1), |
.w_alu_res_1_6_0(w_alu_res_1_6_0), |
.w_alu_res_1_3_0(w_alu_res_1_3_0), |
.w_alu_res_1_1_0(w_alu_res_1_1_0), |
.w_alu_res_1_0_2(w_alu_res_1_0_2), |
.w_alu_res_1_0_1(w_alu_res_1_0_1), |
.w_alu_res_1_0_0(w_alu_res_1_0_0), |
.clk_c(clk_c), |
.w_mem_wr_r(w_mem_wr_r) |
); |
assign rst_i_i_i = ~ rst_i_i; |
endmodule /* wb_mem_man */ |
|
// VQM4.1+ |
module altsyncram_Z2 ( |
address_a, |
clock0, |
q_a, |
q_b |
); |
input [6:0] address_a ; |
input clock0 ; |
output [7:0] q_a ; |
output [0:0] q_b ; |
altsyncram U1 ( |
.address_a(address_a), |
.clock0(clock0), |
.q_a(q_a), |
.q_b(q_b) |
); |
defparam U1.lpm_hint = "ENABLE_RUNTIME_MOD=NO"; |
defparam U1.intended_device_family = "Cyclone"; |
defparam U1.init_file = "init_file.mif"; |
defparam U1.operation_mode = "ROM"; |
defparam U1.width_byteena_a = 1; |
defparam U1.outdata_aclr_a = "NONE"; |
defparam U1.address_aclr_a = "NONE"; |
defparam U1.outdata_reg_a = "UNREGISTERED"; |
defparam U1.numwords_a = 128; |
defparam U1.widthad_a = 7; |
defparam U1.width_a = 8; |
endmodule /* altsyncram_Z2 */ |
|
// VQM4.1+ |
module rom128x12 ( |
w_ins_7, |
w_ins_6, |
w_ins_4, |
w_ins_3, |
w_ins_2, |
w_ins_1, |
w_ins_0, |
sclrsclrw_pc_nxt_0_0_a2_x_6, |
sclrsclrw_pc_nxt_0_0_a2_x_5, |
sclrsclrw_pc_nxt_0_0_a2_x_4, |
sclrsclrw_pc_nxt_0_0_a2_x_3, |
sclrsclrw_pc_nxt_0_0_a2_x_2, |
sclrsclrw_pc_nxt_0_0_a2_x_1, |
sclrsclrw_pc_nxt_0_0_a2_x_0, |
w_mem_wr, |
clk_c |
); |
output w_ins_7 ; |
output w_ins_6 ; |
output w_ins_4 ; |
output w_ins_3 ; |
output w_ins_2 ; |
output w_ins_1 ; |
output w_ins_0 ; |
input sclrsclrw_pc_nxt_0_0_a2_x_6 ; |
input sclrsclrw_pc_nxt_0_0_a2_x_5 ; |
input sclrsclrw_pc_nxt_0_0_a2_x_4 ; |
input sclrsclrw_pc_nxt_0_0_a2_x_3 ; |
input sclrsclrw_pc_nxt_0_0_a2_x_2 ; |
input sclrsclrw_pc_nxt_0_0_a2_x_1 ; |
input sclrsclrw_pc_nxt_0_0_a2_x_0 ; |
output w_mem_wr ; |
input clk_c ; |
wire w_ins_7 ; |
wire w_ins_6 ; |
wire w_ins_4 ; |
wire w_ins_3 ; |
wire w_ins_2 ; |
wire w_ins_1 ; |
wire w_ins_0 ; |
wire sclrsclrw_pc_nxt_0_0_a2_x_6 ; |
wire sclrsclrw_pc_nxt_0_0_a2_x_5 ; |
wire sclrsclrw_pc_nxt_0_0_a2_x_4 ; |
wire sclrsclrw_pc_nxt_0_0_a2_x_3 ; |
wire sclrsclrw_pc_nxt_0_0_a2_x_2 ; |
wire sclrsclrw_pc_nxt_0_0_a2_x_1 ; |
wire sclrsclrw_pc_nxt_0_0_a2_x_0 ; |
wire w_mem_wr ; |
wire clk_c ; |
wire [0:0] q_b; |
wire NC0 ; |
wire NC1 ; |
wire NC2 ; |
wire NC3 ; |
wire NC4 ; |
wire NC5 ; |
wire NC6 ; |
wire NC7 ; |
wire NC8 ; |
wire NC9 ; |
wire NC10 ; |
wire NC11 ; |
wire NC12 ; |
wire NC13 ; |
wire NC14 ; |
wire NC15 ; |
wire NC16 ; |
wire NC17 ; |
wire NC18 ; |
wire NC19 ; |
wire NC20 ; |
wire NC21 ; |
wire GND ; |
wire VCC ; |
assign VCC = 1'b1; |
assign GND = 1'b0; |
// @18:54 |
altsyncram_Z2 altsyncram_component_Z ( |
.address_a({sclrsclrw_pc_nxt_0_0_a2_x_6, sclrsclrw_pc_nxt_0_0_a2_x_5, |
sclrsclrw_pc_nxt_0_0_a2_x_4, sclrsclrw_pc_nxt_0_0_a2_x_3, sclrsclrw_pc_nxt_0_0_a2_x_2, |
sclrsclrw_pc_nxt_0_0_a2_x_1, sclrsclrw_pc_nxt_0_0_a2_x_0}), |
.clock0(clk_c), |
.q_a({w_ins_7, w_ins_6, w_mem_wr, w_ins_4, w_ins_3, w_ins_2, w_ins_1, |
w_ins_0}), |
.q_b(q_b[0]) |
); |
endmodule /* rom128x12 */ |
|
// VQM4.1+ |
module pram ( |
sclrsclrw_pc_nxt_0_0_a2_x_0, |
sclrsclrw_pc_nxt_0_0_a2_x_1, |
sclrsclrw_pc_nxt_0_0_a2_x_2, |
sclrsclrw_pc_nxt_0_0_a2_x_3, |
sclrsclrw_pc_nxt_0_0_a2_x_4, |
sclrsclrw_pc_nxt_0_0_a2_x_5, |
sclrsclrw_pc_nxt_0_0_a2_x_6, |
w_ins_0, |
w_ins_1, |
w_ins_2, |
w_ins_3, |
w_ins_4, |
w_ins_6, |
w_ins_7, |
clk_c, |
w_mem_wr |
); |
input sclrsclrw_pc_nxt_0_0_a2_x_0 ; |
input sclrsclrw_pc_nxt_0_0_a2_x_1 ; |
input sclrsclrw_pc_nxt_0_0_a2_x_2 ; |
input sclrsclrw_pc_nxt_0_0_a2_x_3 ; |
input sclrsclrw_pc_nxt_0_0_a2_x_4 ; |
input sclrsclrw_pc_nxt_0_0_a2_x_5 ; |
input sclrsclrw_pc_nxt_0_0_a2_x_6 ; |
output w_ins_0 ; |
output w_ins_1 ; |
output w_ins_2 ; |
output w_ins_3 ; |
output w_ins_4 ; |
output w_ins_6 ; |
output w_ins_7 ; |
input clk_c ; |
output w_mem_wr ; |
wire sclrsclrw_pc_nxt_0_0_a2_x_0 ; |
wire sclrsclrw_pc_nxt_0_0_a2_x_1 ; |
wire sclrsclrw_pc_nxt_0_0_a2_x_2 ; |
wire sclrsclrw_pc_nxt_0_0_a2_x_3 ; |
wire sclrsclrw_pc_nxt_0_0_a2_x_4 ; |
wire sclrsclrw_pc_nxt_0_0_a2_x_5 ; |
wire sclrsclrw_pc_nxt_0_0_a2_x_6 ; |
wire w_ins_0 ; |
wire w_ins_1 ; |
wire w_ins_2 ; |
wire w_ins_3 ; |
wire w_ins_4 ; |
wire w_ins_6 ; |
wire w_ins_7 ; |
wire clk_c ; |
wire w_mem_wr ; |
wire GND ; |
wire VCC ; |
assign VCC = 1'b1; |
assign GND = 1'b0; |
// @9:23 |
rom128x12 i_alt_ram ( |
.w_ins_7(w_ins_7), |
.w_ins_6(w_ins_6), |
.w_ins_4(w_ins_4), |
.w_ins_3(w_ins_3), |
.w_ins_2(w_ins_2), |
.w_ins_1(w_ins_1), |
.w_ins_0(w_ins_0), |
.sclrsclrw_pc_nxt_0_0_a2_x_6(sclrsclrw_pc_nxt_0_0_a2_x_6), |
.sclrsclrw_pc_nxt_0_0_a2_x_5(sclrsclrw_pc_nxt_0_0_a2_x_5), |
.sclrsclrw_pc_nxt_0_0_a2_x_4(sclrsclrw_pc_nxt_0_0_a2_x_4), |
.sclrsclrw_pc_nxt_0_0_a2_x_3(sclrsclrw_pc_nxt_0_0_a2_x_3), |
.sclrsclrw_pc_nxt_0_0_a2_x_2(sclrsclrw_pc_nxt_0_0_a2_x_2), |
.sclrsclrw_pc_nxt_0_0_a2_x_1(sclrsclrw_pc_nxt_0_0_a2_x_1), |
.sclrsclrw_pc_nxt_0_0_a2_x_0(sclrsclrw_pc_nxt_0_0_a2_x_0), |
.w_mem_wr(w_mem_wr), |
.clk_c(clk_c) |
); |
endmodule /* pram */ |
|
// VQM4.1+ |
module ClaiRISC_core ( |
clk, |
rst, |
in0, |
in1, |
out0, |
out1 |
); |
input clk ; |
input rst ; |
input [7:0] in0 ; |
input [7:0] in1 ; |
output [7:0] out0 /* synthesis syn_tristate = 1 */; |
output [7:0] out1 /* synthesis syn_tristate = 1 */; |
wire clk ; |
wire rst ; |
wire [8:1] un87_w_alu_res; |
wire [6:0] un87_w_alu_res_cout; |
wire [6:0] sclrsclrw_pc_nxt_0_0_a2_x; |
wire [6:0] w_pc; |
wire [6:1] un4_w_pc_nxt; |
wire [4:0] w_ek_r; |
wire [7:0] w_ins; |
wire [7:0] w_wreg; |
wire [7:5] w_alu_res_1_6_1; |
wire [7:5] w_alu_res_1_6_a; |
wire [4:4] w_alu_res_1_3_1; |
wire [4:4] w_alu_res_1_3_a; |
wire [3:3] w_alu_res_1_1_1; |
wire [3:3] w_alu_res_1_1_a; |
wire [2:0] w_alu_res_1_0_a2_0; |
wire [2:2] w_alu_res_1_0_0; |
wire [1:0] w_alu_res_1_0_a2_2_0; |
wire [7:0] mem_man_dout; |
wire [2:0] w_alu_res_1_0_a2_1; |
wire [2:0] w_alu_res_1_0; |
wire [4:0] w_alu_op_r; |
wire [2:2] w_alu_op_0_0_o2_0_a2_0; |
wire [7:5] w_alu_res_1_6; |
wire [4:4] w_alu_res_1_3; |
wire [3:3] w_alu_res_1_1; |
wire [1:0] w_alu_res_1_0_a2_0_a; |
wire [2:0] w_alu_res_1_11_i_1; |
wire [2:1] w_alu_res_1_11_i_0; |
wire [1:1] w_alu_res_1_11_i_a2_0; |
wire [0:0] w_alu_res_1_0_a3_2; |
wire [7:3] w_alu_res_1_5; |
wire [7:2] w_alu_res_1_4; |
wire [0:0] w_alu_res_1_0_a3_1; |
wire [2:0] w_alu_res_1_11_i_1_a; |
wire [7:1] un74_w_alu_res; |
wire [0:0] w_alu_res_1_11_i_x3; |
wire [7:5] w_alu_res_1_6_1_a; |
wire [3:3] w_alu_res_1_1_a3_1; |
wire [3:3] w_alu_res_1_1_1_a; |
wire [4:4] w_alu_res_1_3_1_a; |
wire [2:1] w_alu_res_1_11_i_0_a; |
wire [2:0] w_alu_res_1_0_a2_1_a; |
wire [0:0] w_alu_res_1_0_a3_1_a; |
wire [0:0] w_alu_res_1_0_a3_2_a; |
wire [2:2] w_alu_op_0_0_o2_0_a2_0_a; |
wire [4:0] un4_w_pc_nxt_cout; |
wire [5:0] un74_w_alu_res_cout; |
wire [7:0] in1_c; |
wire [7:0] in0_c; |
wire [7:0] mem_man_out1; |
wire [7:0] mem_man_out0; |
wire VCC ; |
wire GND ; |
wire rst_i_i ; |
wire rst_c ; |
wire un11_w_alu_res_carry_7 ; |
wire un11_w_alu_res_add7_cout ; |
wire clk_c ; |
wire w_c_2mem_i_a3 ; |
wire un11_w_alu_res_add7 ; |
wire w_w_wr_r ; |
wire un11_w_alu_res_add6 ; |
wire un11_w_alu_res_add5 ; |
wire un11_w_alu_res_add4 ; |
wire un11_w_alu_res_add3 ; |
wire w_mem_wr ; |
wire w_z_wr_r ; |
wire w_mem_wr_r ; |
wire w_c_wr_r ; |
wire un11_w_alu_res_add0 ; |
wire un11_w_alu_res_add2 ; |
wire un11_w_alu_res_add1 ; |
wire w_alu_res_1_sn_m7_0_a2 ; |
wire w_alu_res142_0_3_0_a2 ; |
wire w_alu_res_add2 ; |
wire G_271 ; |
wire mem_man_write_out0_0_a3_0_o2 ; |
wire w_alu_res_add0 ; |
wire G_279 ; |
wire w_z_0_a2 ; |
wire w_z_0_a2_a ; |
wire w_z_0_a2_1 ; |
wire G_287 ; |
wire G_287_a ; |
wire w_c_2mem_i_a2_0_0 ; |
wire w_alu_res_add1 ; |
wire w_alu_res_add3 ; |
wire w_alu_res_add6 ; |
wire w_alu_res_add7 ; |
wire N_796 ; |
wire w_alu_res_add5 ; |
wire w_alu_res_add4 ; |
wire un11_w_alu_res_carry_6 ; |
wire un11_w_alu_res_carry_5 ; |
wire un11_w_alu_res_carry_4 ; |
wire un11_w_alu_res_carry_3 ; |
wire un11_w_alu_res_carry_2 ; |
wire un11_w_alu_res_carry_1 ; |
wire un11_w_alu_res_carry_0 ; |
wire w_alu_res_carry_6 ; |
wire w_alu_res_carry_5 ; |
wire w_alu_res_carry_4 ; |
wire w_alu_res_carry_3 ; |
wire w_alu_res_carry_2 ; |
wire w_alu_res_carry_1 ; |
wire w_alu_res_carry_0 ; |
wire N_1002 ; |
wire N_996 ; |
wire N_995 ; |
wire N_994 ; |
wire N_586 ; |
wire N_585 ; |
wire N_584 ; |
wire N_583 ; |
wire N_375 ; |
wire N_374 ; |
wire N_373 ; |
wire N_372 ; |
wire N_371 ; |
wire N_370 ; |
wire N_369 ; |
wire N_368 ; |
wire N_365 ; |
wire N_364 ; |
wire N_363 ; |
wire N_1 ; |
wire N_2 ; |
wire N_3 ; |
//@1:1 |
assign VCC = 1'b1; |
//@1:1 |
assign GND = 1'b0; |
assign rst_i_i = ~ rst_c; |
cyclone_lcell un11_w_alu_res_add7_term ( |
.combout(un11_w_alu_res_carry_7), |
.dataa(VCC), |
.datab(VCC), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(un11_w_alu_res_add7_cout), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un11_w_alu_res_add7_term.cin_used="true"; |
defparam un11_w_alu_res_add7_term.operation_mode="normal"; |
defparam un11_w_alu_res_add7_term.output_mode="comb_only"; |
defparam un11_w_alu_res_add7_term.lut_mask="f0f0"; |
defparam un11_w_alu_res_add7_term.synch_mode="off"; |
defparam un11_w_alu_res_add7_term.sum_lutc_input="cin"; |
cyclone_lcell un87_w_alu_res_term_6_ ( |
.combout(un87_w_alu_res[8]), |
.dataa(VCC), |
.datab(VCC), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(un87_w_alu_res_cout[6]), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un87_w_alu_res_term_6_.cin_used="true"; |
defparam un87_w_alu_res_term_6_.operation_mode="normal"; |
defparam un87_w_alu_res_term_6_.output_mode="comb_only"; |
defparam un87_w_alu_res_term_6_.lut_mask="f0f0"; |
defparam un87_w_alu_res_term_6_.synch_mode="off"; |
defparam un87_w_alu_res_term_6_.sum_lutc_input="cin"; |
// @11:52 |
cyclone_lcell w_pc_6__Z ( |
.combout(sclrsclrw_pc_nxt_0_0_a2_x[6]), |
.regout(w_pc[6]), |
.clk(clk_c), |
.dataa(rst_c), |
.datab(un4_w_pc_nxt[6]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_pc_6__Z.operation_mode="normal"; |
defparam w_pc_6__Z.output_mode="reg_and_comb"; |
defparam w_pc_6__Z.lut_mask="4444"; |
defparam w_pc_6__Z.synch_mode="off"; |
defparam w_pc_6__Z.sum_lutc_input="datac"; |
// @11:52 |
cyclone_lcell w_pc_5__Z ( |
.combout(sclrsclrw_pc_nxt_0_0_a2_x[5]), |
.regout(w_pc[5]), |
.clk(clk_c), |
.dataa(rst_c), |
.datab(un4_w_pc_nxt[5]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_pc_5__Z.operation_mode="normal"; |
defparam w_pc_5__Z.output_mode="reg_and_comb"; |
defparam w_pc_5__Z.lut_mask="4444"; |
defparam w_pc_5__Z.synch_mode="off"; |
defparam w_pc_5__Z.sum_lutc_input="datac"; |
// @11:52 |
cyclone_lcell w_pc_4__Z ( |
.combout(sclrsclrw_pc_nxt_0_0_a2_x[4]), |
.regout(w_pc[4]), |
.clk(clk_c), |
.dataa(rst_c), |
.datab(un4_w_pc_nxt[4]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_pc_4__Z.operation_mode="normal"; |
defparam w_pc_4__Z.output_mode="reg_and_comb"; |
defparam w_pc_4__Z.lut_mask="4444"; |
defparam w_pc_4__Z.synch_mode="off"; |
defparam w_pc_4__Z.sum_lutc_input="datac"; |
// @11:52 |
cyclone_lcell w_pc_3__Z ( |
.combout(sclrsclrw_pc_nxt_0_0_a2_x[3]), |
.regout(w_pc[3]), |
.clk(clk_c), |
.dataa(rst_c), |
.datab(un4_w_pc_nxt[3]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_pc_3__Z.operation_mode="normal"; |
defparam w_pc_3__Z.output_mode="reg_and_comb"; |
defparam w_pc_3__Z.lut_mask="4444"; |
defparam w_pc_3__Z.synch_mode="off"; |
defparam w_pc_3__Z.sum_lutc_input="datac"; |
// @11:52 |
cyclone_lcell w_pc_2__Z ( |
.combout(sclrsclrw_pc_nxt_0_0_a2_x[2]), |
.regout(w_pc[2]), |
.clk(clk_c), |
.dataa(rst_c), |
.datab(un4_w_pc_nxt[2]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_pc_2__Z.operation_mode="normal"; |
defparam w_pc_2__Z.output_mode="reg_and_comb"; |
defparam w_pc_2__Z.lut_mask="4444"; |
defparam w_pc_2__Z.synch_mode="off"; |
defparam w_pc_2__Z.sum_lutc_input="datac"; |
// @11:52 |
cyclone_lcell w_pc_1__Z ( |
.combout(sclrsclrw_pc_nxt_0_0_a2_x[1]), |
.regout(w_pc[1]), |
.clk(clk_c), |
.dataa(rst_c), |
.datab(un4_w_pc_nxt[1]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_pc_1__Z.operation_mode="normal"; |
defparam w_pc_1__Z.output_mode="reg_and_comb"; |
defparam w_pc_1__Z.lut_mask="4444"; |
defparam w_pc_1__Z.synch_mode="off"; |
defparam w_pc_1__Z.sum_lutc_input="datac"; |
// @11:52 |
cyclone_lcell w_pc_0__Z ( |
.combout(sclrsclrw_pc_nxt_0_0_a2_x[0]), |
.regout(w_pc[0]), |
.clk(clk_c), |
.dataa(rst_c), |
.datab(w_pc[0]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_pc_0__Z.operation_mode="normal"; |
defparam w_pc_0__Z.output_mode="reg_and_comb"; |
defparam w_pc_0__Z.lut_mask="1111"; |
defparam w_pc_0__Z.synch_mode="off"; |
defparam w_pc_0__Z.sum_lutc_input="datac"; |
// @11:138 |
cyclone_lcell w_ek_r_4__Z ( |
.regout(w_ek_r[4]), |
.clk(clk_c), |
.dataa(VCC), |
.datab(VCC), |
.datac(VCC), |
.datad(w_ins[4]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_ek_r_4__Z.operation_mode="normal"; |
defparam w_ek_r_4__Z.output_mode="reg_only"; |
defparam w_ek_r_4__Z.lut_mask="ff00"; |
defparam w_ek_r_4__Z.synch_mode="off"; |
defparam w_ek_r_4__Z.sum_lutc_input="datac"; |
// @11:138 |
cyclone_lcell w_ek_r_3__Z ( |
.regout(w_ek_r[3]), |
.clk(clk_c), |
.dataa(VCC), |
.datab(VCC), |
.datac(VCC), |
.datad(w_ins[3]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_ek_r_3__Z.operation_mode="normal"; |
defparam w_ek_r_3__Z.output_mode="reg_only"; |
defparam w_ek_r_3__Z.lut_mask="ff00"; |
defparam w_ek_r_3__Z.synch_mode="off"; |
defparam w_ek_r_3__Z.sum_lutc_input="datac"; |
// @11:138 |
cyclone_lcell w_ek_r_2__Z ( |
.regout(w_ek_r[2]), |
.clk(clk_c), |
.dataa(VCC), |
.datab(VCC), |
.datac(VCC), |
.datad(w_ins[2]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_ek_r_2__Z.operation_mode="normal"; |
defparam w_ek_r_2__Z.output_mode="reg_only"; |
defparam w_ek_r_2__Z.lut_mask="ff00"; |
defparam w_ek_r_2__Z.synch_mode="off"; |
defparam w_ek_r_2__Z.sum_lutc_input="datac"; |
// @11:138 |
cyclone_lcell w_ek_r_1__Z ( |
.regout(w_ek_r[1]), |
.clk(clk_c), |
.dataa(VCC), |
.datab(VCC), |
.datac(VCC), |
.datad(w_ins[1]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_ek_r_1__Z.operation_mode="normal"; |
defparam w_ek_r_1__Z.output_mode="reg_only"; |
defparam w_ek_r_1__Z.lut_mask="ff00"; |
defparam w_ek_r_1__Z.synch_mode="off"; |
defparam w_ek_r_1__Z.sum_lutc_input="datac"; |
// @11:138 |
cyclone_lcell w_ek_r_0__Z ( |
.regout(w_ek_r[0]), |
.clk(clk_c), |
.dataa(VCC), |
.datab(VCC), |
.datac(VCC), |
.datad(w_ins[0]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_ek_r_0__Z.operation_mode="normal"; |
defparam w_ek_r_0__Z.output_mode="reg_only"; |
defparam w_ek_r_0__Z.lut_mask="ff00"; |
defparam w_ek_r_0__Z.synch_mode="off"; |
defparam w_ek_r_0__Z.sum_lutc_input="datac"; |
// @11:128 |
cyclone_lcell w_wreg_7__Z ( |
.regout(w_wreg[7]), |
.clk(clk_c), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add7), |
.datac(w_alu_res_1_6_1[7]), |
.datad(w_alu_res_1_6_a[7]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(w_w_wr_r), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_wreg_7__Z.operation_mode="normal"; |
defparam w_wreg_7__Z.output_mode="reg_only"; |
defparam w_wreg_7__Z.lut_mask="f8ff"; |
defparam w_wreg_7__Z.synch_mode="off"; |
defparam w_wreg_7__Z.sum_lutc_input="datac"; |
// @11:128 |
cyclone_lcell w_wreg_6__Z ( |
.regout(w_wreg[6]), |
.clk(clk_c), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add6), |
.datac(w_alu_res_1_6_1[6]), |
.datad(w_alu_res_1_6_a[6]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(w_w_wr_r), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_wreg_6__Z.operation_mode="normal"; |
defparam w_wreg_6__Z.output_mode="reg_only"; |
defparam w_wreg_6__Z.lut_mask="f8ff"; |
defparam w_wreg_6__Z.synch_mode="off"; |
defparam w_wreg_6__Z.sum_lutc_input="datac"; |
// @11:128 |
cyclone_lcell w_wreg_5__Z ( |
.regout(w_wreg[5]), |
.clk(clk_c), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add5), |
.datac(w_alu_res_1_6_1[5]), |
.datad(w_alu_res_1_6_a[5]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(w_w_wr_r), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_wreg_5__Z.operation_mode="normal"; |
defparam w_wreg_5__Z.output_mode="reg_only"; |
defparam w_wreg_5__Z.lut_mask="f8ff"; |
defparam w_wreg_5__Z.synch_mode="off"; |
defparam w_wreg_5__Z.sum_lutc_input="datac"; |
// @11:128 |
cyclone_lcell w_wreg_4__Z ( |
.regout(w_wreg[4]), |
.clk(clk_c), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add4), |
.datac(w_alu_res_1_3_1[4]), |
.datad(w_alu_res_1_3_a[4]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(w_w_wr_r), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_wreg_4__Z.operation_mode="normal"; |
defparam w_wreg_4__Z.output_mode="reg_only"; |
defparam w_wreg_4__Z.lut_mask="f8ff"; |
defparam w_wreg_4__Z.synch_mode="off"; |
defparam w_wreg_4__Z.sum_lutc_input="datac"; |
// @11:128 |
cyclone_lcell w_wreg_3__Z ( |
.regout(w_wreg[3]), |
.clk(clk_c), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add3), |
.datac(w_alu_res_1_1_1[3]), |
.datad(w_alu_res_1_1_a[3]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(w_w_wr_r), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_wreg_3__Z.operation_mode="normal"; |
defparam w_wreg_3__Z.output_mode="reg_only"; |
defparam w_wreg_3__Z.lut_mask="f8ff"; |
defparam w_wreg_3__Z.synch_mode="off"; |
defparam w_wreg_3__Z.sum_lutc_input="datac"; |
// @11:128 |
cyclone_lcell w_wreg_2__Z ( |
.regout(w_wreg[2]), |
.clk(clk_c), |
.dataa(VCC), |
.datab(VCC), |
.datac(w_alu_res_1_0_a2_0[2]), |
.datad(w_alu_res_1_0_0[2]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(w_w_wr_r), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_wreg_2__Z.operation_mode="normal"; |
defparam w_wreg_2__Z.output_mode="reg_only"; |
defparam w_wreg_2__Z.lut_mask="fff0"; |
defparam w_wreg_2__Z.synch_mode="off"; |
defparam w_wreg_2__Z.sum_lutc_input="datac"; |
// @11:128 |
cyclone_lcell w_wreg_1__Z ( |
.regout(w_wreg[1]), |
.clk(clk_c), |
.dataa(w_alu_res_1_0_a2_2_0[1]), |
.datab(mem_man_dout[1]), |
.datac(w_alu_res_1_0_a2_1[1]), |
.datad(w_alu_res_1_0_a2_0[1]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(w_w_wr_r), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_wreg_1__Z.operation_mode="normal"; |
defparam w_wreg_1__Z.output_mode="reg_only"; |
defparam w_wreg_1__Z.lut_mask="fff8"; |
defparam w_wreg_1__Z.synch_mode="off"; |
defparam w_wreg_1__Z.sum_lutc_input="datac"; |
// @11:128 |
cyclone_lcell w_wreg_0__Z ( |
.regout(w_wreg[0]), |
.clk(clk_c), |
.dataa(VCC), |
.datab(VCC), |
.datac(VCC), |
.datad(w_alu_res_1_0[0]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(w_w_wr_r), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_wreg_0__Z.operation_mode="normal"; |
defparam w_wreg_0__Z.output_mode="reg_only"; |
defparam w_wreg_0__Z.lut_mask="ff00"; |
defparam w_wreg_0__Z.synch_mode="off"; |
defparam w_wreg_0__Z.sum_lutc_input="datac"; |
// @11:102 |
cyclone_lcell w_alu_op_r_4__Z ( |
.regout(w_alu_op_r[4]), |
.clk(clk_c), |
.dataa(VCC), |
.datab(w_mem_wr), |
.datac(w_ins[7]), |
.datad(w_ins[6]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_op_r_4__Z.operation_mode="normal"; |
defparam w_alu_op_r_4__Z.output_mode="reg_only"; |
defparam w_alu_op_r_4__Z.lut_mask="000c"; |
defparam w_alu_op_r_4__Z.synch_mode="off"; |
defparam w_alu_op_r_4__Z.sum_lutc_input="datac"; |
// @11:102 |
cyclone_lcell w_alu_op_r_3__Z ( |
.regout(w_alu_op_r[3]), |
.clk(clk_c), |
.dataa(w_mem_wr), |
.datab(w_ins[7]), |
.datac(w_ins[6]), |
.datad(w_alu_op_0_0_o2_0_a2_0[2]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_op_r_3__Z.operation_mode="normal"; |
defparam w_alu_op_r_3__Z.output_mode="reg_only"; |
defparam w_alu_op_r_3__Z.lut_mask="ffe0"; |
defparam w_alu_op_r_3__Z.synch_mode="off"; |
defparam w_alu_op_r_3__Z.sum_lutc_input="datac"; |
// @11:102 |
cyclone_lcell w_alu_op_r_0__Z ( |
.regout(w_alu_op_r[0]), |
.clk(clk_c), |
.dataa(VCC), |
.datab(VCC), |
.datac(w_ins[7]), |
.datad(w_ins[6]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_op_r_0__Z.operation_mode="normal"; |
defparam w_alu_op_r_0__Z.output_mode="reg_only"; |
defparam w_alu_op_r_0__Z.lut_mask="f000"; |
defparam w_alu_op_r_0__Z.synch_mode="off"; |
defparam w_alu_op_r_0__Z.sum_lutc_input="datac"; |
// @11:112 |
cyclone_lcell w_z_wr_r_Z ( |
.regout(w_z_wr_r), |
.clk(clk_c), |
.dataa(w_mem_wr), |
.datab(w_ins[7]), |
.datac(w_ins[6]), |
.datad(w_alu_op_0_0_o2_0_a2_0[2]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_z_wr_r_Z.operation_mode="normal"; |
defparam w_z_wr_r_Z.output_mode="reg_only"; |
defparam w_z_wr_r_Z.lut_mask="ffec"; |
defparam w_z_wr_r_Z.synch_mode="off"; |
defparam w_z_wr_r_Z.sum_lutc_input="datac"; |
// @11:122 |
cyclone_lcell w_mem_wr_r_Z ( |
.regout(w_mem_wr_r), |
.clk(clk_c), |
.dataa(VCC), |
.datab(VCC), |
.datac(VCC), |
.datad(w_mem_wr), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_mem_wr_r_Z.operation_mode="normal"; |
defparam w_mem_wr_r_Z.output_mode="reg_only"; |
defparam w_mem_wr_r_Z.lut_mask="ff00"; |
defparam w_mem_wr_r_Z.synch_mode="off"; |
defparam w_mem_wr_r_Z.sum_lutc_input="datac"; |
// @11:116 |
cyclone_lcell w_c_wr_r_Z ( |
.regout(w_c_wr_r), |
.clk(clk_c), |
.dataa(VCC), |
.datab(VCC), |
.datac(w_ins[7]), |
.datad(w_ins[6]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_c_wr_r_Z.operation_mode="normal"; |
defparam w_c_wr_r_Z.output_mode="reg_only"; |
defparam w_c_wr_r_Z.lut_mask="00f0"; |
defparam w_c_wr_r_Z.synch_mode="off"; |
defparam w_c_wr_r_Z.sum_lutc_input="datac"; |
// @11:135 |
cyclone_lcell w_w_wr_r_Z ( |
.regout(w_w_wr_r), |
.clk(clk_c), |
.dataa(VCC), |
.datab(w_mem_wr), |
.datac(w_ins[7]), |
.datad(w_alu_op_0_0_o2_0_a2_0[2]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_w_wr_r_Z.operation_mode="normal"; |
defparam w_w_wr_r_Z.output_mode="reg_only"; |
defparam w_w_wr_r_Z.lut_mask="3330"; |
defparam w_w_wr_r_Z.synch_mode="off"; |
defparam w_w_wr_r_Z.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell retw_alu_res_1_6_7_ ( |
.combout(w_alu_res_1_6[7]), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add7), |
.datac(w_alu_res_1_6_1[7]), |
.datad(w_alu_res_1_6_a[7]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam retw_alu_res_1_6_7_.operation_mode="normal"; |
defparam retw_alu_res_1_6_7_.output_mode="comb_only"; |
defparam retw_alu_res_1_6_7_.lut_mask="f8ff"; |
defparam retw_alu_res_1_6_7_.synch_mode="off"; |
defparam retw_alu_res_1_6_7_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell retw_alu_res_1_6_0_6_ ( |
.combout(w_alu_res_1_6[6]), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add6), |
.datac(w_alu_res_1_6_1[6]), |
.datad(w_alu_res_1_6_a[6]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam retw_alu_res_1_6_0_6_.operation_mode="normal"; |
defparam retw_alu_res_1_6_0_6_.output_mode="comb_only"; |
defparam retw_alu_res_1_6_0_6_.lut_mask="f8ff"; |
defparam retw_alu_res_1_6_0_6_.synch_mode="off"; |
defparam retw_alu_res_1_6_0_6_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell retw_alu_res_1_6_0_5_ ( |
.combout(w_alu_res_1_6[5]), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add5), |
.datac(w_alu_res_1_6_1[5]), |
.datad(w_alu_res_1_6_a[5]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam retw_alu_res_1_6_0_5_.operation_mode="normal"; |
defparam retw_alu_res_1_6_0_5_.output_mode="comb_only"; |
defparam retw_alu_res_1_6_0_5_.lut_mask="f8ff"; |
defparam retw_alu_res_1_6_0_5_.synch_mode="off"; |
defparam retw_alu_res_1_6_0_5_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell retw_alu_res_1_3_0_4_ ( |
.combout(w_alu_res_1_3[4]), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add4), |
.datac(w_alu_res_1_3_1[4]), |
.datad(w_alu_res_1_3_a[4]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam retw_alu_res_1_3_0_4_.operation_mode="normal"; |
defparam retw_alu_res_1_3_0_4_.output_mode="comb_only"; |
defparam retw_alu_res_1_3_0_4_.lut_mask="f8ff"; |
defparam retw_alu_res_1_3_0_4_.synch_mode="off"; |
defparam retw_alu_res_1_3_0_4_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell retw_alu_res_1_1_0_3_ ( |
.combout(w_alu_res_1_1[3]), |
.dataa(w_c_2mem_i_a3), |
.datab(un11_w_alu_res_add3), |
.datac(w_alu_res_1_1_1[3]), |
.datad(w_alu_res_1_1_a[3]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam retw_alu_res_1_1_0_3_.operation_mode="normal"; |
defparam retw_alu_res_1_1_0_3_.output_mode="comb_only"; |
defparam retw_alu_res_1_1_0_3_.lut_mask="f8ff"; |
defparam retw_alu_res_1_1_0_3_.synch_mode="off"; |
defparam retw_alu_res_1_1_0_3_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell retw_alu_res_1_0_0_2_ ( |
.combout(w_alu_res_1_0[2]), |
.dataa(VCC), |
.datab(VCC), |
.datac(w_alu_res_1_0_a2_0[2]), |
.datad(w_alu_res_1_0_0[2]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam retw_alu_res_1_0_0_2_.operation_mode="normal"; |
defparam retw_alu_res_1_0_0_2_.output_mode="comb_only"; |
defparam retw_alu_res_1_0_0_2_.lut_mask="fff0"; |
defparam retw_alu_res_1_0_0_2_.synch_mode="off"; |
defparam retw_alu_res_1_0_0_2_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell retw_alu_res_1_0_0_1_ ( |
.combout(w_alu_res_1_0[1]), |
.dataa(w_alu_res_1_0_a2_2_0[1]), |
.datab(mem_man_dout[1]), |
.datac(w_alu_res_1_0_a2_0[1]), |
.datad(w_alu_res_1_0_a2_1[1]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam retw_alu_res_1_0_0_1_.operation_mode="normal"; |
defparam retw_alu_res_1_0_0_1_.output_mode="comb_only"; |
defparam retw_alu_res_1_0_0_1_.lut_mask="fff8"; |
defparam retw_alu_res_1_0_0_1_.synch_mode="off"; |
defparam retw_alu_res_1_0_0_1_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_0_a2_0_0_ ( |
.combout(w_alu_res_1_0_a2_0[0]), |
.dataa(w_alu_op_r[0]), |
.datab(w_alu_res_1_0_a2_0_a[0]), |
.datac(un11_w_alu_res_add0), |
.datad(w_alu_res_1_11_i_1[0]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_0_a2_0_0_.operation_mode="normal"; |
defparam w_alu_res_1_0_a2_0_0_.output_mode="comb_only"; |
defparam w_alu_res_1_0_a2_0_0_.lut_mask="00c8"; |
defparam w_alu_res_1_0_a2_0_0_.synch_mode="off"; |
defparam w_alu_res_1_0_a2_0_0_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_0_a2_0_a_0_ ( |
.combout(w_alu_res_1_0_a2_0_a[0]), |
.dataa(w_alu_op_r[4]), |
.datab(w_alu_op_r[0]), |
.datac(w_alu_op_r[3]), |
.datad(w_c_wr_r), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_0_a2_0_a_0_.operation_mode="normal"; |
defparam w_alu_res_1_0_a2_0_a_0_.output_mode="comb_only"; |
defparam w_alu_res_1_0_a2_0_a_0_.lut_mask="4140"; |
defparam w_alu_res_1_0_a2_0_a_0_.synch_mode="off"; |
defparam w_alu_res_1_0_a2_0_a_0_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_0_a2_0_2_ ( |
.combout(w_alu_res_1_0_a2_0[2]), |
.dataa(w_alu_op_r[0]), |
.datab(w_alu_res_1_0_a2_0_a[0]), |
.datac(un11_w_alu_res_add2), |
.datad(w_alu_res_1_11_i_1[2]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_0_a2_0_2_.operation_mode="normal"; |
defparam w_alu_res_1_0_a2_0_2_.output_mode="comb_only"; |
defparam w_alu_res_1_0_a2_0_2_.lut_mask="00c8"; |
defparam w_alu_res_1_0_a2_0_2_.synch_mode="off"; |
defparam w_alu_res_1_0_a2_0_2_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_0_a2_0_1_ ( |
.combout(w_alu_res_1_0_a2_0[1]), |
.dataa(w_alu_op_r[4]), |
.datab(w_alu_res_1_11_i_0[1]), |
.datac(w_alu_res_1_11_i_a2_0[1]), |
.datad(w_alu_res_1_0_a2_0_a[1]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_0_a2_0_1_.operation_mode="normal"; |
defparam w_alu_res_1_0_a2_0_1_.output_mode="comb_only"; |
defparam w_alu_res_1_0_a2_0_1_.lut_mask="0001"; |
defparam w_alu_res_1_0_a2_0_1_.synch_mode="off"; |
defparam w_alu_res_1_0_a2_0_1_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_0_a2_0_a_1_ ( |
.combout(w_alu_res_1_0_a2_0_a[1]), |
.dataa(w_alu_op_r[0]), |
.datab(w_alu_op_r[3]), |
.datac(w_c_wr_r), |
.datad(un11_w_alu_res_add1), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_0_a2_0_a_1_.operation_mode="normal"; |
defparam w_alu_res_1_0_a2_0_a_1_.output_mode="comb_only"; |
defparam w_alu_res_1_0_a2_0_a_1_.lut_mask="6777"; |
defparam w_alu_res_1_0_a2_0_a_1_.synch_mode="off"; |
defparam w_alu_res_1_0_a2_0_a_1_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_1_a_3_ ( |
.combout(w_alu_res_1_1_a[3]), |
.dataa(w_wreg[3]), |
.datab(w_alu_res_1_0_a3_2[0]), |
.datac(w_alu_res_1_sn_m7_0_a2), |
.datad(w_alu_res_1_5[3]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_1_a_3_.operation_mode="normal"; |
defparam w_alu_res_1_1_a_3_.output_mode="comb_only"; |
defparam w_alu_res_1_1_a_3_.lut_mask="737f"; |
defparam w_alu_res_1_1_a_3_.synch_mode="off"; |
defparam w_alu_res_1_1_a_3_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_3_a_4_ ( |
.combout(w_alu_res_1_3_a[4]), |
.dataa(w_alu_res_1_0_a3_2[0]), |
.datab(w_alu_res_1_sn_m7_0_a2), |
.datac(w_alu_res_1_4[4]), |
.datad(w_alu_res_1_5[4]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_3_a_4_.operation_mode="normal"; |
defparam w_alu_res_1_3_a_4_.output_mode="comb_only"; |
defparam w_alu_res_1_3_a_4_.lut_mask="5d7f"; |
defparam w_alu_res_1_3_a_4_.synch_mode="off"; |
defparam w_alu_res_1_3_a_4_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_6_a_5_ ( |
.combout(w_alu_res_1_6_a[5]), |
.dataa(w_alu_res_1_0_a3_2[0]), |
.datab(w_alu_res_1_sn_m7_0_a2), |
.datac(w_alu_res_1_4[5]), |
.datad(w_alu_res_1_5[5]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_6_a_5_.operation_mode="normal"; |
defparam w_alu_res_1_6_a_5_.output_mode="comb_only"; |
defparam w_alu_res_1_6_a_5_.lut_mask="5d7f"; |
defparam w_alu_res_1_6_a_5_.synch_mode="off"; |
defparam w_alu_res_1_6_a_5_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_6_a_6_ ( |
.combout(w_alu_res_1_6_a[6]), |
.dataa(w_wreg[6]), |
.datab(w_alu_res_1_0_a3_2[0]), |
.datac(w_alu_res_1_sn_m7_0_a2), |
.datad(w_alu_res_1_5[6]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_6_a_6_.operation_mode="normal"; |
defparam w_alu_res_1_6_a_6_.output_mode="comb_only"; |
defparam w_alu_res_1_6_a_6_.lut_mask="737f"; |
defparam w_alu_res_1_6_a_6_.synch_mode="off"; |
defparam w_alu_res_1_6_a_6_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_6_a_7_ ( |
.combout(w_alu_res_1_6_a[7]), |
.dataa(w_alu_res_1_0_a3_2[0]), |
.datab(w_alu_res_1_sn_m7_0_a2), |
.datac(w_alu_res_1_4[7]), |
.datad(w_alu_res_1_5[7]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_6_a_7_.operation_mode="normal"; |
defparam w_alu_res_1_6_a_7_.output_mode="comb_only"; |
defparam w_alu_res_1_6_a_7_.lut_mask="5d7f"; |
defparam w_alu_res_1_6_a_7_.synch_mode="off"; |
defparam w_alu_res_1_6_a_7_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_0_0_2_ ( |
.combout(w_alu_res_1_0_0[2]), |
.dataa(w_wreg[2]), |
.datab(w_alu_res_1_0_a3_1[0]), |
.datac(mem_man_dout[2]), |
.datad(w_alu_res_1_0_a2_1[2]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_0_0_2_.operation_mode="normal"; |
defparam w_alu_res_1_0_0_2_.output_mode="comb_only"; |
defparam w_alu_res_1_0_0_2_.lut_mask="ff80"; |
defparam w_alu_res_1_0_0_2_.synch_mode="off"; |
defparam w_alu_res_1_0_0_2_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_11_i_1_2_ ( |
.combout(w_alu_res_1_11_i_1[2]), |
.dataa(w_c_wr_r), |
.datab(w_alu_res_1_11_i_1_a[2]), |
.datac(w_alu_res_1_11_i_0[2]), |
.datad(un74_w_alu_res[2]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_11_i_1_2_.operation_mode="normal"; |
defparam w_alu_res_1_11_i_1_2_.output_mode="comb_only"; |
defparam w_alu_res_1_11_i_1_2_.lut_mask="f8f9"; |
defparam w_alu_res_1_11_i_1_2_.synch_mode="off"; |
defparam w_alu_res_1_11_i_1_2_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_11_i_1_a_2_ ( |
.combout(w_alu_res_1_11_i_1_a[2]), |
.dataa(w_alu_op_r[0]), |
.datab(w_alu_op_r[3]), |
.datac(w_c_wr_r), |
.datad(mem_man_dout[2]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_11_i_1_a_2_.operation_mode="normal"; |
defparam w_alu_res_1_11_i_1_a_2_.output_mode="comb_only"; |
defparam w_alu_res_1_11_i_1_a_2_.lut_mask="0787"; |
defparam w_alu_res_1_11_i_1_a_2_.synch_mode="off"; |
defparam w_alu_res_1_11_i_1_a_2_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_11_i_1_0_ ( |
.combout(w_alu_res_1_11_i_1[0]), |
.dataa(w_alu_op_r[0]), |
.datab(w_alu_op_r[3]), |
.datac(mem_man_dout[0]), |
.datad(w_alu_res_1_11_i_1_a[0]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_11_i_1_0_.operation_mode="normal"; |
defparam w_alu_res_1_11_i_1_0_.output_mode="comb_only"; |
defparam w_alu_res_1_11_i_1_0_.lut_mask="a208"; |
defparam w_alu_res_1_11_i_1_0_.synch_mode="off"; |
defparam w_alu_res_1_11_i_1_0_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_11_i_1_a_0_ ( |
.combout(w_alu_res_1_11_i_1_a[0]), |
.dataa(w_alu_op_r[3]), |
.datab(w_c_wr_r), |
.datac(mem_man_dout[1]), |
.datad(w_alu_res_1_11_i_x3[0]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_11_i_1_a_0_.operation_mode="normal"; |
defparam w_alu_res_1_11_i_1_a_0_.output_mode="comb_only"; |
defparam w_alu_res_1_11_i_1_a_0_.lut_mask="2637"; |
defparam w_alu_res_1_11_i_1_a_0_.synch_mode="off"; |
defparam w_alu_res_1_11_i_1_a_0_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_6_1_6_ ( |
.combout(w_alu_res_1_6_1[6]), |
.dataa(w_wreg[6]), |
.datab(w_alu_res_1_0_a3_1[0]), |
.datac(mem_man_dout[6]), |
.datad(w_alu_res_1_6_1_a[6]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_6_1_6_.operation_mode="normal"; |
defparam w_alu_res_1_6_1_6_.output_mode="comb_only"; |
defparam w_alu_res_1_6_1_6_.lut_mask="8ff0"; |
defparam w_alu_res_1_6_1_6_.synch_mode="off"; |
defparam w_alu_res_1_6_1_6_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_6_1_a_6_ ( |
.combout(w_alu_res_1_6_1_a[6]), |
.dataa(w_c_wr_r), |
.datab(w_alu_res_1_1_a3_1[3]), |
.datac(mem_man_dout[6]), |
.datad(un74_w_alu_res[6]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_6_1_a_6_.operation_mode="normal"; |
defparam w_alu_res_1_6_1_a_6_.output_mode="comb_only"; |
defparam w_alu_res_1_6_1_a_6_.lut_mask="3470"; |
defparam w_alu_res_1_6_1_a_6_.synch_mode="off"; |
defparam w_alu_res_1_6_1_a_6_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_1_1_3_ ( |
.combout(w_alu_res_1_1_1[3]), |
.dataa(w_wreg[3]), |
.datab(w_alu_res_1_0_a3_1[0]), |
.datac(mem_man_dout[3]), |
.datad(w_alu_res_1_1_1_a[3]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_1_1_3_.operation_mode="normal"; |
defparam w_alu_res_1_1_1_3_.output_mode="comb_only"; |
defparam w_alu_res_1_1_1_3_.lut_mask="8ff0"; |
defparam w_alu_res_1_1_1_3_.synch_mode="off"; |
defparam w_alu_res_1_1_1_3_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_1_1_a_3_ ( |
.combout(w_alu_res_1_1_1_a[3]), |
.dataa(w_c_wr_r), |
.datab(w_alu_res_1_1_a3_1[3]), |
.datac(mem_man_dout[3]), |
.datad(un74_w_alu_res[3]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_1_1_a_3_.operation_mode="normal"; |
defparam w_alu_res_1_1_1_a_3_.output_mode="comb_only"; |
defparam w_alu_res_1_1_1_a_3_.lut_mask="3470"; |
defparam w_alu_res_1_1_1_a_3_.synch_mode="off"; |
defparam w_alu_res_1_1_1_a_3_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_6_1_7_ ( |
.combout(w_alu_res_1_6_1[7]), |
.dataa(w_wreg[7]), |
.datab(w_alu_res_1_0_a3_1[0]), |
.datac(mem_man_dout[7]), |
.datad(w_alu_res_1_6_1_a[7]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_6_1_7_.operation_mode="normal"; |
defparam w_alu_res_1_6_1_7_.output_mode="comb_only"; |
defparam w_alu_res_1_6_1_7_.lut_mask="8ff0"; |
defparam w_alu_res_1_6_1_7_.synch_mode="off"; |
defparam w_alu_res_1_6_1_7_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_6_1_a_7_ ( |
.combout(w_alu_res_1_6_1_a[7]), |
.dataa(w_c_wr_r), |
.datab(w_alu_res_1_1_a3_1[3]), |
.datac(mem_man_dout[7]), |
.datad(un74_w_alu_res[7]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_6_1_a_7_.operation_mode="normal"; |
defparam w_alu_res_1_6_1_a_7_.output_mode="comb_only"; |
defparam w_alu_res_1_6_1_a_7_.lut_mask="3470"; |
defparam w_alu_res_1_6_1_a_7_.synch_mode="off"; |
defparam w_alu_res_1_6_1_a_7_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_6_1_5_ ( |
.combout(w_alu_res_1_6_1[5]), |
.dataa(w_wreg[5]), |
.datab(w_alu_res_1_0_a3_1[0]), |
.datac(mem_man_dout[5]), |
.datad(w_alu_res_1_6_1_a[5]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_6_1_5_.operation_mode="normal"; |
defparam w_alu_res_1_6_1_5_.output_mode="comb_only"; |
defparam w_alu_res_1_6_1_5_.lut_mask="8ff0"; |
defparam w_alu_res_1_6_1_5_.synch_mode="off"; |
defparam w_alu_res_1_6_1_5_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_6_1_a_5_ ( |
.combout(w_alu_res_1_6_1_a[5]), |
.dataa(w_c_wr_r), |
.datab(w_alu_res_1_1_a3_1[3]), |
.datac(mem_man_dout[5]), |
.datad(un74_w_alu_res[5]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_6_1_a_5_.operation_mode="normal"; |
defparam w_alu_res_1_6_1_a_5_.output_mode="comb_only"; |
defparam w_alu_res_1_6_1_a_5_.lut_mask="3470"; |
defparam w_alu_res_1_6_1_a_5_.synch_mode="off"; |
defparam w_alu_res_1_6_1_a_5_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_3_1_4_ ( |
.combout(w_alu_res_1_3_1[4]), |
.dataa(w_wreg[4]), |
.datab(w_alu_res_1_0_a3_1[0]), |
.datac(mem_man_dout[4]), |
.datad(w_alu_res_1_3_1_a[4]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_3_1_4_.operation_mode="normal"; |
defparam w_alu_res_1_3_1_4_.output_mode="comb_only"; |
defparam w_alu_res_1_3_1_4_.lut_mask="8ff0"; |
defparam w_alu_res_1_3_1_4_.synch_mode="off"; |
defparam w_alu_res_1_3_1_4_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_3_1_a_4_ ( |
.combout(w_alu_res_1_3_1_a[4]), |
.dataa(w_c_wr_r), |
.datab(w_alu_res_1_1_a3_1[3]), |
.datac(mem_man_dout[4]), |
.datad(un74_w_alu_res[4]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_3_1_a_4_.operation_mode="normal"; |
defparam w_alu_res_1_3_1_a_4_.output_mode="comb_only"; |
defparam w_alu_res_1_3_1_a_4_.lut_mask="3470"; |
defparam w_alu_res_1_3_1_a_4_.synch_mode="off"; |
defparam w_alu_res_1_3_1_a_4_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_11_i_0_2_ ( |
.combout(w_alu_res_1_11_i_0[2]), |
.dataa(w_wreg[2]), |
.datab(w_c_wr_r), |
.datac(mem_man_dout[2]), |
.datad(w_alu_res_1_11_i_0_a[2]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_11_i_0_2_.operation_mode="normal"; |
defparam w_alu_res_1_11_i_0_2_.output_mode="comb_only"; |
defparam w_alu_res_1_11_i_0_2_.lut_mask="ed00"; |
defparam w_alu_res_1_11_i_0_2_.synch_mode="off"; |
defparam w_alu_res_1_11_i_0_2_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_11_i_0_a_2_ ( |
.combout(w_alu_res_1_11_i_0_a[2]), |
.dataa(w_alu_op_r[0]), |
.datab(w_alu_op_r[3]), |
.datac(w_c_wr_r), |
.datad(mem_man_dout[3]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_11_i_0_a_2_.operation_mode="normal"; |
defparam w_alu_res_1_11_i_0_a_2_.output_mode="comb_only"; |
defparam w_alu_res_1_11_i_0_a_2_.lut_mask="0222"; |
defparam w_alu_res_1_11_i_0_a_2_.synch_mode="off"; |
defparam w_alu_res_1_11_i_0_a_2_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_11_i_0_1_ ( |
.combout(w_alu_res_1_11_i_0[1]), |
.dataa(VCC), |
.datab(w_alu_op_r[0]), |
.datac(w_alu_op_r[3]), |
.datad(w_alu_res_1_11_i_0_a[1]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_11_i_0_1_.operation_mode="normal"; |
defparam w_alu_res_1_11_i_0_1_.output_mode="comb_only"; |
defparam w_alu_res_1_11_i_0_1_.lut_mask="0c00"; |
defparam w_alu_res_1_11_i_0_1_.synch_mode="off"; |
defparam w_alu_res_1_11_i_0_1_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_11_i_0_a_1_ ( |
.combout(w_alu_res_1_11_i_0_a[1]), |
.dataa(w_wreg[1]), |
.datab(w_c_wr_r), |
.datac(mem_man_dout[2]), |
.datad(mem_man_dout[1]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_11_i_0_a_1_.operation_mode="normal"; |
defparam w_alu_res_1_11_i_0_a_1_.output_mode="comb_only"; |
defparam w_alu_res_1_11_i_0_a_1_.lut_mask="2e1d"; |
defparam w_alu_res_1_11_i_0_a_1_.synch_mode="off"; |
defparam w_alu_res_1_11_i_0_a_1_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_0_a2_1_2_ ( |
.combout(w_alu_res_1_0_a2_1[2]), |
.dataa(w_alu_res_1_0_a3_2[0]), |
.datab(w_alu_res_1_sn_m7_0_a2), |
.datac(w_alu_res_1_4[2]), |
.datad(w_alu_res_1_0_a2_1_a[2]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_0_a2_1_2_.operation_mode="normal"; |
defparam w_alu_res_1_0_a2_1_2_.output_mode="comb_only"; |
defparam w_alu_res_1_0_a2_1_2_.lut_mask="80a2"; |
defparam w_alu_res_1_0_a2_1_2_.synch_mode="off"; |
defparam w_alu_res_1_0_a2_1_2_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_0_a2_1_a_2_ ( |
.combout(w_alu_res_1_0_a2_1_a[2]), |
.dataa(VCC), |
.datab(w_alu_res142_0_3_0_a2), |
.datac(un87_w_alu_res[2]), |
.datad(w_alu_res_add2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_0_a2_1_a_2_.operation_mode="normal"; |
defparam w_alu_res_1_0_a2_1_a_2_.output_mode="comb_only"; |
defparam w_alu_res_1_0_a2_1_a_2_.lut_mask="0c3f"; |
defparam w_alu_res_1_0_a2_1_a_2_.synch_mode="off"; |
defparam w_alu_res_1_0_a2_1_a_2_.sum_lutc_input="datac"; |
cyclone_lcell G_271_cZ ( |
.combout(G_271), |
.dataa(rst_c), |
.datab(w_ek_r[2]), |
.datac(w_ek_r[0]), |
.datad(mem_man_write_out0_0_a3_0_o2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam G_271_cZ.operation_mode="normal"; |
defparam G_271_cZ.output_mode="comb_only"; |
defparam G_271_cZ.lut_mask="aaea"; |
defparam G_271_cZ.synch_mode="off"; |
defparam G_271_cZ.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_0_a2_1_0_ ( |
.combout(w_alu_res_1_0_a2_1[0]), |
.dataa(w_wreg[0]), |
.datab(w_alu_res_1_0_a3_2[0]), |
.datac(w_alu_res_1_sn_m7_0_a2), |
.datad(w_alu_res_1_0_a2_1_a[0]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_0_a2_1_0_.operation_mode="normal"; |
defparam w_alu_res_1_0_a2_1_0_.output_mode="comb_only"; |
defparam w_alu_res_1_0_a2_1_0_.lut_mask="8c80"; |
defparam w_alu_res_1_0_a2_1_0_.synch_mode="off"; |
defparam w_alu_res_1_0_a2_1_0_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_0_a2_1_a_0_ ( |
.combout(w_alu_res_1_0_a2_1_a[0]), |
.dataa(VCC), |
.datab(w_alu_res142_0_3_0_a2), |
.datac(mem_man_dout[0]), |
.datad(w_alu_res_add0), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_0_a2_1_a_0_.operation_mode="normal"; |
defparam w_alu_res_1_0_a2_1_a_0_.output_mode="comb_only"; |
defparam w_alu_res_1_0_a2_1_a_0_.lut_mask="3f0c"; |
defparam w_alu_res_1_0_a2_1_a_0_.synch_mode="off"; |
defparam w_alu_res_1_0_a2_1_a_0_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_0_a3_1_0_ ( |
.combout(w_alu_res_1_0_a3_1[0]), |
.dataa(VCC), |
.datab(w_alu_op_r[3]), |
.datac(w_alu_res_1_0_a3_1_a[0]), |
.datad(w_alu_res142_0_3_0_a2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_0_a3_1_0_.operation_mode="normal"; |
defparam w_alu_res_1_0_a3_1_0_.output_mode="comb_only"; |
defparam w_alu_res_1_0_a3_1_0_.lut_mask="0030"; |
defparam w_alu_res_1_0_a3_1_0_.synch_mode="off"; |
defparam w_alu_res_1_0_a3_1_0_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_0_a3_1_a_0_ ( |
.combout(w_alu_res_1_0_a3_1_a[0]), |
.dataa(VCC), |
.datab(w_alu_op_r[4]), |
.datac(w_alu_op_r[0]), |
.datad(w_c_wr_r), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_0_a3_1_a_0_.operation_mode="normal"; |
defparam w_alu_res_1_0_a3_1_a_0_.output_mode="comb_only"; |
defparam w_alu_res_1_0_a3_1_a_0_.lut_mask="3cc0"; |
defparam w_alu_res_1_0_a3_1_a_0_.synch_mode="off"; |
defparam w_alu_res_1_0_a3_1_a_0_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_11_i_a2_0_1_ ( |
.combout(w_alu_res_1_11_i_a2_0[1]), |
.dataa(w_alu_op_r[0]), |
.datab(w_c_wr_r), |
.datac(mem_man_dout[1]), |
.datad(un74_w_alu_res[1]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_11_i_a2_0_1_.operation_mode="normal"; |
defparam w_alu_res_1_11_i_a2_0_1_.output_mode="comb_only"; |
defparam w_alu_res_1_11_i_a2_0_1_.lut_mask="082a"; |
defparam w_alu_res_1_11_i_a2_0_1_.synch_mode="off"; |
defparam w_alu_res_1_11_i_a2_0_1_.sum_lutc_input="datac"; |
cyclone_lcell G_279_cZ ( |
.combout(G_279), |
.dataa(rst_c), |
.datab(w_ek_r[2]), |
.datac(w_ek_r[0]), |
.datad(mem_man_write_out0_0_a3_0_o2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam G_279_cZ.operation_mode="normal"; |
defparam G_279_cZ.output_mode="comb_only"; |
defparam G_279_cZ.lut_mask="aaae"; |
defparam G_279_cZ.synch_mode="off"; |
defparam G_279_cZ.sum_lutc_input="datac"; |
// @11:169 |
cyclone_lcell w_z_0_a2_cZ ( |
.combout(w_z_0_a2), |
.dataa(w_alu_res_1_6[6]), |
.datab(w_z_0_a2_a), |
.datac(w_alu_res_1_0[2]), |
.datad(w_z_0_a2_1), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_z_0_a2_cZ.operation_mode="normal"; |
defparam w_z_0_a2_cZ.output_mode="comb_only"; |
defparam w_z_0_a2_cZ.lut_mask="0400"; |
defparam w_z_0_a2_cZ.synch_mode="off"; |
defparam w_z_0_a2_cZ.sum_lutc_input="datac"; |
// @11:169 |
cyclone_lcell w_z_0_a2_a_cZ ( |
.combout(w_z_0_a2_a), |
.dataa(w_alu_res_1_0[0]), |
.datab(w_alu_res_1_0[1]), |
.datac(w_alu_res_1_6[7]), |
.datad(w_alu_res_1_6[5]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_z_0_a2_a_cZ.operation_mode="normal"; |
defparam w_z_0_a2_a_cZ.output_mode="comb_only"; |
defparam w_z_0_a2_a_cZ.lut_mask="0001"; |
defparam w_z_0_a2_a_cZ.synch_mode="off"; |
defparam w_z_0_a2_a_cZ.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_4_7_ ( |
.combout(w_alu_res_1_4[7]), |
.dataa(VCC), |
.datab(w_wreg[7]), |
.datac(w_alu_op_r[3]), |
.datad(mem_man_dout[6]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_4_7_.operation_mode="normal"; |
defparam w_alu_res_1_4_7_.output_mode="comb_only"; |
defparam w_alu_res_1_4_7_.lut_mask="fc0c"; |
defparam w_alu_res_1_4_7_.synch_mode="off"; |
defparam w_alu_res_1_4_7_.sum_lutc_input="datac"; |
cyclone_lcell G_287_cZ ( |
.combout(G_287), |
.dataa(rst_c), |
.datab(w_ek_r[1]), |
.datac(w_ek_r[2]), |
.datad(G_287_a), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam G_287_cZ.operation_mode="normal"; |
defparam G_287_cZ.output_mode="comb_only"; |
defparam G_287_cZ.lut_mask="baaa"; |
defparam G_287_cZ.synch_mode="off"; |
defparam G_287_cZ.sum_lutc_input="datac"; |
cyclone_lcell G_287_a_cZ ( |
.combout(G_287_a), |
.dataa(w_mem_wr_r), |
.datab(w_ek_r[3]), |
.datac(w_ek_r[4]), |
.datad(w_ek_r[0]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam G_287_a_cZ.operation_mode="normal"; |
defparam G_287_a_cZ.output_mode="comb_only"; |
defparam G_287_a_cZ.lut_mask="0002"; |
defparam G_287_a_cZ.synch_mode="off"; |
defparam G_287_a_cZ.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_0_a3_2_0_ ( |
.combout(w_alu_res_1_0_a3_2[0]), |
.dataa(w_alu_op_r[3]), |
.datab(w_c_wr_r), |
.datac(w_alu_res_1_0_a3_2_a[0]), |
.datad(w_alu_res142_0_3_0_a2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_0_a3_2_0_.operation_mode="normal"; |
defparam w_alu_res_1_0_a3_2_0_.output_mode="comb_only"; |
defparam w_alu_res_1_0_a3_2_0_.lut_mask="1f10"; |
defparam w_alu_res_1_0_a3_2_0_.synch_mode="off"; |
defparam w_alu_res_1_0_a3_2_0_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_0_a3_2_a_0_ ( |
.combout(w_alu_res_1_0_a3_2_a[0]), |
.dataa(w_alu_op_r[4]), |
.datab(w_alu_op_r[0]), |
.datac(w_alu_op_r[3]), |
.datad(w_c_wr_r), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_0_a3_2_a_0_.operation_mode="normal"; |
defparam w_alu_res_1_0_a3_2_a_0_.output_mode="comb_only"; |
defparam w_alu_res_1_0_a3_2_a_0_.lut_mask="4146"; |
defparam w_alu_res_1_0_a3_2_a_0_.synch_mode="off"; |
defparam w_alu_res_1_0_a3_2_a_0_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_4_2_ ( |
.combout(w_alu_res_1_4[2]), |
.dataa(VCC), |
.datab(w_wreg[2]), |
.datac(w_alu_op_r[3]), |
.datad(mem_man_dout[1]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_4_2_.operation_mode="normal"; |
defparam w_alu_res_1_4_2_.output_mode="comb_only"; |
defparam w_alu_res_1_4_2_.lut_mask="fc0c"; |
defparam w_alu_res_1_4_2_.synch_mode="off"; |
defparam w_alu_res_1_4_2_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_11_i_x3_0_ ( |
.combout(w_alu_res_1_11_i_x3[0]), |
.dataa(VCC), |
.datab(VCC), |
.datac(w_wreg[0]), |
.datad(mem_man_dout[0]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_11_i_x3_0_.operation_mode="normal"; |
defparam w_alu_res_1_11_i_x3_0_.output_mode="comb_only"; |
defparam w_alu_res_1_11_i_x3_0_.lut_mask="0ff0"; |
defparam w_alu_res_1_11_i_x3_0_.synch_mode="off"; |
defparam w_alu_res_1_11_i_x3_0_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_4_5_ ( |
.combout(w_alu_res_1_4[5]), |
.dataa(VCC), |
.datab(w_wreg[5]), |
.datac(w_alu_op_r[3]), |
.datad(mem_man_dout[4]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_4_5_.operation_mode="normal"; |
defparam w_alu_res_1_4_5_.output_mode="comb_only"; |
defparam w_alu_res_1_4_5_.lut_mask="fc0c"; |
defparam w_alu_res_1_4_5_.synch_mode="off"; |
defparam w_alu_res_1_4_5_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_4_4_ ( |
.combout(w_alu_res_1_4[4]), |
.dataa(VCC), |
.datab(w_wreg[4]), |
.datac(w_alu_op_r[3]), |
.datad(mem_man_dout[3]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_4_4_.operation_mode="normal"; |
defparam w_alu_res_1_4_4_.output_mode="comb_only"; |
defparam w_alu_res_1_4_4_.lut_mask="fc0c"; |
defparam w_alu_res_1_4_4_.synch_mode="off"; |
defparam w_alu_res_1_4_4_.sum_lutc_input="datac"; |
// @11:173 |
cyclone_lcell w_c_2mem_i_a2_0_0_cZ ( |
.combout(w_c_2mem_i_a2_0_0), |
.dataa(w_alu_op_r[4]), |
.datab(w_alu_op_r[0]), |
.datac(w_alu_op_r[3]), |
.datad(w_c_wr_r), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_c_2mem_i_a2_0_0_cZ.operation_mode="normal"; |
defparam w_c_2mem_i_a2_0_0_cZ.output_mode="comb_only"; |
defparam w_c_2mem_i_a2_0_0_cZ.lut_mask="0e0f"; |
defparam w_c_2mem_i_a2_0_0_cZ.synch_mode="off"; |
defparam w_c_2mem_i_a2_0_0_cZ.sum_lutc_input="datac"; |
// @11:236 |
cyclone_lcell w_alu_op_0_0_o2_0_a2_0_2_ ( |
.combout(w_alu_op_0_0_o2_0_a2_0[2]), |
.dataa(w_ins[1]), |
.datab(w_ins[4]), |
.datac(w_ins[6]), |
.datad(w_alu_op_0_0_o2_0_a2_0_a[2]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_op_0_0_o2_0_a2_0_2_.operation_mode="normal"; |
defparam w_alu_op_0_0_o2_0_a2_0_2_.output_mode="comb_only"; |
defparam w_alu_op_0_0_o2_0_a2_0_2_.lut_mask="1000"; |
defparam w_alu_op_0_0_o2_0_a2_0_2_.synch_mode="off"; |
defparam w_alu_op_0_0_o2_0_a2_0_2_.sum_lutc_input="datac"; |
// @11:236 |
cyclone_lcell w_alu_op_0_0_o2_0_a2_0_a_2_ ( |
.combout(w_alu_op_0_0_o2_0_a2_0_a[2]), |
.dataa(VCC), |
.datab(w_ins[2]), |
.datac(w_ins[3]), |
.datad(w_ins[0]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_op_0_0_o2_0_a2_0_a_2_.operation_mode="normal"; |
defparam w_alu_op_0_0_o2_0_a2_0_a_2_.output_mode="comb_only"; |
defparam w_alu_op_0_0_o2_0_a2_0_a_2_.lut_mask="0003"; |
defparam w_alu_op_0_0_o2_0_a2_0_a_2_.synch_mode="off"; |
defparam w_alu_op_0_0_o2_0_a2_0_a_2_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_0_a2_1_1_ ( |
.combout(w_alu_res_1_0_a2_1[1]), |
.dataa(w_wreg[1]), |
.datab(w_alu_res_1_0_a3_2[0]), |
.datac(w_alu_res_1_sn_m7_0_a2), |
.datad(w_alu_res_1_0_a2_1_a[1]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_0_a2_1_1_.operation_mode="normal"; |
defparam w_alu_res_1_0_a2_1_1_.output_mode="comb_only"; |
defparam w_alu_res_1_0_a2_1_1_.lut_mask="808c"; |
defparam w_alu_res_1_0_a2_1_1_.synch_mode="off"; |
defparam w_alu_res_1_0_a2_1_1_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_0_a2_1_a_1_ ( |
.combout(w_alu_res_1_0_a2_1_a[1]), |
.dataa(VCC), |
.datab(w_alu_res142_0_3_0_a2), |
.datac(un87_w_alu_res[1]), |
.datad(w_alu_res_add1), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_0_a2_1_a_1_.operation_mode="normal"; |
defparam w_alu_res_1_0_a2_1_a_1_.output_mode="comb_only"; |
defparam w_alu_res_1_0_a2_1_a_1_.lut_mask="0c3f"; |
defparam w_alu_res_1_0_a2_1_a_1_.synch_mode="off"; |
defparam w_alu_res_1_0_a2_1_a_1_.sum_lutc_input="datac"; |
// @11:164 |
cyclone_lcell w_alu_res142_0_3_0_a2_cZ ( |
.combout(w_alu_res142_0_3_0_a2), |
.dataa(w_alu_op_r[4]), |
.datab(w_alu_op_r[0]), |
.datac(w_alu_op_r[3]), |
.datad(w_c_wr_r), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res142_0_3_0_a2_cZ.operation_mode="normal"; |
defparam w_alu_res142_0_3_0_a2_cZ.output_mode="comb_only"; |
defparam w_alu_res142_0_3_0_a2_cZ.lut_mask="1000"; |
defparam w_alu_res142_0_3_0_a2_cZ.synch_mode="off"; |
defparam w_alu_res142_0_3_0_a2_cZ.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_1_a3_1_3_ ( |
.combout(w_alu_res_1_1_a3_1[3]), |
.dataa(VCC), |
.datab(w_alu_op_r[4]), |
.datac(w_alu_op_r[0]), |
.datad(w_alu_op_r[3]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_1_a3_1_3_.operation_mode="normal"; |
defparam w_alu_res_1_1_a3_1_3_.output_mode="comb_only"; |
defparam w_alu_res_1_1_a3_1_3_.lut_mask="3000"; |
defparam w_alu_res_1_1_a3_1_3_.synch_mode="off"; |
defparam w_alu_res_1_1_a3_1_3_.sum_lutc_input="datac"; |
// @11:173 |
cyclone_lcell w_c_2mem_i_a3_cZ ( |
.combout(w_c_2mem_i_a3), |
.dataa(w_alu_op_r[4]), |
.datab(w_alu_op_r[0]), |
.datac(w_alu_op_r[3]), |
.datad(w_c_wr_r), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_c_2mem_i_a3_cZ.operation_mode="normal"; |
defparam w_c_2mem_i_a3_cZ.output_mode="comb_only"; |
defparam w_c_2mem_i_a3_cZ.lut_mask="0100"; |
defparam w_c_2mem_i_a3_cZ.synch_mode="off"; |
defparam w_c_2mem_i_a3_cZ.sum_lutc_input="datac"; |
// @11:169 |
cyclone_lcell w_z_0_a2_1_cZ ( |
.combout(w_z_0_a2_1), |
.dataa(VCC), |
.datab(VCC), |
.datac(w_alu_res_1_1[3]), |
.datad(w_alu_res_1_3[4]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_z_0_a2_1_cZ.operation_mode="normal"; |
defparam w_z_0_a2_1_cZ.output_mode="comb_only"; |
defparam w_z_0_a2_1_cZ.lut_mask="000f"; |
defparam w_z_0_a2_1_cZ.synch_mode="off"; |
defparam w_z_0_a2_1_cZ.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_0_a2_2_0_0_ ( |
.combout(w_alu_res_1_0_a2_2_0[0]), |
.dataa(VCC), |
.datab(VCC), |
.datac(w_wreg[0]), |
.datad(w_alu_res_1_0_a3_1[0]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_0_a2_2_0_0_.operation_mode="normal"; |
defparam w_alu_res_1_0_a2_2_0_0_.output_mode="comb_only"; |
defparam w_alu_res_1_0_a2_2_0_0_.lut_mask="f000"; |
defparam w_alu_res_1_0_a2_2_0_0_.synch_mode="off"; |
defparam w_alu_res_1_0_a2_2_0_0_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_0_a2_2_0_1_ ( |
.combout(w_alu_res_1_0_a2_2_0[1]), |
.dataa(VCC), |
.datab(VCC), |
.datac(w_wreg[1]), |
.datad(w_alu_res_1_0_a3_1[0]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_0_a2_2_0_1_.operation_mode="normal"; |
defparam w_alu_res_1_0_a2_2_0_1_.output_mode="comb_only"; |
defparam w_alu_res_1_0_a2_2_0_1_.lut_mask="f000"; |
defparam w_alu_res_1_0_a2_2_0_1_.synch_mode="off"; |
defparam w_alu_res_1_0_a2_2_0_1_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_5_3_ ( |
.combout(w_alu_res_1_5[3]), |
.dataa(VCC), |
.datab(w_alu_res142_0_3_0_a2), |
.datac(un87_w_alu_res[3]), |
.datad(w_alu_res_add3), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_5_3_.operation_mode="normal"; |
defparam w_alu_res_1_5_3_.output_mode="comb_only"; |
defparam w_alu_res_1_5_3_.lut_mask="f3c0"; |
defparam w_alu_res_1_5_3_.synch_mode="off"; |
defparam w_alu_res_1_5_3_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_5_6_ ( |
.combout(w_alu_res_1_5[6]), |
.dataa(VCC), |
.datab(w_alu_res142_0_3_0_a2), |
.datac(un87_w_alu_res[6]), |
.datad(w_alu_res_add6), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_5_6_.operation_mode="normal"; |
defparam w_alu_res_1_5_6_.output_mode="comb_only"; |
defparam w_alu_res_1_5_6_.lut_mask="f3c0"; |
defparam w_alu_res_1_5_6_.synch_mode="off"; |
defparam w_alu_res_1_5_6_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_5_7_ ( |
.combout(w_alu_res_1_5[7]), |
.dataa(VCC), |
.datab(w_alu_res142_0_3_0_a2), |
.datac(un87_w_alu_res[7]), |
.datad(w_alu_res_add7), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_5_7_.operation_mode="normal"; |
defparam w_alu_res_1_5_7_.output_mode="comb_only"; |
defparam w_alu_res_1_5_7_.lut_mask="f3c0"; |
defparam w_alu_res_1_5_7_.synch_mode="off"; |
defparam w_alu_res_1_5_7_.sum_lutc_input="datac"; |
// @11:166 |
cyclone_lcell w_alu_res_1_sn_m7_0_a2_cZ ( |
.combout(w_alu_res_1_sn_m7_0_a2), |
.dataa(VCC), |
.datab(VCC), |
.datac(w_alu_op_r[0]), |
.datad(w_alu_res142_0_3_0_a2), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_sn_m7_0_a2_cZ.operation_mode="normal"; |
defparam w_alu_res_1_sn_m7_0_a2_cZ.output_mode="comb_only"; |
defparam w_alu_res_1_sn_m7_0_a2_cZ.lut_mask="000f"; |
defparam w_alu_res_1_sn_m7_0_a2_cZ.synch_mode="off"; |
defparam w_alu_res_1_sn_m7_0_a2_cZ.sum_lutc_input="datac"; |
// @11:173 |
cyclone_lcell w_c_2mem_i_a2_0 ( |
.combout(N_796), |
.dataa(VCC), |
.datab(VCC), |
.datac(w_alu_op_r[3]), |
.datad(un87_w_alu_res[8]), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_c_2mem_i_a2_0.operation_mode="normal"; |
defparam w_c_2mem_i_a2_0.output_mode="comb_only"; |
defparam w_c_2mem_i_a2_0.lut_mask="00f0"; |
defparam w_c_2mem_i_a2_0.synch_mode="off"; |
defparam w_c_2mem_i_a2_0.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_5_5_ ( |
.combout(w_alu_res_1_5[5]), |
.dataa(VCC), |
.datab(w_alu_res142_0_3_0_a2), |
.datac(un87_w_alu_res[5]), |
.datad(w_alu_res_add5), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_5_5_.operation_mode="normal"; |
defparam w_alu_res_1_5_5_.output_mode="comb_only"; |
defparam w_alu_res_1_5_5_.lut_mask="f3c0"; |
defparam w_alu_res_1_5_5_.synch_mode="off"; |
defparam w_alu_res_1_5_5_.sum_lutc_input="datac"; |
// @11:151 |
cyclone_lcell w_alu_res_1_5_4_ ( |
.combout(w_alu_res_1_5[4]), |
.dataa(VCC), |
.datab(w_alu_res142_0_3_0_a2), |
.datac(un87_w_alu_res[4]), |
.datad(w_alu_res_add4), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_1_5_4_.operation_mode="normal"; |
defparam w_alu_res_1_5_4_.output_mode="comb_only"; |
defparam w_alu_res_1_5_4_.lut_mask="f3c0"; |
defparam w_alu_res_1_5_4_.synch_mode="off"; |
defparam w_alu_res_1_5_4_.sum_lutc_input="datac"; |
// @11:153 |
cyclone_lcell un11_w_alu_res_add7_cZ ( |
.combout(un11_w_alu_res_add7), |
.cout(un11_w_alu_res_add7_cout), |
.dataa(w_wreg[7]), |
.datab(mem_man_dout[7]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(un11_w_alu_res_carry_6), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un11_w_alu_res_add7_cZ.cin_used="true"; |
defparam un11_w_alu_res_add7_cZ.operation_mode="arithmetic"; |
defparam un11_w_alu_res_add7_cZ.output_mode="comb_only"; |
defparam un11_w_alu_res_add7_cZ.lut_mask="69d4"; |
defparam un11_w_alu_res_add7_cZ.synch_mode="off"; |
defparam un11_w_alu_res_add7_cZ.sum_lutc_input="cin"; |
// @11:153 |
cyclone_lcell un11_w_alu_res_add6_cZ ( |
.combout(un11_w_alu_res_add6), |
.cout(un11_w_alu_res_carry_6), |
.dataa(w_wreg[6]), |
.datab(mem_man_dout[6]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(un11_w_alu_res_carry_5), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un11_w_alu_res_add6_cZ.cin_used="true"; |
defparam un11_w_alu_res_add6_cZ.operation_mode="arithmetic"; |
defparam un11_w_alu_res_add6_cZ.output_mode="comb_only"; |
defparam un11_w_alu_res_add6_cZ.lut_mask="69d4"; |
defparam un11_w_alu_res_add6_cZ.synch_mode="off"; |
defparam un11_w_alu_res_add6_cZ.sum_lutc_input="cin"; |
// @11:153 |
cyclone_lcell un11_w_alu_res_add5_cZ ( |
.combout(un11_w_alu_res_add5), |
.cout(un11_w_alu_res_carry_5), |
.dataa(w_wreg[5]), |
.datab(mem_man_dout[5]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(un11_w_alu_res_carry_4), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un11_w_alu_res_add5_cZ.cin_used="true"; |
defparam un11_w_alu_res_add5_cZ.operation_mode="arithmetic"; |
defparam un11_w_alu_res_add5_cZ.output_mode="comb_only"; |
defparam un11_w_alu_res_add5_cZ.lut_mask="69d4"; |
defparam un11_w_alu_res_add5_cZ.synch_mode="off"; |
defparam un11_w_alu_res_add5_cZ.sum_lutc_input="cin"; |
// @11:153 |
cyclone_lcell un11_w_alu_res_add4_cZ ( |
.combout(un11_w_alu_res_add4), |
.cout(un11_w_alu_res_carry_4), |
.dataa(w_wreg[4]), |
.datab(mem_man_dout[4]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(un11_w_alu_res_carry_3), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un11_w_alu_res_add4_cZ.cin_used="true"; |
defparam un11_w_alu_res_add4_cZ.operation_mode="arithmetic"; |
defparam un11_w_alu_res_add4_cZ.output_mode="comb_only"; |
defparam un11_w_alu_res_add4_cZ.lut_mask="69d4"; |
defparam un11_w_alu_res_add4_cZ.synch_mode="off"; |
defparam un11_w_alu_res_add4_cZ.sum_lutc_input="cin"; |
// @11:153 |
cyclone_lcell un11_w_alu_res_add3_cZ ( |
.combout(un11_w_alu_res_add3), |
.cout(un11_w_alu_res_carry_3), |
.dataa(w_wreg[3]), |
.datab(mem_man_dout[3]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(un11_w_alu_res_carry_2), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un11_w_alu_res_add3_cZ.cin_used="true"; |
defparam un11_w_alu_res_add3_cZ.operation_mode="arithmetic"; |
defparam un11_w_alu_res_add3_cZ.output_mode="comb_only"; |
defparam un11_w_alu_res_add3_cZ.lut_mask="69d4"; |
defparam un11_w_alu_res_add3_cZ.synch_mode="off"; |
defparam un11_w_alu_res_add3_cZ.sum_lutc_input="cin"; |
// @11:153 |
cyclone_lcell un11_w_alu_res_add2_cZ ( |
.combout(un11_w_alu_res_add2), |
.cout(un11_w_alu_res_carry_2), |
.dataa(w_wreg[2]), |
.datab(mem_man_dout[2]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(un11_w_alu_res_carry_1), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un11_w_alu_res_add2_cZ.cin_used="true"; |
defparam un11_w_alu_res_add2_cZ.operation_mode="arithmetic"; |
defparam un11_w_alu_res_add2_cZ.output_mode="comb_only"; |
defparam un11_w_alu_res_add2_cZ.lut_mask="69d4"; |
defparam un11_w_alu_res_add2_cZ.synch_mode="off"; |
defparam un11_w_alu_res_add2_cZ.sum_lutc_input="cin"; |
// @11:153 |
cyclone_lcell un11_w_alu_res_add1_cZ ( |
.combout(un11_w_alu_res_add1), |
.cout(un11_w_alu_res_carry_1), |
.dataa(w_wreg[1]), |
.datab(mem_man_dout[1]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(un11_w_alu_res_carry_0), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un11_w_alu_res_add1_cZ.cin_used="true"; |
defparam un11_w_alu_res_add1_cZ.operation_mode="arithmetic"; |
defparam un11_w_alu_res_add1_cZ.output_mode="comb_only"; |
defparam un11_w_alu_res_add1_cZ.lut_mask="69d4"; |
defparam un11_w_alu_res_add1_cZ.synch_mode="off"; |
defparam un11_w_alu_res_add1_cZ.sum_lutc_input="cin"; |
// @11:153 |
cyclone_lcell un11_w_alu_res_add0_cZ ( |
.combout(un11_w_alu_res_add0), |
.cout(un11_w_alu_res_carry_0), |
.dataa(w_wreg[0]), |
.datab(mem_man_dout[0]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un11_w_alu_res_add0_cZ.operation_mode="arithmetic"; |
defparam un11_w_alu_res_add0_cZ.output_mode="comb_only"; |
defparam un11_w_alu_res_add0_cZ.lut_mask="66dd"; |
defparam un11_w_alu_res_add0_cZ.synch_mode="off"; |
defparam un11_w_alu_res_add0_cZ.sum_lutc_input="datac"; |
// @11:152 |
cyclone_lcell w_alu_res_add7_cZ ( |
.combout(w_alu_res_add7), |
.dataa(w_wreg[7]), |
.datab(mem_man_dout[7]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(w_alu_res_carry_6), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_add7_cZ.cin_used="true"; |
defparam w_alu_res_add7_cZ.operation_mode="normal"; |
defparam w_alu_res_add7_cZ.output_mode="comb_only"; |
defparam w_alu_res_add7_cZ.lut_mask="9696"; |
defparam w_alu_res_add7_cZ.synch_mode="off"; |
defparam w_alu_res_add7_cZ.sum_lutc_input="cin"; |
// @11:152 |
cyclone_lcell w_alu_res_add6_cZ ( |
.combout(w_alu_res_add6), |
.cout(w_alu_res_carry_6), |
.dataa(w_wreg[6]), |
.datab(mem_man_dout[6]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(w_alu_res_carry_5), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_add6_cZ.cin_used="true"; |
defparam w_alu_res_add6_cZ.operation_mode="arithmetic"; |
defparam w_alu_res_add6_cZ.output_mode="comb_only"; |
defparam w_alu_res_add6_cZ.lut_mask="96e8"; |
defparam w_alu_res_add6_cZ.synch_mode="off"; |
defparam w_alu_res_add6_cZ.sum_lutc_input="cin"; |
// @11:152 |
cyclone_lcell w_alu_res_add5_cZ ( |
.combout(w_alu_res_add5), |
.cout(w_alu_res_carry_5), |
.dataa(w_wreg[5]), |
.datab(mem_man_dout[5]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(w_alu_res_carry_4), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_add5_cZ.cin_used="true"; |
defparam w_alu_res_add5_cZ.operation_mode="arithmetic"; |
defparam w_alu_res_add5_cZ.output_mode="comb_only"; |
defparam w_alu_res_add5_cZ.lut_mask="96e8"; |
defparam w_alu_res_add5_cZ.synch_mode="off"; |
defparam w_alu_res_add5_cZ.sum_lutc_input="cin"; |
// @11:152 |
cyclone_lcell w_alu_res_add4_cZ ( |
.combout(w_alu_res_add4), |
.cout(w_alu_res_carry_4), |
.dataa(w_wreg[4]), |
.datab(mem_man_dout[4]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(w_alu_res_carry_3), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_add4_cZ.cin_used="true"; |
defparam w_alu_res_add4_cZ.operation_mode="arithmetic"; |
defparam w_alu_res_add4_cZ.output_mode="comb_only"; |
defparam w_alu_res_add4_cZ.lut_mask="96e8"; |
defparam w_alu_res_add4_cZ.synch_mode="off"; |
defparam w_alu_res_add4_cZ.sum_lutc_input="cin"; |
// @11:152 |
cyclone_lcell w_alu_res_add3_cZ ( |
.combout(w_alu_res_add3), |
.cout(w_alu_res_carry_3), |
.dataa(w_wreg[3]), |
.datab(mem_man_dout[3]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(w_alu_res_carry_2), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_add3_cZ.cin_used="true"; |
defparam w_alu_res_add3_cZ.operation_mode="arithmetic"; |
defparam w_alu_res_add3_cZ.output_mode="comb_only"; |
defparam w_alu_res_add3_cZ.lut_mask="96e8"; |
defparam w_alu_res_add3_cZ.synch_mode="off"; |
defparam w_alu_res_add3_cZ.sum_lutc_input="cin"; |
// @11:152 |
cyclone_lcell w_alu_res_add2_cZ ( |
.combout(w_alu_res_add2), |
.cout(w_alu_res_carry_2), |
.dataa(w_wreg[2]), |
.datab(mem_man_dout[2]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(w_alu_res_carry_1), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_add2_cZ.cin_used="true"; |
defparam w_alu_res_add2_cZ.operation_mode="arithmetic"; |
defparam w_alu_res_add2_cZ.output_mode="comb_only"; |
defparam w_alu_res_add2_cZ.lut_mask="96e8"; |
defparam w_alu_res_add2_cZ.synch_mode="off"; |
defparam w_alu_res_add2_cZ.sum_lutc_input="cin"; |
// @11:152 |
cyclone_lcell w_alu_res_add1_cZ ( |
.combout(w_alu_res_add1), |
.cout(w_alu_res_carry_1), |
.dataa(w_wreg[1]), |
.datab(mem_man_dout[1]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(w_alu_res_carry_0), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_add1_cZ.cin_used="true"; |
defparam w_alu_res_add1_cZ.operation_mode="arithmetic"; |
defparam w_alu_res_add1_cZ.output_mode="comb_only"; |
defparam w_alu_res_add1_cZ.lut_mask="96e8"; |
defparam w_alu_res_add1_cZ.synch_mode="off"; |
defparam w_alu_res_add1_cZ.sum_lutc_input="cin"; |
// @11:152 |
cyclone_lcell w_alu_res_add0_cZ ( |
.combout(w_alu_res_add0), |
.cout(w_alu_res_carry_0), |
.dataa(w_wreg[0]), |
.datab(mem_man_dout[0]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam w_alu_res_add0_cZ.operation_mode="arithmetic"; |
defparam w_alu_res_add0_cZ.output_mode="comb_only"; |
defparam w_alu_res_add0_cZ.lut_mask="6688"; |
defparam w_alu_res_add0_cZ.synch_mode="off"; |
defparam w_alu_res_add0_cZ.sum_lutc_input="datac"; |
// @11:222 |
cyclone_lcell un4_w_pc_nxt_6_ ( |
.combout(un4_w_pc_nxt[6]), |
.dataa(w_pc[6]), |
.datab(VCC), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(un4_w_pc_nxt_cout[4]), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un4_w_pc_nxt_6_.cin_used="true"; |
defparam un4_w_pc_nxt_6_.operation_mode="normal"; |
defparam un4_w_pc_nxt_6_.output_mode="comb_only"; |
defparam un4_w_pc_nxt_6_.lut_mask="5a5a"; |
defparam un4_w_pc_nxt_6_.synch_mode="off"; |
defparam un4_w_pc_nxt_6_.sum_lutc_input="cin"; |
// @11:222 |
cyclone_lcell un4_w_pc_nxt_5_ ( |
.combout(un4_w_pc_nxt[5]), |
.dataa(w_pc[4]), |
.datab(w_pc[5]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(un4_w_pc_nxt_cout[3]), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un4_w_pc_nxt_5_.cin_used="true"; |
defparam un4_w_pc_nxt_5_.operation_mode="normal"; |
defparam un4_w_pc_nxt_5_.output_mode="comb_only"; |
defparam un4_w_pc_nxt_5_.lut_mask="6c6c"; |
defparam un4_w_pc_nxt_5_.synch_mode="off"; |
defparam un4_w_pc_nxt_5_.sum_lutc_input="cin"; |
// @11:222 |
cyclone_lcell un4_w_pc_nxt_4_ ( |
.combout(un4_w_pc_nxt[4]), |
.cout(un4_w_pc_nxt_cout[4]), |
.dataa(w_pc[4]), |
.datab(w_pc[5]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(un4_w_pc_nxt_cout[2]), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un4_w_pc_nxt_4_.cin_used="true"; |
defparam un4_w_pc_nxt_4_.operation_mode="arithmetic"; |
defparam un4_w_pc_nxt_4_.output_mode="comb_only"; |
defparam un4_w_pc_nxt_4_.lut_mask="5a80"; |
defparam un4_w_pc_nxt_4_.synch_mode="off"; |
defparam un4_w_pc_nxt_4_.sum_lutc_input="cin"; |
// @11:222 |
cyclone_lcell un4_w_pc_nxt_3_ ( |
.combout(un4_w_pc_nxt[3]), |
.cout(un4_w_pc_nxt_cout[3]), |
.dataa(w_pc[2]), |
.datab(w_pc[3]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(un4_w_pc_nxt_cout[1]), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un4_w_pc_nxt_3_.cin_used="true"; |
defparam un4_w_pc_nxt_3_.operation_mode="arithmetic"; |
defparam un4_w_pc_nxt_3_.output_mode="comb_only"; |
defparam un4_w_pc_nxt_3_.lut_mask="6c80"; |
defparam un4_w_pc_nxt_3_.synch_mode="off"; |
defparam un4_w_pc_nxt_3_.sum_lutc_input="cin"; |
// @11:222 |
cyclone_lcell un4_w_pc_nxt_2_ ( |
.combout(un4_w_pc_nxt[2]), |
.cout(un4_w_pc_nxt_cout[2]), |
.dataa(w_pc[2]), |
.datab(w_pc[3]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(un4_w_pc_nxt_cout[0]), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un4_w_pc_nxt_2_.cin_used="true"; |
defparam un4_w_pc_nxt_2_.operation_mode="arithmetic"; |
defparam un4_w_pc_nxt_2_.output_mode="comb_only"; |
defparam un4_w_pc_nxt_2_.lut_mask="5a80"; |
defparam un4_w_pc_nxt_2_.synch_mode="off"; |
defparam un4_w_pc_nxt_2_.sum_lutc_input="cin"; |
// @11:222 |
cyclone_lcell un4_w_pc_nxt_1_ ( |
.combout(un4_w_pc_nxt[1]), |
.cout(un4_w_pc_nxt_cout[1]), |
.dataa(w_pc[0]), |
.datab(w_pc[1]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un4_w_pc_nxt_1_.operation_mode="arithmetic"; |
defparam un4_w_pc_nxt_1_.output_mode="comb_only"; |
defparam un4_w_pc_nxt_1_.lut_mask="6688"; |
defparam un4_w_pc_nxt_1_.synch_mode="off"; |
defparam un4_w_pc_nxt_1_.sum_lutc_input="datac"; |
// @11:222 |
cyclone_lcell un4_w_pc_nxt_0_ ( |
.combout(N_1), |
.cout(un4_w_pc_nxt_cout[0]), |
.dataa(w_pc[0]), |
.datab(w_pc[1]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un4_w_pc_nxt_0_.operation_mode="arithmetic"; |
defparam un4_w_pc_nxt_0_.output_mode="comb_only"; |
defparam un4_w_pc_nxt_0_.lut_mask="5588"; |
defparam un4_w_pc_nxt_0_.synch_mode="off"; |
defparam un4_w_pc_nxt_0_.sum_lutc_input="datac"; |
// @11:164 |
cyclone_lcell un87_w_alu_res_7_ ( |
.combout(un87_w_alu_res[7]), |
.dataa(mem_man_dout[6]), |
.datab(mem_man_dout[7]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(un87_w_alu_res_cout[5]), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un87_w_alu_res_7_.cin_used="true"; |
defparam un87_w_alu_res_7_.operation_mode="normal"; |
defparam un87_w_alu_res_7_.output_mode="comb_only"; |
defparam un87_w_alu_res_7_.lut_mask="6c6c"; |
defparam un87_w_alu_res_7_.synch_mode="off"; |
defparam un87_w_alu_res_7_.sum_lutc_input="cin"; |
// @11:164 |
cyclone_lcell un87_w_alu_res_6_ ( |
.combout(un87_w_alu_res[6]), |
.cout(un87_w_alu_res_cout[6]), |
.dataa(mem_man_dout[6]), |
.datab(mem_man_dout[7]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(un87_w_alu_res_cout[4]), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un87_w_alu_res_6_.cin_used="true"; |
defparam un87_w_alu_res_6_.operation_mode="arithmetic"; |
defparam un87_w_alu_res_6_.output_mode="comb_only"; |
defparam un87_w_alu_res_6_.lut_mask="5a80"; |
defparam un87_w_alu_res_6_.synch_mode="off"; |
defparam un87_w_alu_res_6_.sum_lutc_input="cin"; |
// @11:164 |
cyclone_lcell un87_w_alu_res_5_ ( |
.combout(un87_w_alu_res[5]), |
.cout(un87_w_alu_res_cout[5]), |
.dataa(mem_man_dout[4]), |
.datab(mem_man_dout[5]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(un87_w_alu_res_cout[3]), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un87_w_alu_res_5_.cin_used="true"; |
defparam un87_w_alu_res_5_.operation_mode="arithmetic"; |
defparam un87_w_alu_res_5_.output_mode="comb_only"; |
defparam un87_w_alu_res_5_.lut_mask="6c80"; |
defparam un87_w_alu_res_5_.synch_mode="off"; |
defparam un87_w_alu_res_5_.sum_lutc_input="cin"; |
// @11:164 |
cyclone_lcell un87_w_alu_res_4_ ( |
.combout(un87_w_alu_res[4]), |
.cout(un87_w_alu_res_cout[4]), |
.dataa(mem_man_dout[4]), |
.datab(mem_man_dout[5]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(un87_w_alu_res_cout[2]), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un87_w_alu_res_4_.cin_used="true"; |
defparam un87_w_alu_res_4_.operation_mode="arithmetic"; |
defparam un87_w_alu_res_4_.output_mode="comb_only"; |
defparam un87_w_alu_res_4_.lut_mask="5a80"; |
defparam un87_w_alu_res_4_.synch_mode="off"; |
defparam un87_w_alu_res_4_.sum_lutc_input="cin"; |
// @11:164 |
cyclone_lcell un87_w_alu_res_3_ ( |
.combout(un87_w_alu_res[3]), |
.cout(un87_w_alu_res_cout[3]), |
.dataa(mem_man_dout[2]), |
.datab(mem_man_dout[3]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(un87_w_alu_res_cout[1]), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un87_w_alu_res_3_.cin_used="true"; |
defparam un87_w_alu_res_3_.operation_mode="arithmetic"; |
defparam un87_w_alu_res_3_.output_mode="comb_only"; |
defparam un87_w_alu_res_3_.lut_mask="6c80"; |
defparam un87_w_alu_res_3_.synch_mode="off"; |
defparam un87_w_alu_res_3_.sum_lutc_input="cin"; |
// @11:164 |
cyclone_lcell un87_w_alu_res_2_ ( |
.combout(un87_w_alu_res[2]), |
.cout(un87_w_alu_res_cout[2]), |
.dataa(mem_man_dout[2]), |
.datab(mem_man_dout[3]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(un87_w_alu_res_cout[0]), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un87_w_alu_res_2_.cin_used="true"; |
defparam un87_w_alu_res_2_.operation_mode="arithmetic"; |
defparam un87_w_alu_res_2_.output_mode="comb_only"; |
defparam un87_w_alu_res_2_.lut_mask="5a80"; |
defparam un87_w_alu_res_2_.synch_mode="off"; |
defparam un87_w_alu_res_2_.sum_lutc_input="cin"; |
// @11:164 |
cyclone_lcell un87_w_alu_res_1_ ( |
.combout(un87_w_alu_res[1]), |
.cout(un87_w_alu_res_cout[1]), |
.dataa(mem_man_dout[0]), |
.datab(mem_man_dout[1]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un87_w_alu_res_1_.operation_mode="arithmetic"; |
defparam un87_w_alu_res_1_.output_mode="comb_only"; |
defparam un87_w_alu_res_1_.lut_mask="6688"; |
defparam un87_w_alu_res_1_.synch_mode="off"; |
defparam un87_w_alu_res_1_.sum_lutc_input="datac"; |
// @11:164 |
cyclone_lcell un87_w_alu_res_0_ ( |
.combout(N_2), |
.cout(un87_w_alu_res_cout[0]), |
.dataa(mem_man_dout[0]), |
.datab(mem_man_dout[1]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un87_w_alu_res_0_.operation_mode="arithmetic"; |
defparam un87_w_alu_res_0_.output_mode="comb_only"; |
defparam un87_w_alu_res_0_.lut_mask="5588"; |
defparam un87_w_alu_res_0_.synch_mode="off"; |
defparam un87_w_alu_res_0_.sum_lutc_input="datac"; |
// @11:163 |
cyclone_lcell un74_w_alu_res_7_ ( |
.combout(un74_w_alu_res[7]), |
.dataa(mem_man_dout[6]), |
.datab(mem_man_dout[7]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(un74_w_alu_res_cout[5]), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un74_w_alu_res_7_.cin_used="true"; |
defparam un74_w_alu_res_7_.operation_mode="normal"; |
defparam un74_w_alu_res_7_.output_mode="comb_only"; |
defparam un74_w_alu_res_7_.lut_mask="c9c9"; |
defparam un74_w_alu_res_7_.synch_mode="off"; |
defparam un74_w_alu_res_7_.sum_lutc_input="cin"; |
// @11:163 |
cyclone_lcell un74_w_alu_res_6_ ( |
.combout(un74_w_alu_res[6]), |
.dataa(mem_man_dout[6]), |
.datab(VCC), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(un74_w_alu_res_cout[4]), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un74_w_alu_res_6_.cin_used="true"; |
defparam un74_w_alu_res_6_.operation_mode="normal"; |
defparam un74_w_alu_res_6_.output_mode="comb_only"; |
defparam un74_w_alu_res_6_.lut_mask="a5a5"; |
defparam un74_w_alu_res_6_.synch_mode="off"; |
defparam un74_w_alu_res_6_.sum_lutc_input="cin"; |
// @11:163 |
cyclone_lcell un74_w_alu_res_5_ ( |
.combout(un74_w_alu_res[5]), |
.cout(un74_w_alu_res_cout[5]), |
.dataa(mem_man_dout[4]), |
.datab(mem_man_dout[5]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(un74_w_alu_res_cout[3]), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un74_w_alu_res_5_.cin_used="true"; |
defparam un74_w_alu_res_5_.operation_mode="arithmetic"; |
defparam un74_w_alu_res_5_.output_mode="comb_only"; |
defparam un74_w_alu_res_5_.lut_mask="c9fe"; |
defparam un74_w_alu_res_5_.synch_mode="off"; |
defparam un74_w_alu_res_5_.sum_lutc_input="cin"; |
// @11:163 |
cyclone_lcell un74_w_alu_res_4_ ( |
.combout(un74_w_alu_res[4]), |
.cout(un74_w_alu_res_cout[4]), |
.dataa(mem_man_dout[4]), |
.datab(mem_man_dout[5]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(un74_w_alu_res_cout[2]), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un74_w_alu_res_4_.cin_used="true"; |
defparam un74_w_alu_res_4_.operation_mode="arithmetic"; |
defparam un74_w_alu_res_4_.output_mode="comb_only"; |
defparam un74_w_alu_res_4_.lut_mask="a5fe"; |
defparam un74_w_alu_res_4_.synch_mode="off"; |
defparam un74_w_alu_res_4_.sum_lutc_input="cin"; |
// @11:163 |
cyclone_lcell un74_w_alu_res_3_ ( |
.combout(un74_w_alu_res[3]), |
.cout(un74_w_alu_res_cout[3]), |
.dataa(mem_man_dout[2]), |
.datab(mem_man_dout[3]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(un74_w_alu_res_cout[1]), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un74_w_alu_res_3_.cin_used="true"; |
defparam un74_w_alu_res_3_.operation_mode="arithmetic"; |
defparam un74_w_alu_res_3_.output_mode="comb_only"; |
defparam un74_w_alu_res_3_.lut_mask="c9fe"; |
defparam un74_w_alu_res_3_.synch_mode="off"; |
defparam un74_w_alu_res_3_.sum_lutc_input="cin"; |
// @11:163 |
cyclone_lcell un74_w_alu_res_2_ ( |
.combout(un74_w_alu_res[2]), |
.cout(un74_w_alu_res_cout[2]), |
.dataa(mem_man_dout[2]), |
.datab(mem_man_dout[3]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.cin(un74_w_alu_res_cout[0]), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un74_w_alu_res_2_.cin_used="true"; |
defparam un74_w_alu_res_2_.operation_mode="arithmetic"; |
defparam un74_w_alu_res_2_.output_mode="comb_only"; |
defparam un74_w_alu_res_2_.lut_mask="a5fe"; |
defparam un74_w_alu_res_2_.synch_mode="off"; |
defparam un74_w_alu_res_2_.sum_lutc_input="cin"; |
// @11:163 |
cyclone_lcell un74_w_alu_res_1_ ( |
.combout(un74_w_alu_res[1]), |
.cout(un74_w_alu_res_cout[1]), |
.dataa(mem_man_dout[0]), |
.datab(mem_man_dout[1]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un74_w_alu_res_1_.operation_mode="arithmetic"; |
defparam un74_w_alu_res_1_.output_mode="comb_only"; |
defparam un74_w_alu_res_1_.lut_mask="99ee"; |
defparam un74_w_alu_res_1_.synch_mode="off"; |
defparam un74_w_alu_res_1_.sum_lutc_input="datac"; |
// @11:163 |
cyclone_lcell un74_w_alu_res_0_ ( |
.combout(N_3), |
.cout(un74_w_alu_res_cout[0]), |
.dataa(mem_man_dout[0]), |
.datab(mem_man_dout[1]), |
.datac(VCC), |
.datad(VCC), |
.aclr(GND), |
.sclr(GND), |
.sload(GND), |
.ena(VCC), |
.inverta(GND), |
.aload(GND), |
.regcascin(GND) |
); |
defparam un74_w_alu_res_0_.operation_mode="arithmetic"; |
defparam un74_w_alu_res_0_.output_mode="comb_only"; |
defparam un74_w_alu_res_0_.lut_mask="55ee"; |
defparam un74_w_alu_res_0_.synch_mode="off"; |
defparam un74_w_alu_res_0_.sum_lutc_input="datac"; |
// @11:6 |
cyclone_io in1_in_7_ ( |
.padio(in1[7]), |
.combout(in1_c[7]), |
.datain(GND), |
.oe(GND), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam in1_in_7_.operation_mode = "input"; |
// @11:6 |
cyclone_io in1_in_6_ ( |
.padio(in1[6]), |
.combout(in1_c[6]), |
.datain(GND), |
.oe(GND), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam in1_in_6_.operation_mode = "input"; |
// @11:6 |
cyclone_io in1_in_5_ ( |
.padio(in1[5]), |
.combout(in1_c[5]), |
.datain(GND), |
.oe(GND), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam in1_in_5_.operation_mode = "input"; |
// @11:6 |
cyclone_io in1_in_4_ ( |
.padio(in1[4]), |
.combout(in1_c[4]), |
.datain(GND), |
.oe(GND), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam in1_in_4_.operation_mode = "input"; |
// @11:6 |
cyclone_io in1_in_3_ ( |
.padio(in1[3]), |
.combout(in1_c[3]), |
.datain(GND), |
.oe(GND), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam in1_in_3_.operation_mode = "input"; |
// @11:6 |
cyclone_io in1_in_2_ ( |
.padio(in1[2]), |
.combout(in1_c[2]), |
.datain(GND), |
.oe(GND), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam in1_in_2_.operation_mode = "input"; |
// @11:6 |
cyclone_io in1_in_1_ ( |
.padio(in1[1]), |
.combout(in1_c[1]), |
.datain(GND), |
.oe(GND), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam in1_in_1_.operation_mode = "input"; |
// @11:6 |
cyclone_io in1_in_0_ ( |
.padio(in1[0]), |
.combout(in1_c[0]), |
.datain(GND), |
.oe(GND), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam in1_in_0_.operation_mode = "input"; |
// @11:5 |
cyclone_io in0_in_7_ ( |
.padio(in0[7]), |
.combout(in0_c[7]), |
.datain(GND), |
.oe(GND), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam in0_in_7_.operation_mode = "input"; |
// @11:5 |
cyclone_io in0_in_6_ ( |
.padio(in0[6]), |
.combout(in0_c[6]), |
.datain(GND), |
.oe(GND), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam in0_in_6_.operation_mode = "input"; |
// @11:5 |
cyclone_io in0_in_5_ ( |
.padio(in0[5]), |
.combout(in0_c[5]), |
.datain(GND), |
.oe(GND), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam in0_in_5_.operation_mode = "input"; |
// @11:5 |
cyclone_io in0_in_4_ ( |
.padio(in0[4]), |
.combout(in0_c[4]), |
.datain(GND), |
.oe(GND), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam in0_in_4_.operation_mode = "input"; |
// @11:5 |
cyclone_io in0_in_3_ ( |
.padio(in0[3]), |
.combout(in0_c[3]), |
.datain(GND), |
.oe(GND), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam in0_in_3_.operation_mode = "input"; |
// @11:5 |
cyclone_io in0_in_2_ ( |
.padio(in0[2]), |
.combout(in0_c[2]), |
.datain(GND), |
.oe(GND), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam in0_in_2_.operation_mode = "input"; |
// @11:5 |
cyclone_io in0_in_1_ ( |
.padio(in0[1]), |
.combout(in0_c[1]), |
.datain(GND), |
.oe(GND), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam in0_in_1_.operation_mode = "input"; |
// @11:5 |
cyclone_io in0_in_0_ ( |
.padio(in0[0]), |
.combout(in0_c[0]), |
.datain(GND), |
.oe(GND), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam in0_in_0_.operation_mode = "input"; |
// @11:4 |
cyclone_io rst_in ( |
.padio(rst), |
.combout(rst_c), |
.datain(GND), |
.oe(GND), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam rst_in.operation_mode = "input"; |
// @11:3 |
cyclone_io clk_in ( |
.padio(clk), |
.combout(clk_c), |
.datain(GND), |
.oe(GND), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam clk_in.operation_mode = "input"; |
// @11:8 |
cyclone_io out1_out_7_ ( |
.padio(out1[7]), |
.datain(mem_man_out1[7]), |
.oe(VCC), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam out1_out_7_.operation_mode = "output"; |
// @11:8 |
cyclone_io out1_out_6_ ( |
.padio(out1[6]), |
.datain(mem_man_out1[6]), |
.oe(VCC), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam out1_out_6_.operation_mode = "output"; |
// @11:8 |
cyclone_io out1_out_5_ ( |
.padio(out1[5]), |
.datain(mem_man_out1[5]), |
.oe(VCC), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam out1_out_5_.operation_mode = "output"; |
// @11:8 |
cyclone_io out1_out_4_ ( |
.padio(out1[4]), |
.datain(mem_man_out1[4]), |
.oe(VCC), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam out1_out_4_.operation_mode = "output"; |
// @11:8 |
cyclone_io out1_out_3_ ( |
.padio(out1[3]), |
.datain(mem_man_out1[3]), |
.oe(VCC), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam out1_out_3_.operation_mode = "output"; |
// @11:8 |
cyclone_io out1_out_2_ ( |
.padio(out1[2]), |
.datain(mem_man_out1[2]), |
.oe(VCC), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam out1_out_2_.operation_mode = "output"; |
// @11:8 |
cyclone_io out1_out_1_ ( |
.padio(out1[1]), |
.datain(mem_man_out1[1]), |
.oe(VCC), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam out1_out_1_.operation_mode = "output"; |
// @11:8 |
cyclone_io out1_out_0_ ( |
.padio(out1[0]), |
.datain(mem_man_out1[0]), |
.oe(VCC), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam out1_out_0_.operation_mode = "output"; |
// @11:7 |
cyclone_io out0_out_7_ ( |
.padio(out0[7]), |
.datain(mem_man_out0[7]), |
.oe(VCC), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam out0_out_7_.operation_mode = "output"; |
// @11:7 |
cyclone_io out0_out_6_ ( |
.padio(out0[6]), |
.datain(mem_man_out0[6]), |
.oe(VCC), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam out0_out_6_.operation_mode = "output"; |
// @11:7 |
cyclone_io out0_out_5_ ( |
.padio(out0[5]), |
.datain(mem_man_out0[5]), |
.oe(VCC), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam out0_out_5_.operation_mode = "output"; |
// @11:7 |
cyclone_io out0_out_4_ ( |
.padio(out0[4]), |
.datain(mem_man_out0[4]), |
.oe(VCC), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam out0_out_4_.operation_mode = "output"; |
// @11:7 |
cyclone_io out0_out_3_ ( |
.padio(out0[3]), |
.datain(mem_man_out0[3]), |
.oe(VCC), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam out0_out_3_.operation_mode = "output"; |
// @11:7 |
cyclone_io out0_out_2_ ( |
.padio(out0[2]), |
.datain(mem_man_out0[2]), |
.oe(VCC), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam out0_out_2_.operation_mode = "output"; |
// @11:7 |
cyclone_io out0_out_1_ ( |
.padio(out0[1]), |
.datain(mem_man_out0[1]), |
.oe(VCC), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam out0_out_1_.operation_mode = "output"; |
// @11:7 |
cyclone_io out0_out_0_ ( |
.padio(out0[0]), |
.datain(mem_man_out0[0]), |
.oe(VCC), |
.outclk(GND), |
.outclkena(VCC), |
.inclk(GND), |
.inclkena(VCC), |
.areset(GND), |
.sreset(GND) |
); |
defparam out0_out_0_.operation_mode = "output"; |
//@7:72 |
//@7:72 |
//@7:72 |
// @11:80 |
wb_mem_man mem_man ( |
.w_ins_0(w_ins[0]), |
.w_ins_1(w_ins[1]), |
.w_ins_2(w_ins[2]), |
.w_ins_3(w_ins[3]), |
.w_ins_4(w_ins[4]), |
.out0_0(mem_man_out0[0]), |
.out0_1(mem_man_out0[1]), |
.out0_2(mem_man_out0[2]), |
.out0_3(mem_man_out0[3]), |
.out0_4(mem_man_out0[4]), |
.out0_5(mem_man_out0[5]), |
.out0_6(mem_man_out0[6]), |
.out0_7(mem_man_out0[7]), |
.out1_0(mem_man_out1[0]), |
.out1_1(mem_man_out1[1]), |
.out1_2(mem_man_out1[2]), |
.out1_3(mem_man_out1[3]), |
.out1_4(mem_man_out1[4]), |
.out1_5(mem_man_out1[5]), |
.out1_6(mem_man_out1[6]), |
.out1_7(mem_man_out1[7]), |
.w_alu_res_1_1_0(w_alu_res_1_1[3]), |
.w_alu_res_1_3_0(w_alu_res_1_3[4]), |
.w_alu_res_1_6_0(w_alu_res_1_6[5]), |
.w_alu_res_1_6_1(w_alu_res_1_6[6]), |
.w_alu_res_1_6_2(w_alu_res_1_6[7]), |
.in0_c_0(in0_c[0]), |
.in0_c_1(in0_c[1]), |
.in0_c_2(in0_c[2]), |
.in0_c_3(in0_c[3]), |
.in0_c_4(in0_c[4]), |
.in0_c_5(in0_c[5]), |
.in0_c_6(in0_c[6]), |
.in0_c_7(in0_c[7]), |
.w_alu_res_1_0_1(w_alu_res_1_0[1]), |
.w_alu_res_1_0_2(w_alu_res_1_0[2]), |
.w_alu_res_1_0_0(w_alu_res_1_0[0]), |
.w_alu_res_1_0_a2_1_0(w_alu_res_1_0_a2_1[0]), |
.w_alu_res_1_0_a2_1_1(w_alu_res_1_0_a2_1[1]), |
.dout_4(mem_man_dout[4]), |
.dout_7(mem_man_dout[7]), |
.dout_5(mem_man_dout[5]), |
.dout_3(mem_man_dout[3]), |
.dout_2(mem_man_dout[2]), |
.dout_6(mem_man_dout[6]), |
.dout_0(mem_man_dout[0]), |
.dout_1(mem_man_dout[1]), |
.w_alu_res_1_0_a2_2_0_0(w_alu_res_1_0_a2_2_0[0]), |
.w_alu_res_1_0_a2_2_0_1(w_alu_res_1_0_a2_2_0[1]), |
.w_alu_res_1_0_0_0(w_alu_res_1_0_0[2]), |
.w_alu_res_1_0_a2_0_0(w_alu_res_1_0_a2_0[0]), |
.w_alu_res_1_0_a2_0_1(w_alu_res_1_0_a2_0[1]), |
.w_alu_res_1_0_a2_0_2(w_alu_res_1_0_a2_0[2]), |
.w_alu_res_1_1_a_0(w_alu_res_1_1_a[3]), |
.w_alu_res_1_1_1_0(w_alu_res_1_1_1[3]), |
.w_alu_res_1_3_a_0(w_alu_res_1_3_a[4]), |
.w_alu_res_1_3_1_0(w_alu_res_1_3_1[4]), |
.w_alu_res_1_6_a_2(w_alu_res_1_6_a[7]), |
.w_alu_res_1_6_a_0(w_alu_res_1_6_a[5]), |
.w_alu_res_1_6_a_1(w_alu_res_1_6_a[6]), |
.w_alu_res_1_6_1_2(w_alu_res_1_6_1[7]), |
.w_alu_res_1_6_1_0(w_alu_res_1_6_1[5]), |
.w_alu_res_1_6_1_1(w_alu_res_1_6_1[6]), |
.in1_c_7(in1_c[7]), |
.in1_c_6(in1_c[6]), |
.in1_c_5(in1_c[5]), |
.in1_c_4(in1_c[4]), |
.in1_c_3(in1_c[3]), |
.in1_c_2(in1_c[2]), |
.in1_c_1(in1_c[1]), |
.in1_c_0(in1_c[0]), |
.w_ek_r_4(w_ek_r[4]), |
.w_ek_r_3(w_ek_r[3]), |
.w_ek_r_2(w_ek_r[2]), |
.w_ek_r_1(w_ek_r[1]), |
.w_ek_r_0(w_ek_r[0]), |
.write_out0_0_a3_0_o2(mem_man_write_out0_0_a3_0_o2), |
.rst_c(rst_c), |
.un11_w_alu_res_carry_7(un11_w_alu_res_carry_7), |
.w_c_2mem_i_a2_0_0(w_c_2mem_i_a2_0_0), |
.N_796(N_796), |
.w_c_wr_r(w_c_wr_r), |
.w_z_0_a2(w_z_0_a2), |
.w_z_wr_r(w_z_wr_r), |
.G_287(G_287), |
.G_279(G_279), |
.G_271(G_271), |
.rst_i_i(rst_i_i), |
.un11_w_alu_res_add7(un11_w_alu_res_add7), |
.un11_w_alu_res_add3(un11_w_alu_res_add3), |
.un11_w_alu_res_add4(un11_w_alu_res_add4), |
.un11_w_alu_res_add5(un11_w_alu_res_add5), |
.un11_w_alu_res_add6(un11_w_alu_res_add6), |
.w_c_2mem_i_a3(w_c_2mem_i_a3), |
.w_mem_wr_r(w_mem_wr_r), |
.clk_c(clk_c) |
); |
// @11:209 |
pram program_rom ( |
.sclrsclrw_pc_nxt_0_0_a2_x_0(sclrsclrw_pc_nxt_0_0_a2_x[0]), |
.sclrsclrw_pc_nxt_0_0_a2_x_1(sclrsclrw_pc_nxt_0_0_a2_x[1]), |
.sclrsclrw_pc_nxt_0_0_a2_x_2(sclrsclrw_pc_nxt_0_0_a2_x[2]), |
.sclrsclrw_pc_nxt_0_0_a2_x_3(sclrsclrw_pc_nxt_0_0_a2_x[3]), |
.sclrsclrw_pc_nxt_0_0_a2_x_4(sclrsclrw_pc_nxt_0_0_a2_x[4]), |
.sclrsclrw_pc_nxt_0_0_a2_x_5(sclrsclrw_pc_nxt_0_0_a2_x[5]), |
.sclrsclrw_pc_nxt_0_0_a2_x_6(sclrsclrw_pc_nxt_0_0_a2_x[6]), |
.w_ins_0(w_ins[0]), |
.w_ins_1(w_ins[1]), |
.w_ins_2(w_ins[2]), |
.w_ins_3(w_ins[3]), |
.w_ins_4(w_ins[4]), |
.w_ins_6(w_ins[6]), |
.w_ins_7(w_ins[7]), |
.clk_c(clk_c), |
.w_mem_wr(w_mem_wr) |
); |
endmodule /* ClaiRISC_core */ |
|
/trunk/SYN/rev_1/ClaiRISC_core_cons.tcl
0,0 → 1,6
source "C:/Program Files/Synplicity/fpga_81/lib/altera/quartus_cons.tcl" |
syn_create_and_open_prj ClaiRISC_core |
source $::quartus(binpath)/prj_asd_import.tcl |
syn_create_and_open_csf ClaiRISC_core |
syn_handle_cons ClaiRISC_core |
syn_compile_quartus |
/trunk/SYN/rev_1/rpt_ClaiRISC_core.areasrr
0,0 → 1,286
#### START OF AREA REPORT #####[ |
|
Part: EP1C6QC240-6 (Altera) |
|
----------------------------------------------------------------------------- |
######## Utilization report for Top level view: ClaiRISC_core ######## |
============================================================================= |
|
SEQUENTIAL ATOMS |
**************** |
|
Name Total elements Utilization Notes |
------------------------------------------------------ |
REGISTERS 88 100 % |
====================================================== |
Total SEQUENTIAL ATOMS in the block ClaiRISC_core: 88 (27.94 % Utilization) |
|
|
COMBINATIONAL ATOMS |
******************* |
|
Name Total elements Utilization Notes |
------------------------------------------------------------ |
ATOMS 118 100 % |
ARITHMETIC MODE 33 100 % |
============================================================ |
Total COMBINATIONAL ATOMS in the block ClaiRISC_core: 151 (47.94 % Utilization) |
|
|
RAMS |
**** |
|
Name Total elements Number of bits Utilization Notes |
------------------------------------------------------------------------- |
SYNC RAMS 0 0 0.0 % |
LPMs 2 2 100 % |
========================================================================= |
Total RAMS in the block ClaiRISC_core: 2 (0.63 % Utilization) |
|
|
DSPs |
**** |
|
Name Total elements Utilization Notes |
------------------------------------------------- |
MACs 0 0.0 % |
================================================= |
Total DSPs in the block ClaiRISC_core: 0 (0.00 % Utilization) |
|
|
Black Boxes |
*********** |
|
Name Total elements Utilization Notes |
-------------------------------------------------------- |
BLACK BOXES 0 0.0 % |
======================================================== |
Total Black Boxes in the block ClaiRISC_core: 0 (0.00 % Utilization) |
|
---------------------------------------------------------- |
######## Utilization report for cell: pram ######## |
Instance path: ClaiRISC_core.pram |
========================================================== |
|
SEQUENTIAL ATOMS |
**************** |
|
Name Total elements Utilization Notes |
------------------------------------------------------ |
REGISTERS 0 0.0 % |
====================================================== |
Total SEQUENTIAL ATOMS in the block ClaiRISC_core.pram: 0 (0.00 % Utilization) |
|
|
COMBINATIONAL ATOMS |
******************* |
|
Name Total elements Utilization Notes |
------------------------------------------------------------ |
ATOMS 0 0.0 % |
ARITHMETIC MODE 0 0.0 % |
============================================================ |
Total COMBINATIONAL ATOMS in the block ClaiRISC_core.pram: 0 (0.00 % Utilization) |
|
|
RAMS |
**** |
|
Name Total elements Number of bits Utilization Notes |
------------------------------------------------------------------------- |
SYNC RAMS 0 0 0.0 % |
LPMs 1 1 50. % |
========================================================================= |
Total RAMS in the block ClaiRISC_core.pram: 1 (0.32 % Utilization) |
|
|
DSPs |
**** |
|
Name Total elements Utilization Notes |
------------------------------------------------- |
MACs 0 0.0 % |
================================================= |
Total DSPs in the block ClaiRISC_core.pram: 0 (0.00 % Utilization) |
|
|
Black Boxes |
*********** |
|
Name Total elements Utilization Notes |
-------------------------------------------------------- |
BLACK BOXES 0 0.0 % |
======================================================== |
Total Black Boxes in the block ClaiRISC_core.pram: 0 (0.00 % Utilization) |
|
--------------------------------------------------------------- |
######## Utilization report for cell: rom128x12 ######## |
Instance path: pram.rom128x12 |
=============================================================== |
|
SEQUENTIAL ATOMS |
**************** |
|
Name Total elements Utilization Notes |
------------------------------------------------------ |
REGISTERS 0 0.0 % |
====================================================== |
Total SEQUENTIAL ATOMS in the block pram.rom128x12: 0 (0.00 % Utilization) |
|
|
COMBINATIONAL ATOMS |
******************* |
|
Name Total elements Utilization Notes |
------------------------------------------------------------ |
ATOMS 0 0.0 % |
ARITHMETIC MODE 0 0.0 % |
============================================================ |
Total COMBINATIONAL ATOMS in the block pram.rom128x12: 0 (0.00 % Utilization) |
|
|
RAMS |
**** |
|
Name Total elements Number of bits Utilization Notes |
------------------------------------------------------------------------- |
SYNC RAMS 0 0 0.0 % |
LPMs 1 1 50. % |
========================================================================= |
Total RAMS in the block pram.rom128x12: 1 (0.32 % Utilization) |
|
|
DSPs |
**** |
|
Name Total elements Utilization Notes |
------------------------------------------------- |
MACs 0 0.0 % |
================================================= |
Total DSPs in the block pram.rom128x12: 0 (0.00 % Utilization) |
|
|
Black Boxes |
*********** |
|
Name Total elements Utilization Notes |
-------------------------------------------------------- |
BLACK BOXES 0 0.0 % |
======================================================== |
Total Black Boxes in the block pram.rom128x12: 0 (0.00 % Utilization) |
|
---------------------------------------------------------------- |
######## Utilization report for cell: wb_mem_man ######## |
Instance path: ClaiRISC_core.wb_mem_man |
================================================================ |
|
SEQUENTIAL ATOMS |
**************** |
|
Name Total elements Utilization Notes |
------------------------------------------------------ |
REGISTERS 61 69.3 % |
====================================================== |
Total SEQUENTIAL ATOMS in the block ClaiRISC_core.wb_mem_man: 61 (19.37 % Utilization) |
|
|
COMBINATIONAL ATOMS |
******************* |
|
Name Total elements Utilization Notes |
------------------------------------------------------------ |
ATOMS 44 37.3 % |
ARITHMETIC MODE 0 0.0 % |
============================================================ |
Total COMBINATIONAL ATOMS in the block ClaiRISC_core.wb_mem_man: 44 (13.97 % Utilization) |
|
|
RAMS |
**** |
|
Name Total elements Number of bits Utilization Notes |
------------------------------------------------------------------------- |
SYNC RAMS 0 0 0.0 % |
LPMs 1 1 50. % |
========================================================================= |
Total RAMS in the block ClaiRISC_core.wb_mem_man: 1 (0.32 % Utilization) |
|
|
DSPs |
**** |
|
Name Total elements Utilization Notes |
------------------------------------------------- |
MACs 0 0.0 % |
================================================= |
Total DSPs in the block ClaiRISC_core.wb_mem_man: 0 (0.00 % Utilization) |
|
|
Black Boxes |
*********** |
|
Name Total elements Utilization Notes |
-------------------------------------------------------- |
BLACK BOXES 0 0.0 % |
======================================================== |
Total Black Boxes in the block ClaiRISC_core.wb_mem_man: 0 (0.00 % Utilization) |
|
-------------------------------------------------------------- |
######## Utilization report for cell: ram128x8 ######## |
Instance path: wb_mem_man.ram128x8 |
============================================================== |
|
SEQUENTIAL ATOMS |
**************** |
|
Name Total elements Utilization Notes |
------------------------------------------------------ |
REGISTERS 0 0.0 % |
====================================================== |
Total SEQUENTIAL ATOMS in the block wb_mem_man.ram128x8: 0 (0.00 % Utilization) |
|
|
COMBINATIONAL ATOMS |
******************* |
|
Name Total elements Utilization Notes |
------------------------------------------------------------ |
ATOMS 0 0.0 % |
ARITHMETIC MODE 0 0.0 % |
============================================================ |
Total COMBINATIONAL ATOMS in the block wb_mem_man.ram128x8: 0 (0.00 % Utilization) |
|
|
RAMS |
**** |
|
Name Total elements Number of bits Utilization Notes |
------------------------------------------------------------------------- |
SYNC RAMS 0 0 0.0 % |
LPMs 1 1 50. % |
========================================================================= |
Total RAMS in the block wb_mem_man.ram128x8: 1 (0.32 % Utilization) |
|
|
DSPs |
**** |
|
Name Total elements Utilization Notes |
------------------------------------------------- |
MACs 0 0.0 % |
================================================= |
Total DSPs in the block wb_mem_man.ram128x8: 0 (0.00 % Utilization) |
|
|
Black Boxes |
*********** |
|
Name Total elements Utilization Notes |
-------------------------------------------------------- |
BLACK BOXES 0 0.0 % |
======================================================== |
Total Black Boxes in the block wb_mem_man.ram128x8: 0 (0.00 % Utilization) |
|
|
##### END OF AREA REPORT #####] |
|
/trunk/SYN/rev_1/AutoConstraint_ClaiRISC_core.sdc
0,0 → 1,4
|
#Begin clock constraint |
define_clock -name {b:ClaiRISC_core|clk} -period 8.288 -clockgroup Autoconstr_clkgroup_0 -rise 0.000 -fall 4.144 -route 0.000 |
#End clock constraint |
/trunk/SYN/rev_1/syntmp/rom256x12_flink.htm
0,0 → 1,9
<table border="0" cellpadding="0" cellspacing="2"> |
<tr> |
<td nowrap width="500" class="content" valign="top"> |
<body bgcolor="rgb(245,245,255)"> |
<font size=2 face="arial"> |
<a><b>Log File Links:</a></b><br> |
<a href="C:\Program Files\Synplicity\fpga_81\examples\stdout.log:@XP_FILE" target="srrFrame">Session Log</a><br> |
<br><b>rev_1</a></b><br> |
<br><b>rev_1\par_1</a></b><br> |
/trunk/SYN/rev_1/syntmp/ClaiRISC_core_cons_ui.tcl
0,0 → 1,5
source "C:/Program Files/Synplicity/fpga_81/lib/altera/quartus_cons.tcl" |
syn_create_and_open_prj ClaiRISC_core |
source $::quartus(binpath)/prj_asd_import.tcl |
syn_create_and_open_csf ClaiRISC_core |
syn_handle_cons ClaiRISC_core |
/trunk/SYN/rev_1/syntmp/ClaiRISC_core.plg
0,0 → 1,11
@P: Part : EP1C6QC240-6 |
@P: Worst Slack : -1.463 |
@P: ClaiRISC_core|clk - Estimated Frequency : 102.6 MHz |
@P: ClaiRISC_core|clk - Requested Frequency : 120.7 MHz |
@P: ClaiRISC_core|clk - Estimated Period : 9.750 |
@P: ClaiRISC_core|clk - Requested Period : 8.288 |
@P: ClaiRISC_core|clk - Slack : -1.463 |
@P: ClaiRISC_core Part : ep1c6qc240-6 |
@P: ClaiRISC_core I/O ATOMs : 34 |
@P: ClaiRISC_core Total LUTs: : 247 of 5980 ( 4%) |
@P: ClaiRISC_core Logic resources : 247 ATOMs of 5980 ( 4%) |
/trunk/SYN/rev_1/syntmp/ClaiRISC_core.msg
--- trunk/SYN/rev_1/syntmp/ClaiRISC_core_toc.htm (nonexistent)
+++ trunk/SYN/rev_1/syntmp/ClaiRISC_core_toc.htm (revision 9)
@@ -0,0 +1,8 @@
+
+
+
+
+
+
/trunk/SYN/rev_1/syntmp/ClaiRISC_core_srr.htm
0,0 → 1,67
/trunk/SYN/rev_1/verif/ClaiRISC_core.vif
0,0 → 1,149
/trunk/SYN/rev_1/verif/ClaiRISC_core_bb.v
0,0 → 1,44
/trunk/SYN/rev_1/rpt_ClaiRISC_core_areasrr.htm
0,0 → 1,317
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