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Rev 8 → Rev 9
/trunk/FIFO/fifo.vhdl
824,6 → 824,126
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
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------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
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-- Exactly teh same as FIFO_v5 but ieee.numeric_std.all is used |
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library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
--USE ieee.std_logic_signed.ALL; |
--USE ieee.std_logic_arith.ALL; |
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------------------------------------------------------------------------------- |
-- purpose: FIFO Architecture |
architecture FIFO_v6 of FIFO is |
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-- constant values |
constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1'); |
constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0'); |
constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) :="01111111";--(ADD_WIDTH -1 downto ADD_WIDTH -1 => '0' ,others => '1'); |
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signal R_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Read Address |
signal W_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Write Address |
signal D_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Diff Address |
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signal REN_INT : std_logic; -- Internal Read Enable |
signal WEN_INT : std_logic; -- Internal Write Enable |
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component dpmem |
generic (ADD_WIDTH : integer := 8; |
WIDTH : integer := 8 ); |
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port (clk : in std_logic; |
reset : in std_logic; |
w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 ); |
r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 ); |
data_in : in std_logic_vector(WIDTH - 1 downto 0); |
data_out : out std_logic_vector(WIDTH - 1 downto 0 ); |
WR : in std_logic; |
RE : in std_logic); |
end component; |
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begin -- FIFO_v6 |
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------------------------------------------------------------------------------- |
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memcore: dpmem |
generic map (WIDTH => 8, |
ADD_WIDTH =>8) |
port map (clk => clk, |
reset => reset, |
w_add => w_add, |
r_add => r_add, |
Data_in => data_in, |
data_out => data_out, |
wr => wen_int, |
re => ren_int); |
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------------------------------------------------------------------------------- |
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wen_int <= '1' when (WE = '1' and ( FULL = '0')) else '0'; |
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ren_int <= '1' when RE = '1' and ( EMPTY = '0') else '0'; |
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------------------------------------------------------------------------------- |
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Add_gen: process(clk,reset) |
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begin -- process ADD_gen |
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-- activities triggered by asynchronous reset (active low) |
if reset = '0' then |
W_ADD <= (others =>'0'); |
R_ADD <= (others =>'0'); |
D_ADD <= (others =>'0'); |
-- activities triggered by rising edge of clock |
elsif clk'event and clk = '1' then |
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if WE = '1' and ( FULL = '0') then |
W_ADD <= W_ADD + 1; |
D_ADD <= D_ADD +1; |
-- else |
-- W_ADD <= W_ADD; |
-- D_ADD <= D_ADD; |
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end if; |
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if RE = '1' and ( EMPTY = '0') then |
R_ADD <= R_ADD + 1; |
D_ADD <= D_ADD -1; |
-- else |
-- R_ADD <= R_ADD; |
-- D_ADD <= D_ADD; |
end if; |
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end if; |
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-- R_ADD <= q2; |
-- W_ADD <= q1; |
-- D_ADD <= q3; |
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end process ADD_gen; |
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------------------------------------------------------------------------------- |
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FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0'; |
EMPTY <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MIN_ADDR) else '0'; |
HALF_FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) > HALF_ADDR) else '0'; |
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------------------------------------------------------------------------------- |
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end FIFO_v6; |
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------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
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configuration fifo_conf of fifo is |
for fifo_v1 |
for memcore:dpmem |