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URL https://opencores.org/ocsvn/mpmc8/mpmc8/trunk

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Rev 8 → Rev 9

/mpmc8/trunk/rtl/mpmc10/mpcm10_cache_wb.sv
295,15 → 295,15
always_comb vbito7a[g] <= vbit[g][radrr[7][HIBIT:LOBIT]];
always_comb vbito8a[g] <= vbit[g][radrr[8][HIBIT:LOBIT]];
always_ff @(posedge ch0clk) hit0a[g] = (doutb[0].lines[g].tag==radrr[0][31:HIBIT+1]) && (vbito0a[g]==1'b1);
always_ff @(posedge ch1clk) hit1a[g] = (doutb[1].lines[g].tag==radrr[1][31:HIBIT+1]) && (vbito1a[g]==1'b1);
always_ff @(posedge ch2clk) hit2a[g] = (doutb[2].lines[g].tag==radrr[2][31:HIBIT+1]) && (vbito2a[g]==1'b1);
always_ff @(posedge ch3clk) hit3a[g] = (doutb[3].lines[g].tag==radrr[3][31:HIBIT+1]) && (vbito3a[g]==1'b1);
always_ff @(posedge ch4clk) hit4a[g] = (doutb[4].lines[g].tag==radrr[4][31:HIBIT+1]) && (vbito4a[g]==1'b1);
always_ff @(posedge ch5clk) hit5a[g] = (doutb[5].lines[g].tag==radrr[5][31:HIBIT+1]) && (vbito5a[g]==1'b1);
always_ff @(posedge ch6clk) hit6a[g] = (doutb[6].lines[g].tag==radrr[6][31:HIBIT+1]) && (vbito6a[g]==1'b1);
always_ff @(posedge ch7clk) hit7a[g] = (doutb[7].lines[g].tag==radrr[7][31:HIBIT+1]) && (vbito7a[g]==1'b1);
always_ff @(posedge wclk) hit8a[g] = (doutb[8].lines[g].tag==radrr[8][31:HIBIT+1]) && (vbito8a[g]==1'b1);
always_ff @(posedge ch0clk) hit0a[g] = (doutb[0].lines[g].tag==radrr[0][31:LOBIT]) && (vbito0a[g]==1'b1);
always_ff @(posedge ch1clk) hit1a[g] = (doutb[1].lines[g].tag==radrr[1][31:LOBIT]) && (vbito1a[g]==1'b1);
always_ff @(posedge ch2clk) hit2a[g] = (doutb[2].lines[g].tag==radrr[2][31:LOBIT]) && (vbito2a[g]==1'b1);
always_ff @(posedge ch3clk) hit3a[g] = (doutb[3].lines[g].tag==radrr[3][31:LOBIT]) && (vbito3a[g]==1'b1);
always_ff @(posedge ch4clk) hit4a[g] = (doutb[4].lines[g].tag==radrr[4][31:LOBIT]) && (vbito4a[g]==1'b1);
always_ff @(posedge ch5clk) hit5a[g] = (doutb[5].lines[g].tag==radrr[5][31:LOBIT]) && (vbito5a[g]==1'b1);
always_ff @(posedge ch6clk) hit6a[g] = (doutb[6].lines[g].tag==radrr[6][31:LOBIT]) && (vbito6a[g]==1'b1);
always_ff @(posedge ch7clk) hit7a[g] = (doutb[7].lines[g].tag==radrr[7][31:LOBIT]) && (vbito7a[g]==1'b1);
always_ff @(posedge wclk) hit8a[g] = (doutb[8].lines[g].tag==radrr[8][31:LOBIT]) && (vbito8a[g]==1'b1);
end
always_comb ch0o.ack = (|hit0a & stb0) | (ch0wack & stb0);
always_comb ch1o.ack = (|hit1a & stb1) | (ch1wack & stb1);
426,11 → 426,11
always_ff @(posedge wclk)
begin
if (ldcycd2) begin
wdata.lines[0].tag <= {5'd0,wadr2[31:HIBIT+1]}; // set tag
wdata.lines[0].tag <= wadr2[31:LOBIT]; // set tag
wdata.lines[1].tag <= t0;
wdata.lines[2].tag <= t1;
wdata.lines[3].tag <= t2;
wdata.lines[0].modified <= 1'b0; // clear modified flags
wdata.lines[0].modified <= 1'b0; // clear modified flags
wdata.lines[1].modified <= m0;
wdata.lines[2].modified <= m1;
wdata.lines[3].modified <= m2;
508,7 → 508,7
wack <= 1'b0;
else begin
wack <= 1'b0;
if (wchi.stb & ~ld.stb & wchi.we)
if (wchi_stb & ~ld.stb & wchi.we)
wack <= 1'b1;
end
assign wcho.ack = wack & wchi.stb;
/mpmc8/trunk/rtl/mpmc10/mpmc10_pkg.sv
44,26 → 44,29
parameter FALSE = 1'b0;
parameter CMD_READ = 3'b001;
parameter CMD_WRITE = 3'b000;
 
// State machine states
parameter IDLE = 4'd0;
parameter PRESET1 = 4'd1;
parameter PRESET2 = 4'd2;
parameter WRITE_DATA0 = 4'd3;
parameter WRITE_DATA1 = 4'd4;
parameter WRITE_DATA2 = 4'd5;
parameter WRITE_DATA3 = 4'd6;
parameter READ_DATA = 4'd7;
parameter READ_DATA0 = 4'd8;
parameter READ_DATA1 = 4'd9;
parameter READ_DATA2 = 4'd10;
parameter WAIT_NACK = 4'd11;
parameter WRITE_TRAMP = 4'd12; // write trampoline
parameter WRITE_TRAMP1 = 4'd13;
parameter PRESET3 = 4'd14;
typedef enum logic [3:0] {
IDLE = 4'd0,
PRESET1 = 4'd1,
PRESET2 = 4'd2,
WRITE_DATA0 = 4'd3,
WRITE_DATA1 = 4'd4,
WRITE_DATA2 = 4'd5,
WRITE_DATA3 = 4'd6,
READ_DATA = 4'd7,
READ_DATA0 = 4'd8,
READ_DATA1 = 4'd9,
READ_DATA2 = 4'd10,
WAIT_NACK = 4'd11,
WRITE_TRAMP = 4'd12, // write trampoline
WRITE_TRAMP1 = 4'd13,
PRESET3 = 4'd14
} mpmc10_state_t;
 
typedef struct packed
{
logic [18:0] tag;
logic [31:4] tag;
logic modified;
logic [127:0] data;
} mpmc10_cache_line_t;

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