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/openverifla/trunk/openverifla_2.0/java/VeriFLA.class Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

/openverifla/trunk/openverifla_2.0/java/VeriFLA.class

openverifla/trunk/openverifla_2.0/java/VeriFLA.class Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: openverifla/trunk/openverifla_2.0/java/VeriFLA.java =================================================================== --- openverifla/trunk/openverifla_2.0/java/VeriFLA.java (nonexistent) +++ openverifla/trunk/openverifla_2.0/java/VeriFLA.java (revision 9) @@ -0,0 +1,684 @@ +/* +VeriFLA.java +License: GNU GPL + +Revision history: +revistion date: 2018/07/20; author: Laurentiu Duca +- port of SerialPort jssc instead of rxtx +- redesign of memory contents implied modification in the java source +revision date: 2007/Sep/03; author: Laurentiu Duca +- sendMonResetAndRun feature +- consider that the bt_queue_head_address is wrote at the end of the data capture. +- use HOUR_OF_DAY (0..23) + +revision date: 2007/Jul/4; author: Laurentiu DUCA +- v01 +*/ + + +import java.io.IOException; +import java.io.InputStream; +import java.io.OutputStream; +import java.io.File; +import java.io.FileInputStream; +import java.io.FileOutputStream; +import java.io.FileNotFoundException; +import java.io.FileReader; +import java.io.BufferedReader; +import java.util.Properties; +import java.util.Enumeration; +import java.util.Calendar; +import java.util.GregorianCalendar; +import java.util.StringTokenizer; + +import jssc.SerialPort; +import jssc.SerialPortException; + +public class VeriFLA extends Object { + + // Data members are declared at the end. + + /** + * Creates a new object. + * + */ + public VeriFLA() { + this.serialPort = null; + this.properties = new Properties(); + } + + /** + * Attaches the given serial serialPort to the device object. + * The method will try to open the serialPort. + */ + public boolean attach(String portName) { + serialPort = new SerialPort(portName); + try { + serialPort.openPort();//Open serial port + serialPort.setParams(SerialPort.BAUDRATE_115200, + SerialPort.DATABITS_8, + SerialPort.STOPBITS_1, + SerialPort.PARITY_NONE); + //Set params. Also you can set params by this string: serialPort.setParams(9600, 8, 1, 0); + //serialPort.writeBytes("This is a test string".getBytes());//Write data to port + } catch (SerialPortException ex) { + ex.printStackTrace(System.out); + return false; + } + + return true; + } + + /** + * Detaches the currently attached serialPort, if one exists. + * This will close the serial port. + * + */ + public void detach() { + if (serialPort != null) { + try { + serialPort.closePort(); + } catch (SerialPortException ex) { + ex.printStackTrace(System.out); + } + } + } + + public void run() throws IOException, SerialPortException { + byte rawByte[]=new byte[1]; + + if(sendMonResetAndRun == 1) { + // Send USERCMD_RESET command + rawByte[0]=USERCMD_RESET; + System.out.println("Sending USERCMD_RESET command"); + serialPort.writeBytes(rawByte); + System.out.println("Done sending USERCMD_RESET command."); + + // Send USERCMD_RUN command + rawByte[0]=USERCMD_RUN; + System.out.println("Sending USERCMD_RUN command"); + serialPort.writeBytes(rawByte); + System.out.println("Done sending USERCMD_RUN command."); + } + + // Read Captured data + System.out.println("Waiting for data capture:"); + int i,j,ret; + rawByte = new byte[memWords * octetsPerWord]; + //rawByte = serialPort.readBytes(memWords * octetsPerWord); + for(i=0; i=0; j--) + System.out.printf("%02x ", memoryLineBytes[i][j]); + System.out.println(); + } + + //System.exit(1); + } + + public void getCapturedData(String portName) + { + boolean found; + found = attach(portName); + if(!found) { + System.out.println("Port " + portName + " not found.\n"+ + "\tPlease update the properties file.\n"); + System.exit(0); + } + try { + run(); + } catch (Exception ex) { + ex.printStackTrace(System.out); + } + detach(); + } + + public void saveCapturedData() throws IOException + { + // Create a new file with the name "capture_timestamp.v". + String strTime=getTime(); + String outputFileName, moduleName; + moduleName="capture_"+strTime; + outputFileName = moduleName+".v"; + File outputFile = new File(outputFileName); + if (!outputFile.createNewFile()) { + System.out.println("Error: Can not create file: " + outputFileName); + System.exit(-1); + } + OutputStream stream = new FileOutputStream(outputFile); + + + // Write the timescale directive. + String strLine; + int i,j,k; + strLine = "`timescale " + strTimescaleUnit + " / " + strTimescalePrecision + "\n\n"; + stream.write(strLine.getBytes()); + + + // Write the module name and output params. + strLine = "module " + moduleName + "(clk_of_verifla, la_trigger_matched, "; + for (i = 0; i < signalGroups; i++) { + strLine += groupName[i]; + if(i != (signalGroups - 1)) + strLine += ", "; + } + strLine += ", memory_line_id"; + strLine += ");\n\n"; + stream.write(strLine.getBytes()); + + + // Write the declaration of signals + strLine = "output clk_of_verifla;\n" + "output la_trigger_matched;\n" + "output ["+(memWords/4)+":0] memory_line_id;\n"; + stream.write(strLine.getBytes()); + for (k = 0; k < 2; k++) { + for (i = 0; i < signalGroups; i++) { + if(k == 0) + strLine = "output "; + else + strLine = "reg "; + if(groupSize[i] > 1) { + if(groupEndian[i] != 0) + strLine += "[0:"+(groupSize[i]-1)+"] "; + else + strLine += "["+(groupSize[i]-1)+":0] "; + } + strLine += groupName[i] + ";\n"; + stream.write(strLine.getBytes()); + } + } + strLine = + "reg ["+(memWords/4)+":0] memory_line_id;\n" + + "reg la_trigger_matched;\n" + + "reg clk_of_verifla;" + "\n\n" + + "parameter PERIOD = " + clockPeriod + ";" + "\n"; + stream.write(strLine.getBytes()); + + + // Write the clock task. + strLine = + "initial // Clock process for clk_of_verifla" + "\n" + + "begin" + "\n" + + " forever" + "\n" + + " begin" + "\n" + + " clk_of_verifla = 1'b0;" + "\n" + + " #("+ (int)(clockPeriod / 2) + "); clk_of_verifla = 1'b1;" + "\n" + + " #("+ (int)(clockPeriod / 2) + ");" + "\n" + + " end" + "\n" + + "end" + "\n\n" ; + stream.write(strLine.getBytes()); + + + // Write captured data + strLine = "initial begin\n"; + strLine += "#("+ (int)(clockPeriod / 2) + ");\n"; + strLine += "la_trigger_matched = 0;\n"; + stream.write(strLine.getBytes()); + + // Compute the name of the signals + String signalsToken; + signalsToken = "{"; + for (i = signalGroups-1; i >= 0 ; i--) { + signalsToken += groupName[i]; + if (i > 0) + signalsToken += ","; + } + signalsToken += "} = "; + + // Write name of the signals, values and delays in the verilog file. + String strWord; + int currentTime=(clockPeriod / 2), delay; + + // compute the oldest wrote-info before trigger event + int bt_queue_head_address=0, bt_queue_tail_address=0; + // the word at address (memWords-1) represents bt_queue_tail_address. + for(j = 0; j < (octetsPerWord-1); j++) { + bt_queue_tail_address += ((0x000000FF) & (int) memoryLineBytes[memWords-1][j]) << (8*j); + } + System.out.println("bt_queue_tail_address=" + bt_queue_tail_address); + // Find the first + // before the trigger event (not an memory word). + if(bt_queue_tail_address == (triggerMatchMemAddr - 1)) + bt_queue_head_address = 0; + else + bt_queue_head_address = bt_queue_tail_address + 1; + boolean before_trigger=true; + boolean foundAnEffectiveCaptureWord=false, wentBack=false; + i = bt_queue_head_address; + do + { + for(j = 0; j < (octetsPerWord-1); j++) { + if(memoryLineBytes[i][j] != 0) + foundAnEffectiveCaptureWord = true; + } + if(foundAnEffectiveCaptureWord) + break; + i++; + if(i >= triggerMatchMemAddr) + if(!foundAnEffectiveCaptureWord && !wentBack) { + i = 0; + wentBack = true; + } + } while (i <= triggerMatchMemAddr); + if(!foundAnEffectiveCaptureWord) + fatalError("Could not find the first efffective capture before trigger match"); + if(i >= triggerMatchMemAddr) + before_trigger=false; + + // Walk through the captured data and write it to capture.v + do { + // Check if this is an empty line + boolean allMemoryLineIsZero=true; + for(j=octetsPerWord-1; j>=0; j--) { + if(memoryLineBytes[i][j] != 0) { + allMemoryLineIsZero = false; + break; + } + } + if(allMemoryLineIsZero) { + if(debugVeriFLA) { + strLine = "// info: line "+i+" is empty.\n"; + System.out.println(strLine); + stream.write(strLine.getBytes()); + } + } else { + // Write memory line index. + strLine = "memory_line_id=" + i + ";\n"; + stream.write(strLine.getBytes()); + // Data capture + strWord = totalSignals + "'b"; + for(j=octetsPerWord-1; j>=0; j--) { + if((j * 8) < dataWordLenBits) + for(k=7; k>=0; k--) { + if((j*8+k) < totalSignals) { + strWord += (memoryLineBytes[i][j] >> k) & 1; + } + } + } + strWord += ';'; + strLine = signalsToken + strWord + "\n"; + if(i == triggerMatchMemAddr) + strLine += "la_trigger_matched = 1;\n"; + //strLine += "#" + clockPeriod + ";\n"; + // Write to file + //System.out.println(strLine); + stream.write(strLine.getBytes()); + + + // Time interval in which data is constant. + delay=0; + for(j = 0; j < octetsPerWord; j++) { + if((j * 8) >= dataWordLenBits) + delay += ((0x000000FF) & (int) memoryLineBytes[i][j]) << (8*j - dataWordLenBits); + } + currentTime += delay * clockPeriod; + strLine = "#" + (delay * clockPeriod) + ";\n"; + // Write to file + //System.out.println(strLine); + stream.write(strLine.getBytes()); + // Also write the time stamp + strLine = "// ------------- Current Time: " + currentTime + "*(" + strTimescaleUnit + ") "+"\n"; + stream.write(strLine.getBytes()); + } + + // Compute the new value of i + if(before_trigger) { + i = (i+1) % triggerMatchMemAddr; + if(i == bt_queue_head_address) { + before_trigger = false; + i = triggerMatchMemAddr; + } + } + else + i = i + 1; + } while (i < (memWords-1)); + + strLine = "$stop;\nend\nendmodule\n"; + stream.write(strLine.getBytes()); + + // Write raw memory information. + strLine = "/*\n"+STR_ORIGINAL_CAPTURE_DUMP+"\n"; + for(i=0; i=0; j--) { + //strLine += "["+j+"]"+" " + Integer.toHexString(memoryLineBytes[i][j]) + " "; + if((0x000000FF & (int) memoryLineBytes[i][j]) <= 0x0F) + strLine += "0"; + strLine += Integer.toHexString( + 0x000000FF & (int) memoryLineBytes[i][j]).toUpperCase() + " "; + } + strLine += "\n"; + } +/* + for(i=0; i=0; j--) { + if((0x000000FF & (int) memoryLineBytes[i][j]) <= 0x0F) + strLine += "0"; + strLine += Integer.toHexString( + 0x000000FF & (int) memoryLineBytes[i][j]).toUpperCase() + " "; + } + strLine += "\n"; + stream.write(strLine.getBytes()); + } +*/ + strLine += "*/\n"; + stream.write(strLine.getBytes()); + + stream.close(); + System.out.println("Job done. Please simulate " + outputFileName); + } + + private void allocateMemory() + { + // Allocate memory + int i,j; + memoryLineBytes = new byte[memWords][]; + for(i=0; i=0; j--) { + memoryLineBytes[i][j] = (byte) Integer.parseInt(st.nextToken(), 16); + } + i++; + if(i >= memWords) + allMemoryRead = true; + //} + //else + //if (line.startsWith(STR_ORIGINAL_CAPTURE_DUMP)) { + // startOfMemory=true; + // i = 0; + //} + } while (!allMemoryRead); + } catch (Exception e) { + e.printStackTrace(); + fatalError("rebuildCapturedDataFromFile exception"); + } + } + + public void job(String propertiesFileName, String strRebuildFileName) + { + getProperties(propertiesFileName); + allocateMemory(); + if(strRebuildFileName == null) + getCapturedData(portName); + else + rebuildCapturedDataFromFile(strRebuildFileName); + try { + saveCapturedData(); + } catch (IOException e) { + e.printStackTrace(); + fatalError("Error saving Captured Data"); + } + } + + public static void fatalError(String errorName) + { + System.out.println("Fatal error: " + errorName); + System.exit(-1); + } + + public void getProperties(String fileName) + { + File f; + f = new File(fileName); + if (!f.isFile()) { + System.out.println("Error: File does not exist: " + fileName); + System.exit(-1); + } + + InputStream stream; + try { + stream = new FileInputStream(f); + try { + properties.load(stream); + } catch (IOException e) { + fatalError("IOException " + fileName); + } + } catch (FileNotFoundException e) { + fatalError("FileNotFoundException "+ fileName); + } + + String strVal; + portName = properties.getProperty(NAME + ".portName"); + if(portName == null) + fatalError("Properties: missing portName"); + + // time units + strTimescaleUnit=properties.getProperty(NAME + ".timescaleUnit"); + strTimescalePrecision=properties.getProperty(NAME + ".timescalePrecision"); + if(strTimescaleUnit == null || strTimescalePrecision == null) + fatalError("Properties: Not found timescale - unit or precision"); + // clockPeriod + strVal=properties.getProperty(NAME + ".clockPeriod"); + if(strVal != null) + clockPeriod=Integer.parseInt(strVal); + else + fatalError("Properties: clockPeriod not found"); + + // User signals + strVal=properties.getProperty(NAME + ".totalSignals"); + if(strVal != null) + totalSignals=Integer.parseInt(strVal); + else + fatalError("Properties: endian not found"); + // Groups of signals + strVal=properties.getProperty(NAME + ".signalGroups"); + if(strVal != null) + signalGroups=Integer.parseInt(strVal); + else + fatalError("Properties: signalGroups not found"); + groupName=new String[signalGroups]; + groupSize=new int[signalGroups]; + groupEndian=new int[signalGroups]; + int i; + int sumOfSignals=0; + for (i=0; i < signalGroups; i++) + { + String strGroupName, strGroupSize, strGroupEndian; + strGroupName=properties.getProperty(NAME + ".groupName."+i); + strGroupSize=properties.getProperty(NAME + ".groupSize."+i); + strGroupEndian=properties.getProperty(NAME + ".groupEndian."+i); + if(strGroupName == null || strGroupSize == null || strGroupEndian == null) + fatalError("Properties: group " + i + " not found groupName or groupSize or groupEndian"); + else { + groupName[i]=strGroupName; + groupSize[i]=Integer.parseInt(strGroupSize); + sumOfSignals += groupSize[i]; + groupEndian[i]=Integer.parseInt(strGroupEndian); + } + } + if(sumOfSignals != totalSignals) + fatalError("Properties: totalSignals != sum of all group sizes: " + totalSignals + " != "+sumOfSignals); + + + // Memory + strVal=properties.getProperty(NAME + ".memWords"); + if(strVal != null) + memWords=Integer.parseInt(strVal); + else + fatalError("Properties: memWords not found"); + strVal=properties.getProperty(NAME + ".dataWordLenBits"); + if(strVal != null) + dataWordLenBits=Integer.parseInt(strVal); + else + fatalError("Properties: dataWordLenBits not found"); + if((dataWordLenBits % 8) != 0) + fatalError("Properties: dataWordLenBits is not multiple of 8"); + strVal=properties.getProperty(NAME + ".clonesWordLenBits"); + if(strVal != null) + clonesWordLenBits=Integer.parseInt(strVal); + else + fatalError("Properties: clonesWordLenBits not found"); + if((clonesWordLenBits % 8) != 0) + fatalError("Properties: clonesWordLenBits is not multiple of 8"); + memWordLenBits = dataWordLenBits + clonesWordLenBits; + // Compute sizes + // octetsPerWord + octetsPerWord = memWordLenBits / 8; + if (memWordLenBits % 8 > 0) + octetsPerWord++; + totalmemoryDataBytes = memWords*octetsPerWord; + // Trigger + strVal=properties.getProperty(NAME + ".triggerMatchMemAddr"); + if(strVal != null) + triggerMatchMemAddr=Integer.parseInt(strVal); + else + fatalError("Properties: triggerMatchMemAddr not found"); +/* + strVal=properties.getProperty(NAME + ".maxSamplesAfterTrigger"); + if(strVal != null) + maxSamplesAfterTrigger=Integer.parseInt(strVal); + else + fatalError("Properties: maxSamplesAfterTrigger not found"); + + // triggerLastValue + strVal=properties.getProperty(NAME + ".triggerLastValue"); + if(strVal != null) { + StringTokenizer st; + int j, tNo; + st = new StringTokenizer(strVal," "); + tNo= st.countTokens(); + if(tNo != octetsPerWord) + fatalError("triggerLastValue " + " tNo != octetsPerWord: " + tNo + " != " + octetsPerWord); + triggerLastValue = new int[octetsPerWord]; + for(j=octetsPerWord-1; j>=0; j--) { + triggerLastValue[j] = (byte) Integer.parseInt(st.nextToken(), 16); + } + } + else + fatalError("Properties: triggerLastValue not found"); +*/ + } + + public String getTime() + { + Calendar calendar=new GregorianCalendar(); + String strTime; + int field; + strTime = "" + calendar.get(Calendar.YEAR); + field = 1 + calendar.get(Calendar.MONTH); + if(field < 10) + strTime += "0"; + strTime += field; + if(calendar.get(Calendar.DAY_OF_MONTH) < 10) + strTime += "0"; + strTime += calendar.get(Calendar.DAY_OF_MONTH) + "_" ; + if(calendar.get(Calendar.HOUR_OF_DAY) < 10) + strTime += "0"; + strTime += calendar.get(Calendar.HOUR_OF_DAY); + if(calendar.get(Calendar.MINUTE) < 10) + strTime += "0"; + strTime += calendar.get(Calendar.MINUTE) + "_"; + if(calendar.get(Calendar.SECOND) < 10) + strTime += "0"; + strTime += calendar.get(Calendar.SECOND) ; + System.out.println("date and time: "+strTime); + return strTime; + } + + public static void main(String[] args) throws Exception + { + if(args.length < 1) + VeriFLA.fatalError("Too few arguments: "+args.length+ + "\nSintax is:\n\tjava VeriFLA [=0/1 (default 0)] [sourceToRebuild_capture]\n"+ + "Examples:\n1. Wait for FPGA to send capture:\n\tjava VeriFLA verifla_properties_keyboard.txt\n"+ + "2. Send to the monitor reset and run and wait for FPGA to send capture:\n\tjava VeriFLA verifla_properties_keyboard.txt 1\n" + ); + // 1st arg. + System.out.println("propertiesFileName = " + args[0]); + // 2nd arg. + sendMonResetAndRun = 0; + if(args.length >= 2) { + System.out.println(" sendMonResetAndRun = " + args[1]); + sendMonResetAndRun = Integer.parseInt(args[1]); + } + // 3rd arg. + String sourceToRebuildCaptureFile=null; + if(args.length >= 3) { + System.out.println(" sourceToRebuild_capture = " + args[2]); + sourceToRebuildCaptureFile = args[2]; + } + VeriFLA verifla; + verifla = new VeriFLA(); + verifla.job(args[0], sourceToRebuildCaptureFile); + } + + // This java app. data members + boolean debugVeriFLA=true; + + String propertiesFileName; + Properties properties; + SerialPort serialPort; + final static String NAME = "LA"; + final static String STR_ORIGINAL_CAPTURE_DUMP = "ORIGINAL CAPTURE DUMP"; + final static int USERCMD_RESET=0x00, USERCMD_RUN = 0x01; + byte [][] memoryLineBytes; + int octetsPerWord, totalmemoryDataBytes; + int totalSignals; + public static int sendMonResetAndRun=0; + int clockPeriod; + + // Properties file members + String portName; + int memWords, memWordLenBits, dataWordLenBits, clonesWordLenBits, + triggerMatchMemAddr, maxSamplesAfterTrigger; + //int [] triggerLastValue; + String strTimescaleUnit, strTimescalePrecision; + int signalGroups; + String [] groupName; + int [] groupSize, groupEndian; +} Index: openverifla/trunk/openverifla_2.0/java/capture_20180802_1832_35.v =================================================================== --- openverifla/trunk/openverifla_2.0/java/capture_20180802_1832_35.v (nonexistent) +++ openverifla/trunk/openverifla_2.0/java/capture_20180802_1832_35.v (revision 9) @@ -0,0 +1,356 @@ +`timescale 1ns / 10ps + +module capture_20180802_1832_35(clk_of_verifla, la_trigger_matched, KBD_KEY, kbd_clk_line, kbd_data_line, not_used, memory_line_id); + +output clk_of_verifla; +output la_trigger_matched; +output [16:0] memory_line_id; +output [7:0] KBD_KEY; +output kbd_clk_line; +output kbd_data_line; +output [5:0] not_used; +reg [7:0] KBD_KEY; +reg kbd_clk_line; +reg kbd_data_line; +reg [5:0] not_used; +reg [16:0] memory_line_id; +reg la_trigger_matched; +reg clk_of_verifla; + +parameter PERIOD = 20; +initial // Clock process for clk_of_verifla +begin + forever + begin + clk_of_verifla = 1'b0; + #(10); clk_of_verifla = 1'b1; + #(10); + end +end + +initial begin +#(10); +la_trigger_matched = 0; +memory_line_id=0; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000; +#1310660; +// ------------- Current Time: 1310670*(1ns) +memory_line_id=1; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000; +#1310660; +// ------------- Current Time: 2621330*(1ns) +memory_line_id=2; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000; +#1310660; +// ------------- Current Time: 3931990*(1ns) +memory_line_id=3; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000; +#1310660; +// ------------- Current Time: 5242650*(1ns) +memory_line_id=4; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000; +#1310660; +// ------------- Current Time: 6553310*(1ns) +memory_line_id=5; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000; +#1310660; +// ------------- Current Time: 7863970*(1ns) +memory_line_id=6; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000; +#554200; +// ------------- Current Time: 8418170*(1ns) +memory_line_id=7; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000000100000000; +#11460; +// ------------- Current Time: 8429630*(1ns) +memory_line_id=8; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000000000000000; +la_trigger_matched = 1; +#60; +// ------------- Current Time: 8429690*(1ns) +memory_line_id=9; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000010000000000; +#43900; +// ------------- Current Time: 8473590*(1ns) +memory_line_id=10; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000010100000000; +#34020; +// ------------- Current Time: 8507610*(1ns) +memory_line_id=11; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000010000000000; +#60; +// ------------- Current Time: 8507670*(1ns) +memory_line_id=12; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000100000000000; +#42880; +// ------------- Current Time: 8550550*(1ns) +memory_line_id=13; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000100100000000; +#34020; +// ------------- Current Time: 8584570*(1ns) +memory_line_id=14; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000100000000000; +#60; +// ------------- Current Time: 8584630*(1ns) +memory_line_id=15; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000110000000000; +#42880; +// ------------- Current Time: 8627510*(1ns) +memory_line_id=16; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000110100000000; +#11380; +// ------------- Current Time: 8638890*(1ns) +memory_line_id=17; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000111100000000; +#24700; +// ------------- Current Time: 8663590*(1ns) +memory_line_id=18; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000111000000000; +#60; +// ------------- Current Time: 8663650*(1ns) +memory_line_id=19; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001001010000000; +#42840; +// ------------- Current Time: 8706490*(1ns) +memory_line_id=20; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001001110000000; +#36140; +// ------------- Current Time: 8742630*(1ns) +memory_line_id=21; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001001010000000; +#60; +// ------------- Current Time: 8742690*(1ns) +memory_line_id=22; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001011011000000; +#42840; +// ------------- Current Time: 8785530*(1ns) +memory_line_id=23; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001011111000000; +#36140; +// ------------- Current Time: 8821670*(1ns) +memory_line_id=24; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001011011000000; +#60; +// ------------- Current Time: 8821730*(1ns) +memory_line_id=25; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001101011100000; +#42820; +// ------------- Current Time: 8864550*(1ns) +memory_line_id=26; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001101111100000; +#12220; +// ------------- Current Time: 8876770*(1ns) +memory_line_id=27; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001100111100000; +#21860; +// ------------- Current Time: 8898630*(1ns) +memory_line_id=28; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001100011100000; +#60; +// ------------- Current Time: 8898690*(1ns) +memory_line_id=29; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001110001110000; +#42880; +// ------------- Current Time: 8941570*(1ns) +memory_line_id=30; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001110101110000; +#34020; +// ------------- Current Time: 8975590*(1ns) +memory_line_id=31; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001110001110000; +#60; +// ------------- Current Time: 8975650*(1ns) +memory_line_id=32; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010000000111000; +#42860; +// ------------- Current Time: 9018510*(1ns) +memory_line_id=33; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010000100111000; +#34020; +// ------------- Current Time: 9052530*(1ns) +memory_line_id=34; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010000000111000; +#60; +// ------------- Current Time: 9052590*(1ns) +memory_line_id=35; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010010000011100; +#43920; +// ------------- Current Time: 9096510*(1ns) +memory_line_id=36; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010010100011100; +#41300; +// ------------- Current Time: 9137810*(1ns) +memory_line_id=37; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010010000011100; +#60; +// ------------- Current Time: 9137870*(1ns) +memory_line_id=38; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010100000011100; +#42880; +// ------------- Current Time: 9180750*(1ns) +memory_line_id=39; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010100100011100; +#11380; +// ------------- Current Time: 9192130*(1ns) +memory_line_id=40; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010101100011100; +#29900; +// ------------- Current Time: 9222030*(1ns) +memory_line_id=41; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010101000011100; +#60; +// ------------- Current Time: 9222090*(1ns) +memory_line_id=42; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111000011100; +#49080; +// ------------- Current Time: 9271170*(1ns) +memory_line_id=43; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 10581830*(1ns) +memory_line_id=44; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 11892490*(1ns) +memory_line_id=45; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 13203150*(1ns) +memory_line_id=46; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 14513810*(1ns) +memory_line_id=47; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 15824470*(1ns) +memory_line_id=48; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 17135130*(1ns) +memory_line_id=49; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 18445790*(1ns) +memory_line_id=50; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 19756450*(1ns) +memory_line_id=51; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 21067110*(1ns) +memory_line_id=52; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 22377770*(1ns) +memory_line_id=53; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 23688430*(1ns) +memory_line_id=54; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 24999090*(1ns) +memory_line_id=55; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 26309750*(1ns) +memory_line_id=56; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 27620410*(1ns) +memory_line_id=57; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 28931070*(1ns) +memory_line_id=58; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 30241730*(1ns) +memory_line_id=59; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 31552390*(1ns) +memory_line_id=60; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 32863050*(1ns) +memory_line_id=61; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 34173710*(1ns) +memory_line_id=62; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 35484370*(1ns) +$stop; +end +endmodule +/* +ORIGINAL CAPTURE DUMP +memory_line_id=0: FF FD 03 00 +memory_line_id=1: FF FD 03 00 +memory_line_id=2: FF FD 03 00 +memory_line_id=3: FF FD 03 00 +memory_line_id=4: FF FD 03 00 +memory_line_id=5: FF FD 03 00 +memory_line_id=6: 6C 3E 03 00 +memory_line_id=7: 02 3D 01 00 +memory_line_id=8: 00 03 00 00 +memory_line_id=9: 08 93 04 00 +memory_line_id=10: 06 A5 05 00 +memory_line_id=11: 00 03 04 00 +memory_line_id=12: 08 60 08 00 +memory_line_id=13: 06 A5 09 00 +memory_line_id=14: 00 03 08 00 +memory_line_id=15: 08 60 0C 00 +memory_line_id=16: 02 39 0D 00 +memory_line_id=17: 04 D3 0F 00 +memory_line_id=18: 00 03 0E 00 +memory_line_id=19: 08 5E 12 80 +memory_line_id=20: 07 0F 13 80 +memory_line_id=21: 00 03 12 80 +memory_line_id=22: 08 5E 16 C0 +memory_line_id=23: 07 0F 17 C0 +memory_line_id=24: 00 03 16 C0 +memory_line_id=25: 08 5D 1A E0 +memory_line_id=26: 02 63 1B E0 +memory_line_id=27: 04 45 19 E0 +memory_line_id=28: 00 03 18 E0 +memory_line_id=29: 08 60 1C 70 +memory_line_id=30: 06 A5 1D 70 +memory_line_id=31: 00 03 1C 70 +memory_line_id=32: 08 5F 20 38 +memory_line_id=33: 06 A5 21 38 +memory_line_id=34: 00 03 20 38 +memory_line_id=35: 08 94 24 1C +memory_line_id=36: 08 11 25 1C +memory_line_id=37: 00 03 24 1C +memory_line_id=38: 08 60 28 1C +memory_line_id=39: 02 39 29 1C +memory_line_id=40: 05 D7 2B 1C +memory_line_id=41: 00 03 2A 1C +memory_line_id=42: 09 96 2E 1C +memory_line_id=43: FF FD 2F 1C +memory_line_id=44: FF FD 2F 1C +memory_line_id=45: FF FD 2F 1C +memory_line_id=46: FF FD 2F 1C +memory_line_id=47: FF FD 2F 1C +memory_line_id=48: FF FD 2F 1C +memory_line_id=49: FF FD 2F 1C +memory_line_id=50: FF FD 2F 1C +memory_line_id=51: FF FD 2F 1C +memory_line_id=52: FF FD 2F 1C +memory_line_id=53: FF FD 2F 1C +memory_line_id=54: FF FD 2F 1C +memory_line_id=55: FF FD 2F 1C +memory_line_id=56: FF FD 2F 1C +memory_line_id=57: FF FD 2F 1C +memory_line_id=58: FF FD 2F 1C +memory_line_id=59: FF FD 2F 1C +memory_line_id=60: FF FD 2F 1C +memory_line_id=61: FF FD 2F 1C +memory_line_id=62: FF FD 2F 1C +memory_line_id=63: 00 00 00 07 +*/ Index: openverifla/trunk/openverifla_2.0/java/capture_20180804_1024_17.v =================================================================== --- openverifla/trunk/openverifla_2.0/java/capture_20180804_1024_17.v (nonexistent) +++ openverifla/trunk/openverifla_2.0/java/capture_20180804_1024_17.v (revision 9) @@ -0,0 +1,356 @@ +`timescale 1ns / 10ps + +module capture_20180804_1024_17(clk_of_verifla, la_trigger_matched, KBD_KEY, kbd_clk_line, kbd_data_line, not_used, memory_line_id); + +output clk_of_verifla; +output la_trigger_matched; +output [16:0] memory_line_id; +output [7:0] KBD_KEY; +output kbd_clk_line; +output kbd_data_line; +output [5:0] not_used; +reg [7:0] KBD_KEY; +reg kbd_clk_line; +reg kbd_data_line; +reg [5:0] not_used; +reg [16:0] memory_line_id; +reg la_trigger_matched; +reg clk_of_verifla; + +parameter PERIOD = 20; +initial // Clock process for clk_of_verifla +begin + forever + begin + clk_of_verifla = 1'b0; + #(10); clk_of_verifla = 1'b1; + #(10); + end +end + +initial begin +#(10); +la_trigger_matched = 0; +memory_line_id=1; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000; +#1310660; +// ------------- Current Time: 1310670*(1ns) +memory_line_id=2; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000; +#1310660; +// ------------- Current Time: 2621330*(1ns) +memory_line_id=3; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000; +#1310660; +// ------------- Current Time: 3931990*(1ns) +memory_line_id=4; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000; +#1310660; +// ------------- Current Time: 5242650*(1ns) +memory_line_id=5; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000; +#1310660; +// ------------- Current Time: 6553310*(1ns) +memory_line_id=6; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000; +#1310660; +// ------------- Current Time: 7863970*(1ns) +memory_line_id=7; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000; +#980440; +// ------------- Current Time: 8844410*(1ns) +memory_line_id=0; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000000100000000; +#11480; +// ------------- Current Time: 8855890*(1ns) +memory_line_id=8; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000000000000000; +la_trigger_matched = 1; +#60; +// ------------- Current Time: 8855950*(1ns) +memory_line_id=9; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000010000000000; +#43940; +// ------------- Current Time: 8899890*(1ns) +memory_line_id=10; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000010100000000; +#34040; +// ------------- Current Time: 8933930*(1ns) +memory_line_id=11; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000010000000000; +#60; +// ------------- Current Time: 8933990*(1ns) +memory_line_id=12; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000100000000000; +#42900; +// ------------- Current Time: 8976890*(1ns) +memory_line_id=13; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000100100000000; +#34060; +// ------------- Current Time: 9010950*(1ns) +memory_line_id=14; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000100000000000; +#60; +// ------------- Current Time: 9011010*(1ns) +memory_line_id=15; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000110000000000; +#42880; +// ------------- Current Time: 9053890*(1ns) +memory_line_id=16; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000110100000000; +#11400; +// ------------- Current Time: 9065290*(1ns) +memory_line_id=17; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000111100000000; +#24720; +// ------------- Current Time: 9090010*(1ns) +memory_line_id=18; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000111000000000; +#60; +// ------------- Current Time: 9090070*(1ns) +memory_line_id=19; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001001010000000; +#42860; +// ------------- Current Time: 9132930*(1ns) +memory_line_id=20; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001001110000000; +#36180; +// ------------- Current Time: 9169110*(1ns) +memory_line_id=21; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001001010000000; +#60; +// ------------- Current Time: 9169170*(1ns) +memory_line_id=22; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001011011000000; +#42860; +// ------------- Current Time: 9212030*(1ns) +memory_line_id=23; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001011111000000; +#36160; +// ------------- Current Time: 9248190*(1ns) +memory_line_id=24; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001011011000000; +#60; +// ------------- Current Time: 9248250*(1ns) +memory_line_id=25; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001101011100000; +#42860; +// ------------- Current Time: 9291110*(1ns) +memory_line_id=26; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001101111100000; +#12240; +// ------------- Current Time: 9303350*(1ns) +memory_line_id=27; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001100111100000; +#21860; +// ------------- Current Time: 9325210*(1ns) +memory_line_id=28; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001100011100000; +#60; +// ------------- Current Time: 9325270*(1ns) +memory_line_id=29; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001110001110000; +#42900; +// ------------- Current Time: 9368170*(1ns) +memory_line_id=30; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001110101110000; +#34060; +// ------------- Current Time: 9402230*(1ns) +memory_line_id=31; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001110001110000; +#60; +// ------------- Current Time: 9402290*(1ns) +memory_line_id=32; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010000000111000; +#42900; +// ------------- Current Time: 9445190*(1ns) +memory_line_id=33; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010000100111000; +#34060; +// ------------- Current Time: 9479250*(1ns) +memory_line_id=34; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010000000111000; +#60; +// ------------- Current Time: 9479310*(1ns) +memory_line_id=35; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010010000011100; +#43940; +// ------------- Current Time: 9523250*(1ns) +memory_line_id=36; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010010100011100; +#41320; +// ------------- Current Time: 9564570*(1ns) +memory_line_id=37; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010010000011100; +#60; +// ------------- Current Time: 9564630*(1ns) +memory_line_id=38; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010100000011100; +#42900; +// ------------- Current Time: 9607530*(1ns) +memory_line_id=39; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010100100011100; +#11400; +// ------------- Current Time: 9618930*(1ns) +memory_line_id=40; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010101100011100; +#29920; +// ------------- Current Time: 9648850*(1ns) +memory_line_id=41; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010101000011100; +#60; +// ------------- Current Time: 9648910*(1ns) +memory_line_id=42; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111000011100; +#49120; +// ------------- Current Time: 9698030*(1ns) +memory_line_id=43; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 11008690*(1ns) +memory_line_id=44; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 12319350*(1ns) +memory_line_id=45; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 13630010*(1ns) +memory_line_id=46; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 14940670*(1ns) +memory_line_id=47; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 16251330*(1ns) +memory_line_id=48; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 17561990*(1ns) +memory_line_id=49; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 18872650*(1ns) +memory_line_id=50; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 20183310*(1ns) +memory_line_id=51; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 21493970*(1ns) +memory_line_id=52; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 22804630*(1ns) +memory_line_id=53; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 24115290*(1ns) +memory_line_id=54; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 25425950*(1ns) +memory_line_id=55; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 26736610*(1ns) +memory_line_id=56; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 28047270*(1ns) +memory_line_id=57; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 29357930*(1ns) +memory_line_id=58; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 30668590*(1ns) +memory_line_id=59; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 31979250*(1ns) +memory_line_id=60; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 33289910*(1ns) +memory_line_id=61; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 34600570*(1ns) +memory_line_id=62; +{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100; +#1310660; +// ------------- Current Time: 35911230*(1ns) +$stop; +end +endmodule +/* +ORIGINAL CAPTURE DUMP +memory_line_id=0: 02 3E 01 00 +memory_line_id=1: FF FD 03 00 +memory_line_id=2: FF FD 03 00 +memory_line_id=3: FF FD 03 00 +memory_line_id=4: FF FD 03 00 +memory_line_id=5: FF FD 03 00 +memory_line_id=6: FF FD 03 00 +memory_line_id=7: BF 7E 03 00 +memory_line_id=8: 00 03 00 00 +memory_line_id=9: 08 95 04 00 +memory_line_id=10: 06 A6 05 00 +memory_line_id=11: 00 03 04 00 +memory_line_id=12: 08 61 08 00 +memory_line_id=13: 06 A7 09 00 +memory_line_id=14: 00 03 08 00 +memory_line_id=15: 08 60 0C 00 +memory_line_id=16: 02 3A 0D 00 +memory_line_id=17: 04 D4 0F 00 +memory_line_id=18: 00 03 0E 00 +memory_line_id=19: 08 5F 12 80 +memory_line_id=20: 07 11 13 80 +memory_line_id=21: 00 03 12 80 +memory_line_id=22: 08 5F 16 C0 +memory_line_id=23: 07 10 17 C0 +memory_line_id=24: 00 03 16 C0 +memory_line_id=25: 08 5F 1A E0 +memory_line_id=26: 02 64 1B E0 +memory_line_id=27: 04 45 19 E0 +memory_line_id=28: 00 03 18 E0 +memory_line_id=29: 08 61 1C 70 +memory_line_id=30: 06 A7 1D 70 +memory_line_id=31: 00 03 1C 70 +memory_line_id=32: 08 61 20 38 +memory_line_id=33: 06 A7 21 38 +memory_line_id=34: 00 03 20 38 +memory_line_id=35: 08 95 24 1C +memory_line_id=36: 08 12 25 1C +memory_line_id=37: 00 03 24 1C +memory_line_id=38: 08 61 28 1C +memory_line_id=39: 02 3A 29 1C +memory_line_id=40: 05 D8 2B 1C +memory_line_id=41: 00 03 2A 1C +memory_line_id=42: 09 98 2E 1C +memory_line_id=43: FF FD 2F 1C +memory_line_id=44: FF FD 2F 1C +memory_line_id=45: FF FD 2F 1C +memory_line_id=46: FF FD 2F 1C +memory_line_id=47: FF FD 2F 1C +memory_line_id=48: FF FD 2F 1C +memory_line_id=49: FF FD 2F 1C +memory_line_id=50: FF FD 2F 1C +memory_line_id=51: FF FD 2F 1C +memory_line_id=52: FF FD 2F 1C +memory_line_id=53: FF FD 2F 1C +memory_line_id=54: FF FD 2F 1C +memory_line_id=55: FF FD 2F 1C +memory_line_id=56: FF FD 2F 1C +memory_line_id=57: FF FD 2F 1C +memory_line_id=58: FF FD 2F 1C +memory_line_id=59: FF FD 2F 1C +memory_line_id=60: FF FD 2F 1C +memory_line_id=61: FF FD 2F 1C +memory_line_id=62: FF FD 2F 1C +memory_line_id=63: 00 00 00 00 +*/ Index: openverifla/trunk/openverifla_2.0/java/compile.bat =================================================================== --- openverifla/trunk/openverifla_2.0/java/compile.bat (nonexistent) +++ openverifla/trunk/openverifla_2.0/java/compile.bat (revision 9) @@ -0,0 +1,2 @@ +set CLASSPATH=jssc.jar;. +javac *java Index: openverifla/trunk/openverifla_2.0/java/compile.sh =================================================================== --- openverifla/trunk/openverifla_2.0/java/compile.sh (nonexistent) +++ openverifla/trunk/openverifla_2.0/java/compile.sh (revision 9) @@ -0,0 +1,2 @@ +export CLASSPATH="jssc.jar:." +javac *java

openverifla/trunk/openverifla_2.0/java/compile.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: openverifla/trunk/openverifla_2.0/java/jssc.jar =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: openverifla/trunk/openverifla_2.0/java/jssc.jar =================================================================== --- openverifla/trunk/openverifla_2.0/java/jssc.jar (nonexistent) +++ openverifla/trunk/openverifla_2.0/java/jssc.jar (revision 9)

openverifla/trunk/openverifla_2.0/java/jssc.jar Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: openverifla/trunk/openverifla_2.0/java/run.bat =================================================================== --- openverifla/trunk/openverifla_2.0/java/run.bat (nonexistent) +++ openverifla/trunk/openverifla_2.0/java/run.bat (revision 9) @@ -0,0 +1,2 @@ +set CLASSPATH=jssc.jar;. +java %1 %2 %3 %4 %5 Index: openverifla/trunk/openverifla_2.0/java/run.sh =================================================================== --- openverifla/trunk/openverifla_2.0/java/run.sh (nonexistent) +++ openverifla/trunk/openverifla_2.0/java/run.sh (revision 9) @@ -0,0 +1,3 @@ +export CLASSPATH="jssc.jar:." +echo "CLASSPATH=$CLASSPATH" +java $1 $2 $3 $4 $5

openverifla/trunk/openverifla_2.0/java/run.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: openverifla/trunk/openverifla_2.0/java/verifla_properties_keyboard.txt =================================================================== --- openverifla/trunk/openverifla_2.0/java/verifla_properties_keyboard.txt (nonexistent) +++ openverifla/trunk/openverifla_2.0/java/verifla_properties_keyboard.txt (revision 9) @@ -0,0 +1,44 @@ +# VeriFLA Logic Analyzer Project File + +# Serial port +# On Windows this would be COM5 or similar +LA.portName=/dev/ttyUSB0 + +# Memory +# ==== +LA.memWords=64 +# Data input width and indentical samples bits (clones) must be multiple of 8. +LA.dataWordLenBits=16 +LA.clonesWordLenBits=16 +LA.triggerMatchMemAddr=8 + + +# Generated verilog +# ==== +LA.timescaleUnit=1ns +LA.timescalePrecision=10ps +# clockPeriod expressed in [timescaleUnit] +LA.clockPeriod=20 + +# User data signals +LA.totalSignals=16 +# Big endian (1) or Little endian (0). +LA.signalGroups=4 +# Group 0 +LA.groupName.0=KBD_KEY +LA.groupSize.0=8 +LA.groupEndian.0=0 +# Group 1 +LA.groupName.1=kbd_clk_line +LA.groupSize.1=1 +LA.groupEndian.1=0 +# Group 2 +LA.groupName.2=kbd_data_line +LA.groupSize.2=1 +LA.groupEndian.2=0 +# Group 3 +LA.groupName.3=not_used +LA.groupSize.3=6 +LA.groupEndian.3=0 + + Index: openverifla/trunk/openverifla_2.0/verilog/keyboard-driver/keyboard.ucf =================================================================== --- openverifla/trunk/openverifla_2.0/verilog/keyboard-driver/keyboard.ucf (nonexistent) +++ openverifla/trunk/openverifla_2.0/verilog/keyboard-driver/keyboard.ucf (revision 9) @@ -0,0 +1,28 @@ +#NET "switch[0]" LOC="L13"; +#NET "switch[1]" LOC="L14"; +#NET "switch[2]" LOC="H18"; +#NET "switch[3]" LOC="N17"; + +NET "clk" LOC = "C9"; +NET "reset" LOC = "L13"; + +NET "kbd_data_line" LOC = "G13"; +NET "kbd_clk" LOC = "G14"; + +#NET "J1_0" LOC = "N15"; +#NET "J1_1" LOC = "N14"; +#NET "J1_2" LOC = "E15"; +#NET "J1_3" LOC = "V7"; + +#leds +NET "kbd_key[0]" LOC="D4"; +NET "kbd_key[1]" LOC="C3"; +NET "kbd_key[2]" LOC="D6"; +NET "kbd_key[3]" LOC="E6"; +NET "kbd_key[4]" LOC="D13"; +NET "kbd_key[5]" LOC="A7"; +NET "kbd_key[6]" LOC="G9"; +NET "kbd_key[7]" LOC="A8"; + +NET "uart_REC_dataH" LOC = "R13"; +NET "uart_XMIT_dataH" LOC = "P13"; Index: openverifla/trunk/openverifla_2.0/verilog/keyboard-driver/keyboard.v =================================================================== --- openverifla/trunk/openverifla_2.0/verilog/keyboard-driver/keyboard.v (nonexistent) +++ openverifla/trunk/openverifla_2.0/verilog/keyboard-driver/keyboard.v (revision 9) @@ -0,0 +1,81 @@ +module keyboard(kbd_data_line, kbd_clk, kbd_key, + clk, reset, + //top_of_verifla transceiver + uart_XMIT_dataH, uart_REC_dataH +); + + +input clk, reset; +//top_of_verifla transceiver +input uart_REC_dataH; +output uart_XMIT_dataH; + +// App. specific +input kbd_data_line, kbd_clk; +output [7:0] kbd_key; // register for storing keyboard data + +reg [7:0] kbd_key; +reg [3:0] i; // initial value needs to be not equal to 0 through 7. set initial to 10. + +wire negedge_kbd_clk; + + +// This is the keyboard driver logic (fsm). +always @ (posedge clk or posedge reset) +begin + if(reset) + begin + i=10; + kbd_key=8'h0; //{8'b00010010};//8'h0; + end + else begin + if(negedge_kbd_clk) + begin + if ((i >= 0) && (i <= 7)) + // If i is pointing to a bit of data let us keep it. + begin + kbd_key = {kbd_data_line, kbd_key[7:1]}; + i = i + 1; + end + else if ((i == 8) || (i == 9)) + // Otherwise if i is pointing to the parity bit or the stop bit let us ignore it. + begin + i = i + 1; + end + else // Else we have a start bit + begin + i = 0; + end + end + end +end + + +reg [2:0] kbd_clk_buf=3'b000; +always @ (posedge clk) kbd_clk_buf={kbd_clk_buf[1:0], kbd_clk}; +assign negedge_kbd_clk = kbd_clk_buf[2:1]==2'b10; + + +// VeriFLA +reg [5:0] cnt=0; +always @(posedge clk or posedge reset) +begin + if(reset) + cnt = 0; + else + if(negedge_kbd_clk) + cnt = cnt+1; +end + +top_of_verifla verifla (.clk(clk), .rst_l(!reset), .sys_run(1'b1), + .data_in({cnt, kbd_data_line, kbd_clk, kbd_key}), + //{6'b0, kbd_data_line, kbd_clk, kbd_key}, + // Transceiver + .uart_XMIT_dataH(uart_XMIT_dataH), .uart_REC_dataH(uart_REC_dataH) + ); + +endmodule + +// Local Variables: +// verilog-library-directories:(".", "../verifla") +// End: Index: openverifla/trunk/openverifla_2.0/verilog/keyboard-driver/keyboard_driver_test.v =================================================================== --- openverifla/trunk/openverifla_2.0/verilog/keyboard-driver/keyboard_driver_test.v (nonexistent) +++ openverifla/trunk/openverifla_2.0/verilog/keyboard-driver/keyboard_driver_test.v (revision 9) @@ -0,0 +1,90 @@ +`timescale 1ns / 1ps +module keyboard_driver_test(kbd_key); + +`include "../verifla/common_internal_verifla.v" + +// This test module is wrote +// in the following scenario: the driver is on the FPGA and the keyboard +// is attached to the FPGA development board + +// Declaration +output [7:0] kbd_key; +wire [7:0] kbd_key; +// This signals must explicitly added to the simulation. +// For debugging purposes, also add the register named "i" from the keyboard driver +reg reset, clk; +reg kbd_clk, kbd_data_line; +wire uart_XMIT_dataH; +reg uart_REC_dataH=1; + +reg [64:0] i; + +keyboard kd (kbd_data_line, kbd_clk, kbd_key, + clk, reset, + //top_of_verifla transceiver + uart_XMIT_dataH, uart_REC_dataH +); + +always begin + clk = 0; + #5; + clk = 1; + #5; +end + +// Reset the driver by using the reset button of the FPGA board. +initial begin + $dumpfile("kbd.vcd"); + $dumpvars; + reset = 0; + #10; + reset = 1; + #10; + reset = 0; +end + +// Now, simulate the keyboard. +// Consider the keyboard clock period to be about 100 units. +initial begin + // At the begining, the line is idle for some periods. + kbd_clk=1; kbd_data_line=1; #2050; #2050; + + // When a key is pressed, the keyboard sends its scan code + // on the data line. For the 'a' key, the scan code is 1Ch=00011100b. + // The order is LSb first, so the bits are sent in the following order: 00111000. + // Simulate pressing the 'a' key. + // Send start bit. + kbd_clk=1; #250; kbd_data_line=0; #250; kbd_clk=0; #500; + // Send the scan code + kbd_clk=1; #250; kbd_data_line=0; #250; kbd_clk=0; #500; + kbd_clk=1; #250; kbd_data_line=0; #250; kbd_clk=0; #500; + kbd_clk=1; #250; kbd_data_line=1; #250; kbd_clk=0; #500; + kbd_clk=1; #250; kbd_data_line=1; #250; kbd_clk=0; #500; + kbd_clk=1; #250; kbd_data_line=1; #250; kbd_clk=0; #500; + kbd_clk=1; #250; kbd_data_line=0; #250; kbd_clk=0; #500; + kbd_clk=1; #250; kbd_data_line=0; #250; kbd_clk=0; #500; + kbd_clk=1; #250; kbd_data_line=0; #250; kbd_clk=0; #500; + // Send the parity bit which is '1' for the 'a' key. + kbd_clk=1; #250; kbd_data_line=1; #250; kbd_clk=0; #500; + // Send the stop bit. + kbd_clk=1; #250; kbd_data_line=1; #250; kbd_clk=0; #500; + // Put the line idle for two periods. + kbd_clk=1; kbd_data_line=1; #2050; #2050; + #1000; + // When the 'a' key - that is now pressed, + // will be released, then the keyboard will send F0h, 1Ch. + // We do not simulate this because the process is similar. + +`ifdef DEBUG_LA + //$display("value: %b", {{{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1}, {LA_DATA_INPUT_WORDLEN_BITS{1'b0}}}); + for(i = 0; i <= LA_MEM_LAST_ADDR; i = i + 1) begin + //$display("i=%d m2[i]=%d m1[i]=%b", i, kd.verifla.mi.m2[i], kd.verifla.mi.m1[i]); + $display("%d %h %h %h %h", i, kd.verifla.mi.mem[i][31:24], kd.verifla.mi.mem[i][22:16], + kd.verifla.mi.mem[i][15:8], kd.verifla.mi.mem[i][7:0]); + end + //$display("m[%d]=%d", LA_MEM_LAST_ADDR, kd.verifla.mi.mem[LA_MEM_LAST_ADDR]); +`endif + $stop; +end + +endmodule Index: openverifla/trunk/openverifla_2.0/verilog/verifla/baud.v =================================================================== --- openverifla/trunk/openverifla_2.0/verilog/verifla/baud.v (nonexistent) +++ openverifla/trunk/openverifla_2.0/verilog/verifla/baud.v (revision 9) @@ -0,0 +1,40 @@ + +module baud( + sys_clk, + sys_rst_l, + baud_clk + ); + + +`include "inc.v" + + +input sys_clk; +input sys_rst_l; +output baud_clk; +reg baud_clk; + +reg [BAUD_COUNTER_SIZE-1:0] counter=0; //{BAUD_COUNTER_SIZE{1'b0}}; + +always @(posedge sys_clk or negedge sys_rst_l) +begin + if(~sys_rst_l) begin + baud_clk <= 0; + counter <= 0; + end else if (counter < T2_div_T1_div_2) begin + counter <= counter + 1; + baud_clk <= baud_clk; + end else begin + counter <= 0; + baud_clk <= ~baud_clk; + end +end + +/* +reg [2:0] baud_vec=3'b000; +always @(posedge clk) baud_vec = {baud_vec[1:0], baud_clk}; +wire baud_clk_posedge=(baud_vec[2:1]=2'b01; +wire baud_clk_negedge=(baud_vec[2:1]=2'b10; +*/ + +endmodule Index: openverifla/trunk/openverifla_2.0/verilog/verifla/common_internal_verifla.v =================================================================== --- openverifla/trunk/openverifla_2.0/verilog/verifla/common_internal_verifla.v (nonexistent) +++ openverifla/trunk/openverifla_2.0/verilog/verifla/common_internal_verifla.v (revision 9) @@ -0,0 +1,40 @@ + +// Data input width and indentical samples bits must be multiple of 8. +parameter LA_DATA_INPUT_WORDLEN_BITS=16; + +// Trigger +parameter LA_TRIGGER_VALUE={LA_DATA_INPUT_WORDLEN_BITS{1'b0}}, + LA_TRIGGER_MASK={{(LA_DATA_INPUT_WORDLEN_BITS - 10){1'b0}}, 2'b11, 8'h00}; + +// Memory +`define LA_MEM_CLEAN_BEFORE_RUN 1 +parameter LA_IDENTICAL_SAMPLES_BITS=16; +parameter LA_MEM_WORDLEN_BITS=(LA_DATA_INPUT_WORDLEN_BITS+LA_IDENTICAL_SAMPLES_BITS); +parameter LA_MEM_WORDLEN_OCTETS=((LA_MEM_WORDLEN_BITS+7)/8), + LA_LOG2_MEM_WORDLEN_OCTETS=3; +parameter LA_MEM_ADDRESS_BITS=6; +parameter LA_MEM_FIRST_ADDR=0, + LA_MEM_LAST_ADDR=((1<> 3), + LA_MEM_LAST_ADDR_BEFORE_TRIGGER=(LA_TRIGGER_MATCH_MEM_ADDR-1), + LA_MEM_ONE_TO_LAST_ADDR_BEFORE_TRIGGER=(LA_TRIGGER_MATCH_MEM_ADDR-2); +parameter LA_MAX_SAMPLES_AFTER_TRIGGER_BITS=26, + LA_MAX_SAMPLES_AFTER_TRIGGER={1'b0, {(LA_MAX_SAMPLES_AFTER_TRIGGER_BITS-1){1'b1}}}; + +// Identical samples +parameter LA_MAX_IDENTICAL_SAMPLES=((1 << LA_IDENTICAL_SAMPLES_BITS) - 2); //{LA_IDENTICAL_SAMPLES_BITS{1'b1}}; + +/* +Reserved mem words +1) the word situated at LA_BT_QUEUE_HEAD_ADDRESS. +2) LA_MEM_EMPTY_SLOT which represents an empty and not used memory slot. +It has sense if LA_MEM_CLEAN_BEFORE_RUN and + a) when the trigger event arrives before the filling of the full btqueue. + b) after the trigger event and after capturing LA_MAX_SAMPLES_AFTER_TRIGGER +*/ +parameter LA_MEM_EMPTY_SLOT={LA_MEM_WORDLEN_BITS{1'b0}}; + +//`define DEBUG_LA \ No newline at end of file Index: openverifla/trunk/openverifla_2.0/verilog/verifla/computer_input_of_verifla.v =================================================================== --- openverifla/trunk/openverifla_2.0/verilog/verifla/computer_input_of_verifla.v (nonexistent) +++ openverifla/trunk/openverifla_2.0/verilog/verifla/computer_input_of_verifla.v (revision 9) @@ -0,0 +1,107 @@ +/* +file: computer_input_of_verifla.v +license: GNU GPL + +Revision history +revision date: 2007/Sep/03; author: Laurentiu DUCA +- USERCMD_RESET + +revision date: 2007/Jul/4; author: Laurentiu DUCA +- v01 +*/ + + +module computer_input_of_verifla (clk, rst_l, + rec_dataH, rec_readyH, user_reset_low, user_run); +// user commands +parameter USERCMD_RESET = 8'h00, + USERCMD_RUN = 8'h01; +// CI_states +parameter CI_STATES_BITS=4, + CI_STATE_IDLE=0, + CI_STATE_START_OF_NEW_CMD=1; + +// input +input clk, rst_l; +input rec_readyH; +input [7:0] rec_dataH; +// output +output user_reset_low, user_run; +reg user_reset_low, user_run; +// locals +reg [CI_STATES_BITS-1:0] ci_state, next_ci_state; +reg [7:0] ci_indata, next_ci_indata; +wire ci_new_octet_received; + +// T(clk)<= log2(T2_T1_div_2) bits +parameter BAUD_COUNTER_SIZE = 15; +//`define DEBUG +/* +1s ... 50000000 T1 +1bit ... 16 T2 +1s .. 115200 bits +=> +1s .. 115200 * 16 T2 + +T2 = 5000000 T1 / (115200 * 16) = T1 * 50000000 / (115200 * 16) +*/ Index: openverifla/trunk/openverifla_2.0/verilog/verifla/memory.v =================================================================== --- openverifla/trunk/openverifla_2.0/verilog/verifla/memory.v (nonexistent) +++ openverifla/trunk/openverifla_2.0/verilog/verifla/memory.v (revision 9) @@ -0,0 +1,51 @@ +/* +Author: Laurentiu Duca +License: GNU GPL +*/ + +module memory ( + clka, rst_l, //clkb, + addra, wea, dina, addrb, doutb +); + +`include "common_internal_verifla.v" + +input rst_l; +input clka; +//input clkb; +input wea; +input [LA_MEM_ADDRESS_BITS-1:0] addra; +input [LA_MEM_ADDRESS_BITS-1:0] addrb; +output [LA_MEM_WORDLEN_BITS-1:0] doutb; +input [LA_MEM_WORDLEN_BITS-1:0] dina; + +reg [LA_MEM_WORDLEN_BITS-1:0] mem[LA_MEM_LAST_ADDR:0]; +//reg [LA_MEM_WORDLEN_BITS-1:0] i; +`ifdef DEBUG_LA +reg [LA_DATA_INPUT_WORDLEN_BITS-1:0] m1[LA_MEM_LAST_ADDR:0]; +reg [LA_IDENTICAL_SAMPLES_BITS-1:0] m2[LA_MEM_LAST_ADDR:0]; +`endif + +assign doutb = mem[addrb]; + +always @(posedge clka or negedge rst_l) +begin + if(~rst_l) begin + if(!(`LA_MEM_CLEAN_BEFORE_RUN)) begin:INITIAL_SECTION + integer i; + for(i=0; i<=LA_MEM_LAST_ADDR; i=i+1) + mem[i] <= LA_MEM_EMPTY_SLOT; + end + end else begin + if(wea) begin +`ifdef DEBUG_LA + m1[addra] <= dina[LA_DATA_INPUT_WORDLEN_BITS-1:0]; + m2[addra] <= dina[LA_MEM_WORDLEN_BITS-1:LA_DATA_INPUT_WORDLEN_BITS]; +`endif + mem[addra] <= dina; + end + end +end + +endmodule + Index: openverifla/trunk/openverifla_2.0/verilog/verifla/monitor_of_verifla.v =================================================================== --- openverifla/trunk/openverifla_2.0/verilog/verifla/monitor_of_verifla.v (nonexistent) +++ openverifla/trunk/openverifla_2.0/verilog/verifla/monitor_of_verifla.v (revision 9) @@ -0,0 +1,290 @@ +/* +file: monitor_of_verifla.v +license: GNU GPL +Revision history +revision date: 20180730-1500; Laurentiu Duca +- redesign of mem struct +- the bt_queue_tail_address is wrote at the end of capture. +revision date: 2007/Sep/03; author: Laurentiu DUCA +- the bt_queue_head_address is wrote at the end of capture. +- zero all memory at a mon_run (if LA_MEM_CLEAN_BEFORE_RUN). +- note that _at_ means after trigger event and _bt_ means before trigger event + +revision date: 2007/Jul/4; author: Laurentiu DUCA +- v01 +*/ + + +module monitor_of_verifla (clk, rst_l, + mon_run, data_in, + mem_port_A_address, mem_port_A_data_in, mem_port_A_wen, + ack_sc_run, sc_done, sc_run); + +`include "common_internal_verifla.v" + +// MON_states +parameter + MON_STATES_BITS=4, + MON_STATE_IDLE=0, + MON_STATE_DO_MEM_CLEAN=1, + MON_STATE_PREPARE_RUN=2, + MON_STATE_WAIT_TRIGGER_MATCH=3, + MON_STATE_AFTER_TRIGGER=4, + MON_STATE_DATA_CAPTURED=5, + MON_STATE_SC_RUN=6, + MON_STATE_WAIT_SC_DONE=7; + +// input +input clk, rst_l; +input [LA_DATA_INPUT_WORDLEN_BITS-1:0] data_in; +input mon_run, ack_sc_run, sc_done; +// output +output [LA_MEM_ADDRESS_BITS-1:0] mem_port_A_address; +output [LA_MEM_WORDLEN_BITS-1:0] mem_port_A_data_in; +output mem_port_A_wen; +output sc_run; +reg [LA_MEM_ADDRESS_BITS-1:0] mem_port_A_address; +reg [LA_MEM_WORDLEN_BITS-1:0] mem_port_A_data_in; +reg mem_port_A_wen; +reg sc_run, next_sc_run; + +// local +reg [MON_STATES_BITS-1:0] mon_state, next_mon_state; +reg [LA_MAX_SAMPLES_AFTER_TRIGGER_BITS-1:0] + next_mon_samples_after_trigger, mon_samples_after_trigger; +reg [LA_MEM_ADDRESS_BITS-1:0] next_mon_write_address, mon_write_address, old_mon_write_address; +reg [LA_MEM_ADDRESS_BITS-1:0] next_bt_queue_tail_address, bt_queue_tail_address; +reg [LA_DATA_INPUT_WORDLEN_BITS-1:0] mon_old_data_in, + mon_current_data_in; //={LA_DATA_INPUT_WORDLEN_BITS{1'b0}}; +reg [LA_IDENTICAL_SAMPLES_BITS-1:0] mon_clones_nr, next_mon_clones_nr; + + +// Register the input data +// such that mon_current_data_in is constant the full clock period. +always @(posedge clk or negedge rst_l) +begin + if(~rst_l) + begin + mon_old_data_in <= 0; + mon_current_data_in <= 0; + end + else begin + mon_old_data_in <= mon_current_data_in; + mon_current_data_in <= data_in; + end +end + +// set new values +always @(posedge clk or negedge rst_l) +begin + if(~rst_l) + begin + mon_state <= MON_STATE_IDLE; + sc_run <= 0; + old_mon_write_address <= LA_MEM_FIRST_ADDR; + mon_write_address <= LA_MEM_FIRST_ADDR; + bt_queue_tail_address <= 0; + mon_samples_after_trigger <= 0; + mon_clones_nr <= 1; + end + else begin + mon_state <= next_mon_state; + sc_run <= next_sc_run; + old_mon_write_address <= mon_write_address; + mon_write_address <= next_mon_write_address; + bt_queue_tail_address <= next_bt_queue_tail_address; + mon_samples_after_trigger <= next_mon_samples_after_trigger; + mon_clones_nr <= next_mon_clones_nr; + end +end + + +// continuous assignments +wire [LA_MEM_ADDRESS_BITS-1:0] one_plus_mon_write_address = (mon_write_address+1); +wire [LA_IDENTICAL_SAMPLES_BITS-1:0] oneplus_mon_clones_nr = (mon_clones_nr+1); +wire data_in_changed = (mon_current_data_in != mon_old_data_in); +wire last_mem_addr_before_trigger = (mon_write_address == LA_MEM_LAST_ADDR_BEFORE_TRIGGER); +wire not_maximum_mon_clones_nr = (mon_clones_nr < LA_MAX_IDENTICAL_SAMPLES); + + +// mon_prepare_run is called from states MON_STATE_IDLE and MON_STATE_PREPARE_RUN +task mon_prepare_run; +begin + // we share the same clock as memory. + mem_port_A_address=LA_MEM_FIRST_ADDR; + mem_port_A_data_in={{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in}; + mem_port_A_wen=1; + next_mon_write_address=LA_MEM_FIRST_ADDR; + next_mon_clones_nr=2; + next_mon_state = MON_STATE_WAIT_TRIGGER_MATCH; +end +endtask + + +// state machine +always @(*) +/* + mon_state or mon_run + or ack_sc_run or sc_done or sc_run + // eliminate warnings + or mon_write_address or bt_queue_tail_address or mon_samples_after_trigger + or mon_current_data_in or mon_old_data_in or mon_clones_nr + or data_in_changed or oneplus_mon_clones_nr or one_plus_mon_write_address + or not_maximum_mon_clones_nr + or last_mem_addr_before_trigger or old_mon_write_address) +*/ +begin + // implicit + next_mon_state=mon_state; + next_sc_run=sc_run; + next_mon_write_address=mon_write_address; + next_bt_queue_tail_address=bt_queue_tail_address; + next_mon_samples_after_trigger=mon_samples_after_trigger; + next_mon_clones_nr = mon_clones_nr; + mem_port_A_address=0; + mem_port_A_data_in=0; + mem_port_A_wen=0; + + // state dependent + case(mon_state) + MON_STATE_IDLE: + begin + if(mon_run) + begin + if(`LA_MEM_CLEAN_BEFORE_RUN) + begin + next_mon_write_address=LA_MEM_FIRST_ADDR; + next_mon_state=MON_STATE_DO_MEM_CLEAN; + end + else + mon_prepare_run; + end + else + next_mon_state=MON_STATE_IDLE; + end + + MON_STATE_DO_MEM_CLEAN: + begin + mem_port_A_address=mon_write_address; + mem_port_A_data_in=LA_MEM_EMPTY_SLOT; + mem_port_A_wen=1; + if(mon_write_address < LA_MEM_LAST_ADDR) + begin + next_mon_write_address=mon_write_address+1; + next_mon_state = MON_STATE_DO_MEM_CLEAN; + end + else + // at the new posedge clock, will clean memory at its last address + next_mon_state = MON_STATE_PREPARE_RUN; + end + + MON_STATE_PREPARE_RUN: + begin + mon_prepare_run; + end + + MON_STATE_WAIT_TRIGGER_MATCH: + begin + // circular queue + if((mon_current_data_in & LA_TRIGGER_MASK) != + (LA_TRIGGER_VALUE & LA_TRIGGER_MASK)) + begin + next_mon_state = MON_STATE_WAIT_TRIGGER_MATCH; + mem_port_A_wen = 1; + mem_port_A_address = data_in_changed ? + (last_mem_addr_before_trigger ? LA_MEM_FIRST_ADDR : one_plus_mon_write_address) : + (not_maximum_mon_clones_nr ? mon_write_address : + (last_mem_addr_before_trigger ? LA_MEM_FIRST_ADDR : one_plus_mon_write_address)); + mem_port_A_data_in = data_in_changed ? + {{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in} : + (not_maximum_mon_clones_nr ? {mon_clones_nr, mon_current_data_in} : + {{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in}); + next_mon_clones_nr = data_in_changed ? 2 : + (not_maximum_mon_clones_nr ? oneplus_mon_clones_nr : 2); + next_mon_write_address = data_in_changed ? + (last_mem_addr_before_trigger ? LA_MEM_FIRST_ADDR: one_plus_mon_write_address) : + (not_maximum_mon_clones_nr ? mon_write_address : + (last_mem_addr_before_trigger ? LA_MEM_FIRST_ADDR : one_plus_mon_write_address)); + end + else begin + // trigger matched + next_mon_state=MON_STATE_AFTER_TRIGGER; + mem_port_A_address=LA_TRIGGER_MATCH_MEM_ADDR; + mem_port_A_data_in = {{{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1}, mon_current_data_in}; + mem_port_A_wen=1; + next_mon_write_address=LA_TRIGGER_MATCH_MEM_ADDR; + next_mon_clones_nr=2; + next_bt_queue_tail_address = old_mon_write_address; + next_mon_samples_after_trigger=1; + end + end + + MON_STATE_AFTER_TRIGGER: + begin + if((mon_samples_after_trigger < LA_MAX_SAMPLES_AFTER_TRIGGER) && + (mon_write_address < LA_MEM_LAST_ADDR)) + begin + mem_port_A_wen = 1; + mem_port_A_address = data_in_changed ? one_plus_mon_write_address : + (not_maximum_mon_clones_nr ? mon_write_address : one_plus_mon_write_address); + mem_port_A_data_in = data_in_changed ? {{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in} : + (not_maximum_mon_clones_nr ? {mon_clones_nr, mon_current_data_in} : + {{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in}); + next_mon_clones_nr = data_in_changed ? 2 : + (not_maximum_mon_clones_nr ? oneplus_mon_clones_nr : 2); + next_mon_write_address = data_in_changed ? one_plus_mon_write_address : + (not_maximum_mon_clones_nr ? mon_write_address : one_plus_mon_write_address); + next_mon_samples_after_trigger=mon_samples_after_trigger+1; + next_mon_state=MON_STATE_AFTER_TRIGGER; + end + else begin + mem_port_A_wen=0; + next_mon_state=MON_STATE_DATA_CAPTURED; + end + end + + MON_STATE_DATA_CAPTURED: + begin + // Save bt_queue_tail_address + mem_port_A_address = LA_BT_QUEUE_TAIL_ADDRESS; + mem_port_A_data_in = + {{(LA_MEM_WORDLEN_BITS-LA_MEM_ADDRESS_BITS){1'b0}}, + bt_queue_tail_address}; + mem_port_A_wen = 1; + next_mon_state=MON_STATE_SC_RUN; + end + + MON_STATE_SC_RUN: + begin + next_mon_state=MON_STATE_WAIT_SC_DONE; + next_sc_run=1; + end + MON_STATE_WAIT_SC_DONE: + begin + // sc_run must already be 1, when entering state MON_STATE_SEND_CAPTURE. + if(ack_sc_run) + next_sc_run=0; + if((sc_run == 0) && (sc_done)) + next_mon_state=MON_STATE_IDLE; + else + next_mon_state=MON_STATE_WAIT_SC_DONE; + end + + + default: // should never get here + begin + next_mon_state=4'bxxxx; + next_sc_run=1'bx; + next_mon_write_address={LA_MEM_ADDRESS_BITS{1'bx}}; + next_bt_queue_tail_address={(LA_MEM_ADDRESS_BITS){1'bx}}; + next_mon_samples_after_trigger={LA_MAX_SAMPLES_AFTER_TRIGGER_BITS{1'bx}}; + next_mon_clones_nr={LA_IDENTICAL_SAMPLES_BITS{1'bx}}; + mem_port_A_address={LA_MEM_ADDRESS_BITS{1'bx}}; + mem_port_A_data_in={LA_MEM_WORDLEN_BITS{1'bx}}; + mem_port_A_wen=1'bx; + end + endcase +end + + +endmodule Index: openverifla/trunk/openverifla_2.0/verilog/verifla/send_capture_of_verifla.v =================================================================== --- openverifla/trunk/openverifla_2.0/verilog/verifla/send_capture_of_verifla.v (nonexistent) +++ openverifla/trunk/openverifla_2.0/verilog/verifla/send_capture_of_verifla.v (revision 9) @@ -0,0 +1,162 @@ +/* +file: send_capture_of_verifla.v +license: GNU GPL +Revision history +revision date: 2007/Jul/4; author: Laurentiu DUCA +- v01 +*/ + + +//`timescale 1ns/1ps +module send_capture_of_verifla(clk, rst_l, + sc_run, ack_sc_run, sc_done, + mem_port_B_address, mem_port_B_dout, + xmit_doneH, xmitH, xmit_dataH); + +`include "common_internal_verifla.v" + +// SC_states +parameter + SC_STATES_BITS=4, + SC_STATE_IDLE=0, + SC_STATE_ACK_SC_RUN=1, + SC_STATE_SET_MEMADDR_TO_READ_FROM=2, + SC_STATE_GET_MEM_OUTPUT_DATA=3, + SC_STATE_SEND_OCTET=4, + SC_STATE_WAIT_OCTET_SENT=5, + SC_STATE_WORD_SENT=6; + +// input +input clk, rst_l; +input sc_run; +input [LA_MEM_WORDLEN_BITS-1:0] mem_port_B_dout; +input xmit_doneH; +// output +output [LA_MEM_ADDRESS_BITS-1:0] mem_port_B_address; +output xmitH; +output [7:0] xmit_dataH; +output ack_sc_run, sc_done; +reg [LA_MEM_ADDRESS_BITS-1:0] mem_port_B_address; +reg xmitH; +reg [7:0] xmit_dataH; +reg ack_sc_run, sc_done; +// local +reg [SC_STATES_BITS-1:0] sc_state, next_sc_state; +reg [LA_MEM_ADDRESS_BITS-1:0] sc_current_address, next_sc_current_address; +reg [LA_LOG2_MEM_WORDLEN_OCTETS-1:0] sc_octet_id, next_sc_octet_id; +reg [LA_MEM_WORDLEN_BITS-1:0] sc_word_bits, next_sc_word_bits; + +// set up next value +always @(posedge clk or negedge rst_l) +begin + if(~rst_l) + begin + sc_state=SC_STATE_IDLE; + sc_current_address=0; + sc_word_bits=0; + sc_octet_id=0; + end + else + begin + sc_state=next_sc_state; + sc_current_address=next_sc_current_address; + sc_word_bits=next_sc_word_bits; + sc_octet_id=next_sc_octet_id; + end +end + +// state machine +always @(sc_state or sc_run or xmit_doneH + // not important but xilinx warnings. + or sc_current_address or mem_port_B_dout or sc_word_bits or sc_octet_id) +begin + // implicitly + next_sc_state=sc_state; + ack_sc_run=0; + sc_done=0; + xmit_dataH=0; + xmitH=0; + mem_port_B_address=sc_current_address; + next_sc_current_address=sc_current_address; + next_sc_word_bits=sc_word_bits; + next_sc_octet_id=sc_octet_id; + + // state dependent + case(sc_state) + SC_STATE_IDLE: + begin + if(sc_run) + begin + next_sc_state = SC_STATE_ACK_SC_RUN; + next_sc_current_address=LA_MEM_LAST_ADDR; + end + else + next_sc_state = SC_STATE_IDLE; + end + SC_STATE_ACK_SC_RUN: + begin + ack_sc_run=1; + next_sc_state = SC_STATE_SET_MEMADDR_TO_READ_FROM; + end + SC_STATE_SET_MEMADDR_TO_READ_FROM: + begin + mem_port_B_address=sc_current_address; + // next clock cycle we have memory dout of our read. + next_sc_state = SC_STATE_GET_MEM_OUTPUT_DATA; + end + SC_STATE_GET_MEM_OUTPUT_DATA: + begin + next_sc_word_bits=mem_port_B_dout; + // LSB first + next_sc_octet_id=0; + next_sc_state = SC_STATE_SEND_OCTET; + end + SC_STATE_SEND_OCTET: + begin + xmit_dataH=sc_word_bits[7:0]; + next_sc_word_bits={8'd0, sc_word_bits[LA_MEM_WORDLEN_BITS-1:8]}; //sc_word_bits>>8; + xmitH=1; + next_sc_octet_id=sc_octet_id+1; + next_sc_state = SC_STATE_WAIT_OCTET_SENT; + end + SC_STATE_WAIT_OCTET_SENT: + begin + if(xmit_doneH) + begin + if(sc_octet_id < LA_MEM_WORDLEN_OCTETS) + next_sc_state = SC_STATE_SEND_OCTET; + else + next_sc_state = SC_STATE_WORD_SENT; + end + else + next_sc_state = SC_STATE_WAIT_OCTET_SENT; + end + SC_STATE_WORD_SENT: + begin + if(sc_current_address > LA_MEM_FIRST_ADDR) + begin + next_sc_current_address=sc_current_address-1; + next_sc_state = SC_STATE_SET_MEMADDR_TO_READ_FROM; + end + else + begin + // done sending all captured data + sc_done = 1; + next_sc_state = SC_STATE_IDLE; + end + end + default: // should never get here + begin + next_sc_state=4'bxxxx; + sc_done=1'bx; + xmit_dataH=1'bx; + xmitH=1'bx; + mem_port_B_address={LA_MEM_ADDRESS_BITS{1'bx}}; + next_sc_current_address={LA_MEM_ADDRESS_BITS{1'bx}}; + next_sc_word_bits={LA_MEM_WORDLEN_BITS{1'bx}}; + next_sc_octet_id={LA_LOG2_MEM_WORDLEN_OCTETS{1'bx}}; + end + endcase +end + +endmodule \ No newline at end of file Index: openverifla/trunk/openverifla_2.0/verilog/verifla/single_pulse_of_verifla.v =================================================================== --- openverifla/trunk/openverifla_2.0/verilog/verifla/single_pulse_of_verifla.v (nonexistent) +++ openverifla/trunk/openverifla_2.0/verilog/verifla/single_pulse_of_verifla.v (revision 9) @@ -0,0 +1,64 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:17:26 02/23/2007 +// Design Name: +// Module Name: single_pulse +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +// Author: Laurentiu Duca, Politehnica University of Bucharest. +// License: GNU GPL +// +////////////////////////////////////////////////////////////////////////////////// +module single_pulse(clk, reset, ub, ubsing); +input clk, reset; +input ub; +output ubsing; +reg [1:0] q; + + +/* +Truth table +==== +before (posedge clk) | after (posedge clk) +ub / state(q1q0) | state(q1q0) / ubsing +0 / 00 | 00 / 0 +1 / 00 | 01 / 1 +x / 01 | 10 / 0 +0 / 10 | 00 / 0 +1 / 10 | 10 / 0 + +Notes: +- works only if the (posedge ub) comes 2 clk periods after the prevoius (negedge ub). +- after reset, ub can be either 0 or 1. +*/ + +assign ubsing = q[0]; + +always @ (posedge clk or negedge reset) +begin + +if(~reset) +begin + q[0] <= 0; + q[1] <= 0; +end +else +begin + q[0] <= ~q[0] && ub && ~q[1]; + q[1] <= q[0] || (~q[0] && ub && q[1]); +end +end + +endmodule Index: openverifla/trunk/openverifla_2.0/verilog/verifla/top_of_verifla.v =================================================================== --- openverifla/trunk/openverifla_2.0/verilog/verifla/top_of_verifla.v (nonexistent) +++ openverifla/trunk/openverifla_2.0/verilog/verifla/top_of_verifla.v (revision 9) @@ -0,0 +1,70 @@ +/* +file: top_of_verifla.v +license: GNU GPL +Revision history +revision date: 2007/Sep/03; author: Laurentiu DUCA +- sys_run: an internal possible run command +- combined_reset_low which allows the user to reset the monitor + +revision date: 2007/Jul/4; author: Laurentiu DUCA +- v01 +*/ + + +module top_of_verifla(clk, rst_l, sys_run, data_in, + // Transceiver + uart_XMIT_dataH, uart_REC_dataH + ); + +`include "common_internal_verifla.v" + +input clk, rst_l, sys_run; +input [LA_DATA_INPUT_WORDLEN_BITS-1:0] data_in; +output uart_XMIT_dataH; +input uart_REC_dataH; + +// App. specific. +wire [LA_MEM_WORDLEN_BITS-1:0] mem_port_A_data_in, mem_port_B_dout; +wire [LA_MEM_ADDRESS_BITS-1:0] mem_port_A_address, mem_port_B_address; +wire mem_port_A_wen; +wire user_reset_low, user_run, mon_run; +wire combined_reset_low; +wire sc_run, ack_sc_run, sc_done; + +// Transceiver +wire [7:0] xmit_dataH; +wire xmit_doneH; +wire xmitH; + +// Receiver +wire [7:0] rec_dataH; +wire rec_readyH; + +uart iUART (clk, rst_l, uart_clk, + // Transmitter + uart_XMIT_dataH, xmitH, xmit_dataH, xmit_doneH, + // Receiver + uart_REC_dataH, rec_dataH, rec_readyH); + +memory mi ( + .addra(mem_port_A_address), .addrb(mem_port_B_address), + .clka(clk), .rst_l(rst_l), //.clkb(uart_clk), + .dina(mem_port_A_data_in), .doutb(mem_port_B_dout), + .wea(mem_port_A_wen)); + +assign combined_reset_low=(rst_l && user_reset_low); +assign mon_run = (sys_run || user_run); +computer_input_of_verifla ci (clk, rst_l, + rec_dataH, rec_readyH, user_reset_low, user_run); +monitor_of_verifla mon (clk, combined_reset_low, + mon_run, data_in, + mem_port_A_address, mem_port_A_data_in, mem_port_A_wen, + ack_sc_run, sc_done, sc_run); +// send_capture_of_verifla must use only rst_l which resets the uart, too. +send_capture_of_verifla sc (uart_clk, rst_l, + sc_run, ack_sc_run, sc_done, + mem_port_B_address, mem_port_B_dout, + xmit_doneH, xmitH, xmit_dataH); + +endmodule + Index: openverifla/trunk/openverifla_2.0/verilog/verifla/u_rec.v =================================================================== --- openverifla/trunk/openverifla_2.0/verilog/verifla/u_rec.v (nonexistent) +++ openverifla/trunk/openverifla_2.0/verilog/verifla/u_rec.v (revision 9) @@ -0,0 +1,166 @@ + +/* Update: Laurentiu Duca, 20180724_1550: + - removed "rdy_o <= 1'b0;" from idle state + and moved to STA_CHECK_START_BIT. + - sample in the middle of the data bit + - correct init values and sizes +*/ + +///////////////////////////////////////////////////////////////////// +//// Author: Zhangfeifei //// +//// //// +//// Advance Test Technology Laboratory, //// +//// Institute of Computing Technology, //// +//// Chinese Academy of Sciences //// +//// //// +//// If you encountered any problem, please contact : //// +//// Email: zhangfeifei@ict.ac.cn or whitewill@opencores.org //// +//// Tel: +86-10-6256 5533 ext. 5673 //// +//// //// +//// Downloaded from: //// +//// http://www.opencores.org/pdownloads.cgi/list/ucore //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2005-2006 Zhangfeifei //// +//// zhangfeifei@ict.ac.cn //// +//// //// +//// //// +//// This source file may be used and distributed freely without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and any derivative work contains the //// +//// original copyright notice and the associated disclaimer. //// +//// //// +//// Please let the author know if it is used //// +//// for commercial purpose. //// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// //// +//// Date of Creation: 2005.12.3 //// +//// //// +//// Version: 0.0.1 //// +//// //// +//// Description: rx module of the uart module,data format is //// +//// 8bits data,1 bits stop bit,and no parity check //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Change log: //// +//// //// +///////////////////////////////////////////////////////////////////// + +//`include "defines.v" + +module u_rec( + clk_i,rst_i,//system signal + rxd_i,//serial data in + rdy_o,data_o //data ready and parallel data out signal + ); + + parameter // state difinition + STA_IDDLE = 0, + STA_CHECK_START_BIT = 1, + STA_RECEIVE = 2; + + input clk_i; + input rst_i; + input rxd_i; + + output rdy_o; + output [7:0] data_o; + + reg rdy_o; + reg [7:0] data_o; + + reg [7:0] rsr;//reciving shift register + reg [3:0] num_of_rec; + + reg [1:0] reg_sta; + + //the counter to count the clk in + reg [3:0] count; + reg count_c;//the carry of count + + always @(posedge clk_i or posedge rst_i) + begin + if(rst_i) + begin + data_o <= 8'b0; + rdy_o <= 1'b0; + rsr <= 8'h0; + num_of_rec <= 4'b0; + count <= 4'b0; + count_c <= 1'b0; + + reg_sta <= STA_IDDLE; + end + else begin + case (reg_sta) + STA_IDDLE: + begin + num_of_rec <= 4'd0; + count <= 4'd0; + if(!rxd_i) + reg_sta <= STA_CHECK_START_BIT;//recive a start bit + else + reg_sta <= STA_IDDLE; + end + STA_CHECK_START_BIT: + begin + if(count >= 7) + begin + count <= 0; + if(!rxd_i) begin + //has passed 8 clk and rxd_i is still zero,then start bit has been confirmed + rdy_o <= 1'b0; + reg_sta <= STA_RECEIVE; + end + else + reg_sta <= STA_IDDLE; + end + else begin + reg_sta <= STA_CHECK_START_BIT; + count <= count +1; + end + end + STA_RECEIVE: + begin + {count_c,count} <= count +1; + //has passed 16 clk after the last bit has been checked,sampling a bit + if(count_c) + begin + if(num_of_rec <=3'd7) + begin //sampling the received bit + rsr <= {rxd_i,rsr[7:1]}; + num_of_rec <= num_of_rec +1; + reg_sta <= STA_RECEIVE; + end + else begin//sampling the stop bit + //if(rxd_i)//if stop bit exist + //begin + data_o <= rsr; + rdy_o <= 1'b1; + //end + reg_sta <= STA_IDDLE; + end + end + end + endcase + end + end + +endmodule Index: openverifla/trunk/openverifla_2.0/verilog/verifla/u_xmit.v =================================================================== --- openverifla/trunk/openverifla_2.0/verilog/verifla/u_xmit.v (nonexistent) +++ openverifla/trunk/openverifla_2.0/verilog/verifla/u_xmit.v (revision 9) @@ -0,0 +1,158 @@ +/* +Update: Laurentiu Duca, 20180724_1550: + - In state STA_TRANS, put num_of_trans <= 4'd8 instead of 7. + in order to send stop bit. + - correct init values and sizes +*/ + + +///////////////////////////////////////////////////////////////////// +//// Author: Zhangfeifei //// +//// //// +//// Advance Test Technology Laboratory, //// +//// Institute of Computing Technology, //// +//// Chinese Academy of Sciences //// +//// //// +//// If you encountered any problem, please contact : //// +//// Email: zhangfeifei@ict.ac.cn or whitewill@opencores.org //// +//// Tel: +86-10-6256 5533 ext. 5673 //// +//// //// +//// Downloaded from: //// +//// http://www.opencores.org/pdownloads.cgi/list/ucore //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2005-2006 Zhangfeifei //// +//// zhangfeifei@ict.ac.cn //// +//// //// +//// //// +//// This source file may be used and distributed freely without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and any derivative work contains the //// +//// original copyright notice and the associated disclaimer. //// +//// //// +//// Please let the author know if it is used //// +//// for commercial purpose. //// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// //// +//// Date of Creation: 2005.12.3 //// +//// //// +//// Version: 0.0.1 //// +//// //// +//// Description: tx module of the uart module,data format is //// +//// 8bits data,1 bits stop bit,and no parity check //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Change log: //// +//// //// +///////////////////////////////////////////////////////////////////// + +//`include "defines.v" + +module u_xmit( + clk_i,rst_i,//system signal + data_i,wen_i,//parallel data in and enable signal + txd_o,//serial data out + tre_o// ready to transmit flag + ); + + parameter // state difinition + STA_IDDLE = 0, + STA_TRANS = 1, + STA_FINISH = 2; + + input clk_i; + input rst_i; + input [7:0] data_i; + input wen_i; + + output txd_o; + output tre_o; + + reg txd_o; + reg tre_o; + + reg [7:0] tsr;//transmitting shift register + reg [3:0] num_of_trans; + + reg [1:0] reg_sta; + + //the counter to count the clk in + reg [3:0] count; + reg count_c;//the carry of count + + always @(posedge clk_i or posedge rst_i) + begin + if(rst_i) + begin + + tsr <= 8'b0; + txd_o <= 1'b1; + tre_o <= 1'b1; + num_of_trans <= 4'b0; + count_c <= 1'b0; + count <= 4'b0; + + reg_sta <= STA_IDDLE; + end + else begin + + case(reg_sta) + STA_IDDLE: + begin + num_of_trans <= 4'd0; + count <= 4'd0; + count_c <= 1'b0; + if(wen_i) + begin + tsr <= data_i; + tre_o <= 1'b0; + txd_o <= 1'b0;// transmit the start bit + reg_sta <= STA_TRANS; + end + else + reg_sta <= STA_IDDLE; + end + STA_TRANS: + begin + {count_c,count} <= count + 1; + + if(count_c) + begin + if(num_of_trans <=4'd8) + begin + //note ,when num_of_trans==8 ,we transmit the stop bit + tsr <= {1'b1,tsr[7:1]}; + txd_o <= tsr[0]; + num_of_trans <= num_of_trans+1; + reg_sta <= STA_TRANS; + end + else begin + txd_o <= 1'b1; + tre_o <= 1'b1; + reg_sta <= STA_IDDLE; + end + end + end + endcase + end + end + + +endmodule Index: openverifla/trunk/openverifla_2.0/verilog/verifla/uart.v =================================================================== --- openverifla/trunk/openverifla_2.0/verilog/verifla/uart.v (nonexistent) +++ openverifla/trunk/openverifla_2.0/verilog/verifla/uart.v (revision 9) @@ -0,0 +1,87 @@ +module uart ( sys_clk, + sys_rst_l, + uart_clk, + + // Transmitter + uart_XMIT_dataH, + xmitH, + xmit_dataH, + xmit_doneH, + + // Receiver + uart_REC_dataH, + rec_dataH, + rec_readyH + ); + + +`include "inc.v" + +input sys_clk; +input sys_rst_l; +output uart_clk; + +// Trasmitter +output uart_XMIT_dataH; +input xmitH; +input [7:0] xmit_dataH; +output xmit_doneH; + +// Receiver +input uart_REC_dataH; +output [7:0] rec_dataH; +output rec_readyH; + +wire uart_clk; +wire [7:0] rec_dataH; +wire rec_readyH; + + + +// Instantiate the Transmitter +u_xmit txd1 ( + .clk_i(uart_clk), + .rst_i(!sys_rst_l), + .data_i(xmit_dataH), + .wen_i(xmitH), + .txd_o(uart_XMIT_dataH), + .tre_o(xmit_doneH) + ); +/* +u_xmit iXMIT( .sys_clk(uart_clk), + .sys_rst_l(sys_rst_l), + + .uart_xmitH(uart_XMIT_dataH), + .xmitH(xmitH), + .xmit_dataH(xmit_dataH), + .xmit_doneH(xmit_doneH) + ); +*/ + +// Instantiate the Receiver +u_rec rxd1( + .clk_i(uart_clk), .rst_i(!sys_rst_l),//system signal + .rxd_i(uart_REC_dataH),//serial data in + .rdy_o (rec_readyH), .data_o(rec_dataH) //data ready and parallel data out signal + ); +/* +u_rec iRECEIVER (// system connections + .sys_rst_l(sys_rst_l), + .sys_clk(uart_clk), + // uart + .uart_dataH(uart_REC_dataH), + .rec_dataH(rec_dataH), + .rec_readyH(rec_readyH) + ); +*/ + +// Instantiate the Baud Rate Generator + +baud baud1( .sys_clk(sys_clk), + .sys_rst_l(sys_rst_l), + .baud_clk(uart_clk) + ); + + + +endmodule Index: openverifla/trunk/openverifla_manual.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: openverifla/trunk/openverifla_manual.pdf =================================================================== --- openverifla/trunk/openverifla_manual.pdf (nonexistent) +++ openverifla/trunk/openverifla_manual.pdf (revision 9)

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