URL
https://opencores.org/ocsvn/pcie_mini/pcie_mini/trunk
Subversion Repositories pcie_mini
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Rev 8 → Rev 9
/pcie_mini/trunk/example_design/xilinx_pcie2wb.vhd
6,7 → 6,7
-- Modify date: 08/10/2012 |
-- Design Name: pcie_mini |
-- Module Name: xilinx_pcie2wb - Behavioral |
-- Version: 1.2 |
-- Version: 1.4 |
-- Project Name: |
-- Target Devices: Xilinx Series-5/6/7 FPGAs |
-- Tool versions: ISE-DS 12.1 |
46,6 → 46,8
-- Revision 1.0 - File Created by Istvan Nagy |
-- Revision 1.1 - some fixes by Istvan Nagy |
-- Revision 1.2 - interrupt fix by Stephen Battazzo |
-- Revision 1.3 - 64-bit read fix, support for unaligned 32-bit read, and custom BAR0 address space size by Scott Cogan, FRIB |
-- Revision 1.4 - Compatibility for MSI and Legacy interrupts by Scott Cogan, FRIB |
-- |
---------------------------------------------------------------------------------- |
|
62,6 → 64,12
|
|
entity xilinx_pcie2wb is |
generic ( |
-- BAR0_WIDTH = 28 sets address space for 2^28 bytes = 256MB, BARO = x"F0000000" |
-- BAR0_WIDTH = 22 sets address space for 2^22 bytes = 4MB, BARO = x"FFC00000" |
BAR0 : bit_vector := x"FFC00000"; |
BAR0_WIDTH : integer := 22 |
); |
Port ( --FPGA PINS(EXTERNAL): |
pci_exp_txp : out std_logic; |
pci_exp_txn : out std_logic; |
83,6 → 91,7
pcie_bar0_wb_sel_o : out std_logic_vector(3 downto 0); |
--OTHER: |
pcie_irq : in std_logic; |
pcie_msi_enabled : out std_logic; -- added to monitor if MSI interrupt is enabled |
pcie_resetout : out std_logic --active high |
); |
end xilinx_pcie2wb; |
213,7 → 222,7
--this signal added by StBa, AAC Microtec |
SIGNAL irq_prohibit : std_logic; |
|
SIGNAL pcieirq_state : std_logic_vector(7 downto 0); |
SIGNAL pcieirq_state : std_logic_vector(2 downto 0); |
SIGNAL txtrn_counter : std_logic_vector(7 downto 0); |
SIGNAL trn_rx_counter : std_logic_vector(7 downto 0); |
SIGNAL cfg_completer_id : std_logic_vector(15 downto 0); |
276,7 → 285,7
VC0_TOTAL_CREDITS_CH : integer := 40; |
VC0_TOTAL_CREDITS_CD : integer := 211; |
VC0_CPL_INFINITE : boolean := TRUE; |
BAR0 : bit_vector := x"F0000000"; |
BAR0 : bit_vector := BAR0; --x"F0000000"; |
BAR1 : bit_vector := x"00000000"; |
BAR2 : bit_vector := x"00000000"; |
BAR3 : bit_vector := x"00000000"; |
1154,7 → 1163,7
--********** WRITE STATE ********** |
--initiate WB write(s) (1...N DWORD accesses) |
when "00000010" => --state 2 |
pcie_bar0_wb_addr_o_feed(27 downto 2) <= rxtlp_decodedaddress(27 downto 2) + tlp_datacount -1; --256MBytes size is hardcoded here, by cutting 4-MSB off |
pcie_bar0_wb_addr_o_feed(BAR0_WIDTH-1 downto 2) <= rxtlp_decodedaddress(BAR0_WIDTH-1 downto 2) + tlp_datacount -1; -- BAR0 size is hardcoded here, by cutting MSB's off |
pcie_bar0_wb_addr_o_feed(1 downto 0) <= bit10(1 downto 0); |
pcie_bar0_wb_sel_o_feed <= rxtlp_firstdw_be; |
pcie_bar0_wb_data_o_feed <= bram_rxtlp_readdata; |
1182,7 → 1191,7
--********** READ STATE ********** |
--initiate WB read, then go to completion state |
when "00000011" => --state 3 |
pcie_bar0_wb_addr_o_feed(27 downto 2) <= rxtlp_decodedaddress(27 downto 2) + tlp_datacount -1; |
pcie_bar0_wb_addr_o_feed(BAR0_WIDTH-1 downto 2) <= rxtlp_decodedaddress(BAR0_WIDTH-1 downto 2) + tlp_datacount -1; |
pcie_bar0_wb_addr_o_feed(1 downto 0) <= bit10(1 downto 0); |
pcie_bar0_wb_sel_o_feed <= rxtlp_firstdw_be; |
tlp_state_copy <= tlp_state; |
1199,7 → 1208,6
--bram_txtlp_writeaddress remains the same to capture data in next clock cycle |
else |
tlp_state <= "00011110"; --one more wb read |
bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1; |
tlp_datacount <= tlp_datacount +1; |
end if; |
else |
1207,6 → 1215,8
end if; |
--* read restart STATE * |
when "00011110" => --state 30 |
tlp_state_copy <= tlp_state; -- SC: required to re-trigger additional reads, start_read_wb0 <= '1' |
bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1; -- SC: increment address here (moved) |
tlp_state <= "00000011"; |
bram_txtlp_we <= "0"; |
--intermediate state before completion (to ensure data latch at address-4) |
1380,56 → 1390,64
-- added by StBa, AAC Microtec, 2012 |
irq_prohibit <= not tlpstm_isin_idle; |
|
-- fixed compatibility with both MSI interrupts and legacy interrupts |
-- added by SC, FRIB, 2016 |
pcie_msi_enabled <= cfg_interrupt_msienable; |
|
process (pciewb_localreset_n, trn_clk, pcie_irq, pcieirq_state, |
cfg_interrupt_rdy_n) |
begin |
if (pciewb_localreset_n='0') then |
pcieirq_state <= "00000000"; |
pcieirq_state <= "000"; |
cfg_interrupt_n <= '1'; |
cfg_interrupt_assert_n_1 <= '1'; |
cfg_interrupt_assert_n_1 <= '1'; |
else |
if (trn_clk'event and trn_clk = '1') then |
case ( pcieirq_state ) is |
|
case ( pcieirq_state ) is |
--********** idle STATE ********** |
when "00000000" => --state 0 |
if (pcie_irq = '1' and irq_prohibit = '0') then |
pcieirq_state <= "00000001"; |
cfg_interrupt_n <= '0'; --active |
else |
cfg_interrupt_n <= '1'; --inactive |
end if; |
cfg_interrupt_assert_n_1 <= '0'; --0=assert, 1=deassert |
|
when "000" => --state 0 |
cfg_interrupt_n <= '1'; --inactive |
cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert |
if (pcie_irq = '1') then |
pcieirq_state <= "001"; |
end if; |
--********** wait for not irq_prohibit ********** |
when "001" => --state 1 |
if (irq_prohibit = '0') then |
pcieirq_state <= "010"; |
cfg_interrupt_n <= '0'; --active |
cfg_interrupt_assert_n_1 <= '0'; --0=assert, 1=deassert |
end if; |
--********** assert STATE ********** |
when "00000001" => --state 1 |
if (cfg_interrupt_rdy_n ='0') then --ep accepted it |
cfg_interrupt_n <= '1'; --deassert the request |
pcieirq_state <= "00000010"; |
else |
cfg_interrupt_n <= '0'; --request INTA assertion |
end if; |
|
--********** pcie_irq kept asserted STATE ********** |
when "00000010" => --state 2 |
if (pcie_irq = '0' and irq_prohibit='0') then --pcie_irq gets deasserted |
pcieirq_state <= "00000011"; |
end if; |
cfg_interrupt_n <= '1'; --inactive |
cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert |
|
when "010" => --state 2 |
cfg_interrupt_n <= '0'; --request INTA assertion |
if (cfg_interrupt_rdy_n ='0') then --ep accepted it |
cfg_interrupt_n <= '1'; --deassert the request |
cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert |
pcieirq_state <= "011"; -- wait for IRQ deassert |
end if; |
--********** (LEGACY) pcie_irq kept asserted STATE ********** |
when "011" => --state 3 |
if (pcie_irq='0' and irq_prohibit='0' and cfg_interrupt_msienable='0') then |
pcieirq_state <= "100"; -- LEGACY, pcie_irq gets deasserted |
end if; |
if (pcie_irq='0' and cfg_interrupt_msienable='1') then |
pcieirq_state <= "000"; -- MSI IRQ, back to IDLE when pcie_irq deasserted |
end if; |
cfg_interrupt_n <= '1'; --inactive |
cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert |
--********** DEassert STATE ********** |
when "00000011" => --state 3 |
if (cfg_interrupt_rdy_n ='0') then --ep accepted it |
cfg_interrupt_n <= '1'; --deassert the request |
pcieirq_state <= "00000000"; |
else |
cfg_interrupt_n <= '0'; --request INTA DEassertion |
end if; |
-- below state only used for legacy interrupts |
when "100" => --state 4 |
cfg_interrupt_n <= '0'; --request INTA DEassertion |
if (cfg_interrupt_rdy_n ='0') then --ep accepted it |
cfg_interrupt_n <= '1'; --deassert the request |
pcieirq_state <= "000"; |
end if; |
|
when others => --error |
pcieirq_state <= "00000000"; --go to state 0 |
end case; |
when others => --error |
pcieirq_state <= "000"; --go to state 0 |
end case; |
end if; |
end if; |
end process; |
/pcie_mini/trunk/example_design_full/ReferenceDesign-s6bf_board-iseds121.zip
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/pcie_mini/trunk/main_sources/xilinx_pcie2wb.vhd
6,7 → 6,7
-- Modify date: 08/10/2012 |
-- Design Name: pcie_mini |
-- Module Name: xilinx_pcie2wb - Behavioral |
-- Version: 1.2 |
-- Version: 1.4 |
-- Project Name: |
-- Target Devices: Xilinx Series-5/6/7 FPGAs |
-- Tool versions: ISE-DS 12.1 |
46,6 → 46,8
-- Revision 1.0 - File Created by Istvan Nagy |
-- Revision 1.1 - some fixes by Istvan Nagy |
-- Revision 1.2 - interrupt fix by Stephen Battazzo |
-- Revision 1.3 - 64-bit read fix, support for unaligned 32-bit read, and custom BAR0 address space size by Scott Cogan, FRIB |
-- Revision 1.4 - Compatibility for MSI and Legacy interrupts by Scott Cogan, FRIB |
-- |
---------------------------------------------------------------------------------- |
|
62,6 → 64,12
|
|
entity xilinx_pcie2wb is |
generic ( |
-- BAR0_WIDTH = 28 sets address space for 2^28 bytes = 256MB, BARO = x"F0000000" |
-- BAR0_WIDTH = 22 sets address space for 2^22 bytes = 4MB, BARO = x"FFC00000" |
BAR0 : bit_vector := x"FFC00000"; |
BAR0_WIDTH : integer := 22 |
); |
Port ( --FPGA PINS(EXTERNAL): |
pci_exp_txp : out std_logic; |
pci_exp_txn : out std_logic; |
83,6 → 91,7
pcie_bar0_wb_sel_o : out std_logic_vector(3 downto 0); |
--OTHER: |
pcie_irq : in std_logic; |
pcie_msi_enabled : out std_logic; -- added to monitor if MSI interrupt is enabled |
pcie_resetout : out std_logic --active high |
); |
end xilinx_pcie2wb; |
213,7 → 222,7
--this signal added by StBa, AAC Microtec |
SIGNAL irq_prohibit : std_logic; |
|
SIGNAL pcieirq_state : std_logic_vector(7 downto 0); |
SIGNAL pcieirq_state : std_logic_vector(2 downto 0); |
SIGNAL txtrn_counter : std_logic_vector(7 downto 0); |
SIGNAL trn_rx_counter : std_logic_vector(7 downto 0); |
SIGNAL cfg_completer_id : std_logic_vector(15 downto 0); |
276,7 → 285,7
VC0_TOTAL_CREDITS_CH : integer := 40; |
VC0_TOTAL_CREDITS_CD : integer := 211; |
VC0_CPL_INFINITE : boolean := TRUE; |
BAR0 : bit_vector := x"F0000000"; |
BAR0 : bit_vector := BAR0; --x"F0000000"; |
BAR1 : bit_vector := x"00000000"; |
BAR2 : bit_vector := x"00000000"; |
BAR3 : bit_vector := x"00000000"; |
1154,7 → 1163,7
--********** WRITE STATE ********** |
--initiate WB write(s) (1...N DWORD accesses) |
when "00000010" => --state 2 |
pcie_bar0_wb_addr_o_feed(27 downto 2) <= rxtlp_decodedaddress(27 downto 2) + tlp_datacount -1; --256MBytes size is hardcoded here, by cutting 4-MSB off |
pcie_bar0_wb_addr_o_feed(BAR0_WIDTH-1 downto 2) <= rxtlp_decodedaddress(BAR0_WIDTH-1 downto 2) + tlp_datacount -1; -- BAR0 size is hardcoded here, by cutting MSB's off |
pcie_bar0_wb_addr_o_feed(1 downto 0) <= bit10(1 downto 0); |
pcie_bar0_wb_sel_o_feed <= rxtlp_firstdw_be; |
pcie_bar0_wb_data_o_feed <= bram_rxtlp_readdata; |
1182,7 → 1191,7
--********** READ STATE ********** |
--initiate WB read, then go to completion state |
when "00000011" => --state 3 |
pcie_bar0_wb_addr_o_feed(27 downto 2) <= rxtlp_decodedaddress(27 downto 2) + tlp_datacount -1; |
pcie_bar0_wb_addr_o_feed(BAR0_WIDTH-1 downto 2) <= rxtlp_decodedaddress(BAR0_WIDTH-1 downto 2) + tlp_datacount -1; |
pcie_bar0_wb_addr_o_feed(1 downto 0) <= bit10(1 downto 0); |
pcie_bar0_wb_sel_o_feed <= rxtlp_firstdw_be; |
tlp_state_copy <= tlp_state; |
1199,7 → 1208,6
--bram_txtlp_writeaddress remains the same to capture data in next clock cycle |
else |
tlp_state <= "00011110"; --one more wb read |
bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1; |
tlp_datacount <= tlp_datacount +1; |
end if; |
else |
1207,6 → 1215,8
end if; |
--* read restart STATE * |
when "00011110" => --state 30 |
tlp_state_copy <= tlp_state; -- SC: required to re-trigger additional reads, start_read_wb0 <= '1' |
bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1; -- SC: increment address here (moved) |
tlp_state <= "00000011"; |
bram_txtlp_we <= "0"; |
--intermediate state before completion (to ensure data latch at address-4) |
1380,56 → 1390,64
-- added by StBa, AAC Microtec, 2012 |
irq_prohibit <= not tlpstm_isin_idle; |
|
-- fixed compatibility with both MSI interrupts and legacy interrupts |
-- added by SC, FRIB, 2016 |
pcie_msi_enabled <= cfg_interrupt_msienable; |
|
process (pciewb_localreset_n, trn_clk, pcie_irq, pcieirq_state, |
cfg_interrupt_rdy_n) |
begin |
if (pciewb_localreset_n='0') then |
pcieirq_state <= "00000000"; |
pcieirq_state <= "000"; |
cfg_interrupt_n <= '1'; |
cfg_interrupt_assert_n_1 <= '1'; |
cfg_interrupt_assert_n_1 <= '1'; |
else |
if (trn_clk'event and trn_clk = '1') then |
case ( pcieirq_state ) is |
|
case ( pcieirq_state ) is |
--********** idle STATE ********** |
when "00000000" => --state 0 |
if (pcie_irq = '1' and irq_prohibit = '0') then |
pcieirq_state <= "00000001"; |
cfg_interrupt_n <= '0'; --active |
else |
cfg_interrupt_n <= '1'; --inactive |
end if; |
cfg_interrupt_assert_n_1 <= '0'; --0=assert, 1=deassert |
|
when "000" => --state 0 |
cfg_interrupt_n <= '1'; --inactive |
cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert |
if (pcie_irq = '1') then |
pcieirq_state <= "001"; |
end if; |
--********** wait for not irq_prohibit ********** |
when "001" => --state 1 |
if (irq_prohibit = '0') then |
pcieirq_state <= "010"; |
cfg_interrupt_n <= '0'; --active |
cfg_interrupt_assert_n_1 <= '0'; --0=assert, 1=deassert |
end if; |
--********** assert STATE ********** |
when "00000001" => --state 1 |
if (cfg_interrupt_rdy_n ='0') then --ep accepted it |
cfg_interrupt_n <= '1'; --deassert the request |
pcieirq_state <= "00000010"; |
else |
cfg_interrupt_n <= '0'; --request INTA assertion |
end if; |
|
--********** pcie_irq kept asserted STATE ********** |
when "00000010" => --state 2 |
if (pcie_irq = '0' and irq_prohibit='0') then --pcie_irq gets deasserted |
pcieirq_state <= "00000011"; |
end if; |
cfg_interrupt_n <= '1'; --inactive |
cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert |
|
when "010" => --state 2 |
cfg_interrupt_n <= '0'; --request INTA assertion |
if (cfg_interrupt_rdy_n ='0') then --ep accepted it |
cfg_interrupt_n <= '1'; --deassert the request |
cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert |
pcieirq_state <= "011"; -- wait for IRQ deassert |
end if; |
--********** (LEGACY) pcie_irq kept asserted STATE ********** |
when "011" => --state 3 |
if (pcie_irq='0' and irq_prohibit='0' and cfg_interrupt_msienable='0') then |
pcieirq_state <= "100"; -- LEGACY, pcie_irq gets deasserted |
end if; |
if (pcie_irq='0' and cfg_interrupt_msienable='1') then |
pcieirq_state <= "000"; -- MSI IRQ, back to IDLE when pcie_irq deasserted |
end if; |
cfg_interrupt_n <= '1'; --inactive |
cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert |
--********** DEassert STATE ********** |
when "00000011" => --state 3 |
if (cfg_interrupt_rdy_n ='0') then --ep accepted it |
cfg_interrupt_n <= '1'; --deassert the request |
pcieirq_state <= "00000000"; |
else |
cfg_interrupt_n <= '0'; --request INTA DEassertion |
end if; |
-- below state only used for legacy interrupts |
when "100" => --state 4 |
cfg_interrupt_n <= '0'; --request INTA DEassertion |
if (cfg_interrupt_rdy_n ='0') then --ep accepted it |
cfg_interrupt_n <= '1'; --deassert the request |
pcieirq_state <= "000"; |
end if; |
|
when others => --error |
pcieirq_state <= "00000000"; --go to state 0 |
end case; |
when others => --error |
pcieirq_state <= "000"; --go to state 0 |
end case; |
end if; |
end if; |
end process; |