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URL https://opencores.org/ocsvn/robust_reg/robust_reg/trunk

Subversion Repositories robust_reg

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  • This comparison shows the changes necessary to convert path
    /
    from Rev 8 to Rev 9
    Reverse comparison

Rev 8 → Rev 9

/robust_reg/trunk/run/run.bat
1,8 → 1,7
 
echo off
 
..\..\..\robust.exe ../src/regfile.v -od out -list list.txt -listpath -header
..\..\..\robust.exe ../src/regfile.h -od out -header
..\..\..\robust.exe ../src/regfile.html -od out
..\..\..\robust.exe ../src/base/regfile.h -od out -header -gui
..\..\..\robust.exe ../src/base/regfile.html -od out -gui
..\..\..\robust.exe ../src/base/regfile.v -od out -list list.txt -listpath -header -gui
 
echo Completed RobustVerilog regfile run - results in run/out/
/robust_reg/trunk/run/run.sh
1,7 → 1,5
#!/bin/bash
 
../../../robust ../src/regfile.v -od out -list list.txt -listpath -header ${@}
../../../robust ../src/regfile.h -od out -header ${@}
../../../robust ../src/regfile.html -od out ${@}
 
echo Completed RobustVerilog regfile run - results in run/out/
../../../robust ../src/base/regfile.v -od out -list list.txt -listpath -header -gui ${@}
../../../robust ../src/base/regfile.h -od out -header -gui ${@}
../../../robust ../src/base/regfile.html -od out -gui ${@}
/robust_reg/trunk/src/regs.xls Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
robust_reg/trunk/src/regs.xls Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: robust_reg/trunk/src/regfile.html =================================================================== --- robust_reg/trunk/src/regfile.html (revision 8) +++ robust_reg/trunk/src/regfile.html (nonexistent) @@ -1,50 +0,0 @@ -<##////////////////////////////////////////////////////////////////// -//// //// -//// Author: Eyal Hochberg //// -//// eyal@provartec.com //// -//// //// -//// Downloaded from: http://www.opencores.org //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2010 Provartec LTD //// -//// www.provartec.com //// -//// info@provartec.com //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation.//// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more//// -//// details. http://www.gnu.org/licenses/lgpl.html //// -//// //// -//////////////////////////////////////////////////////////////////##> - -OUTFILE REGNAME_regfile.html -INCLUDE def_regfile.txt - - - - -LOOP RX REG_NUM -
    -
  • GROUP_REGS[RX] -
      -
    • Offset: 0xGROUP_REGS[RX].ADDR -
    • Access: TYPE_GROUP_REGS[RX].TYPE -
    • Description: GROUP_REGS[RX].DESC -
    • Fields: -
        - GROUP_REGRX [EXPR(GROUP_REGRX.WIDTH+GROUP_REGRX.START-1):GROUP_REGRX.START]

          Description: GROUP_REGRX.DESC

          Access: TYPE_GROUP_REGRX.TYPE

          Default value: GROUP_REGRX.DEFAULT

        -
      -
    -
- -ENDLOOP RX Index: robust_reg/trunk/src/base/regfile.html =================================================================== --- robust_reg/trunk/src/base/regfile.html (nonexistent) +++ robust_reg/trunk/src/base/regfile.html (revision 9) @@ -0,0 +1,50 @@ +<##////////////////////////////////////////////////////////////////// +//// //// +//// Author: Eyal Hochberg //// +//// eyal@provartec.com //// +//// //// +//// Downloaded from: http://www.opencores.org //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2010 Provartec LTD //// +//// www.provartec.com //// +//// info@provartec.com //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation.//// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more//// +//// details. http://www.gnu.org/licenses/lgpl.html //// +//// //// +//////////////////////////////////////////////////////////////////##> + +OUTFILE REGNAME_regfile.html +INCLUDE def_regfile.txt + + + + +LOOP RX REG_NUM +
    +
  • GROUP_REGS[RX] +
      +
    • Offset: 0xGROUP_REGS[RX].ADDR +
    • Access: TYPE_GROUP_REGS[RX].TYPE +
    • Description: GROUP_REGS[RX].DESC +
    • Fields: +
        + GROUP_REGRX [EXPR(GROUP_REGRX.WIDTH+GROUP_REGRX.START-1):GROUP_REGRX.START]

          Description: GROUP_REGRX.DESC

          Access: TYPE_GROUP_REGRX.TYPE

          Default value: GROUP_REGRX.DEFAULT

        +
      +
    +
+ +ENDLOOP RX Index: robust_reg/trunk/src/base/regfile.v =================================================================== --- robust_reg/trunk/src/base/regfile.v (nonexistent) +++ robust_reg/trunk/src/base/regfile.v (revision 9) @@ -0,0 +1,162 @@ +<##////////////////////////////////////////////////////////////////// +//// //// +//// Author: Eyal Hochberg //// +//// eyal@provartec.com //// +//// //// +//// Downloaded from: http://www.opencores.org //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2010 Provartec LTD //// +//// www.provartec.com //// +//// info@provartec.com //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation.//// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more//// +//// details. http://www.gnu.org/licenses/lgpl.html //// +//// //// +//////////////////////////////////////////////////////////////////##> + +OUTFILE REGNAME_regfile.v +INCLUDE def_regfile.txt + +ITER RX REG_NUM + +module REGNAME_regfile (PORTS); + + parameter ADDR_BITS = 16; + + input clk; + input reset; + port GROUP_APB; + + + input GROUP_REGRX.SON(TYPE == TYPE_RO); + output GROUP_REGRX.SON(TYPE == TYPE_RW); + output wr_GROUP_REGRX.SON(TYPE == TYPE_WO); + output GROUP_REGRX.SON(TYPE == TYPE_IW); + + + wire gpwrite; + wire gpread; + reg [31:0] prdata_pre; + reg pslverr_pre; + reg [31:0] prdata; + reg pslverr; + reg pready; + + wire + STOMP NEWLINE ;; GONCAT(wr_regGROUP_REGS.SON(TYPE != TYPE_RO).IDX ,); + reg [31:0] + STOMP NEWLINE ;; GONCAT(rd_regGROUP_REGS.SON(TYPE != TYPE_WO).IDX ,); + + reg GROUP_REGRX.SON(TYPE == TYPE_IW); + reg GROUP_REGRX.SON(TYPE == TYPE_RW); + + wire wr_GROUP_REGRX.SON(TYPE == TYPE_WO); + wire wr_GROUP_REGRX.SON(TYPE == TYPE_IW); + + + //---------------------- addresses----------------------------------- + parameter GROUP_REGS = 'hGROUP_REGS.ADDR; //GROUP_REGS.DESC + + //---------------------- gating ------------------------------------- + assign gpwrite = psel & (~penable) & pwrite; + assign gpread = psel & (~penable) & (~pwrite); + + + //---------------------- Write Operations --------------------------- + assign wr_regGROUP_REGS.SON(TYPE != TYPE_RO).IDX = gpwrite & (paddr == GROUP_REGS); + + LOOP RX REG_NUM + IFDEF TRUE(GROUP_REGS[RX].TYPE == TYPE_RW) + //GROUP_REGS[RX].DESC + always @(posedge clk or posedge reset) + if (reset) + begin + GROUP_REGRX.SON(TYPE==TYPE_RW) <= #FFD GROUP_REGRX.WIDTH'dGROUP_REGRX.DEFAULT; //GROUP_REGRX.DESC + end + else if (wr_regRX) + begin + GROUP_REGRX.SON(TYPE==TYPE_RW) <= #FFD pwdata[EXPR(GROUP_REGRX.WIDTH+GROUP_REGRX.START-1):GROUP_REGRX.START]; + end + + ENDIF TRUE(GROUP_REGS[RX].TYPE == TYPE_RW) + assign wr_GROUP_REGRX.SON(TYPE==TYPE_WO) = {GROUP_REGRX.WIDTH{wr_regRX}} & pwdata[EXPR(GROUP_REGRX.WIDTH-1):0]; + assign wr_GROUP_REGRX.SON(TYPE==TYPE_IW) = {GROUP_REGRX.WIDTH{wr_regRX}} & pwdata[EXPR(GROUP_REGRX.WIDTH-1):0]; + ENDLOOP RX + + //---------------------- Read Operations ---------------------------- + always @(*) + begin + rd_regGROUP_REGS.SON(TYPE != TYPE_WO).IDX = {32{1'b0}}; + + rd_regRX[EXPR(GROUP_REGRX.WIDTH+GROUP_REGRX.START-1):GROUP_REGRX.START] = GROUP_REGRX.SON(TYPE != TYPE_WO); //GROUP_REGRX.DESC + end + + always @(*) + begin + prdata_pre = {32{1'b0}}; + + case (paddr) + GROUP_REGS : prdata_pre = rd_regGROUP_REGS.SON(TYPE != TYPE_WO).IDX; + + default : prdata_pre = {32{1'b0}}; + endcase + end + + + always @(paddr or gpread or gpwrite or psel) + begin + pslverr_pre = 1'b0; + + case (paddr) + GROUP_REGS.SON(TYPE==TYPE_RW) : pslverr_pre = 1'b0; //read and write + GROUP_REGS.SON(TYPE==TYPE_RO) : pslverr_pre = gpwrite; //read only + GROUP_REGS.SON(TYPE==TYPE_WO) : pslverr_pre = gpread; //write only + + default : pslverr_pre = psel; //decode error + endcase + end + + + //---------------------- Sample outputs ----------------------------- + always @(posedge clk or posedge reset) + if (reset) + prdata <= #FFD {32{1'b0}}; + else if (gpread & pclken) + prdata <= #FFD prdata_pre; + else if (pclken) + prdata <= #FFD {32{1'b0}}; + + always @(posedge clk or posedge reset) + if (reset) + begin + pslverr <= #FFD 1'b0; + pready <= #FFD 1'b0; + end + else if ((gpread | gpwrite) & pclken) + begin + pslverr <= #FFD pslverr_pre; + pready <= #FFD 1'b1; + end + else if (pclken) + begin + pslverr <= #FFD 1'b0; + pready <= #FFD 1'b0; + end + + +endmodule + + Index: robust_reg/trunk/src/base/def_fields.txt =================================================================== --- robust_reg/trunk/src/base/def_fields.txt (nonexistent) +++ robust_reg/trunk/src/base/def_fields.txt (revision 9) @@ -0,0 +1,500 @@ + + + + + GROUP REG0 is { ;; rd_start_addr 32 SON(START 0) SON(DEFAULT 0) SON(TYPE TYPE_RW) ;; } + GROUP REG1 is { ;; wr_start_addr 32 SON(START 0) SON(DEFAULT 0) SON(TYPE TYPE_RW) ;; } + GROUP REG2 is { ;; buffer_size 32 SON(START 0) SON(DEFAULT 0) SON(TYPE TYPE_RW) ;; } + GROUP REG3 is { ;; set_int 1 SON(START 0) SON(DEFAULT 0) SON(TYPE TYPE_RO) + cmd_last 1 SON(START 1) SON(DEFAULT 1) SON(TYPE TYPE_RW) + next_addr 28 SON(START 4) SON(DEFAULT 0) SON(TYPE TYPE_RW) ;; } + GROUP REG4 is { ;; ch_start 1 SON(START 0) SON(DEFAULT 0) SON(TYPE TYPE_WO) ;; } + GROUP REG5 is { ;; buff_count 16 SON(START 0) SON(DEFAULT 0) SON(TYPE TYPE_RO) + int_count 6 SON(START 16) SON(DEFAULT 0) SON(TYPE TYPE_RO) ;; } + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: robust_reg/trunk/src/base/regfile.h =================================================================== --- robust_reg/trunk/src/base/regfile.h (nonexistent) +++ robust_reg/trunk/src/base/regfile.h (revision 9) @@ -0,0 +1,45 @@ +<##////////////////////////////////////////////////////////////////// +//// //// +//// Author: Eyal Hochberg //// +//// eyal@provartec.com //// +//// //// +//// Downloaded from: http://www.opencores.org //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2010 Provartec LTD //// +//// www.provartec.com //// +//// info@provartec.com //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation.//// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more//// +//// details. http://www.gnu.org/licenses/lgpl.html //// +//// //// +//////////////////////////////////////////////////////////////////##> + +OUTFILE REGNAME_regfile.h +INCLUDE def_regfile.txt + +//registers +#define REGNAME_GROUP_REGS_ADDR 0xGROUP_REGS.ADDR + +//fields +LOOP RX REG_NUM +//register GROUP_REGS[RX]: +#define REGNAME_GROUP_REGRX_ADDR 0xGROUP_REGS[RX].ADDR +#define REGNAME_GROUP_REGRX_START GROUP_REGRX.START +#define REGNAME_GROUP_REGRX_BITS GROUP_REGRX.WIDTH +#define REGNAME_GROUP_REGRX_MASK 0xHEX(EXPR((2^GROUP_REGRX.WIDTH-1) << GROUP_REGRX.START) 32 NOPRE) + +ENDLOOP RX + Index: robust_reg/trunk/src/base/regs.xls =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: robust_reg/trunk/src/base/regs.xls =================================================================== --- robust_reg/trunk/src/base/regs.xls (nonexistent) +++ robust_reg/trunk/src/base/regs.xls (revision 9)
robust_reg/trunk/src/base/regs.xls Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: robust_reg/trunk/src/base/def_regfile.txt =================================================================== --- robust_reg/trunk/src/base/def_regfile.txt (nonexistent) +++ robust_reg/trunk/src/base/def_regfile.txt (revision 9) @@ -0,0 +1,57 @@ +<##////////////////////////////////////////////////////////////////// +//// //// +//// Author: Eyal Hochberg //// +//// eyal@provartec.com //// +//// //// +//// Downloaded from: http://www.opencores.org //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2010 Provartec LTD //// +//// www.provartec.com //// +//// info@provartec.com //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation.//// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more//// +//// details. http://www.gnu.org/licenses/lgpl.html //// +//// //// +//////////////////////////////////////////////////////////////////##> + +INCLUDE def_regs.txt +INCLUDE def_fields.txt + +SWAP FFD 1 ##flip-flop delay + +## Types: +## RW - read / write (output from block) +## RO - read only (input to block) +## WO - write only (output to block) +## IW - internal write (output to block - logic is added especially) +## IR - internal read (no port - logic is added especially) +ENUM TYPE_RW TYPE_RO TYPE_WO TYPE_IW TYPE_IR + +SWAP TYPE_TYPE_RW Read and Write +SWAP TYPE_TYPE_RO Read only +SWAP TYPE_TYPE_WO Write only + +GROUP APB is { + pclken 1 input + psel 1 input + penable 1 input + paddr ADDR_BITS input + pwrite 1 input + pwdata 32 input + prdata 32 output + pslverr 1 output + pready 1 output +} Index: robust_reg/trunk/src/base/def_regs.txt =================================================================== --- robust_reg/trunk/src/base/def_regs.txt (nonexistent) +++ robust_reg/trunk/src/base/def_regs.txt (revision 9) @@ -0,0 +1,299 @@ + + + SWAP REGNAME DMA + SWAP REG_NUM 6 + + + GROUP REGS is { + CONFIG0 SON(ADDR 0) SON(TYPE TYPE_RW) ##reg number 0 + CONFIG1 SON(ADDR 4) SON(TYPE TYPE_RW) ##reg number 1 + CONFIG2 SON(ADDR 8) SON(TYPE TYPE_RW) ##reg number 2 + CONFIG3 SON(ADDR C) SON(TYPE TYPE_RW) ##reg number 3 + START SON(ADDR 20) SON(TYPE TYPE_WO) ##reg number 4 + STATUS SON(ADDR 30) SON(TYPE TYPE_RO) ##reg number 5 + } + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

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