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URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

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Rev 8 → Rev 9

/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.dir/5_1.ncd Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.dir/5_1.pad
6,32 → 6,31
PACKAGE: CABGA381
Package Status: Final Version 1.36
 
Tue Jan 17 01:36:59 2017
Wed Jan 18 01:08:45 2017
 
Pinout by Port Name:
+---------------+----------+--------------+-------+-----------+---------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | BC Enable | Properties |
+---------------+----------+--------------+-------+-----------+---------------------------------+
| button | T1/8 | LVCMOS25_IN | PB4B | | PULL:UP CLAMP:ON HYSTERESIS:ON |
| clk | P3/6 | LVDS_IN | PL68C | | CLAMP:ON |
| disp_data[0] | M20/3 | LVCMOS25_OUT | PR35B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[10] | N18/3 | LVCMOS25_OUT | PR41C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[11] | N17/3 | LVCMOS25_OUT | PR44A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[12] | P16/3 | LVCMOS25_OUT | PR44B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[13] | R16/3 | LVCMOS25_OUT | PR44C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[14] | U1/8 | LVCMOS25_OUT | PB6A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[1] | L18/3 | LVCMOS25_OUT | PR38C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[2] | M19/3 | LVCMOS25_OUT | PR35D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[3] | L16/3 | LVCMOS25_OUT | PR38A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[4] | L17/3 | LVCMOS25_OUT | PR38B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[5] | M18/3 | LVCMOS25_OUT | PR38D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[6] | R17/3 | LVCMOS25_OUT | PR44D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[7] | P17/3 | LVCMOS25_OUT | PR41D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[8] | N16/3 | LVCMOS25_OUT | PR41A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[9] | M17/3 | LVCMOS25_OUT | PR41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_sel | J1/6 | LVCMOS25_OUT | PL41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| n_rst | K20/2 | LVCMOS25_IN | PR32D | | PULL:UP CLAMP:ON HYSTERESIS:ON |
+---------------+----------+--------------+-------+-----------+---------------------------------+
+-----------------+----------+--------------+-------+-----------+---------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | BC Enable | Properties |
+-----------------+----------+--------------+-------+-----------+---------------------------------+
| button | T1/8 | LVCMOS25_IN | PB4B | | PULL:UP CLAMP:ON HYSTERESIS:ON |
| clk | P3/6 | LVDS_IN | PL68C | | CLAMP:ON |
| disp_data_q[0] | M20/3 | LVCMOS25_OUT | PR35B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[10] | N18/3 | LVCMOS25_OUT | PR41C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[11] | N17/3 | LVCMOS25_OUT | PR44A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[12] | P16/3 | LVCMOS25_OUT | PR44B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[13] | R16/3 | LVCMOS25_OUT | PR44C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[14] | U1/8 | LVCMOS25_OUT | PB6A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[1] | L18/3 | LVCMOS25_OUT | PR38C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[2] | M19/3 | LVCMOS25_OUT | PR35D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[3] | L16/3 | LVCMOS25_OUT | PR38A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[4] | L17/3 | LVCMOS25_OUT | PR38B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[5] | M18/3 | LVCMOS25_OUT | PR38D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[6] | R17/3 | LVCMOS25_OUT | PR44D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[7] | P17/3 | LVCMOS25_OUT | PR41D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[8] | N16/3 | LVCMOS25_OUT | PR41A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[9] | M17/3 | LVCMOS25_OUT | PR41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| n_rst | K20/2 | LVCMOS25_IN | PR32D | | PULL:UP CLAMP:ON HYSTERESIS:ON |
+-----------------+----------+--------------+-------+-----------+---------------------------------+
 
Vccio by Bank:
+------+-------+
39,7 → 38,7
+------+-------+
| 2 | 2.5V |
| 3 | 2.5V |
| 6 | 2.5V |
| 6 | 1.2V |
| 8 | 2.5V |
+------+-------+
 
175,7 → 174,7
| H17/2 | unused, PULL:DOWN | | | PR20B | RDQ17 | |
| H18/2 | unused, PULL:DOWN | | | PR20A | RDQ17 | |
| H20/2 | unused, PULL:DOWN | | | PR29B | RDQSN29 | |
| J1/6 | disp_sel | LOCATED | LVCMOS25_OUT | PL41B | LDQSN41 | |
| J1/6 | unused, PULL:DOWN | | | PL41B | LDQSN41 | |
| J3/6 | unused, PULL:DOWN | | | PL38C | GR_PCLK6_1/LDQ41 | |
| J4/6 | unused, PULL:DOWN | | | PL38A | GR_PCLK6_0/LDQ41 | |
| J5/6 | unused, PULL:DOWN | | | PL38B | LDQ41 | |
197,9 → 196,9
| L3/6 | unused, PULL:DOWN | | | PL62C | LDQ65 | |
| L4/6 | unused, PULL:DOWN | | | PL44C | LDQ41 | |
| L5/6 | unused, PULL:DOWN | | | PL44D | LDQ41 | |
| L16/3 | disp_data[3] | LOCATED | LVCMOS25_OUT | PR38A | GR_PCLK3_0/RDQ41 | |
| L17/3 | disp_data[4] | LOCATED | LVCMOS25_OUT | PR38B | RDQ41 | |
| L18/3 | disp_data[1] | LOCATED | LVCMOS25_OUT | PR38C | GR_PCLK3_1/RDQ41 | |
| L16/3 | disp_data_q[3] | LOCATED | LVCMOS25_OUT | PR38A | GR_PCLK3_0/RDQ41 | |
| L17/3 | disp_data_q[4] | LOCATED | LVCMOS25_OUT | PR38B | RDQ41 | |
| L18/3 | disp_data_q[1] | LOCATED | LVCMOS25_OUT | PR38C | GR_PCLK3_1/RDQ41 | |
| L19/3 | unused, PULL:DOWN | | | PR35C | PCLKT3_0/RDQ41 | |
| L20/3 | unused, PULL:DOWN | | | PR35A | PCLKT3_1/RDQ41 | |
| M1/6 | unused, PULL:DOWN | | | PL65B | LDQSN65 | |
206,18 → 205,18
| M3/6 | unused, PULL:DOWN | | | PL62B | LDQ65 | |
| M4/6 | unused, PULL:DOWN | | | PL59A | LDQ65 | |
| M5/6 | unused, PULL:DOWN | | | PL53A | LDQS53 | |
| M17/3 | disp_data[9] | LOCATED | LVCMOS25_OUT | PR41B | RDQSN41 | |
| M18/3 | disp_data[5] | LOCATED | LVCMOS25_OUT | PR38D | RDQ41 | |
| M19/3 | disp_data[2] | LOCATED | LVCMOS25_OUT | PR35D | PCLKC3_0/RDQ41 | |
| M20/3 | disp_data[0] | LOCATED | LVCMOS25_OUT | PR35B | PCLKC3_1/RDQ41 | |
| M17/3 | disp_data_q[9] | LOCATED | LVCMOS25_OUT | PR41B | RDQSN41 | |
| M18/3 | disp_data_q[5] | LOCATED | LVCMOS25_OUT | PR38D | RDQ41 | |
| M19/3 | disp_data_q[2] | LOCATED | LVCMOS25_OUT | PR35D | PCLKC3_0/RDQ41 | |
| M20/3 | disp_data_q[0] | LOCATED | LVCMOS25_OUT | PR35B | PCLKC3_1/RDQ41 | |
| N1/6 | unused, PULL:DOWN | | | PL65D | LDQ65 | |
| N2/6 | unused, PULL:DOWN | | | PL65A | LDQS65 | |
| N3/6 | unused, PULL:DOWN | | | PL62A | LDQ65 | |
| N4/6 | unused, PULL:DOWN | | | PL59C | LDQ65 | |
| N5/6 | unused, PULL:DOWN | | | PL59B | LDQ65 | |
| N16/3 | disp_data[8] | LOCATED | LVCMOS25_OUT | PR41A | RDQS41 | |
| N17/3 | disp_data[11] | LOCATED | LVCMOS25_OUT | PR44A | RDQ41 | |
| N18/3 | disp_data[10] | LOCATED | LVCMOS25_OUT | PR41C | RDQ41 | |
| N16/3 | disp_data_q[8] | LOCATED | LVCMOS25_OUT | PR41A | RDQS41 | |
| N17/3 | disp_data_q[11] | LOCATED | LVCMOS25_OUT | PR44A | RDQ41 | |
| N18/3 | disp_data_q[10] | LOCATED | LVCMOS25_OUT | PR41C | RDQ41 | |
| N19/3 | unused, PULL:DOWN | | | PR59A | RDQ65 | |
| N20/3 | unused, PULL:DOWN | | | PR59B | RDQ65 | |
| P1/6 | unused, PULL:DOWN | | | PL68A | LDQ65 | |
225,8 → 224,8
| P3/6 | clk+ | LOCATED | LVDS_IN | PL68C | LLC_GPLL0T_IN/LDQ65 | |
| P4/6 | clk- | | LVDS_IN | PL68D | LLC_GPLL0C_IN/LDQ65 | |
| P5/6 | unused, PULL:DOWN | | | PL59D | LDQ65 | |
| P16/3 | disp_data[12] | LOCATED | LVCMOS25_OUT | PR44B | VREF1_3/RDQ41 | |
| P17/3 | disp_data[7] | LOCATED | LVCMOS25_OUT | PR41D | RDQ41 | |
| P16/3 | disp_data_q[12] | LOCATED | LVCMOS25_OUT | PR44B | VREF1_3/RDQ41 | |
| P17/3 | disp_data_q[7] | LOCATED | LVCMOS25_OUT | PR41D | RDQ41 | |
| P18/3 | unused, PULL:DOWN | | | PR59D | RDQ65 | |
| P19/3 | unused, PULL:DOWN | | | PR59C | RDQ65 | |
| P20/3 | unused, PULL:DOWN | | | PR62A | RDQ65 | |
275,8 → 274,8
| R1/8 | unused, PULL:DOWN | | | PB4A | D7/IO7 | |
| R2/8 | unused, PULL:DOWN | | | PB15A | HOLDN/DI/BUSY/CSSPIN/CEN | |
| R3/8 | unused, PULL:DOWN | | | PB15B | DOUT/CSON | |
| R16/3 | disp_data[13] | LOCATED | LVCMOS25_OUT | PR44C | RDQ41 | |
| R17/3 | disp_data[6] | LOCATED | LVCMOS25_OUT | PR44D | RDQ41 | |
| R16/3 | disp_data_q[13] | LOCATED | LVCMOS25_OUT | PR44C | RDQ41 | |
| R17/3 | disp_data_q[6] | LOCATED | LVCMOS25_OUT | PR44D | RDQ41 | |
| R18/3 | unused, PULL:DOWN | | | PR65B | RDQSN65 | |
| R20/3 | unused, PULL:DOWN | | | PR62B | RDQ65 | |
| T1/8 | button | LOCATED | LVCMOS25_IN | PB4B | D6/IO6 | |
291,7 → 290,7
| TDI/40 | | | | TDI | | |
| TDO/40 | | | | TDO | | |
| TMS/40 | | | | TMS | | |
| U1/8 | disp_data[14] | LOCATED | LVCMOS25_OUT | PB6A | D5/MISO2/IO5 | |
| U1/8 | disp_data_q[14] | LOCATED | LVCMOS25_OUT | PB6A | D5/MISO2/IO5 | |
| U2/8 | unused, PULL:DOWN | | | PB13B | CS1N | |
| U16/3 | unused, PULL:DOWN | | | PR68C | LRC_GPLL0T_IN/RDQ65 | |
| U17/3 | unused, PULL:DOWN | | | PR68B | RDQ65 | |
331,22 → 330,21
 
LOCATE COMP "button" SITE "T1";
LOCATE COMP "clk" SITE "P3";
LOCATE COMP "disp_data[0]" SITE "M20";
LOCATE COMP "disp_data[10]" SITE "N18";
LOCATE COMP "disp_data[11]" SITE "N17";
LOCATE COMP "disp_data[12]" SITE "P16";
LOCATE COMP "disp_data[13]" SITE "R16";
LOCATE COMP "disp_data[14]" SITE "U1";
LOCATE COMP "disp_data[1]" SITE "L18";
LOCATE COMP "disp_data[2]" SITE "M19";
LOCATE COMP "disp_data[3]" SITE "L16";
LOCATE COMP "disp_data[4]" SITE "L17";
LOCATE COMP "disp_data[5]" SITE "M18";
LOCATE COMP "disp_data[6]" SITE "R17";
LOCATE COMP "disp_data[7]" SITE "P17";
LOCATE COMP "disp_data[8]" SITE "N16";
LOCATE COMP "disp_data[9]" SITE "M17";
LOCATE COMP "disp_sel" SITE "J1";
LOCATE COMP "disp_data_q[0]" SITE "M20";
LOCATE COMP "disp_data_q[10]" SITE "N18";
LOCATE COMP "disp_data_q[11]" SITE "N17";
LOCATE COMP "disp_data_q[12]" SITE "P16";
LOCATE COMP "disp_data_q[13]" SITE "R16";
LOCATE COMP "disp_data_q[14]" SITE "U1";
LOCATE COMP "disp_data_q[1]" SITE "L18";
LOCATE COMP "disp_data_q[2]" SITE "M19";
LOCATE COMP "disp_data_q[3]" SITE "L16";
LOCATE COMP "disp_data_q[4]" SITE "L17";
LOCATE COMP "disp_data_q[5]" SITE "M18";
LOCATE COMP "disp_data_q[6]" SITE "R17";
LOCATE COMP "disp_data_q[7]" SITE "P17";
LOCATE COMP "disp_data_q[8]" SITE "N16";
LOCATE COMP "disp_data_q[9]" SITE "M17";
LOCATE COMP "n_rst" SITE "K20";
 
 
359,5 → 357,5
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
Tue Jan 17 01:36:59 2017
Wed Jan 18 01:08:45 2017
 
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.dir/5_1.par
1,6 → 1,6
 
Lattice Place and Route Report for Design "DisplayDriverwDecoder_impl1_map.ncd"
Tue Jan 17 01:36:43 2017
Wed Jan 18 01:08:29 2017
 
PAR: Place And Route Diamond (64-bit) 3.8.0.115.3.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir/5_1.ncd DisplayDriverwDecoder_impl1.prf
9,7 → 9,7
Routing Iterations: 6
 
Loading design for application par from file DisplayDriverwDecoder_impl1_map.ncd.
Design name: DisplayDriverWrapper
Design name: display_driver_wrapper
NCD version: 3.3
Vendor: LATTICE
Device: LFE5UM5G-45F
24,8 → 24,8
Ignore Preference Error(s): True
Device utilization summary:
 
PIO (prelim) 20/245 8% used
20/203 9% bonded
PIO (prelim) 19/245 7% used
19/203 9% bonded
IOLOGIC 1/245 <1% used
 
SLICE 65/21924 <1% used
37,7 → 37,7
Number of Connections: 657
 
Pin Constraint Summary:
19 out of 19 pins locked (100% locked).
18 out of 18 pins locked (100% locked).
 
The following 1 signal is selected to use the primary clock routing resources:
clk_c (driver: clk, clk/ce/sr load #: 9/0/0)
97,9 → 97,9
 
+
I/O Usage Summary (final):
20 out of 245 (8.2%) PIO sites used.
20 out of 203 (9.9%) bonded PIO sites used.
Number of PIO comps: 19; differential: 1.
19 out of 245 (7.8%) PIO sites used.
19 out of 203 (9.4%) bonded PIO sites used.
Number of PIO comps: 18; differential: 1.
Number of Vref pins used: 0.
 
I/O Bank Usage Summary:
110,12 → 110,12
| 1 | 0 / 33 ( 0%) | - | - | - |
| 2 | 1 / 32 ( 3%) | 2.5V | - | - |
| 3 | 14 / 33 ( 42%) | 2.5V | - | - |
| 6 | 3 / 33 ( 9%) | 2.5V | - | - |
| 6 | 2 / 33 ( 6%) | 1.2V | - | - |
| 7 | 0 / 32 ( 0%) | - | - | - |
| 8 | 2 / 13 ( 15%) | 2.5V | - | - |
+----------+----------------+------------+------------+------------+
 
Total placer CPU time: 15 secs
Total placer CPU time: 14 secs
 
Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.
 
122,9 → 122,9
0 connections routed; 657 unrouted.
Starting router resource preassignment
 
Completed router resource preassignment. Real time: 23 secs
Completed router resource preassignment. Real time: 22 secs
 
Start NBR router at 01:37:06 01/17/17
Start NBR router at 01:08:51 01/18/17
 
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
139,26 → 139,26
your design.
*****************************************************************
 
Start NBR special constraint process at 01:37:06 01/17/17
Start NBR special constraint process at 01:08:52 01/18/17
 
Start NBR section for initial routing at 01:37:06 01/17/17
Start NBR section for initial routing at 01:08:52 01/18/17
Level 1, iteration 1
0(0.00%) conflict; 544(82.80%) untouched conns; 8380 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.227ns/-8.380ns; real time: 24 secs
Estimated worst slack/total negative slack<setup>: -1.227ns/-8.380ns; real time: 23 secs
Level 2, iteration 1
0(0.00%) conflict; 542(82.50%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 23 secs
Level 3, iteration 1
0(0.00%) conflict; 523(79.60%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 23 secs
Level 4, iteration 1
5(0.00%) conflicts; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 23 secs
 
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
 
Start NBR section for normal routing at 01:37:07 01/17/17
Start NBR section for normal routing at 01:08:53 01/18/17
Level 1, iteration 1
0(0.00%) conflict; 8(1.22%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
172,17 → 172,17
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
 
Start NBR section for performance tuning (iteration 1) at 01:37:07 01/17/17
Start NBR section for performance tuning (iteration 1) at 01:08:53 01/18/17
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
 
Start NBR section for re-routing at 01:37:07 01/17/17
Start NBR section for re-routing at 01:08:53 01/18/17
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
 
Start NBR section for post-routing at 01:37:07 01/17/17
Start NBR section for post-routing at 01:08:53 01/18/17
 
End NBR router with 0 unrouted connection
 
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.dir/5_1_par.asd
32,9 → 32,9
BANK_3_VREF1 = NA;
BANK_3_VREF2 = NA;
; I/O Bank 6 Usage
BANK_6_USED = 3;
BANK_6_USED = 2;
BANK_6_AVAIL = 33;
BANK_6_VCCIO = 2.5V;
BANK_6_VCCIO = 1.2V;
BANK_6_VREF1 = NA;
BANK_6_VREF2 = NA;
; I/O Bank 7 Usage
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.dir/DisplayDriverwDecoder_impl1.par
4,7 → 4,7
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
Tue Jan 17 01:36:43 2017
Wed Jan 18 01:08:29 2017
 
C:/lscc/diamond/3.8_x64/ispfpga\bin\nt64\par -f DisplayDriverwDecoder_impl1.p2t
DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir
17,11 → 17,11
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 -1.238 7103 0.178 0 26 Complete
5_1 * 0 -1.238 7103 0.178 0 25 Complete
 
 
* : Design saved.
 
Total (real) run time for 1-seed: 26 secs
Total (real) run time for 1-seed: 25 secs
 
par done!
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/dm/layer0.xdm
15,17 → 15,15
/>S1S<FOksC=Rb"\B:DO#O\N8Hl8FM\Ud3_cGn\M#$b#LNCH\DLE\P8M\k#MHoCP83ER8"Nn=""=RD"8PEDO"RD0H#=4"-"DRbH=#0""-4/S>
SF<1kCsOR"b=BD:\#\OO8lHNF\M8d_3UG\nc#b$MLCN#\LDH\8PE\bE$CMsC0P#3ER8"N(=""=RD"8PEDO"RD0H#=4"-"DRbH=#0""-4/S>
SF<1kCsOR"b=BD:\#\OO8lHNF\M8d_3UG\ncO_NCDsHLN\s$#0$MEHC##E\P8CD\Okb6lE3P8N"R=""UR"D=PDE8"DROH=#0""-4RHbD#"0=R/g">S
S<k1FsROCbB=":s\uFO[C0##\HDMoCc-4-o#Cl0CM-#8Hb$DN-H8sP-CsIC-8OCF8ss\uFO[C0F\1kCsO#C\7OHF8Mao_NCLD\v)m_Bq1Q7Q_C8OFC7s\H)#0F#lqO7HHC8OFC7s\H)#0F#lqO7HHC8OFC7s\H)#0F#lqO7HHC8OFCPs3ER8"Ng=""=RD"8PEDO"RD0H#=U"R"DRbH=#0"4R4"
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<F)F0=RM"sIF H38#NbD$s_8HsPC_NIsbsbC3ONsE>"/
<
S!R--vkF8D7CRCMVHHF0HM-R-><
S7RCVMI="F3s )4mv.4UXq$3#MD_LN_O L"FGR"D=PDE8"S>
41,7 → 39,7
/>SqS<R"M=3HFsoOqsElhNCP"R=J"&k;F0#_$MLODN F_LGk&JF"0;/S>
SR<qM3="#_$Mks#CLRL"P4=""
/>SqS<R"M=3CODNbMk_C#0b0._H"lCR"P=jj3jjjjj"
/>SqS<R"M=3CODNbMk_C#0b04_H"lCR"P=j43j66n."
/>SqS<R"M=3CODNbMk_C#0b04_H"lCR"P=jj3jjjjj"
/>SqS<R"M=#_$MLODN F_LGP"R=""4/
>
 
48,15 → 46,17
/S<7>CV
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S7RCVMI="F3s 70H#)qFl#HOH7FCO83Cs#k0sOs0kCD"R=E"P8>D"
<SSW=RN"Rg"L"D=4R."L"O=(C"RD4=".C"RO.="6/"R>S
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<SSq=RM"F3l8CkDVCHD"=RP"/g">S
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<SSq=RM"D3OCkNMb0_#C_b.0CHl"=RP"jj3jjjjj>"/
<SSq=RM"03#lH0D#H00lRC"Pj="36j4n".6/S>
SR<qMh="t77_)vB_q"1iR"P=4>"/
S7RCVMI="F3s 8FCO8_Cs0DNLCH_8#s0_F#l30Osk0Cks"=RD"8PED
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<SSq=RM"s3FHNohlRC"PI="F3s 8FCO8_Cs0DNLCH_8#s0_F#l30Osk0Cks"
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SR<qM3="lkF8DHCVDRC"Pg=""
/>SqS<R"M=3HFsoOqsElhNCP"R=J"&k;F0#k0sOs0kCk&JF"0;/S>
SR<qM3="ONDCM_kb#b0C.H_0lRC"Pj="3jjjj"jj/S>
SR<qM3="#00lD0H#0CHl"=RP"jj3jjjjj>"/
<SSq=RM"7ht_B7)_1vqiP"R=""4/
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<SS!R--vkF8D)CRCsVCCCMO#QR5MN#0MN0H0MHF#-2R-S>
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SSS<NWR=""gR=LD"".6R=LO"Rc"C"D=.R6"C"O=4R4"/S>
171,56 → 171,60
V>S7</C
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<SSW=RN""44R=LD""46R=LO"R("C"D=4R6"C"O=4Rg"/S>
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/>SqS<R"M=3ONsEDVHCP"R=4"4"
/>SqS<R"M=38lFkVDCH"DCR"P=4/4">S
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/>SqS<R"M=3CODNbMk_C#0b04_H"lCR"P=jj3jjjjj"
/>SqS<R"M=3l#00#DH0l0HCP"R=3"jjjjjj/j">
 
 
 
<SS!R--vkF8D)CRCsVCCCMO#QR5MN#0MN0H0MHF#-2R-S>
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<SSq=RM"s3NOHEVDRC"P4=".>"/
<SSq=RM"F3l8CkDVCHD"=RP""4./S>
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S<MqR=O"3DMCNk#b_04Cb_l0HCP"R=3"jjjjjj/j">S
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<SS!R--vkF8D)CRCsVCCCMO#QR5MN#0MN0H0MHF#-2R-S>
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SSS<NWR=4"4"DRL=6"d"ORL=("."DRC=6"d"ORC=j"6">R/
<SS/V)C><
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/>S/S<)>CV
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SR<WN4="dL"RD4="6L"RO(=""DRC=6"4"ORC=U".">R/
<SSq=RM"s3NOHEVDRC"P4="d>"/
<SSq=RM"F3l8CkDVCHD"=RP""4d/S>
SR<qM3="FosHqEsOhCNl"=RP"k&JFN0;s&OEJ0kF;>"/
<SSq=RM"D3OCkNMb0_#C_b.0CHl"=RP"jj3jjjjj>"/
<SSq=RM"D3OCkNMb0_#C_b40CHl"=RP"jj3jjjjj>"/
<SSq=RM"03#lH0D#H00lRC"Pj="3jjjj"jj/S>
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/>
 
 
<SS!R--vkF8D)CRCsVCCCMO#QR5MN#0MN0H0MHF#-2R-S>
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SWS<R"N=4Rd"L"D=UR."L"O=cRj"C"D=UR."C"O=nRU"/S>
S)</C
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<SSq=RM"s3FHNohlRC"P&="J0kF;#7Hb$DN7PsHCssWNCbbsk&JF"0;/
>
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<SS!R--vkF8D)CRCsVCCCMO#QR5MN#0MN0H0MHF#-2R-S>
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/S<7>CV
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@
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/report/DisplayDriverwDecoder_impl1_compiler_notes.txt
1,14 → 1,14
@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd":12:7:12:25|Synthesizing work.distromasciidecoder.structure.
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:28|Top entity is set to display_driver_wrapper.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:28|Synthesizing work.display_driver_wrapper.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":17:7:17:30|Synthesizing work.display_driver_w_decoder.display_driver_w_decoder_arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":15:7:15:19|Synthesizing work.ascii_decoder.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\decoder_table_dist_rom_impl\decoder_table_dist_rom\decoder_table_dist_rom.vhd":12:7:12:28|Synthesizing work.decoder_table_dist_rom.structure.
@N: CD630 :"C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd":801:10:801:18|Synthesizing work.rom128x1a.syn_black_box.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":29:8:29:12|Input wr_en is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":23:8:23:12|Input wr_en is unused.
@N|Running in 64-bit mode
 
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/report/DisplayDriverwDecoder_impl1_compiler_runstatus.xml
18,7 → 18,7
<report_link name="more"><data>C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synlog\report\DisplayDriverwDecoder_impl1_compiler_notes.txt</data></report_link>
</info>
<info name="Warnings">
<data>4</data>
<data>1</data>
<report_link name="more"><data>C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synlog\report\DisplayDriverwDecoder_impl1_compiler_warnings.txt</data></report_link>
</info>
<info name="Errors">
35,7 → 35,7
<data>-</data>
</info>
<info name="Date &amp;Time">
<data type="timestamp">1484608749</data>
<data type="timestamp">1484694493</data>
</info>
</job_info>
</job_run_status>
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/report/DisplayDriverwDecoder_impl1_compiler_warnings.txt
1,5 → 1,2
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":38:11:38:15|Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":53:11:53:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_5. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_fifo_5(3 downto 0). Make sure that there are no unused intermediate registers.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":42:11:42:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
 
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/report/DisplayDriverwDecoder_impl1_fpga_mapper_area_report.xml
9,7 → 9,7
<title>Resource Usage</title>
</report_link>
<parameter tooltip="Total Register bits used" name="Register bits">
<data>9</data>
<data>13</data>
</parameter>
<parameter tooltip="Total I/O cells used" name="I/O cells">
<data>18</data>
21,6 → 21,6
<data>0</data>
</parameter>
<parameter tcl_name="total_luts" tooltip="Total ORCA LUTs used" name="ORCA LUTs">
<data>0</data>
<data>4</data>
</parameter>
</report_table>
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/report/DisplayDriverwDecoder_impl1_fpga_mapper_combined_clk.rpt
5,15 → 5,15
 
#### START OF CLOCK OPTIMIZATION REPORT #####[
 
1 non-gated/non-generated clock tree(s) driving 9 clock pin(s) of sequential element(s)
1 non-gated/non-generated clock tree(s) driving 13 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
8 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
============================= Non-Gated/Non-Generated Clocks ==============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
-------------------------------------------------------------------------------------------
@K:CKID0001 button port 9 symbol_scan_cntr[0]
===========================================================================================
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
@K:CKID0001 clk port 13 bttn_state
=======================================================================================
 
 
##### END OF CLOCK OPTIMIZATION REPORT ######]
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/report/DisplayDriverwDecoder_impl1_fpga_mapper_notes.txt
1,8 → 1,8
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: MT206 |Auto Constrain mode is enabled
@N: FX271 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Replicating instance symbol_scan_cntr[0] (in view: work.DisplayDriverWrapper(arch)) with 15 loads 1 time to improve timing.
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
@N: MT611 :|Automatically generated clock display_driver_wrapper|bttn_state_derived_clock is not used and is being removed
@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/report/DisplayDriverwDecoder_impl1_fpga_mapper_resourceusage.rpt
1,17 → 1,21
Resource Usage Report
Part: lfe5um5g_45f-8
 
Register bits: 9 of 43848 (0%)
Register bits: 13 of 43848 (0%)
PIC Latch: 0
I/O cells: 18
 
Details:
CCU2C: 5
FD1S3DX: 9
FD1P3DX: 8
FD1S3AX: 1
FD1S3JX: 3
GSR: 1
IB: 2
INV: 1
OB: 16
IB: 3
IFS1P3JX: 1
INV: 2
OB: 15
ORCALUT4: 4
PUR: 1
ROM128X1A: 14
VHI: 1
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/report/DisplayDriverwDecoder_impl1_fpga_mapper_runstatus.xml
40,7 → 40,7
<data>145MB</data>
</info>
<info name="Date &amp; Time">
<data type="timestamp">1484608753</data>
<data type="timestamp">1484694497</data>
</info>
</job_info>
</job_run_status>
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/report/DisplayDriverwDecoder_impl1_fpga_mapper_timing_report.xml
15,9 → 15,9
<data tcl_name="slack">Slack</data>
</row>
<row>
<data>DisplayDriverWrapper|button</data>
<data>443.5 MHz</data>
<data>377.0 MHz</data>
<data>-0.398</data>
<data>display_driver_wrapper|clk</data>
<data>433.9 MHz</data>
<data>368.8 MHz</data>
<data>-0.407</data>
</row>
</report_table>
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/report/DisplayDriverwDecoder_impl1_fpga_mapper_warnings.txt
1,9 → 15,9
@W: MT420 |Found inferred clock DisplayDriverWrapper|button with period 2.25ns. Please declare a user-defined clock on object "p:button"
@W: MT420 |Found inferred clock display_driver_wrapper|clk with period 2.30ns. Please declare a user-defined clock on object "p:clk"
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/report/DisplayDriverwDecoder_impl1_premap_runstatus.xml
40,7 → 40,7
<data>141MB</data>
</info>
<info name="Date &amp; Time">
<data type="timestamp">1484608751</data>
<data type="timestamp">1484694495</data>
</info>
</job_info>
</job_run_status>
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/report/DisplayDriverwDecoder_impl1_premap_warnings.txt
1,7 → 40,7
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found inferred clock DisplayDriverWrapper|button which controls 8 sequential elements including symbol_scan_cntr[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":52:8:52:9|Found inferred clock display_driver_wrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/report/impl1_compiler_errors.txt
1,3 → 1,3
@E: CD134 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":32:33:32:35|No such identifier, rst, of proper type in current declarative region
@E: CD178 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":91:19:91:27|Can't find formal disp_data
@E: Parse errors encountered - exiting
 
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/report/impl1_compiler_notes.txt
1,16 → 1,16
@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch.
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":17:7:17:30|Synthesizing work.display_driver_w_decoder.display_driver_w_decoder_arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd":12:7:12:25|Synthesizing work.distromasciidecoder.structure.
@N: CD630 :"C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd":801:10:801:18|Synthesizing work.rom128x1a.syn_black_box.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":29:8:29:12|Input wr_en is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":23:8:23:12|Input wr_en is unused.
@N|Running in 64-bit mode
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
 
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/report/impl1_compiler_runstatus.xml
29,13 → 29,13
<data>-</data>
</info>
<info name="Real Time">
<data>0h:00m:00s</data>
<data>0h:00m:01s</data>
</info>
<info name="Peak Memory">
<data>-</data>
</info>
<info name="Date &amp;Time">
<data type="timestamp">1484609376</data>
<data type="timestamp">1484689280</data>
</info>
</job_info>
</job_run_status>
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/report/impl1_compiler_warnings.txt
1,2 → 1,2
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":53:11:53:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":47:11:47:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
 
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/report/impl1_fpga_mapper_runstatus.xml
40,7 → 40,7
<data>145MB</data>
</info>
<info name="Date &amp; Time">
<data type="timestamp">1484609380</data>
<data type="timestamp">1484689284</data>
</info>
</job_info>
</job_run_status>
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/report/impl1_premap_runstatus.xml
40,7 → 40,7
<data>142MB</data>
</info>
<info name="Date &amp; Time">
<data type="timestamp">1484609378</data>
<data type="timestamp">1484689282</data>
</info>
</job_info>
</job_run_status>
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/report/impl1_premap_warnings.txt
1,7 → 40,7
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":57:4:57:5|Found inferred clock DisplayDriverWrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":57:4:57:5|Found inferred clock DisplayDriverWrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/DisplayDriverwDecoder_impl1_compiler.srr
7,43 → 7,39
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
 
@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:28|Top entity is set to display_driver_wrapper.
File C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\ecp5um.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd changed - recompiling
VHDL syntax check successful!
 
Compiler output is up to date. No re-compile necessary
 
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":38:11:38:15|Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":53:11:53:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd":12:7:12:25|Synthesizing work.distromasciidecoder.structure.
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd changed - recompiling
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:28|Synthesizing work.display_driver_wrapper.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":17:7:17:30|Synthesizing work.display_driver_w_decoder.display_driver_w_decoder_arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":42:11:42:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":15:7:15:19|Synthesizing work.ascii_decoder.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\decoder_table_dist_rom_impl\decoder_table_dist_rom\decoder_table_dist_rom.vhd":12:7:12:28|Synthesizing work.decoder_table_dist_rom.structure.
@N: CD630 :"C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd":801:10:801:18|Synthesizing work.rom128x1a.syn_black_box.
Post processing for work.rom128x1a.syn_black_box
Post processing for work.distromasciidecoder.structure
Post processing for work.asciidecoder.arch
Post processing for work.displaydriverwdecoder_top.arch
Post processing for work.displaydriverwrapper.arch
@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_5. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_fifo_5(3 downto 0). Make sure that there are no unused intermediate registers.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":29:8:29:12|Input wr_en is unused.
Post processing for work.decoder_table_dist_rom.structure
Post processing for work.ascii_decoder.arch
Post processing for work.display_driver_w_decoder.display_driver_w_decoder_arch
Post processing for work.display_driver_wrapper.arch
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":23:8:23:12|Input wr_en is unused.
 
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:19:09 2017
# Wed Jan 18 01:08:13 2017
 
###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
@N|Running in 64-bit mode
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling
 
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
50,7 → 46,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:19:09 2017
# Wed Jan 18 01:08:13 2017
 
###########################################################]
@END
60,6 → 56,6
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:19:09 2017
# Wed Jan 18 01:08:13 2017
 
###########################################################]
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/DisplayDriverwDecoder_impl1_fpga_mapper.srr
30,7 → 30,7
 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":74:8:74:9|Found counter in view:work.display_driver_wrapper(arch) inst symbol_scan_cntr[7:0]
 
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
47,7 → 47,7
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
 
 
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
60,17 → 60,14
 
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -0.70ns 1 / 8
2 0h:00m:00s -0.70ns 1 / 8
@N: FX271 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Replicating instance symbol_scan_cntr[0] (in view: work.DisplayDriverWrapper(arch)) with 15 loads 1 time to improve timing.
Timing driven replication report
Added 1 Registers via timing driven replication
Added 0 LUTs via timing driven replication
1 0h:00m:00s -0.76ns 6 / 13
2 0h:00m:00s -0.76ns 6 / 13
 
3 0h:00m:00s -0.64ns 1 / 9
3 0h:00m:00s -0.62ns 7 / 13
 
4 0h:00m:00s -0.64ns 1 / 9
 
4 0h:00m:00s -0.58ns 6 / 13
 
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
77,6 → 74,7
 
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
 
@N: MT611 :|Automatically generated clock display_driver_wrapper|bttn_state_derived_clock is not used and is being removed
 
 
@S |Clock Optimization Summary
84,15 → 82,15
 
#### START OF CLOCK OPTIMIZATION REPORT #####[
 
1 non-gated/non-generated clock tree(s) driving 9 clock pin(s) of sequential element(s)
1 non-gated/non-generated clock tree(s) driving 13 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
8 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
============================= Non-Gated/Non-Generated Clocks ==============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
-------------------------------------------------------------------------------------------
@K:CKID0001 button port 9 symbol_scan_cntr[0]
===========================================================================================
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
@K:CKID0001 clk port 13 bttn_state
=======================================================================================
 
 
##### END OF CLOCK OPTIMIZATION REPORT ######]
102,7 → 100,7
 
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm
 
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 139MB peak: 141MB)
 
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi
109,21 → 107,21
L-2016.03L-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
 
 
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
 
@W: MT420 |Found inferred clock DisplayDriverWrapper|button with period 2.25ns. Please declare a user-defined clock on object "p:button"
@W: MT420 |Found inferred clock display_driver_wrapper|clk with period 2.30ns. Please declare a user-defined clock on object "p:clk"
 
 
##### START OF TIMING REPORT #####[
# Timing Report written on Tue Jan 17 01:19:13 2017
# Timing Report written on Wed Jan 18 01:08:17 2017
#
 
 
Top view: DisplayDriverWrapper
Requested Frequency: 443.5 MHz
Top view: display_driver_wrapper
Requested Frequency: 433.9 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
137,13 → 135,13
*******************
 
 
Worst slack in design: -0.398
Worst slack in design: -0.407
 
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
-------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button 443.5 MHz 377.0 MHz 2.255 2.652 -0.398 inferred Autoconstr_clkgroup_0
=====================================================================================================================================
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
------------------------------------------------------------------------------------------------------------------------------------
display_driver_wrapper|clk 433.9 MHz 368.8 MHz 2.305 2.712 -0.407 inferred Autoconstr_clkgroup_0
====================================================================================================================================
 
 
 
152,12 → 150,12
Clock Relationships
*******************
 
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-------------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-------------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button DisplayDriverWrapper|button | 2.255 -0.398 | No paths - | No paths - | No paths -
=================================================================================================================================================
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-----------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-----------------------------------------------------------------------------------------------------------------------------------------------
display_driver_wrapper|clk display_driver_wrapper|clk | 2.305 -0.407 | No paths - | No paths - | No paths -
===============================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
171,7 → 169,7
 
 
====================================
Detailed Report for Clock: DisplayDriverWrapper|button
Detailed Report for Clock: display_driver_wrapper|clk
====================================
 
 
179,38 → 177,41
Starting Points with Worst Slack
********************************
 
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[1] 0.933 -0.398
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[2] 0.933 -0.398
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[3] 0.933 -0.339
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[4] 0.933 -0.339
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[5] 0.933 -0.280
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[6] 0.933 -0.280
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr_fast[0] 0.753 -0.277
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[7] 0.798 0.570
================================================================================================================================
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[0] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[0] 0.933 -0.407
symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[1] 0.933 -0.348
symbol_scan_cntr[2] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[2] 0.933 -0.348
symbol_scan_cntr[3] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[3] 0.933 -0.289
symbol_scan_cntr[4] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[4] 0.933 -0.289
symbol_scan_cntr[5] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[5] 0.933 -0.230
symbol_scan_cntr[6] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[6] 0.933 -0.230
bttn_state_fifo[3] display_driver_wrapper|clk FD1S3JX Q bttn_state_fifo[3] 0.798 0.123
bttn_state display_driver_wrapper|clk FD1S3AX Q bttn_state_i 0.753 0.168
bttn_state_fifo[1] display_driver_wrapper|clk FD1S3JX Q bttn_state_fifo[1] 0.838 0.606
=====================================================================================================================
 
 
Ending Points with Worst Slack
******************************
 
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[7] 2.044 -0.398
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[5] 2.044 -0.339
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[6] 2.044 -0.339
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[3] 2.044 -0.280
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[4] 2.044 -0.280
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[1] 2.044 -0.100
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[2] 2.044 -0.100
symbol_scan_cntr[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
==============================================================================================================================
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[7] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[7] 2.094 -0.407
symbol_scan_cntr[5] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[5] 2.094 -0.348
symbol_scan_cntr[6] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[6] 2.094 -0.348
symbol_scan_cntr[3] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[3] 2.094 -0.289
symbol_scan_cntr[4] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[4] 2.094 -0.289
symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[1] 2.094 -0.230
symbol_scan_cntr[2] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[2] 2.094 -0.230
symbol_scan_cntr[0] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
symbol_scan_cntr[2] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
==================================================================================================================================
 
 
 
219,64 → 220,67
 
 
Path information for path number 1:
Requested Period: 2.255
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
= Required time: 2.094
 
- Propagation time: 2.442
- Propagation time: 2.501
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.398
= Slack (critical) : -0.407
 
Number of logic level(s): 4
Starting point: symbol_scan_cntr[1] / Q
Number of logic level(s): 5
Starting point: symbol_scan_cntr[0] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[0] Net - - - - 15
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[0] Net - - - - 1
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.894 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.894 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.501 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.501 -
===========================================================================================
 
 
Path information for path number 2:
Requested Period: 2.255
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
= Required time: 2.094
 
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.398
= Slack (non-critical) : -0.348
 
Number of logic level(s): 4
Starting point: symbol_scan_cntr[2] / Q
Starting point: symbol_scan_cntr[1] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[2] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[2] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr[1] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
288,109 → 292,118
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 3:
Requested Period: 2.255
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
= Required time: 2.094
 
- Propagation time: 2.382
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -0.339
= Slack (non-critical) : -0.348
 
Number of logic level(s): 3
Starting point: symbol_scan_cntr[3] / Q
Number of logic level(s): 4
Starting point: symbol_scan_cntr[2] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[3] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[3] Net - - - - 15
symbol_scan_cntr_cry_0[3] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr[2] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[2] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 4:
Requested Period: 2.255
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
= Required time: 2.094
 
- Propagation time: 2.382
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -0.339
= Slack (non-critical) : -0.348
 
Number of logic level(s): 3
Starting point: symbol_scan_cntr[4] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
Number of logic level(s): 4
Starting point: symbol_scan_cntr[0] / Q
Ending point: symbol_scan_cntr[5] / D
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[4] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[4] Net - - - - 15
symbol_scan_cntr_cry_0[3] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[0] Net - - - - 15
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[0] Net - - - - 1
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[5] Net - - - - 1
symbol_scan_cntr[5] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 5:
Requested Period: 2.255
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
= Required time: 2.094
 
- Propagation time: 2.382
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -0.339
= Slack (non-critical) : -0.348
 
Number of logic level(s): 3
Starting point: symbol_scan_cntr[1] / Q
Ending point: symbol_scan_cntr[5] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
Number of logic level(s): 4
Starting point: symbol_scan_cntr[0] / Q
Ending point: symbol_scan_cntr[6] / D
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[0] Net - - - - 15
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[0] Net - - - - 1
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[5] Net - - - - 1
symbol_scan_cntr[5] FD1S3DX D In 0.000 2.382 -
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_cry_0[5] CCU2C S1 Out 0.607 2.442 -
symbol_scan_cntr_s[6] Net - - - - 1
symbol_scan_cntr[6] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
409,7 → 422,7
Resource Usage Report
Part: lfe5um5g_45f-8
 
Register bits: 9 of 43848 (0%)
Register bits: 13 of 43848 (0%)
PIC Latch: 0
I/O cells: 18
 
416,11 → 429,15
 
Details:
CCU2C: 5
FD1S3DX: 9
FD1P3DX: 8
FD1S3AX: 1
FD1S3JX: 3
GSR: 1
IB: 2
INV: 1
OB: 16
IB: 3
IFS1P3JX: 1
INV: 2
OB: 15
ORCALUT4: 4
PUR: 1
ROM128X1A: 14
VHI: 1
430,6 → 447,6
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 17 01:19:13 2017
# Wed Jan 18 01:08:17 2017
 
###########################################################]
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/DisplayDriverwDecoder_impl1_fpga_mapper.srr_Min
1,12 → 1,12
 
 
##### START OF TIMING REPORT #####[
# Timing Report written on Tue Jan 17 01:19:13 2017
# Timing Report written on Wed Jan 18 01:08:17 2017
#
 
 
Top view: DisplayDriverWrapper
Requested Frequency: 443.5 MHz
Top view: display_driver_wrapper
Requested Frequency: 433.9 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
20,13 → 20,13
*******************
 
 
Worst slack in design: 0.884
Worst slack in design: 0.439
 
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
-------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button 443.5 MHz 377.0 MHz 2.255 2.652 -0.398 inferred Autoconstr_clkgroup_0
=====================================================================================================================================
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
------------------------------------------------------------------------------------------------------------------------------------
display_driver_wrapper|clk 433.9 MHz 368.8 MHz 2.305 2.712 -0.407 inferred Autoconstr_clkgroup_0
====================================================================================================================================
 
 
 
33,12 → 33,12
Clock Relationships
*******************
 
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
------------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
------------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button DisplayDriverWrapper|button | 0.000 0.884 | No paths - | No paths - | No paths -
================================================================================================================================================
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------------------------------------------
display_driver_wrapper|clk display_driver_wrapper|clk | 0.000 0.439 | No paths - | No paths - | No paths -
==============================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
52,7 → 52,7
 
 
====================================
Detailed Report for Clock: DisplayDriverWrapper|button
Detailed Report for Clock: display_driver_wrapper|clk
====================================
 
 
60,38 → 60,41
Starting Points with Worst Slack
********************************
 
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[7] 0.559 0.884
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr_fast[0] 0.527 0.884
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[1] 0.653 0.979
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[2] 0.653 0.979
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[3] 0.653 0.979
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[4] 0.653 0.979
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[5] 0.653 0.979
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[6] 0.653 0.979
===============================================================================================================================
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------------------------
bttn_state_fifo[1] display_driver_wrapper|clk FD1S3JX Q bttn_state_fifo[1] 0.587 0.439
bttn_state_fifo[2] display_driver_wrapper|clk FD1S3JX Q bttn_state_fifo[2] 0.587 0.439
bttn_state_fifo_0io[0] display_driver_wrapper|clk IFS1P3JX Q bttn_state_fifo[0] 0.587 0.439
symbol_scan_cntr[7] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[7] 0.559 0.884
symbol_scan_cntr[0] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[0] 0.653 0.979
symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[1] 0.653 0.979
symbol_scan_cntr[2] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[2] 0.653 0.979
symbol_scan_cntr[3] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[3] 0.653 0.979
symbol_scan_cntr[4] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[4] 0.653 0.979
symbol_scan_cntr[5] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[5] 0.653 0.979
========================================================================================================================
 
 
Ending Points with Worst Slack
******************************
 
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 0.148 0.884
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[7] 0.148 0.884
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 0.148 0.884
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[1] 0.148 0.979
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[2] 0.148 0.979
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[3] 0.148 0.979
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[4] 0.148 0.979
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[5] 0.148 0.979
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[6] 0.148 0.979
=============================================================================================================================
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------------------------------------
bttn_state_fifo[1] display_driver_wrapper|clk FD1S3JX D bttn_state_fifo[0] 0.148 0.439
bttn_state_fifo[2] display_driver_wrapper|clk FD1S3JX D bttn_state_fifo[1] 0.148 0.439
bttn_state_fifo[3] display_driver_wrapper|clk FD1S3JX D bttn_state_fifo[2] 0.148 0.439
bttn_state display_driver_wrapper|clk FD1S3AX D bttn_stateand 0.148 0.679
symbol_scan_cntr[7] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[7] 0.148 0.884
symbol_scan_cntr[0] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 0.128 0.933
symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 0.128 0.933
symbol_scan_cntr[2] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 0.128 0.933
symbol_scan_cntr[3] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 0.128 0.933
symbol_scan_cntr[4] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 0.128 0.933
=================================================================================================================================
 
 
 
100,29 → 103,26
 
 
Path information for path number 1:
Propagation time: 1.032
Propagation time: 0.587
+ Clock delay at starting point: 0.000 (ideal)
- Requested Period: 0.000
- Hold time: 0.148
- Clock delay at ending point: 0.000 (ideal)
= Slack (critical) : 0.884
= Slack (critical) : 0.439
 
Number of logic level(s): 1
Starting point: symbol_scan_cntr[7] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
Number of logic level(s): 0
Starting point: bttn_state_fifo[1] / Q
Ending point: bttn_state_fifo[2] / D
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------------
symbol_scan_cntr[7] FD1S3DX Q Out 0.559 0.559 -
symbol_scan_cntr[7] Net - - - - 2
symbol_scan_cntr_s_0[7] CCU2C A0 In 0.000 0.559 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.473 1.032 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 1.032 -
=========================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------
bttn_state_fifo[1] FD1S3JX Q Out 0.587 0.587 -
bttn_state_fifo[1] Net - - - - 3
bttn_state_fifo[2] FD1S3JX D In 0.000 0.587 -
====================================================================================
 
 
 
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/DisplayDriverwDecoder_impl1_fpga_mapper.szr Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/DisplayDriverwDecoder_impl1_fpga_mapper.xck
1,29 → 103,26
CKID0001:@|S:button@|E:symbol_scan_cntr[0]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001
CKID0001:@|S:clk@|E:bttn_state@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/DisplayDriverwDecoder_impl1_multi_srs_gen.srr
7,6 → 7,6
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:19:11 2017
# Wed Jan 18 01:08:14 2017
 
###########################################################]
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/DisplayDriverwDecoder_impl1_premap.srr
24,7 → 24,7
ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed: 0
syn_allowed_resources : blockrams=108 set on top level netlist DisplayDriverWrapper
syn_allowed_resources : blockrams=108 set on top level netlist display_driver_wrapper
 
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
33,13 → 33,14
Clock Summary
*****************
 
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
--------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button 918.9 MHz 1.088 inferred Autoconstr_clkgroup_0 8
========================================================================================================
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
-------------------------------------------------------------------------------------------------------------------------------------------------------------
display_driver_wrapper|bttn_state_derived_clock 1.0 MHz 1000.000 derived (from display_driver_wrapper|clk) Autoconstr_clkgroup_0 8
display_driver_wrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 5
=============================================================================================================================================================
 
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found inferred clock DisplayDriverWrapper|button which controls 8 sequential elements including symbol_scan_cntr[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":52:8:52:9|Found inferred clock display_driver_wrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
 
Finished Pre Mapping Phase.
 
55,6 → 56,6
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 17 01:19:11 2017
# Wed Jan 18 01:08:15 2017
 
###########################################################]
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/DisplayDriverwDecoder_impl1_premap.szr Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/impl1_compiler.srr
7,23 → 7,26
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
 
@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
Options changed - recompiling
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
File C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\ecp5um.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd changed - recompiling
VHDL syntax check successful!
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":53:11:53:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":17:7:17:30|Synthesizing work.display_driver_w_decoder.display_driver_w_decoder_arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":47:11:47:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd":12:7:12:25|Synthesizing work.distromasciidecoder.structure.
@N: CD630 :"C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd":801:10:801:18|Synthesizing work.rom128x1a.syn_black_box.
Post processing for work.rom128x1a.syn_black_box
Post processing for work.distromasciidecoder.structure
Post processing for work.asciidecoder.arch
Post processing for work.displaydriverwdecoder_top.arch
Post processing for work.display_driver_w_decoder.display_driver_w_decoder_arch
Post processing for work.displaydriverwrapper.arch
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":29:8:29:12|Input wr_en is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":23:8:23:12|Input wr_en is unused.
 
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
 
30,14 → 33,14
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:29:36 2017
# Tue Jan 17 23:41:20 2017
 
###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
@N|Running in 64-bit mode
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
 
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
44,7 → 47,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:29:36 2017
# Tue Jan 17 23:41:20 2017
 
###########################################################]
@END
54,6 → 57,6
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:29:36 2017
# Tue Jan 17 23:41:20 2017
 
###########################################################]
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/impl1_fpga_mapper.srr
30,7 → 30,7
 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":77:4:77:5|Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":77:4:77:5|Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
 
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
107,7 → 107,7
L-2016.03L-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
 
 
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
116,7 → 116,7
 
 
##### START OF TIMING REPORT #####[
# Timing Report written on Tue Jan 17 01:29:40 2017
# Timing Report written on Tue Jan 17 23:41:24 2017
#
 
 
447,6 → 447,6
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 17 01:29:40 2017
# Tue Jan 17 23:41:24 2017
 
###########################################################]
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/impl1_fpga_mapper.srr_Min
1,7 → 1,7
 
 
##### START OF TIMING REPORT #####[
# Timing Report written on Tue Jan 17 01:29:40 2017
# Timing Report written on Tue Jan 17 23:41:24 2017
#
 
 
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/impl1_fpga_mapper.szr Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/impl1_multi_srs_gen.srr
1,8 → 1,8
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
@N|Running in 64-bit mode
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_comp.srs changed - recompiling
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
 
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
9,6 → 9,6
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:29:37 2017
# Tue Jan 17 23:41:21 2017
 
###########################################################]
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/impl1_premap.srr
40,7 → 40,7
DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 5
=========================================================================================================================================================
 
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":57:4:57:5|Found inferred clock DisplayDriverWrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":57:4:57:5|Found inferred clock DisplayDriverWrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
 
Finished Pre Mapping Phase.
 
56,6 → 56,6
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 142MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 17 01:29:38 2017
# Tue Jan 17 23:41:22 2017
 
###########################################################]
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/impl1_premap.szr Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog/syntax_constraint_check.rpt.rptmap
1,6 → 56,6
./impl1_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report
./DisplayDriverwDecoder_impl1_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/syntmp/DisplayDriverwDecoder_impl1.plg
1,16 → 1,16
@P: Worst Slack : -0.398
@P: DisplayDriverWrapper|button - Estimated Frequency : 377.0 MHz
@P: DisplayDriverWrapper|button - Requested Frequency : 443.5 MHz
@P: DisplayDriverWrapper|button - Estimated Period : 2.652
@P: DisplayDriverWrapper|button - Requested Period : 2.255
@P: DisplayDriverWrapper|button - Slack : -0.398
@P: Worst Slack(min analysis) : 0.884
@P: DisplayDriverWrapper|button - Estimated Frequency(min analysis) : 377.0 MHz
@P: DisplayDriverWrapper|button - Requested Frequency(min analysis) : 443.5 MHz
@P: DisplayDriverWrapper|button - Estimated Period(min analysis) : 2.652
@P: DisplayDriverWrapper|button - Requested Period(min analysis) : 2.255
@P: DisplayDriverWrapper|button - Slack(min analysis) : -0.398
@P: Total Area : 1.0
@P: Worst Slack : -0.407
@P: display_driver_wrapper|clk - Estimated Frequency : 368.8 MHz
@P: display_driver_wrapper|clk - Requested Frequency : 433.9 MHz
@P: display_driver_wrapper|clk - Estimated Period : 2.712
@P: display_driver_wrapper|clk - Requested Period : 2.305
@P: display_driver_wrapper|clk - Slack : -0.407
@P: Worst Slack(min analysis) : 0.439
@P: display_driver_wrapper|clk - Estimated Frequency(min analysis) : 368.8 MHz
@P: display_driver_wrapper|clk - Requested Frequency(min analysis) : 433.9 MHz
@P: display_driver_wrapper|clk - Estimated Period(min analysis) : 2.712
@P: display_driver_wrapper|clk - Requested Period(min analysis) : 2.305
@P: display_driver_wrapper|clk - Slack(min analysis) : -0.407
@P: Total Area : 6.0
@P: Total Area : 0.0
@P: Total Area : 0.0
@P: Total Area : 0.0
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/syntmp/DisplayDriverwDecoder_impl1_srr.htm
1,60 → 1,56
<html><body><samp><pre>
<!@TC:1484608749>
<!@TC:1484694493>
#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul 4 2016
#install: C:\lscc\diamond\3.8_x64\synpbase
#OS: Windows 8 6.2
#Hostname: DESKTOP-1AUKF7V
 
# Tue Jan 17 01:19:09 2017
# Wed Jan 18 01:08:13 2017
 
#Implementation: impl1
 
<a name=compilerReport1></a>Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
@N: : <!@TM:1484608749> | Running in 64-bit mode
@N: : <!@TM:1484694493> | Running in 64-bit mode
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
 
<a name=compilerReport2></a>Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
@N: : <!@TM:1484608749> | Running in 64-bit mode
@N: : <!@TM:1484694493> | Running in 64-bit mode
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
 
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1484608749> | Setting time resolution to ns
@N: : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N::@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1484608749> | Top entity is set to DisplayDriverWrapper.
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1484694493> | Setting time resolution to ns
@N: : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd:15:7:15:29:@N::@XP_MSG">display_driver_wrapper.vhd(15)</a><!@TM:1484694493> | Top entity is set to display_driver_wrapper.
File C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\ecp5um.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd changed - recompiling
VHDL syntax check successful!
 
Compiler output is up to date. No re-compile necessary
 
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N:CD630:@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1484608749> | Synthesizing work.displaydriverwrapper.arch.
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:38:11:38:16:@W:CD638:@XP_MSG">DisplayDriverWrapper.vhd(38)</a><!@TM:1484608749> | Signal empty is undriven. Either assign the signal a value or remove the signal declaration.</font>
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd:16:7:16:32:@N:CD630:@XP_MSG">DisplayDriverwDecoder_Top.vhd(16)</a><!@TM:1484608749> | Synthesizing work.displaydriverwdecoder_top.arch.
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd:53:11:53:20:@W:CD638:@XP_MSG">DisplayDriverwDecoder_Top.vhd(53)</a><!@TM:1484608749> | Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.</font>
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd:15:7:15:19:@N:CD630:@XP_MSG">ASCIIDecoder.vhd(15)</a><!@TM:1484608749> | Synthesizing work.asciidecoder.arch.
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd:12:7:12:26:@N:CD630:@XP_MSG">DistRomAsciiDecoder.vhd(12)</a><!@TM:1484608749> | Synthesizing work.distromasciidecoder.structure.
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd:801:10:801:19:@N:CD630:@XP_MSG">ecp5um.vhd(801)</a><!@TM:1484608749> | Synthesizing work.rom128x1a.syn_black_box.
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd changed - recompiling
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd:15:7:15:29:@N:CD630:@XP_MSG">display_driver_wrapper.vhd(15)</a><!@TM:1484694493> | Synthesizing work.display_driver_wrapper.arch.
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd:17:7:17:31:@N:CD630:@XP_MSG">display_driver_w_decoder.vhd(17)</a><!@TM:1484694493> | Synthesizing work.display_driver_w_decoder.display_driver_w_decoder_arch.
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd:42:11:42:20:@W:CD638:@XP_MSG">display_driver_w_decoder.vhd(42)</a><!@TM:1484694493> | Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.</font>
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd:15:7:15:20:@N:CD630:@XP_MSG">ascii_decoder.vhd(15)</a><!@TM:1484694493> | Synthesizing work.ascii_decoder.arch.
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\decoder_table_dist_rom_impl\decoder_table_dist_rom\decoder_table_dist_rom.vhd:12:7:12:29:@N:CD630:@XP_MSG">decoder_table_dist_rom.vhd(12)</a><!@TM:1484694493> | Synthesizing work.decoder_table_dist_rom.structure.
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd:801:10:801:19:@N:CD630:@XP_MSG">ecp5um.vhd(801)</a><!@TM:1484694493> | Synthesizing work.rom128x1a.syn_black_box.
Post processing for work.rom128x1a.syn_black_box
Post processing for work.distromasciidecoder.structure
Post processing for work.asciidecoder.arch
Post processing for work.displaydriverwdecoder_top.arch
Post processing for work.displaydriverwrapper.arch
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:54:4:54:6:@W:CL169:@XP_MSG">DisplayDriverWrapper.vhd(54)</a><!@TM:1484608749> | Pruning unused register bttn_state_5. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:54:4:54:6:@W:CL169:@XP_MSG">DisplayDriverWrapper.vhd(54)</a><!@TM:1484608749> | Pruning unused register bttn_state_fifo_5(3 downto 0). Make sure that there are no unused intermediate registers.</font>
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd:17:8:17:11:@N:CL159:@XP_MSG">ASCIIDecoder.vhd(17)</a><!@TM:1484608749> | Input clk is unused.
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd:18:8:18:13:@N:CL159:@XP_MSG">ASCIIDecoder.vhd(18)</a><!@TM:1484608749> | Input reset is unused.
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd:29:8:29:13:@N:CL159:@XP_MSG">DisplayDriverwDecoder_Top.vhd(29)</a><!@TM:1484608749> | Input wr_en is unused.
Post processing for work.decoder_table_dist_rom.structure
Post processing for work.ascii_decoder.arch
Post processing for work.display_driver_w_decoder.display_driver_w_decoder_arch
Post processing for work.display_driver_wrapper.arch
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd:17:8:17:11:@N:CL159:@XP_MSG">ascii_decoder.vhd(17)</a><!@TM:1484694493> | Input clk is unused.
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd:18:8:18:13:@N:CL159:@XP_MSG">ascii_decoder.vhd(18)</a><!@TM:1484694493> | Input reset is unused.
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd:23:8:23:13:@N:CL159:@XP_MSG">display_driver_w_decoder.vhd(23)</a><!@TM:1484694493> | Input wr_en is unused.
 
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:19:09 2017
# Wed Jan 18 01:08:13 2017
 
###########################################################]
<a name=compilerReport3></a>Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
@N: : <!@TM:1484608749> | Running in 64-bit mode
@N: : <!@TM:1484694493> | Running in 64-bit mode
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling
 
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
61,7 → 57,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:19:09 2017
# Wed Jan 18 01:08:13 2017
 
###########################################################]
@END
71,11 → 67,11
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:19:09 2017
# Wed Jan 18 01:08:13 2017
 
###########################################################]
<a name=compilerReport4></a>Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
@N: : <!@TM:1484608751> | Running in 64-bit mode
@N: : <!@TM:1484694494> | Running in 64-bit mode
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_comp.srs changed - recompiling
 
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
83,7 → 79,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:19:11 2017
# Wed Jan 18 01:08:14 2017
 
###########################################################]
Pre-mapping Report
94,11 → 90,11
 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
 
@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1484608751> | No constraint file specified.
@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1484694495> | No constraint file specified.
Linked File: <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rpt:@XP_FILE">DisplayDriverwDecoder_impl1_scck.rpt</a>
Printing clock summary report in "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rpt" file
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1484608751> | Running in 64-bit mode.
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1484608751> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1484694495> | Running in 64-bit mode.
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1484694495> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
 
114,7 → 110,7
ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed: 0
syn_allowed_resources : blockrams=108 set on top level netlist DisplayDriverWrapper
syn_allowed_resources : blockrams=108 set on top level netlist display_driver_wrapper
 
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
123,13 → 119,14
<a name=mapperReport6></a>Clock Summary</a>
*****************
 
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
--------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button 918.9 MHz 1.088 inferred Autoconstr_clkgroup_0 8
========================================================================================================
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
-------------------------------------------------------------------------------------------------------------------------------------------------------------
display_driver_wrapper|bttn_state_derived_clock 1.0 MHz 1000.000 derived (from display_driver_wrapper|clk) Autoconstr_clkgroup_0 8
display_driver_wrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 5
=============================================================================================================================================================
 
<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd:74:4:74:6:@W:MT529:@XP_MSG">displaydriverwrapper.vhd(74)</a><!@TM:1484608751> | Found inferred clock DisplayDriverWrapper|button which controls 8 sequential elements including symbol_scan_cntr[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd:52:8:52:10:@W:MT529:@XP_MSG">display_driver_wrapper.vhd(52)</a><!@TM:1484694495> | Found inferred clock display_driver_wrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
 
Finished Pre Mapping Phase.
 
145,7 → 142,7
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 17 01:19:11 2017
# Wed Jan 18 01:08:15 2017
 
###########################################################]
Map & Optimize Report
156,8 → 153,8
 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
 
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1484608753> | Running in 64-bit mode.
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1484608753> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1484694497> | Running in 64-bit mode.
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1484694497> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
 
178,11 → 175,11
Available hyper_sources - for debug and ip models
None Found
 
@N:<a href="@N:MT206:@XP_HELP">MT206</a> : <!@TM:1484608753> | Auto Constrain mode is enabled
@N:<a href="@N:MT206:@XP_HELP">MT206</a> : <!@TM:1484694497> | Auto Constrain mode is enabled
 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N: : <a href="c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd:74:4:74:6:@N::@XP_MSG">displaydriverwrapper.vhd(74)</a><!@TM:1484608753> | Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
@N: : <a href="c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd:74:8:74:10:@N::@XP_MSG">display_driver_wrapper.vhd(74)</a><!@TM:1484694497> | Found counter in view:work.display_driver_wrapper(arch) inst symbol_scan_cntr[7:0]
 
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
199,7 → 196,7
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
 
 
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
212,23 → 209,21
 
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -0.70ns 1 / 8
2 0h:00m:00s -0.70ns 1 / 8
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd:74:4:74:6:@N:FX271:@XP_MSG">displaydriverwrapper.vhd(74)</a><!@TM:1484608753> | Replicating instance symbol_scan_cntr[0] (in view: work.DisplayDriverWrapper(arch)) with 15 loads 1 time to improve timing.
Timing driven replication report
Added 1 Registers via timing driven replication
Added 0 LUTs via timing driven replication
1 0h:00m:00s -0.76ns 6 / 13
2 0h:00m:00s -0.76ns 6 / 13
 
3 0h:00m:00s -0.64ns 1 / 9
3 0h:00m:00s -0.62ns 7 / 13
 
4 0h:00m:00s -0.64ns 1 / 9
 
4 0h:00m:00s -0.58ns 6 / 13
 
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1484608753> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1484694497> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
 
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
 
@N:<a href="@N:MT611:@XP_HELP">MT611</a> : <!@TM:1484694497> | Automatically generated clock display_driver_wrapper|bttn_state_derived_clock is not used and is being removed
 
 
@S |Clock Optimization Summary
236,15 → 231,15
 
<a name=clockReport8></a>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>
 
1 non-gated/non-generated clock tree(s) driving 9 clock pin(s) of sequential element(s)
1 non-gated/non-generated clock tree(s) driving 13 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
8 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
============================= Non-Gated/Non-Generated Clocks ==============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
-------------------------------------------------------------------------------------------
<a href="@|S:button@|E:symbol_scan_cntr[0]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001 @XP_NAMES_BY_PROP">ClockId0001 </a> button port 9 symbol_scan_cntr[0]
===========================================================================================
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
<a href="@|S:clk@|E:bttn_state@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001 @XP_NAMES_BY_PROP">ClockId0001 </a> clk port 13 bttn_state
=======================================================================================
 
 
##### END OF CLOCK OPTIMIZATION REPORT ######]
254,34 → 249,34
 
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm
 
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 139MB peak: 141MB)
 
Writing EDIF Netlist and constraint files
@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1484608753> | Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi
@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1484694497> | Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi
L-2016.03L-1
@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1484608753> | Synplicity Constraint File capacitance units using default value of 1pF
@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1484694497> | Synplicity Constraint File capacitance units using default value of 1pF
 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
 
 
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
 
<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1484608753> | Found inferred clock DisplayDriverWrapper|button with period 2.25ns. Please declare a user-defined clock on object "p:button"</font>
<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1484694497> | Found inferred clock display_driver_wrapper|clk with period 2.30ns. Please declare a user-defined clock on object "p:clk"</font>
 
 
<a name=timingReport9></a>##### START OF TIMING REPORT #####[</a>
# Timing Report written on Tue Jan 17 01:19:13 2017
# Timing Report written on Wed Jan 18 01:08:17 2017
#
 
 
Top view: DisplayDriverWrapper
Requested Frequency: 443.5 MHz
Top view: display_driver_wrapper
Requested Frequency: 433.9 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1484608753> | Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1484694497> | Timing report estimates place and route data. Please look at the place and route timing report for final timing.
 
@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1484608753> | Clock constraints cover only FF-to-FF paths associated with the clock.
@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1484694497> | Clock constraints cover only FF-to-FF paths associated with the clock.
 
 
 
289,13 → 284,13
*******************
 
 
Worst slack in design: -0.398
Worst slack in design: -0.407
 
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
-------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button 443.5 MHz 377.0 MHz 2.255 2.652 -0.398 inferred Autoconstr_clkgroup_0
=====================================================================================================================================
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
------------------------------------------------------------------------------------------------------------------------------------
display_driver_wrapper|clk 433.9 MHz 368.8 MHz 2.305 2.712 -0.407 inferred Autoconstr_clkgroup_0
====================================================================================================================================
 
 
 
304,12 → 299,12
<a name=clockRelationships11></a>Clock Relationships</a>
*******************
 
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-------------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-------------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button DisplayDriverWrapper|button | 2.255 -0.398 | No paths - | No paths - | No paths -
=================================================================================================================================================
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-----------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-----------------------------------------------------------------------------------------------------------------------------------------------
display_driver_wrapper|clk display_driver_wrapper|clk | 2.305 -0.407 | No paths - | No paths - | No paths -
===============================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
323,7 → 318,7
 
 
====================================
<a name=clockReport13></a>Detailed Report for Clock: DisplayDriverWrapper|button</a>
<a name=clockReport13></a>Detailed Report for Clock: display_driver_wrapper|clk</a>
====================================
 
 
331,105 → 326,111
<a name=startingSlack14></a>Starting Points with Worst Slack</a>
********************************
 
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[1] 0.933 -0.398
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[2] 0.933 -0.398
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[3] 0.933 -0.339
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[4] 0.933 -0.339
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[5] 0.933 -0.280
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[6] 0.933 -0.280
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr_fast[0] 0.753 -0.277
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[7] 0.798 0.570
================================================================================================================================
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[0] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[0] 0.933 -0.407
symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[1] 0.933 -0.348
symbol_scan_cntr[2] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[2] 0.933 -0.348
symbol_scan_cntr[3] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[3] 0.933 -0.289
symbol_scan_cntr[4] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[4] 0.933 -0.289
symbol_scan_cntr[5] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[5] 0.933 -0.230
symbol_scan_cntr[6] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[6] 0.933 -0.230
bttn_state_fifo[3] display_driver_wrapper|clk FD1S3JX Q bttn_state_fifo[3] 0.798 0.123
bttn_state display_driver_wrapper|clk FD1S3AX Q bttn_state_i 0.753 0.168
bttn_state_fifo[1] display_driver_wrapper|clk FD1S3JX Q bttn_state_fifo[1] 0.838 0.606
=====================================================================================================================
 
 
<a name=endingSlack15></a>Ending Points with Worst Slack</a>
******************************
 
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[7] 2.044 -0.398
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[5] 2.044 -0.339
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[6] 2.044 -0.339
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[3] 2.044 -0.280
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[4] 2.044 -0.280
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[1] 2.044 -0.100
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[2] 2.044 -0.100
symbol_scan_cntr[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
==============================================================================================================================
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[7] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[7] 2.094 -0.407
symbol_scan_cntr[5] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[5] 2.094 -0.348
symbol_scan_cntr[6] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[6] 2.094 -0.348
symbol_scan_cntr[3] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[3] 2.094 -0.289
symbol_scan_cntr[4] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[4] 2.094 -0.289
symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[1] 2.094 -0.230
symbol_scan_cntr[2] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[2] 2.094 -0.230
symbol_scan_cntr[0] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
symbol_scan_cntr[2] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
==================================================================================================================================
 
 
 
<a name=worstPaths16></a>Worst Path Information</a>
<a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.srr:srsfC:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.srs:fp:23288:24683:@XP_NAMES_GATE">View Worst Path in Analyst</a>
<a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.srr:srsfC:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.srs:fp:23312:24986:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************
 
 
Path information for path number 1:
Requested Period: 2.255
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
= Required time: 2.094
 
- Propagation time: 2.442
- Propagation time: 2.501
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.398
= Slack (critical) : -0.407
 
Number of logic level(s): 4
Starting point: symbol_scan_cntr[1] / Q
Number of logic level(s): 5
Starting point: symbol_scan_cntr[0] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[0] Net - - - - 15
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[0] Net - - - - 1
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.894 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.894 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.501 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.501 -
===========================================================================================
 
 
Path information for path number 2:
Requested Period: 2.255
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
= Required time: 2.094
 
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.398
= Slack (non-critical) : -0.348
 
Number of logic level(s): 4
Starting point: symbol_scan_cntr[2] / Q
Starting point: symbol_scan_cntr[1] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[2] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[2] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr[1] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
441,109 → 442,118
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 3:
Requested Period: 2.255
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
= Required time: 2.094
 
- Propagation time: 2.382
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -0.339
= Slack (non-critical) : -0.348
 
Number of logic level(s): 3
Starting point: symbol_scan_cntr[3] / Q
Number of logic level(s): 4
Starting point: symbol_scan_cntr[2] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[3] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[3] Net - - - - 15
symbol_scan_cntr_cry_0[3] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr[2] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[2] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 4:
Requested Period: 2.255
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
= Required time: 2.094
 
- Propagation time: 2.382
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -0.339
= Slack (non-critical) : -0.348
 
Number of logic level(s): 3
Starting point: symbol_scan_cntr[4] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
Number of logic level(s): 4
Starting point: symbol_scan_cntr[0] / Q
Ending point: symbol_scan_cntr[5] / D
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[4] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[4] Net - - - - 15
symbol_scan_cntr_cry_0[3] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[0] Net - - - - 15
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[0] Net - - - - 1
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[5] Net - - - - 1
symbol_scan_cntr[5] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 5:
Requested Period: 2.255
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
= Required time: 2.094
 
- Propagation time: 2.382
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -0.339
= Slack (non-critical) : -0.348
 
Number of logic level(s): 3
Starting point: symbol_scan_cntr[1] / Q
Ending point: symbol_scan_cntr[5] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
Number of logic level(s): 4
Starting point: symbol_scan_cntr[0] / Q
Ending point: symbol_scan_cntr[6] / D
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[0] Net - - - - 15
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[0] Net - - - - 1
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[5] Net - - - - 1
symbol_scan_cntr[5] FD1S3DX D In 0.000 2.382 -
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_cry_0[5] CCU2C S1 Out 0.607 2.442 -
symbol_scan_cntr_s[6] Net - - - - 1
symbol_scan_cntr[6] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
562,7 → 572,7
<a name=resourceUsage17></a>Resource Usage Report</a>
Part: lfe5um5g_45f-8
 
Register bits: 9 of 43848 (0%)
Register bits: 13 of 43848 (0%)
PIC Latch: 0
I/O cells: 18
 
569,11 → 579,15
 
Details:
CCU2C: 5
FD1S3DX: 9
FD1P3DX: 8
FD1S3AX: 1
FD1S3JX: 3
GSR: 1
IB: 2
INV: 1
OB: 16
IB: 3
IFS1P3JX: 1
INV: 2
OB: 15
ORCALUT4: 4
PUR: 1
ROM128X1A: 14
VHI: 1
583,7 → 597,7
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 17 01:19:13 2017
# Wed Jan 18 01:08:17 2017
 
###########################################################]
 
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/syntmp/DisplayDriverwDecoder_impl1_toc.htm
27,14 → 27,14
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\DisplayDriverwDecoder_impl1_srr.htm#interfaceInfo12" target="srrFrame" title="">Interface Information</a> </li>
<li><a href="file:///#" target="srrFrame" title="">Detailed Report for Clocks</a>
<ul >
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\DisplayDriverwDecoder_impl1_srr.htm#clockReport13" target="srrFrame" title="">Clock: DisplayDriverWrapper|button</a>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\DisplayDriverwDecoder_impl1_srr.htm#clockReport13" target="srrFrame" title="">Clock: display_driver_wrapper|clk</a>
<ul >
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\DisplayDriverwDecoder_impl1_srr.htm#startingSlack14" target="srrFrame" title="">Starting Points with Worst Slack</a> </li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\DisplayDriverwDecoder_impl1_srr.htm#endingSlack15" target="srrFrame" title="">Ending Points with Worst Slack</a> </li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\DisplayDriverwDecoder_impl1_srr.htm#worstPaths16" target="srrFrame" title="">Worst Path Information</a> </li></ul></li></ul></li></ul></li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\DisplayDriverwDecoder_impl1_srr.htm#resourceUsage17" target="srrFrame" title="">Resource Utilization</a> </li></ul></li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_cck.rpt" target="srrFrame" title="">Constraint Checker Report (01:19 17-Jan)</a> </li></ul></li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\stdout.log" target="srrFrame" title="">Session Log (01:19 17-Jan)</a>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_cck.rpt" target="srrFrame" title="">Constraint Checker Report (01:08 18-Jan)</a> </li></ul></li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\stdout.log" target="srrFrame" title="">Session Log (01:08 18-Jan)</a>
<ul ></ul></li> </ul>
</li>
</ul>
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/syntmp/hdlorder.tcl
1,14 → 27,14
project -fileorder "C:/lscc/diamond/3.8_x64/cae_library/synthesis/vhdl/ecp5um.vhd" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ASCIIDecoder.vhd" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd"
project -fileorder "C:/lscc/diamond/3.8_x64/cae_library/synthesis/vhdl/ecp5um.vhd" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ascii_decoder.vhd" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/display_driver_w_decoder.vhd" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/display_driver_wrapper.vhd"
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/syntmp/impl1_srr.htm
1,40 → 1,43
<html><body><samp><pre>
<!@TC:1484609376>
<!@TC:1484689279>
#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul 4 2016
#install: C:\lscc\diamond\3.8_x64\synpbase
#OS: Windows 8 6.2
#Hostname: DESKTOP-1AUKF7V
 
# Tue Jan 17 01:29:36 2017
# Tue Jan 17 23:41:19 2017
 
#Implementation: impl1
 
<a name=compilerReport9></a>Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
@N: : <!@TM:1484609376> | Running in 64-bit mode
@N: : <!@TM:1484689280> | Running in 64-bit mode
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
 
<a name=compilerReport10></a>Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
@N: : <!@TM:1484609376> | Running in 64-bit mode
@N: : <!@TM:1484689280> | Running in 64-bit mode
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
 
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1484609376> | Setting time resolution to ns
@N: : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N::@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1484609376> | Top entity is set to DisplayDriverWrapper.
Options changed - recompiling
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1484689280> | Setting time resolution to ns
@N: : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd:15:7:15:27:@N::@XP_MSG">display_driver_wrapper.vhd(15)</a><!@TM:1484689280> | Top entity is set to DisplayDriverWrapper.
File C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\ecp5um.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd changed - recompiling
VHDL syntax check successful!
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N:CD630:@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1484609376> | Synthesizing work.displaydriverwrapper.arch.
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd:16:7:16:32:@N:CD630:@XP_MSG">DisplayDriverwDecoder_Top.vhd(16)</a><!@TM:1484609376> | Synthesizing work.displaydriverwdecoder_top.arch.
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd:53:11:53:20:@W:CD638:@XP_MSG">DisplayDriverwDecoder_Top.vhd(53)</a><!@TM:1484609376> | Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.</font>
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd:15:7:15:19:@N:CD630:@XP_MSG">ASCIIDecoder.vhd(15)</a><!@TM:1484609376> | Synthesizing work.asciidecoder.arch.
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd:12:7:12:26:@N:CD630:@XP_MSG">DistRomAsciiDecoder.vhd(12)</a><!@TM:1484609376> | Synthesizing work.distromasciidecoder.structure.
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd:801:10:801:19:@N:CD630:@XP_MSG">ecp5um.vhd(801)</a><!@TM:1484609376> | Synthesizing work.rom128x1a.syn_black_box.
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd:15:7:15:27:@N:CD630:@XP_MSG">display_driver_wrapper.vhd(15)</a><!@TM:1484689280> | Synthesizing work.displaydriverwrapper.arch.
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd:17:7:17:31:@N:CD630:@XP_MSG">display_driver_w_decoder.vhd(17)</a><!@TM:1484689280> | Synthesizing work.display_driver_w_decoder.display_driver_w_decoder_arch.
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd:47:11:47:20:@W:CD638:@XP_MSG">display_driver_w_decoder.vhd(47)</a><!@TM:1484689280> | Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.</font>
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd:15:7:15:19:@N:CD630:@XP_MSG">ascii_decoder.vhd(15)</a><!@TM:1484689280> | Synthesizing work.asciidecoder.arch.
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd:12:7:12:26:@N:CD630:@XP_MSG">DistRomAsciiDecoder.vhd(12)</a><!@TM:1484689280> | Synthesizing work.distromasciidecoder.structure.
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd:801:10:801:19:@N:CD630:@XP_MSG">ecp5um.vhd(801)</a><!@TM:1484689280> | Synthesizing work.rom128x1a.syn_black_box.
Post processing for work.rom128x1a.syn_black_box
Post processing for work.distromasciidecoder.structure
Post processing for work.asciidecoder.arch
Post processing for work.displaydriverwdecoder_top.arch
Post processing for work.display_driver_w_decoder.display_driver_w_decoder_arch
Post processing for work.displaydriverwrapper.arch
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd:17:8:17:11:@N:CL159:@XP_MSG">ASCIIDecoder.vhd(17)</a><!@TM:1484609376> | Input clk is unused.
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd:18:8:18:13:@N:CL159:@XP_MSG">ASCIIDecoder.vhd(18)</a><!@TM:1484609376> | Input reset is unused.
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd:29:8:29:13:@N:CL159:@XP_MSG">DisplayDriverwDecoder_Top.vhd(29)</a><!@TM:1484609376> | Input wr_en is unused.
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd:17:8:17:11:@N:CL159:@XP_MSG">ascii_decoder.vhd(17)</a><!@TM:1484689280> | Input clk is unused.
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd:18:8:18:13:@N:CL159:@XP_MSG">ascii_decoder.vhd(18)</a><!@TM:1484689280> | Input reset is unused.
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd:23:8:23:13:@N:CL159:@XP_MSG">display_driver_w_decoder.vhd(23)</a><!@TM:1484689280> | Input wr_en is unused.
 
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
 
41,14 → 44,14
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:29:36 2017
# Tue Jan 17 23:41:20 2017
 
###########################################################]
<a name=compilerReport11></a>Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
@N: : <!@TM:1484609376> | Running in 64-bit mode
@N: : <!@TM:1484689280> | Running in 64-bit mode
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N:NF107:@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1484609376> | Selected library: work cell: DisplayDriverWrapper view arch as top level
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N:NF107:@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1484609376> | Selected library: work cell: DisplayDriverWrapper view arch as top level
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd:15:7:15:27:@N:NF107:@XP_MSG">display_driver_wrapper.vhd(15)</a><!@TM:1484689280> | Selected library: work cell: DisplayDriverWrapper view arch as top level
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd:15:7:15:27:@N:NF107:@XP_MSG">display_driver_wrapper.vhd(15)</a><!@TM:1484689280> | Selected library: work cell: DisplayDriverWrapper view arch as top level
 
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
55,7 → 58,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:29:36 2017
# Tue Jan 17 23:41:20 2017
 
###########################################################]
@END
65,14 → 68,14
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:29:36 2017
# Tue Jan 17 23:41:20 2017
 
###########################################################]
<a name=compilerReport12></a>Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
@N: : <!@TM:1484609377> | Running in 64-bit mode
@N: : <!@TM:1484689281> | Running in 64-bit mode
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_comp.srs changed - recompiling
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N:NF107:@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1484609377> | Selected library: work cell: DisplayDriverWrapper view arch as top level
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N:NF107:@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1484609377> | Selected library: work cell: DisplayDriverWrapper view arch as top level
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd:15:7:15:27:@N:NF107:@XP_MSG">display_driver_wrapper.vhd(15)</a><!@TM:1484689281> | Selected library: work cell: DisplayDriverWrapper view arch as top level
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd:15:7:15:27:@N:NF107:@XP_MSG">display_driver_wrapper.vhd(15)</a><!@TM:1484689281> | Selected library: work cell: DisplayDriverWrapper view arch as top level
 
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
79,7 → 82,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:29:37 2017
# Tue Jan 17 23:41:21 2017
 
###########################################################]
Pre-mapping Report
90,11 → 93,11
 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
 
@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1484609378> | No constraint file specified.
@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1484689282> | No constraint file specified.
Linked File: <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_scck.rpt:@XP_FILE">impl1_scck.rpt</a>
Printing clock summary report in "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_scck.rpt" file
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1484609378> | Running in 64-bit mode.
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1484609378> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1484689282> | Running in 64-bit mode.
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1484689282> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
 
126,7 → 129,7
DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 5
=========================================================================================================================================================
 
<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd:57:4:57:6:@W:MT529:@XP_MSG">displaydriverwrapper.vhd(57)</a><!@TM:1484609378> | Found inferred clock DisplayDriverWrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd:57:4:57:6:@W:MT529:@XP_MSG">display_driver_wrapper.vhd(57)</a><!@TM:1484689282> | Found inferred clock DisplayDriverWrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
 
Finished Pre Mapping Phase.
 
142,7 → 145,7
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 142MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 17 01:29:38 2017
# Tue Jan 17 23:41:22 2017
 
###########################################################]
Map & Optimize Report
153,8 → 156,8
 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
 
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1484609380> | Running in 64-bit mode.
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1484609380> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1484689284> | Running in 64-bit mode.
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1484689284> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
 
175,11 → 178,11
Available hyper_sources - for debug and ip models
None Found
 
@N:<a href="@N:MT206:@XP_HELP">MT206</a> : <!@TM:1484609380> | Auto Constrain mode is enabled
@N:<a href="@N:MT206:@XP_HELP">MT206</a> : <!@TM:1484689284> | Auto Constrain mode is enabled
 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N: : <a href="c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd:77:4:77:6:@N::@XP_MSG">displaydriverwrapper.vhd(77)</a><!@TM:1484609380> | Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
@N: : <a href="c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd:77:4:77:6:@N::@XP_MSG">display_driver_wrapper.vhd(77)</a><!@TM:1484689284> | Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
 
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
219,11 → 222,11
 
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1484609380> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1484689284> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
 
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
 
@N:<a href="@N:MT611:@XP_HELP">MT611</a> : <!@TM:1484609380> | Automatically generated clock DisplayDriverWrapper|bttn_state_derived_clock is not used and is being removed
@N:<a href="@N:MT611:@XP_HELP">MT611</a> : <!@TM:1484689284> | Automatically generated clock DisplayDriverWrapper|bttn_state_derived_clock is not used and is being removed
 
 
@S |Clock Optimization Summary
252,20 → 255,20
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
Writing EDIF Netlist and constraint files
@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1484609380> | Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.edi
@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1484689284> | Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.edi
L-2016.03L-1
@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1484609380> | Synplicity Constraint File capacitance units using default value of 1pF
@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1484689284> | Synplicity Constraint File capacitance units using default value of 1pF
 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
 
 
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
 
<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1484609380> | Found inferred clock DisplayDriverWrapper|clk with period 2.30ns. Please declare a user-defined clock on object "p:clk"</font>
<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1484689284> | Found inferred clock DisplayDriverWrapper|clk with period 2.30ns. Please declare a user-defined clock on object "p:clk"</font>
 
 
<a name=timingReport17></a>##### START OF TIMING REPORT #####[</a>
# Timing Report written on Tue Jan 17 01:29:40 2017
# Timing Report written on Tue Jan 17 23:41:24 2017
#
 
 
274,9 → 277,9
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1484609380> | Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1484689284> | Timing report estimates place and route data. Please look at the place and route timing report for final timing.
 
@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1484609380> | Clock constraints cover only FF-to-FF paths associated with the clock.
@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1484689284> | Clock constraints cover only FF-to-FF paths associated with the clock.
 
 
 
365,7 → 368,7
 
 
<a name=worstPaths24></a>Worst Path Information</a>
<a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.srr:srsfC:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.srs:fp:23218:24892:@XP_NAMES_GATE">View Worst Path in Analyst</a>
<a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.srr:srsfC:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.srs:fp:23703:25377:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************
 
 
597,7 → 600,7
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 17 01:29:40 2017
# Tue Jan 17 23:41:24 2017
 
###########################################################]
 
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/syntmp/impl1_toc.htm
33,8 → 33,8
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#endingSlack23" target="srrFrame" title="">Ending Points with Worst Slack</a> </li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#worstPaths24" target="srrFrame" title="">Worst Path Information</a> </li></ul></li></ul></li></ul></li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\syntmp\impl1_srr.htm#resourceUsage25" target="srrFrame" title="">Resource Utilization</a> </li></ul></li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_cck.rpt" target="srrFrame" title="">Constraint Checker Report (01:29 17-Jan)</a> </li></ul></li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\stdout.log" target="srrFrame" title="">Session Log (01:28 17-Jan)</a>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_cck.rpt" target="srrFrame" title="">Constraint Checker Report (23:41 17-Jan)</a> </li></ul></li>
<li><a href="file:///C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\stdout.log" target="srrFrame" title="">Session Log (23:37 17-Jan)</a>
<ul ></ul></li> </ul>
</li>
</ul>
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/syntmp/run_option.xml
6,13 → 6,13
 
-->
<project_attribute_list name="Project Settings">
<option name="project_name" display_name="Project Name">impl1_syn</option>
<option name="project_name" display_name="Project Name">proj_1</option>
<option name="impl_name" display_name="Implementation Name">impl1</option>
<option name="top_module" display_name="Top Module"></option>
<option name="top_module" display_name="Top Module">display_driver_wrapper</option>
<option name="pipe" display_name="Pipelining">1</option>
<option name="retiming" display_name="Retiming">0</option>
<option name="resource_sharing" display_name="Resource Sharing">1</option>
<option name="maxfan" display_name="Fanout Guide">100</option>
<option name="maxfan" display_name="Fanout Guide">1000</option>
<option name="disable_io_insertion" display_name="Disable I/O Insertion">0</option>
<option name="no_sequential_opt" display_name="Disable Sequential Optimizations">0</option>
<option name="fix_gated_and_generated_clocks" display_name="Clock Conversion">1</option>
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/syntmp/statusReport.html
9,11 → 9,11
<table style="border:none;" width="100%" ><tr> <td class="outline">
<table width="100%" border="0" cellspacing="0" cellpadding="0"> <thead class="tablehead"><tr><th colspan="4">Project Settings</th><tr>
<tr> <td class="optionTitle" align="left"> Project Name</td> <td> impl1_syn</td> <td class="optionTitle" align="left"> Implementation Name</td> <td> impl1</td> </tr>
<tr> <td class="optionTitle" align="left"> Project Name</td> <td> proj_1</td> <td class="optionTitle" align="left"> Implementation Name</td> <td> impl1</td> </tr>
</thead>
<tbody> <tr> <td class="optionTitle" align="left"> Top Module</td> <td> [auto]</td> <td class="optionTitle" align="left"> Pipelining</td> <td> 1</td> </tr>
<tbody> <tr> <td class="optionTitle" align="left"> Top Module</td> <td> display_driver_wrapper</td> <td class="optionTitle" align="left"> Pipelining</td> <td> 1</td> </tr>
<tr> <td class="optionTitle" align="left"> Retiming</td> <td> 0</td> <td class="optionTitle" align="left"> Resource Sharing</td> <td> 1</td> </tr>
<tr> <td class="optionTitle" align="left"> Fanout Guide</td> <td> 100</td> <td class="optionTitle" align="left"> Disable I/O Insertion</td> <td> 0</td> </tr>
<tr> <td class="optionTitle" align="left"> Fanout Guide</td> <td> 1000</td> <td class="optionTitle" align="left"> Disable I/O Insertion</td> <td> 0</td> </tr>
<tr> <td class="optionTitle" align="left"> Disable Sequential Optimizations</td> <td> 0</td> <td class="optionTitle" align="left"> Clock Conversion</td> <td> 1</td> </tr>
</tbody>
33,13 → 33,13
</tr>
<tr>
<td class="optionTitle"> (compiler)</td><td>Complete</td>
<td>15</td>
<td>13</td>
<td>1</td>
<td>0</td>
<td>-</td>
<td>0m:00s</td>
<td>-</td>
<td><font size="-1">17-Jan-17</font><br/><font size="-2">01:29:36</font></td>
<td><font size="-1">18-Jan-17</font><br/><font size="-2">01:08:13</font></td>
</tr>
 
<tr>
49,8 → 49,8
<td>0</td>
<td>0m:00s</td>
<td>0m:00s</td>
<td>142MB</td>
<td><font size="-1">17-Jan-17</font><br/><font size="-2">01:29:38</font></td>
<td>141MB</td>
<td><font size="-1">18-Jan-17</font><br/><font size="-2">01:08:15</font></td>
</tr>
 
<tr>
61,12 → 61,12
<td>0m:01s</td>
<td>0m:01s</td>
<td>145MB</td>
<td><font size="-1">17-Jan-17</font><br/><font size="-2">01:29:40</font></td>
<td><font size="-1">18-Jan-17</font><br/><font size="-2">01:08:17</font></td>
</tr>
 
<tr>
<td class="optionTitle">Multi-srs Generator</td>
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td></td><td class="empty"></td><td class="empty"></td><td><font size="-1">17-Jan-17</font><br/><font size="-2">01:29:37</font></td> </tbody>
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td></td><td class="empty"></td><td class="empty"></td><td><font size="-1">18-Jan-17</font><br/><font size="-2">01:08:14</font></td> </tbody>
</table>
<br>
<table width="100%" border="1" cellspacing= "0" cellpadding= "0">
75,7 → 75,7
</tfoot>
<tbody> <tr>
<td title ="Total Register bits used" class="optionTitle" align="left">Register bits</td> <td>13</td>
<td title ="Total I/O cells used" class="optionTitle" align="left">I/O cells</td> <td>19</td>
<td title ="Total I/O cells used" class="optionTitle" align="left">I/O cells</td> <td>18</td>
</tr>
<tr>
<td title ="Total Block RAMs used" class="optionTitle" align="left">Block RAMs
95,7 → 95,7
</tfoot>
<tbody>
<tr><th class="optionTitle" align= "left ">Clock Name</th><th class="optionTitle" align= "left ">Req Freq</th><th class="optionTitle" align= "left ">Est Freq</th><th class="optionTitle" align= "left ">Slack</th></tr>
<tr> <td align="left">DisplayDriverWrapper|clk</td><td align="left">433.9 MHz</td><td align="left">368.8 MHz</td><td align="left">-0.407</td></tr>
<tr> <td align="left">display_driver_wrapper|clk</td><td align="left">433.9 MHz</td><td align="left">368.8 MHz</td><td align="left">-0.407</td></tr>
</tbody>
</table>
<br>
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synwork/.complist File deleted \ No newline at end of file
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synwork/DisplayDriverwDecoder_impl1_m_srm/1.srm Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synwork/DisplayDriverwDecoder_impl1_mult_srs/1.srs Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synwork/DisplayDriverwDecoder_impl1_mult_srs/skeleton.srs Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synwork/impl1_m_srm/1.srm Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synwork/impl1_mult_srs/1.srs Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synwork/impl1_mult_srs/skeleton.srs Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synwork/.cckTransfer Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synwork/DisplayDriverwDecoder_impl1_comp.fdep
1,4 → 1,4
#OPTIONS:"|-layerid|0|-orig_srs|C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Lattice_FPGA_Build\\impl1\\synwork\\DisplayDriverwDecoder_impl1_comp.srs|-top|DisplayDriverWrapper|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
#OPTIONS:"|-layerid|0|-orig_srs|C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Lattice_FPGA_Build\\impl1\\synwork\\DisplayDriverwDecoder_impl1_comp.srs|-top|display_driver_wrapper|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\bin64\\c_vhdl.exe":1467795490
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\location.map":1467984194
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\std.vhd":1467795088
10,16 → 10,16
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\unsigned.vhd":1467795088
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\hyperents.vhd":1467795088
#CUR:"C:\\lscc\\diamond\\3.8_x64\\cae_library\\synthesis\\vhdl\\ecp5um.vhd":1424732222
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\Decoding_Table\\ROM_ASCII_Decoder\\DistRomAsciiDecoder\\DistRomAsciiDecoder\\DistRomAsciiDecoder.vhd":1484342051
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\Decoding_Table\\ROM_ASCII_Decoder\\decoder_table_dist_rom_impl\\decoder_table_dist_rom\\decoder_table_dist_rom.vhd":1484693309
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\lucent\\ecp5um.vhd":1467795226
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\ASCIIDecoder.vhd":1484607277
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverwDecoder_Top.vhd":1484602099
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverWrapper.vhd":1484608465
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\ascii_decoder.vhd":1484694181
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\display_driver_w_decoder.vhd":1484692618
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\display_driver_wrapper.vhd":1484691063
0 "C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd" vhdl
1 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd" vhdl
2 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd" vhdl
3 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd" vhdl
4 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd" vhdl
1 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\decoder_table_dist_rom_impl\decoder_table_dist_rom\decoder_table_dist_rom.vhd" vhdl
2 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd" vhdl
3 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd" vhdl
4 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd" vhdl
#Dependency Lists(Uses List)
0 -1
1 0
33,11 → 33,11
3 4
4 -1
#Design Unit to File Association
module work displaydriverwrapper 4
arch work displaydriverwrapper arch 4
module work displaydriverwdecoder_top 3
arch work displaydriverwdecoder_top arch 3
module work asciidecoder 2
arch work asciidecoder arch 2
module work distromasciidecoder 1
arch work distromasciidecoder structure 1
module work display_driver_wrapper 4
arch work display_driver_wrapper arch 4
module work display_driver_w_decoder 3
arch work display_driver_w_decoder display_driver_w_decoder_arch 3
module work ascii_decoder 2
arch work ascii_decoder arch 2
module work decoder_table_dist_rom 1
arch work decoder_table_dist_rom structure 1
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synwork/DisplayDriverwDecoder_impl1_comp.srs Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synwork/DisplayDriverwDecoder_impl1_hdl_.fdeporig
1,5 → 1,5
#defaultlanguage:vhdl
#OPTIONS:"|-top|DisplayDriverWrapper|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-fileorder|C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Lattice_FPGA_Build\\impl1\\syntmp\\hdlorder.tcl"
#OPTIONS:"|-top|display_driver_wrapper|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-fileorder|C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Lattice_FPGA_Build\\impl1\\syntmp\\hdlorder.tcl"
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\bin64\\c_vhdl.exe":1467795490
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\location.map":1467984194
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\std.vhd":1467795088
11,36 → 11,36
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\unsigned.vhd":1467795088
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\hyperents.vhd":1467795088
#CUR:"C:\\lscc\\diamond\\3.8_x64\\cae_library\\synthesis\\vhdl\\ecp5um.vhd":1424732222
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverwDecoder_Top.vhd":1484602099
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverWrapper.vhd":1484609246
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\ASCIIDecoder.vhd":1484607277
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\Decoding_Table\\ROM_ASCII_Decoder\\DistRomAsciiDecoder\\DistRomAsciiDecoder\\DistRomAsciiDecoder.vhd":1484342051
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\ascii_decoder.vhd":1484694181
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\display_driver_w_decoder.vhd":1484692618
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\display_driver_wrapper.vhd":1484691063
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\Decoding_Table\\ROM_ASCII_Decoder\\decoder_table_dist_rom_impl\\decoder_table_dist_rom\\decoder_table_dist_rom.vhd":1484693309
0 "C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd" vhdl
1 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd" vhdl
2 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd" vhdl
3 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd" vhdl
4 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd" vhdl
1 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd" vhdl
2 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd" vhdl
3 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd" vhdl
4 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\decoder_table_dist_rom_impl\decoder_table_dist_rom\decoder_table_dist_rom.vhd" vhdl
 
# Dependency Lists (Uses list)
0 -1
1 3
1 4
2 1
3 4
3 2
4 0
 
# Dependency Lists (Users Of)
0 4
1 2
2 -1
3 1
4 3
2 3
3 -1
4 1
 
# Design Unit to File Association
arch work displaydriverwdecoder_top arch 1
module work displaydriverwdecoder_top 1
arch work displaydriverwrapper arch 2
module work displaydriverwrapper 2
arch work asciidecoder arch 3
module work asciidecoder 3
arch work distromasciidecoder structure 4
module work distromasciidecoder 4
arch work ascii_decoder arch 1
module work ascii_decoder 1
arch work display_driver_w_decoder display_driver_w_decoder_arch 2
module work display_driver_w_decoder 2
arch work display_driver_wrapper arch 3
module work display_driver_wrapper 3
arch work decoder_table_dist_rom structure 4
module work decoder_table_dist_rom 4
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synwork/DisplayDriverwDecoder_impl1_m.srm Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synwork/DisplayDriverwDecoder_impl1_mult.srs Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synwork/DisplayDriverwDecoder_impl1_prem.srd Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synwork/impl1_comp.fdep
12,32 → 12,32
#CUR:"C:\\lscc\\diamond\\3.8_x64\\cae_library\\synthesis\\vhdl\\ecp5um.vhd":1424732222
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\Decoding_Table\\ROM_ASCII_Decoder\\DistRomAsciiDecoder\\DistRomAsciiDecoder\\DistRomAsciiDecoder.vhd":1484342051
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\lucent\\ecp5um.vhd":1467795226
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\ASCIIDecoder.vhd":1484607277
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverwDecoder_Top.vhd":1484602099
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverWrapper.vhd":1484609359
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\ascii_decoder.vhd":1484685872
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\display_driver_w_decoder.vhd":1484687781
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\display_driver_wrapper.vhd":1484689273
0 "C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd" vhdl
1 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd" vhdl
2 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd" vhdl
3 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd" vhdl
4 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd" vhdl
1 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd" vhdl
2 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd" vhdl
3 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd" vhdl
4 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd" vhdl
#Dependency Lists(Uses List)
0 -1
1 3
1 0
2 1
3 4
4 0
3 2
4 3
#Dependency Lists(Users Of)
0 4
0 1
1 2
2 -1
3 1
4 3
2 3
3 4
4 -1
#Design Unit to File Association
module work distromasciidecoder 4
arch work distromasciidecoder structure 4
module work asciidecoder 3
arch work asciidecoder arch 3
module work displaydriverwrapper 2
arch work displaydriverwrapper arch 2
module work displaydriverwdecoder_top 1
arch work displaydriverwdecoder_top arch 1
module work displaydriverwrapper 4
arch work displaydriverwrapper arch 4
module work display_driver_w_decoder 3
arch work display_driver_w_decoder display_driver_w_decoder_arch 3
module work asciidecoder 2
arch work asciidecoder arch 2
module work distromasciidecoder 1
arch work distromasciidecoder structure 1
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synwork/impl1_comp.srs Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synwork/impl1_m.srm Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synwork/impl1_mult.srs Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synwork/impl1_prem.srd Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synwork/layer0.fdep
1,5 → 1,5
#defaultlanguage:vhdl
#OPTIONS:"|-layerid|0|-orig_srs|C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Lattice_FPGA_Build\\impl1\\synwork\\impl1_comp.srs|-autotop|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
#OPTIONS:"|-layerid|0|-orig_srs|C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Lattice_FPGA_Build\\impl1\\synwork\\DisplayDriverwDecoder_impl1_comp.srs|-top|display_driver_wrapper|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\bin64\\c_vhdl.exe":1467795490
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\location.map":1467984194
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\std.vhd":1467795088
11,40 → 11,40
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\unsigned.vhd":1467795088
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\hyperents.vhd":1467795088
#CUR:"C:\\lscc\\diamond\\3.8_x64\\cae_library\\synthesis\\vhdl\\ecp5um.vhd":1424732222
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\Decoding_Table\\ROM_ASCII_Decoder\\DistRomAsciiDecoder\\DistRomAsciiDecoder\\DistRomAsciiDecoder.vhd":1484342051
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\Decoding_Table\\ROM_ASCII_Decoder\\decoder_table_dist_rom_impl\\decoder_table_dist_rom\\decoder_table_dist_rom.vhd":1484693309
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\lucent\\ecp5um.vhd":1467795226
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\ASCIIDecoder.vhd":1484607277
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverwDecoder_Top.vhd":1484602099
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverWrapper.vhd":1484609359
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\ascii_decoder.vhd":1484694181
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\display_driver_w_decoder.vhd":1484692618
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\display_driver_wrapper.vhd":1484691063
0 "C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd" vhdl
1 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd" vhdl
2 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd" vhdl
3 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd" vhdl
4 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd" vhdl
1 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\decoder_table_dist_rom_impl\decoder_table_dist_rom\decoder_table_dist_rom.vhd" vhdl
2 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd" vhdl
3 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd" vhdl
4 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd" vhdl
 
# Dependency Lists (Uses list)
0 -1
1 3
1 0
2 1
3 4
4 0
3 2
4 3
 
# Dependency Lists (Users Of)
0 4
0 1
1 2
2 -1
3 1
4 3
2 3
3 4
4 -1
 
# Design Unit to File Association
arch work displaydriverwdecoder_top arch 1
module work displaydriverwdecoder_top 1
arch work displaydriverwrapper arch 2
module work displaydriverwrapper 2
arch work asciidecoder arch 3
module work asciidecoder 3
arch work distromasciidecoder structure 4
module work distromasciidecoder 4
arch work decoder_table_dist_rom structure 1
module work decoder_table_dist_rom 1
arch work ascii_decoder arch 2
module work ascii_decoder 2
arch work display_driver_w_decoder display_driver_w_decoder_arch 3
module work display_driver_w_decoder 3
arch work display_driver_wrapper arch 4
module work display_driver_wrapper 4
 
 
# Configuration files used
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synwork/layer0.fdeporig
1,5 → 1,5
#defaultlanguage:vhdl
#OPTIONS:"|-layerid|0|-orig_srs|C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Lattice_FPGA_Build\\impl1\\synwork\\impl1_comp.srs|-autotop|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
#OPTIONS:"|-layerid|0|-orig_srs|C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Lattice_FPGA_Build\\impl1\\synwork\\DisplayDriverwDecoder_impl1_comp.srs|-top|display_driver_wrapper|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\bin64\\c_vhdl.exe":1467795490
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\location.map":1467984194
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\std.vhd":1467795088
11,36 → 11,36
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\unsigned.vhd":1467795088
#CUR:"C:\\lscc\\diamond\\3.8_x64\\synpbase\\lib\\vhd\\hyperents.vhd":1467795088
#CUR:"C:\\lscc\\diamond\\3.8_x64\\cae_library\\synthesis\\vhdl\\ecp5um.vhd":1424732222
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverwDecoder_Top.vhd":1484602099
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\DisplayDriverWrapper.vhd":1484609359
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\ASCIIDecoder.vhd":1484607277
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\Decoding_Table\\ROM_ASCII_Decoder\\DistRomAsciiDecoder\\DistRomAsciiDecoder\\DistRomAsciiDecoder.vhd":1484342051
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\Decoding_Table\\ROM_ASCII_Decoder\\decoder_table_dist_rom_impl\\decoder_table_dist_rom\\decoder_table_dist_rom.vhd":1484693309
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\ascii_decoder.vhd":1484694181
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\display_driver_w_decoder.vhd":1484692618
#CUR:"C:\\Projects\\single-14-segment-display-driver-w-decoder\\Project\\Sources\\display_driver_wrapper.vhd":1484691063
0 "C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd" vhdl
1 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd" vhdl
2 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd" vhdl
3 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd" vhdl
4 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd" vhdl
1 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\decoder_table_dist_rom_impl\decoder_table_dist_rom\decoder_table_dist_rom.vhd" vhdl
2 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd" vhdl
3 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd" vhdl
4 "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd" vhdl
 
# Dependency Lists (Uses list)
0 -1
1 3
1 0
2 1
3 4
4 0
3 2
4 3
 
# Dependency Lists (Users Of)
0 4
0 1
1 2
2 -1
3 1
4 3
2 3
3 4
4 -1
 
# Design Unit to File Association
arch work displaydriverwdecoder_top arch 1
module work displaydriverwdecoder_top 1
arch work displaydriverwrapper arch 2
module work displaydriverwrapper 2
arch work asciidecoder arch 3
module work asciidecoder 3
arch work distromasciidecoder structure 4
module work distromasciidecoder 4
arch work decoder_table_dist_rom structure 1
module work decoder_table_dist_rom 1
arch work ascii_decoder arch 2
module work ascii_decoder 2
arch work display_driver_w_decoder display_driver_w_decoder_arch 3
module work display_driver_w_decoder 3
arch work display_driver_wrapper arch 4
module work display_driver_wrapper 4
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synwork/layer0.srs Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synwork/layer0.tlg
1,14 → 1,14
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":53:11:53:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd":12:7:12:25|Synthesizing work.distromasciidecoder.structure.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:28|Synthesizing work.display_driver_wrapper.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":17:7:17:30|Synthesizing work.display_driver_w_decoder.display_driver_w_decoder_arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":42:11:42:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":15:7:15:19|Synthesizing work.ascii_decoder.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\decoder_table_dist_rom_impl\decoder_table_dist_rom\decoder_table_dist_rom.vhd":12:7:12:28|Synthesizing work.decoder_table_dist_rom.structure.
@N: CD630 :"C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd":801:10:801:18|Synthesizing work.rom128x1a.syn_black_box.
Post processing for work.rom128x1a.syn_black_box
Post processing for work.distromasciidecoder.structure
Post processing for work.asciidecoder.arch
Post processing for work.displaydriverwdecoder_top.arch
Post processing for work.displaydriverwrapper.arch
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":29:8:29:12|Input wr_en is unused.
Post processing for work.decoder_table_dist_rom.structure
Post processing for work.ascii_decoder.arch
Post processing for work.display_driver_w_decoder.display_driver_w_decoder_arch
Post processing for work.display_driver_wrapper.arch
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":23:8:23:12|Input wr_en is unused.
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/.build_status
6,38 → 6,40
<Task name="IBIS_AMI" build_result="0" update_result="3" update_time="0"/>
<Task name="TimingSimFileVlg" build_result="0" update_result="3" update_time="0"/>
<Task name="TimingSimFileVHD" build_result="0" update_result="3" update_time="0"/>
<Task name="Bitgen" build_result="2" update_result="0" update_time="1484609837"/>
<Task name="Bitgen" build_result="2" update_result="0" update_time="1484694544"/>
<Task name="Promgen" build_result="0" update_result="3" update_time="0"/>
</Milestone>
<Milestone name="Map" build_result="2" build_time="1484609799">
<Task name="Map" build_result="2" update_result="0" update_time="1484609799"/>
<Task name="MapTrace" build_result="2" update_result="0" update_time="1484609802"/>
<Milestone name="Map" build_result="2" build_time="1484694504">
<Task name="Map" build_result="2" update_result="0" update_time="1484694504"/>
<Task name="MapTrace" build_result="2" update_result="0" update_time="1484694508"/>
<Task name="MapVerilogSimFile" build_result="0" update_result="3" update_time="0"/>
<Task name="MapVHDLSimFile" build_result="0" update_result="3" update_time="0"/>
</Milestone>
<Milestone name="PAR" build_result="2" build_time="1484609829">
<Task name="PAR" build_result="2" update_result="0" update_time="1484609829"/>
<Milestone name="PAR" build_result="2" build_time="1484694535">
<Task name="PAR" build_result="2" update_result="0" update_time="1484694535"/>
<Task name="PARTrace" build_result="0" update_result="3" update_time="0"/>
<Task name="IOTiming" build_result="0" update_result="3" update_time="0"/>
</Milestone>
<Milestone name="Synthesis" build_result="2" build_time="1484609379">
<Task name="Synplify_Synthesis" build_result="2" update_result="0" update_time="1484609379"/>
<Milestone name="Synthesis" build_result="2" build_time="1484694500">
<Task name="Synplify_Synthesis" build_result="2" update_result="0" update_time="1484694500"/>
</Milestone>
<Milestone name="TOOL_Report" build_result="0" build_time="0">
<Task name="HDLE" build_result="0" update_result="3" update_time="0"/>
<Task name="SSO" build_result="0" update_result="3" update_time="0"/>
<Task name="PIODRC" build_result="0" update_result="3" update_time="0"/>
<Task name="HDLE" build_result="0" update_result="2" update_time="1484693539"/>
<Task name="SSO" build_result="0" update_result="2" update_time="0"/>
<Task name="PIODRC" build_result="0" update_result="2" update_time="0"/>
<Task name="BKM" build_result="0" update_result="2" update_time="0"/>
<Task name="DEC" build_result="0" update_result="2" update_time="0"/>
</Milestone>
<Milestone name="Translate" build_result="2" build_time="1484609390">
<Task name="Translate" build_result="2" update_result="0" update_time="1484609390"/>
<Milestone name="Translate" build_result="2" build_time="1484694501">
<Task name="Translate" build_result="2" update_result="0" update_time="1484694501"/>
</Milestone>
<Report name="DisplayDriverwDecoder_impl1.bgn" last_build_time="1484609837" last_build_size="4457"/>
<Report name="DisplayDriverwDecoder_impl1.bit" last_build_time="1484609837" last_build_size="1032647"/>
<Report name="DisplayDriverwDecoder_impl1.edi" last_build_time="1484609379" last_build_size="51257"/>
<Report name="DisplayDriverwDecoder_impl1.bgn" last_build_time="1484694544" last_build_size="4459"/>
<Report name="DisplayDriverwDecoder_impl1.bit" last_build_time="1484694544" last_build_size="1032647"/>
<Report name="DisplayDriverwDecoder_impl1.edi" last_build_time="1484694497" last_build_size="51915"/>
<Report name="DisplayDriverwDecoder_impl1.lsedata" last_build_time="1483827599" last_build_size="1943"/>
<Report name="DisplayDriverwDecoder_impl1.ncd" last_build_time="1484609829" last_build_size="132097"/>
<Report name="DisplayDriverwDecoder_impl1.ngd" last_build_time="1484609390" last_build_size="42226"/>
<Report name="DisplayDriverwDecoder_impl1.tw1" last_build_time="1484609802" last_build_size="8444"/>
<Report name="DisplayDriverwDecoder_impl1_map.ncd" last_build_time="1484609799" last_build_size="90131"/>
<Report name="DisplayDriverwDecoder_impl1.ncd" last_build_time="1484694535" last_build_size="134466"/>
<Report name="DisplayDriverwDecoder_impl1.ngd" last_build_time="1484694501" last_build_size="42104"/>
<Report name="DisplayDriverwDecoder_impl1.tw1" last_build_time="1484694508" last_build_size="8446"/>
<Report name="DisplayDriverwDecoder_impl1_map.ncd" last_build_time="1484694504" last_build_size="92485"/>
</Strategy>
</BuildStatus>
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/AutoConstraint_display_driver_wrapper.sdc
0,0 → 1,4
 
#Begin clock constraint
define_clock -name {display_driver_wrapper|clk} {p:display_driver_wrapper|clk} -period 2.305 -clockgroup Autoconstr_clkgroup_0 -rise 0.000 -fall 1.152 -route 0.000
#End clock constraint
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.alt
1,26 → 1,25
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
NOTE All Rights Reserved *
NOTE DATE CREATED: Tue Jan 17 01:37:17 2017 *
NOTE DESIGN NAME: DisplayDriverWrapper *
NOTE DATE CREATED: Wed Jan 18 01:09:04 2017 *
NOTE DESIGN NAME: display_driver_wrapper *
NOTE DEVICE NAME: LFE5UM5G-45F-8CABGA381 *
NOTE PIN ASSIGNMENTS *
NOTE PINS disp_data[0] : M20 : out *
NOTE PINS disp_data_q[0] : M20 : out *
NOTE PINS clk : P3 : in *
NOTE PINS disp_sel : J1 : out *
NOTE PINS disp_data[14] : U1 : out *
NOTE PINS disp_data[13] : R16 : out *
NOTE PINS disp_data[12] : P16 : out *
NOTE PINS disp_data[11] : N17 : out *
NOTE PINS disp_data[10] : N18 : out *
NOTE PINS disp_data[9] : M17 : out *
NOTE PINS disp_data[8] : N16 : out *
NOTE PINS disp_data[7] : P17 : out *
NOTE PINS disp_data[6] : R17 : out *
NOTE PINS disp_data[5] : M18 : out *
NOTE PINS disp_data[4] : L17 : out *
NOTE PINS disp_data[3] : L16 : out *
NOTE PINS disp_data[2] : M19 : out *
NOTE PINS disp_data[1] : L18 : out *
NOTE PINS disp_data_q[14] : U1 : out *
NOTE PINS disp_data_q[13] : R16 : out *
NOTE PINS disp_data_q[12] : P16 : out *
NOTE PINS disp_data_q[11] : N17 : out *
NOTE PINS disp_data_q[10] : N18 : out *
NOTE PINS disp_data_q[9] : M17 : out *
NOTE PINS disp_data_q[8] : N16 : out *
NOTE PINS disp_data_q[7] : P17 : out *
NOTE PINS disp_data_q[6] : R17 : out *
NOTE PINS disp_data_q[5] : M18 : out *
NOTE PINS disp_data_q[4] : L17 : out *
NOTE PINS disp_data_q[3] : L16 : out *
NOTE PINS disp_data_q[2] : M19 : out *
NOTE PINS disp_data_q[1] : L18 : out *
NOTE PINS button : T1 : in *
NOTE PINS n_rst : K20 : in *
NOTE CONFIGURATION MODE: JTAG *
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.areasrr
1,9 → 1,9
----------------------------------------------------------------------
Report for cell DisplayDriverWrapper.arch
Report for cell display_driver_wrapper.arch
 
Register bits: 13 of 43848 (0%)
PIC Latch: 0
I/O cells: 19
I/O cells: 18
Cell usage:
cell count Res Usage(%)
CCU2C 5 100.0
14,7 → 14,7
IB 3 100.0
IFS1P3JX 1 100.0
INV 2 100.0
OB 16 100.0
OB 15 100.0
ORCALUT4 4 100.0
PUR 1 100.0
ROM128X1A 14 100.0
21,35 → 21,35
VHI 1 100.0
VLO 1 100.0
SUB MODULES
ASCIIDecoder 1 100.0
DisplayDriverwDecoder_Top 1 100.0
DistRomAsciiDecoder 1 100.0
ascii_decoder 1 100.0
decoder_table_dist_rom 1 100.0
display_driver_w_decoder 1 100.0
TOTAL 64
TOTAL 63
----------------------------------------------------------------------
Report for cell DisplayDriverwDecoder_Top.netlist
Instance path: DDwD_Top
Report for cell display_driver_w_decoder.netlist
Instance path: display_driver_with_decoder
Cell usage:
cell count Res Usage(%)
ROM128X1A 14 100.0
SUB MODULES
ASCIIDecoder 1 100.0
DistRomAsciiDecoder 1 100.0
ascii_decoder 1 100.0
decoder_table_dist_rom 1 100.0
TOTAL 16
----------------------------------------------------------------------
Report for cell ASCIIDecoder.netlist
Instance path: DDwD_Top.ascii_decoder_module
Report for cell ascii_decoder.netlist
Instance path: display_driver_with_decoder.ascii_decoder_module
Cell usage:
cell count Res Usage(%)
ROM128X1A 14 100.0
SUB MODULES
DistRomAsciiDecoder 1 100.0
decoder_table_dist_rom 1 100.0
TOTAL 15
----------------------------------------------------------------------
Report for cell DistRomAsciiDecoder.netlist
Instance path: DDwD_Top.ascii_decoder_module.rom_decoding_table
Report for cell decoder_table_dist_rom.netlist
Instance path: display_driver_with_decoder.ascii_decoder_module.rom_decoding_table
Cell usage:
cell count Res Usage(%)
ROM128X1A 14 100.0
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.bgn
8,7 → 8,7
Command: bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g DisableUES:FALSE -g ES:No -e -s C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.sec -k C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.bek -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml DisplayDriverwDecoder_impl1.ncd DisplayDriverwDecoder_impl1.prf
 
Loading design for application Bitgen from file DisplayDriverwDecoder_impl1.ncd.
Design name: DisplayDriverWrapper
Design name: display_driver_wrapper
NCD version: 3.3
Vendor: LATTICE
Device: LFE5UM5G-45F
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.bit Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.edi
1,10 → 1,10
(edif DisplayDriverWrapper
(edif display_driver_wrapper
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 2017 1 17 1 29 39)
(timeStamp 2017 1 18 1 8 17)
(author "Synopsys, Inc.")
(program "Synplify Pro" (version "L-2016.03L-1, mapper maplat, Build 1498R"))
)
149,11 → 149,11
(library work
(edifLevel 0)
(technology (numberDefinition ))
(cell DistRomAsciiDecoder (cellType GENERIC)
(cell decoder_table_dist_rom (cellType GENERIC)
(view netlist (viewType NETLIST)
(interface
(port (array (rename symbol_scan_cntr "symbol_scan_cntr(6:0)") 7) (direction INPUT))
(port (array (rename disp_data_c "disp_data_c(13:0)") 14) (direction OUTPUT))
(port (array (rename disp_data_q_c "disp_data_q_c(13:0)") 14) (direction OUTPUT))
)
(contents
(instance mem_0_13 (viewRef PRIM (cellRef ROM128X1A (libraryRef LUCENT)))
317,75 → 317,75
(portRef AD6 (instanceRef mem_0_12))
(portRef AD6 (instanceRef mem_0_13))
))
(net (rename disp_data_c_13 "disp_data_c[13]") (joined
(net (rename disp_data_q_c_13 "disp_data_q_c[13]") (joined
(portRef DO0 (instanceRef mem_0_13))
(portRef (member disp_data_c 0))
(portRef (member disp_data_q_c 0))
))
(net (rename disp_data_c_12 "disp_data_c[12]") (joined
(net (rename disp_data_q_c_12 "disp_data_q_c[12]") (joined
(portRef DO0 (instanceRef mem_0_12))
(portRef (member disp_data_c 1))
(portRef (member disp_data_q_c 1))
))
(net (rename disp_data_c_11 "disp_data_c[11]") (joined
(net (rename disp_data_q_c_11 "disp_data_q_c[11]") (joined
(portRef DO0 (instanceRef mem_0_11))
(portRef (member disp_data_c 2))
(portRef (member disp_data_q_c 2))
))
(net (rename disp_data_c_10 "disp_data_c[10]") (joined
(net (rename disp_data_q_c_10 "disp_data_q_c[10]") (joined
(portRef DO0 (instanceRef mem_0_10))
(portRef (member disp_data_c 3))
(portRef (member disp_data_q_c 3))
))
(net (rename disp_data_c_9 "disp_data_c[9]") (joined
(net (rename disp_data_q_c_9 "disp_data_q_c[9]") (joined
(portRef DO0 (instanceRef mem_0_9))
(portRef (member disp_data_c 4))
(portRef (member disp_data_q_c 4))
))
(net (rename disp_data_c_8 "disp_data_c[8]") (joined
(net (rename disp_data_q_c_8 "disp_data_q_c[8]") (joined
(portRef DO0 (instanceRef mem_0_8))
(portRef (member disp_data_c 5))
(portRef (member disp_data_q_c 5))
))
(net (rename disp_data_c_7 "disp_data_c[7]") (joined
(net (rename disp_data_q_c_7 "disp_data_q_c[7]") (joined
(portRef DO0 (instanceRef mem_0_7))
(portRef (member disp_data_c 6))
(portRef (member disp_data_q_c 6))
))
(net (rename disp_data_c_6 "disp_data_c[6]") (joined
(net (rename disp_data_q_c_6 "disp_data_q_c[6]") (joined
(portRef DO0 (instanceRef mem_0_6))
(portRef (member disp_data_c 7))
(portRef (member disp_data_q_c 7))
))
(net (rename disp_data_c_5 "disp_data_c[5]") (joined
(net (rename disp_data_q_c_5 "disp_data_q_c[5]") (joined
(portRef DO0 (instanceRef mem_0_5))
(portRef (member disp_data_c 8))
(portRef (member disp_data_q_c 8))
))
(net (rename disp_data_c_4 "disp_data_c[4]") (joined
(net (rename disp_data_q_c_4 "disp_data_q_c[4]") (joined
(portRef DO0 (instanceRef mem_0_4))
(portRef (member disp_data_c 9))
(portRef (member disp_data_q_c 9))
))
(net (rename disp_data_c_3 "disp_data_c[3]") (joined
(net (rename disp_data_q_c_3 "disp_data_q_c[3]") (joined
(portRef DO0 (instanceRef mem_0_3))
(portRef (member disp_data_c 10))
(portRef (member disp_data_q_c 10))
))
(net (rename disp_data_c_2 "disp_data_c[2]") (joined
(net (rename disp_data_q_c_2 "disp_data_q_c[2]") (joined
(portRef DO0 (instanceRef mem_0_2))
(portRef (member disp_data_c 11))
(portRef (member disp_data_q_c 11))
))
(net (rename disp_data_c_1 "disp_data_c[1]") (joined
(net (rename disp_data_q_c_1 "disp_data_q_c[1]") (joined
(portRef DO0 (instanceRef mem_0_1))
(portRef (member disp_data_c 12))
(portRef (member disp_data_q_c 12))
))
(net (rename disp_data_c_0 "disp_data_c[0]") (joined
(net (rename disp_data_q_c_0 "disp_data_q_c[0]") (joined
(portRef DO0 (instanceRef mem_0_0))
(portRef (member disp_data_c 13))
(portRef (member disp_data_q_c 13))
))
)
(property NGD_DRC_MASK (integer 1))
(property orig_inst_of (string "DistRomAsciiDecoder"))
(property orig_inst_of (string "decoder_table_dist_rom"))
)
)
(cell ASCIIDecoder (cellType GENERIC)
(cell ascii_decoder (cellType GENERIC)
(view netlist (viewType NETLIST)
(interface
(port (array (rename symbol_scan_cntr "symbol_scan_cntr(6:0)") 7) (direction INPUT))
(port (array (rename disp_data_c "disp_data_c(13:0)") 14) (direction OUTPUT))
(port (array (rename disp_data_q_c "disp_data_q_c(13:0)") 14) (direction OUTPUT))
)
(contents
(instance rom_decoding_table (viewRef netlist (cellRef DistRomAsciiDecoder))
(instance rom_decoding_table (viewRef netlist (cellRef decoder_table_dist_rom))
)
(net (rename symbol_scan_cntr_0 "symbol_scan_cntr[0]") (joined
(portRef (member symbol_scan_cntr 6))
415,74 → 415,74
(portRef (member symbol_scan_cntr 0))
(portRef (member symbol_scan_cntr 0) (instanceRef rom_decoding_table))
))
(net (rename disp_data_c_0 "disp_data_c[0]") (joined
(portRef (member disp_data_c 13) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 13))
(net (rename disp_data_q_c_0 "disp_data_q_c[0]") (joined
(portRef (member disp_data_q_c 13) (instanceRef rom_decoding_table))
(portRef (member disp_data_q_c 13))
))
(net (rename disp_data_c_1 "disp_data_c[1]") (joined
(portRef (member disp_data_c 12) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 12))
(net (rename disp_data_q_c_1 "disp_data_q_c[1]") (joined
(portRef (member disp_data_q_c 12) (instanceRef rom_decoding_table))
(portRef (member disp_data_q_c 12))
))
(net (rename disp_data_c_2 "disp_data_c[2]") (joined
(portRef (member disp_data_c 11) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 11))
(net (rename disp_data_q_c_2 "disp_data_q_c[2]") (joined
(portRef (member disp_data_q_c 11) (instanceRef rom_decoding_table))
(portRef (member disp_data_q_c 11))
))
(net (rename disp_data_c_3 "disp_data_c[3]") (joined
(portRef (member disp_data_c 10) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 10))
(net (rename disp_data_q_c_3 "disp_data_q_c[3]") (joined
(portRef (member disp_data_q_c 10) (instanceRef rom_decoding_table))
(portRef (member disp_data_q_c 10))
))
(net (rename disp_data_c_4 "disp_data_c[4]") (joined
(portRef (member disp_data_c 9) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 9))
(net (rename disp_data_q_c_4 "disp_data_q_c[4]") (joined
(portRef (member disp_data_q_c 9) (instanceRef rom_decoding_table))
(portRef (member disp_data_q_c 9))
))
(net (rename disp_data_c_5 "disp_data_c[5]") (joined
(portRef (member disp_data_c 8) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 8))
(net (rename disp_data_q_c_5 "disp_data_q_c[5]") (joined
(portRef (member disp_data_q_c 8) (instanceRef rom_decoding_table))
(portRef (member disp_data_q_c 8))
))
(net (rename disp_data_c_6 "disp_data_c[6]") (joined
(portRef (member disp_data_c 7) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 7))
(net (rename disp_data_q_c_6 "disp_data_q_c[6]") (joined
(portRef (member disp_data_q_c 7) (instanceRef rom_decoding_table))
(portRef (member disp_data_q_c 7))
))
(net (rename disp_data_c_7 "disp_data_c[7]") (joined
(portRef (member disp_data_c 6) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 6))
(net (rename disp_data_q_c_7 "disp_data_q_c[7]") (joined
(portRef (member disp_data_q_c 6) (instanceRef rom_decoding_table))
(portRef (member disp_data_q_c 6))
))
(net (rename disp_data_c_8 "disp_data_c[8]") (joined
(portRef (member disp_data_c 5) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 5))
(net (rename disp_data_q_c_8 "disp_data_q_c[8]") (joined
(portRef (member disp_data_q_c 5) (instanceRef rom_decoding_table))
(portRef (member disp_data_q_c 5))
))
(net (rename disp_data_c_9 "disp_data_c[9]") (joined
(portRef (member disp_data_c 4) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 4))
(net (rename disp_data_q_c_9 "disp_data_q_c[9]") (joined
(portRef (member disp_data_q_c 4) (instanceRef rom_decoding_table))
(portRef (member disp_data_q_c 4))
))
(net (rename disp_data_c_10 "disp_data_c[10]") (joined
(portRef (member disp_data_c 3) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 3))
(net (rename disp_data_q_c_10 "disp_data_q_c[10]") (joined
(portRef (member disp_data_q_c 3) (instanceRef rom_decoding_table))
(portRef (member disp_data_q_c 3))
))
(net (rename disp_data_c_11 "disp_data_c[11]") (joined
(portRef (member disp_data_c 2) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 2))
(net (rename disp_data_q_c_11 "disp_data_q_c[11]") (joined
(portRef (member disp_data_q_c 2) (instanceRef rom_decoding_table))
(portRef (member disp_data_q_c 2))
))
(net (rename disp_data_c_12 "disp_data_c[12]") (joined
(portRef (member disp_data_c 1) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 1))
(net (rename disp_data_q_c_12 "disp_data_q_c[12]") (joined
(portRef (member disp_data_q_c 1) (instanceRef rom_decoding_table))
(portRef (member disp_data_q_c 1))
))
(net (rename disp_data_c_13 "disp_data_c[13]") (joined
(portRef (member disp_data_c 0) (instanceRef rom_decoding_table))
(portRef (member disp_data_c 0))
(net (rename disp_data_q_c_13 "disp_data_q_c[13]") (joined
(portRef (member disp_data_q_c 0) (instanceRef rom_decoding_table))
(portRef (member disp_data_q_c 0))
))
)
(property orig_inst_of (string "ASCIIDecoder"))
(property orig_inst_of (string "ascii_decoder"))
)
)
(cell DisplayDriverwDecoder_Top (cellType GENERIC)
(cell display_driver_w_decoder (cellType GENERIC)
(view netlist (viewType NETLIST)
(interface
(port (array (rename symbol_scan_cntr "symbol_scan_cntr(6:0)") 7) (direction INPUT))
(port (array (rename disp_data_c "disp_data_c(13:0)") 14) (direction OUTPUT))
(port (array (rename disp_data_q_c "disp_data_q_c(13:0)") 14) (direction OUTPUT))
)
(contents
(instance ascii_decoder_module (viewRef netlist (cellRef ASCIIDecoder))
(instance ascii_decoder_module (viewRef netlist (cellRef ascii_decoder))
)
(net (rename symbol_scan_cntr_0 "symbol_scan_cntr[0]") (joined
(portRef (member symbol_scan_cntr 6))
512,74 → 512,73
(portRef (member symbol_scan_cntr 0))
(portRef (member symbol_scan_cntr 0) (instanceRef ascii_decoder_module))
))
(net (rename disp_data_c_0 "disp_data_c[0]") (joined
(portRef (member disp_data_c 13) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 13))
(net (rename disp_data_q_c_0 "disp_data_q_c[0]") (joined
(portRef (member disp_data_q_c 13) (instanceRef ascii_decoder_module))
(portRef (member disp_data_q_c 13))
))
(net (rename disp_data_c_1 "disp_data_c[1]") (joined
(portRef (member disp_data_c 12) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 12))
(net (rename disp_data_q_c_1 "disp_data_q_c[1]") (joined
(portRef (member disp_data_q_c 12) (instanceRef ascii_decoder_module))
(portRef (member disp_data_q_c 12))
))
(net (rename disp_data_c_2 "disp_data_c[2]") (joined
(portRef (member disp_data_c 11) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 11))
(net (rename disp_data_q_c_2 "disp_data_q_c[2]") (joined
(portRef (member disp_data_q_c 11) (instanceRef ascii_decoder_module))
(portRef (member disp_data_q_c 11))
))
(net (rename disp_data_c_3 "disp_data_c[3]") (joined
(portRef (member disp_data_c 10) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 10))
(net (rename disp_data_q_c_3 "disp_data_q_c[3]") (joined
(portRef (member disp_data_q_c 10) (instanceRef ascii_decoder_module))
(portRef (member disp_data_q_c 10))
))
(net (rename disp_data_c_4 "disp_data_c[4]") (joined
(portRef (member disp_data_c 9) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 9))
(net (rename disp_data_q_c_4 "disp_data_q_c[4]") (joined
(portRef (member disp_data_q_c 9) (instanceRef ascii_decoder_module))
(portRef (member disp_data_q_c 9))
))
(net (rename disp_data_c_5 "disp_data_c[5]") (joined
(portRef (member disp_data_c 8) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 8))
(net (rename disp_data_q_c_5 "disp_data_q_c[5]") (joined
(portRef (member disp_data_q_c 8) (instanceRef ascii_decoder_module))
(portRef (member disp_data_q_c 8))
))
(net (rename disp_data_c_6 "disp_data_c[6]") (joined
(portRef (member disp_data_c 7) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 7))
(net (rename disp_data_q_c_6 "disp_data_q_c[6]") (joined
(portRef (member disp_data_q_c 7) (instanceRef ascii_decoder_module))
(portRef (member disp_data_q_c 7))
))
(net (rename disp_data_c_7 "disp_data_c[7]") (joined
(portRef (member disp_data_c 6) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 6))
(net (rename disp_data_q_c_7 "disp_data_q_c[7]") (joined
(portRef (member disp_data_q_c 6) (instanceRef ascii_decoder_module))
(portRef (member disp_data_q_c 6))
))
(net (rename disp_data_c_8 "disp_data_c[8]") (joined
(portRef (member disp_data_c 5) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 5))
(net (rename disp_data_q_c_8 "disp_data_q_c[8]") (joined
(portRef (member disp_data_q_c 5) (instanceRef ascii_decoder_module))
(portRef (member disp_data_q_c 5))
))
(net (rename disp_data_c_9 "disp_data_c[9]") (joined
(portRef (member disp_data_c 4) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 4))
(net (rename disp_data_q_c_9 "disp_data_q_c[9]") (joined
(portRef (member disp_data_q_c 4) (instanceRef ascii_decoder_module))
(portRef (member disp_data_q_c 4))
))
(net (rename disp_data_c_10 "disp_data_c[10]") (joined
(portRef (member disp_data_c 3) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 3))
(net (rename disp_data_q_c_10 "disp_data_q_c[10]") (joined
(portRef (member disp_data_q_c 3) (instanceRef ascii_decoder_module))
(portRef (member disp_data_q_c 3))
))
(net (rename disp_data_c_11 "disp_data_c[11]") (joined
(portRef (member disp_data_c 2) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 2))
(net (rename disp_data_q_c_11 "disp_data_q_c[11]") (joined
(portRef (member disp_data_q_c 2) (instanceRef ascii_decoder_module))
(portRef (member disp_data_q_c 2))
))
(net (rename disp_data_c_12 "disp_data_c[12]") (joined
(portRef (member disp_data_c 1) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 1))
(net (rename disp_data_q_c_12 "disp_data_q_c[12]") (joined
(portRef (member disp_data_q_c 1) (instanceRef ascii_decoder_module))
(portRef (member disp_data_q_c 1))
))
(net (rename disp_data_c_13 "disp_data_c[13]") (joined
(portRef (member disp_data_c 0) (instanceRef ascii_decoder_module))
(portRef (member disp_data_c 0))
(net (rename disp_data_q_c_13 "disp_data_q_c[13]") (joined
(portRef (member disp_data_q_c 0) (instanceRef ascii_decoder_module))
(portRef (member disp_data_q_c 0))
))
)
(property orig_inst_of (string "DisplayDriverwDecoder_Top"))
(property orig_inst_of (string "display_driver_w_decoder"))
)
)
(cell DisplayDriverWrapper (cellType GENERIC)
(cell display_driver_wrapper (cellType GENERIC)
(view arch (viewType NETLIST)
(interface
(port clk (direction INPUT))
(port n_rst (direction INPUT))
(port button (direction INPUT))
(port (array (rename disp_data "disp_data(14:0)") 15) (direction OUTPUT))
(port disp_sel (direction OUTPUT))
(port (array (rename disp_data_q "disp_data_q(14:0)") 15) (direction OUTPUT))
)
(contents
(instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) )
586,7 → 585,7
(instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) )
(instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT)))
)
(instance (rename disp_data_pad_RNO_14 "disp_data_pad_RNO[14]") (viewRef PRIM (cellRef INV (libraryRef LUCENT))) )
(instance (rename disp_data_q_pad_RNO_14 "disp_data_q_pad_RNO[14]") (viewRef PRIM (cellRef INV (libraryRef LUCENT))) )
(instance n_rst_pad_RNIQVTF (viewRef PRIM (cellRef INV (libraryRef LUCENT))) )
(instance (rename bttn_state_fifo_0io_0 "bttn_state_fifo_0io[0]") (viewRef PRIM (cellRef IFS1P3JX (libraryRef LUCENT)))
(property IOB (string "FALSE"))
615,22 → 614,21
)
(instance bttn_state (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
)
(instance disp_sel_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_pad_14 "disp_data_pad[14]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_pad_13 "disp_data_pad[13]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_pad_12 "disp_data_pad[12]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_pad_11 "disp_data_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_pad_10 "disp_data_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_pad_9 "disp_data_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_pad_8 "disp_data_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_pad_7 "disp_data_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_pad_6 "disp_data_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_pad_5 "disp_data_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_pad_4 "disp_data_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_pad_3 "disp_data_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_pad_2 "disp_data_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_pad_1 "disp_data_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_pad_0 "disp_data_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_q_pad_14 "disp_data_q_pad[14]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_q_pad_13 "disp_data_q_pad[13]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_q_pad_12 "disp_data_q_pad[12]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_q_pad_11 "disp_data_q_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_q_pad_10 "disp_data_q_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_q_pad_9 "disp_data_q_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_q_pad_8 "disp_data_q_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_q_pad_7 "disp_data_q_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_q_pad_6 "disp_data_q_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_q_pad_5 "disp_data_q_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_q_pad_4 "disp_data_q_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_q_pad_3 "disp_data_q_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_q_pad_2 "disp_data_q_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_q_pad_1 "disp_data_q_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename disp_data_q_pad_0 "disp_data_q_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance button_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )
(instance n_rst_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )
(instance clk_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))
677,47 → 675,47
(property INJECT1_0 (string "NO"))
(property INIT1 (string "0x5003"))
)
(instance DDwD_Top (viewRef netlist (cellRef DisplayDriverwDecoder_Top))
(instance display_driver_with_decoder (viewRef netlist (cellRef display_driver_w_decoder))
)
(net (rename symbol_scan_cntr_0 "symbol_scan_cntr[0]") (joined
(portRef Q (instanceRef symbol_scan_cntr_0))
(portRef (member symbol_scan_cntr 6) (instanceRef DDwD_Top))
(portRef (member symbol_scan_cntr 6) (instanceRef display_driver_with_decoder))
(portRef A1 (instanceRef symbol_scan_cntr_cry_0_0))
))
(net (rename symbol_scan_cntr_1 "symbol_scan_cntr[1]") (joined
(portRef Q (instanceRef symbol_scan_cntr_1))
(portRef (member symbol_scan_cntr 5) (instanceRef DDwD_Top))
(portRef (member symbol_scan_cntr 5) (instanceRef display_driver_with_decoder))
(portRef A0 (instanceRef symbol_scan_cntr_cry_0_1))
))
(net (rename symbol_scan_cntr_2 "symbol_scan_cntr[2]") (joined
(portRef Q (instanceRef symbol_scan_cntr_2))
(portRef (member symbol_scan_cntr 4) (instanceRef DDwD_Top))
(portRef (member symbol_scan_cntr 4) (instanceRef display_driver_with_decoder))
(portRef A1 (instanceRef symbol_scan_cntr_cry_0_1))
))
(net (rename symbol_scan_cntr_3 "symbol_scan_cntr[3]") (joined
(portRef Q (instanceRef symbol_scan_cntr_3))
(portRef (member symbol_scan_cntr 3) (instanceRef DDwD_Top))
(portRef (member symbol_scan_cntr 3) (instanceRef display_driver_with_decoder))
(portRef A0 (instanceRef symbol_scan_cntr_cry_0_3))
))
(net (rename symbol_scan_cntr_4 "symbol_scan_cntr[4]") (joined
(portRef Q (instanceRef symbol_scan_cntr_4))
(portRef (member symbol_scan_cntr 2) (instanceRef DDwD_Top))
(portRef (member symbol_scan_cntr 2) (instanceRef display_driver_with_decoder))
(portRef A1 (instanceRef symbol_scan_cntr_cry_0_3))
))
(net (rename symbol_scan_cntr_5 "symbol_scan_cntr[5]") (joined
(portRef Q (instanceRef symbol_scan_cntr_5))
(portRef (member symbol_scan_cntr 1) (instanceRef DDwD_Top))
(portRef (member symbol_scan_cntr 1) (instanceRef display_driver_with_decoder))
(portRef A0 (instanceRef symbol_scan_cntr_cry_0_5))
))
(net (rename symbol_scan_cntr_6 "symbol_scan_cntr[6]") (joined
(portRef Q (instanceRef symbol_scan_cntr_6))
(portRef (member symbol_scan_cntr 0) (instanceRef DDwD_Top))
(portRef (member symbol_scan_cntr 0) (instanceRef display_driver_with_decoder))
(portRef A1 (instanceRef symbol_scan_cntr_cry_0_5))
))
(net (rename symbol_scan_cntr_7 "symbol_scan_cntr[7]") (joined
(portRef Q (instanceRef symbol_scan_cntr_7))
(portRef A0 (instanceRef symbol_scan_cntr_s_0_7))
(portRef A (instanceRef disp_data_pad_RNO_14))
(portRef A (instanceRef disp_data_q_pad_RNO_14))
))
(net (rename bttn_state_fifo_0 "bttn_state_fifo[0]") (joined
(portRef Q (instanceRef bttn_state_fifo_0io_0))
863,10 → 861,6
(portRef SP (instanceRef bttn_state_fifo_0io_0))
(portRef GSR (instanceRef GSR_INST))
))
(net GND (joined
(portRef Z (instanceRef GND))
(portRef I (instanceRef disp_sel_pad))
))
(net clk_c (joined
(portRef O (instanceRef clk_pad))
(portRef CK (instanceRef bttn_state))
905,126 → 899,122
(portRef button)
(portRef I (instanceRef button_pad))
))
(net (rename disp_data_c_0 "disp_data_c[0]") (joined
(portRef (member disp_data_c 13) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_0))
(net (rename disp_data_q_c_0 "disp_data_q_c[0]") (joined
(portRef (member disp_data_q_c 13) (instanceRef display_driver_with_decoder))
(portRef I (instanceRef disp_data_q_pad_0))
))
(net (rename disp_data_0 "disp_data[0]") (joined
(portRef O (instanceRef disp_data_pad_0))
(portRef (member disp_data 14))
(net (rename disp_data_q_0 "disp_data_q[0]") (joined
(portRef O (instanceRef disp_data_q_pad_0))
(portRef (member disp_data_q 14))
))
(net (rename disp_data_c_1 "disp_data_c[1]") (joined
(portRef (member disp_data_c 12) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_1))
(net (rename disp_data_q_c_1 "disp_data_q_c[1]") (joined
(portRef (member disp_data_q_c 12) (instanceRef display_driver_with_decoder))
(portRef I (instanceRef disp_data_q_pad_1))
))
(net (rename disp_data_1 "disp_data[1]") (joined
(portRef O (instanceRef disp_data_pad_1))
(portRef (member disp_data 13))
(net (rename disp_data_q_1 "disp_data_q[1]") (joined
(portRef O (instanceRef disp_data_q_pad_1))
(portRef (member disp_data_q 13))
))
(net (rename disp_data_c_2 "disp_data_c[2]") (joined
(portRef (member disp_data_c 11) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_2))
(net (rename disp_data_q_c_2 "disp_data_q_c[2]") (joined
(portRef (member disp_data_q_c 11) (instanceRef display_driver_with_decoder))
(portRef I (instanceRef disp_data_q_pad_2))
))
(net (rename disp_data_2 "disp_data[2]") (joined
(portRef O (instanceRef disp_data_pad_2))
(portRef (member disp_data 12))
(net (rename disp_data_q_2 "disp_data_q[2]") (joined
(portRef O (instanceRef disp_data_q_pad_2))
(portRef (member disp_data_q 12))
))
(net (rename disp_data_c_3 "disp_data_c[3]") (joined
(portRef (member disp_data_c 10) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_3))
(net (rename disp_data_q_c_3 "disp_data_q_c[3]") (joined
(portRef (member disp_data_q_c 10) (instanceRef display_driver_with_decoder))
(portRef I (instanceRef disp_data_q_pad_3))
))
(net (rename disp_data_3 "disp_data[3]") (joined
(portRef O (instanceRef disp_data_pad_3))
(portRef (member disp_data 11))
(net (rename disp_data_q_3 "disp_data_q[3]") (joined
(portRef O (instanceRef disp_data_q_pad_3))
(portRef (member disp_data_q 11))
))
(net (rename disp_data_c_4 "disp_data_c[4]") (joined
(portRef (member disp_data_c 9) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_4))
(net (rename disp_data_q_c_4 "disp_data_q_c[4]") (joined
(portRef (member disp_data_q_c 9) (instanceRef display_driver_with_decoder))
(portRef I (instanceRef disp_data_q_pad_4))
))
(net (rename disp_data_4 "disp_data[4]") (joined
(portRef O (instanceRef disp_data_pad_4))
(portRef (member disp_data 10))
(net (rename disp_data_q_4 "disp_data_q[4]") (joined
(portRef O (instanceRef disp_data_q_pad_4))
(portRef (member disp_data_q 10))
))
(net (rename disp_data_c_5 "disp_data_c[5]") (joined
(portRef (member disp_data_c 8) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_5))
(net (rename disp_data_q_c_5 "disp_data_q_c[5]") (joined
(portRef (member disp_data_q_c 8) (instanceRef display_driver_with_decoder))
(portRef I (instanceRef disp_data_q_pad_5))
))
(net (rename disp_data_5 "disp_data[5]") (joined
(portRef O (instanceRef disp_data_pad_5))
(portRef (member disp_data 9))
(net (rename disp_data_q_5 "disp_data_q[5]") (joined
(portRef O (instanceRef disp_data_q_pad_5))
(portRef (member disp_data_q 9))
))
(net (rename disp_data_c_6 "disp_data_c[6]") (joined
(portRef (member disp_data_c 7) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_6))
(net (rename disp_data_q_c_6 "disp_data_q_c[6]") (joined
(portRef (member disp_data_q_c 7) (instanceRef display_driver_with_decoder))
(portRef I (instanceRef disp_data_q_pad_6))
))
(net (rename disp_data_6 "disp_data[6]") (joined
(portRef O (instanceRef disp_data_pad_6))
(portRef (member disp_data 8))
(net (rename disp_data_q_6 "disp_data_q[6]") (joined
(portRef O (instanceRef disp_data_q_pad_6))
(portRef (member disp_data_q 8))
))
(net (rename disp_data_c_7 "disp_data_c[7]") (joined
(portRef (member disp_data_c 6) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_7))
(net (rename disp_data_q_c_7 "disp_data_q_c[7]") (joined
(portRef (member disp_data_q_c 6) (instanceRef display_driver_with_decoder))
(portRef I (instanceRef disp_data_q_pad_7))
))
(net (rename disp_data_7 "disp_data[7]") (joined
(portRef O (instanceRef disp_data_pad_7))
(portRef (member disp_data 7))
(net (rename disp_data_q_7 "disp_data_q[7]") (joined
(portRef O (instanceRef disp_data_q_pad_7))
(portRef (member disp_data_q 7))
))
(net (rename disp_data_c_8 "disp_data_c[8]") (joined
(portRef (member disp_data_c 5) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_8))
(net (rename disp_data_q_c_8 "disp_data_q_c[8]") (joined
(portRef (member disp_data_q_c 5) (instanceRef display_driver_with_decoder))
(portRef I (instanceRef disp_data_q_pad_8))
))
(net (rename disp_data_8 "disp_data[8]") (joined
(portRef O (instanceRef disp_data_pad_8))
(portRef (member disp_data 6))
(net (rename disp_data_q_8 "disp_data_q[8]") (joined
(portRef O (instanceRef disp_data_q_pad_8))
(portRef (member disp_data_q 6))
))
(net (rename disp_data_c_9 "disp_data_c[9]") (joined
(portRef (member disp_data_c 4) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_9))
(net (rename disp_data_q_c_9 "disp_data_q_c[9]") (joined
(portRef (member disp_data_q_c 4) (instanceRef display_driver_with_decoder))
(portRef I (instanceRef disp_data_q_pad_9))
))
(net (rename disp_data_9 "disp_data[9]") (joined
(portRef O (instanceRef disp_data_pad_9))
(portRef (member disp_data 5))
(net (rename disp_data_q_9 "disp_data_q[9]") (joined
(portRef O (instanceRef disp_data_q_pad_9))
(portRef (member disp_data_q 5))
))
(net (rename disp_data_c_10 "disp_data_c[10]") (joined
(portRef (member disp_data_c 3) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_10))
(net (rename disp_data_q_c_10 "disp_data_q_c[10]") (joined
(portRef (member disp_data_q_c 3) (instanceRef display_driver_with_decoder))
(portRef I (instanceRef disp_data_q_pad_10))
))
(net (rename disp_data_10 "disp_data[10]") (joined
(portRef O (instanceRef disp_data_pad_10))
(portRef (member disp_data 4))
(net (rename disp_data_q_10 "disp_data_q[10]") (joined
(portRef O (instanceRef disp_data_q_pad_10))
(portRef (member disp_data_q 4))
))
(net (rename disp_data_c_11 "disp_data_c[11]") (joined
(portRef (member disp_data_c 2) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_11))
(net (rename disp_data_q_c_11 "disp_data_q_c[11]") (joined
(portRef (member disp_data_q_c 2) (instanceRef display_driver_with_decoder))
(portRef I (instanceRef disp_data_q_pad_11))
))
(net (rename disp_data_11 "disp_data[11]") (joined
(portRef O (instanceRef disp_data_pad_11))
(portRef (member disp_data 3))
(net (rename disp_data_q_11 "disp_data_q[11]") (joined
(portRef O (instanceRef disp_data_q_pad_11))
(portRef (member disp_data_q 3))
))
(net (rename disp_data_c_12 "disp_data_c[12]") (joined
(portRef (member disp_data_c 1) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_12))
(net (rename disp_data_q_c_12 "disp_data_q_c[12]") (joined
(portRef (member disp_data_q_c 1) (instanceRef display_driver_with_decoder))
(portRef I (instanceRef disp_data_q_pad_12))
))
(net (rename disp_data_12 "disp_data[12]") (joined
(portRef O (instanceRef disp_data_pad_12))
(portRef (member disp_data 2))
(net (rename disp_data_q_12 "disp_data_q[12]") (joined
(portRef O (instanceRef disp_data_q_pad_12))
(portRef (member disp_data_q 2))
))
(net (rename disp_data_c_13 "disp_data_c[13]") (joined
(portRef (member disp_data_c 0) (instanceRef DDwD_Top))
(portRef I (instanceRef disp_data_pad_13))
(net (rename disp_data_q_c_13 "disp_data_q_c[13]") (joined
(portRef (member disp_data_q_c 0) (instanceRef display_driver_with_decoder))
(portRef I (instanceRef disp_data_q_pad_13))
))
(net (rename disp_data_13 "disp_data[13]") (joined
(portRef O (instanceRef disp_data_pad_13))
(portRef (member disp_data 1))
(net (rename disp_data_q_13 "disp_data_q[13]") (joined
(portRef O (instanceRef disp_data_q_pad_13))
(portRef (member disp_data_q 1))
))
(net (rename disp_data_14 "disp_data[14]") (joined
(portRef O (instanceRef disp_data_pad_14))
(portRef (member disp_data 0))
(net (rename disp_data_q_14 "disp_data_q[14]") (joined
(portRef O (instanceRef disp_data_q_pad_14))
(portRef (member disp_data_q 0))
))
(net disp_sel (joined
(portRef O (instanceRef disp_sel_pad))
(portRef disp_sel)
))
(net n_rst_c_i (joined
(portRef Z (instanceRef n_rst_pad_RNIQVTF))
(portRef PD (instanceRef bttn_state_fifo_3))
1041,17 → 1031,17
(portRef PD (instanceRef bttn_state_fifo_0io_0))
))
(net (rename symbol_scan_cntr_i_7 "symbol_scan_cntr_i[7]") (joined
(portRef Z (instanceRef disp_data_pad_RNO_14))
(portRef I (instanceRef disp_data_pad_14))
(portRef Z (instanceRef disp_data_q_pad_RNO_14))
(portRef I (instanceRef disp_data_q_pad_14))
))
(net N_1 (joined
(portRef CIN (instanceRef symbol_scan_cntr_cry_0_0))
))
)
(property orig_inst_of (string "DisplayDriverWrapper"))
(property orig_inst_of (string "display_driver_wrapper"))
)
)
)
(design DisplayDriverWrapper (cellRef DisplayDriverWrapper (libraryRef work))
(design display_driver_wrapper (cellRef display_driver_wrapper (libraryRef work))
(property PART (string "lfe5um5g_45f-8") ))
)
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.mrp
1,5 → 1,5
 
Lattice Mapping Report File for Design Module 'DisplayDriverWrapper'
Lattice Mapping Report File for Design Module 'display_driver_wrapper'
 
 
Design Information
17,7 → 17,7
Target Device: LFE5UM5G-45FCABGA381
Target Performance: 8
Mapper: sa5p00g, version: Diamond (64-bit) 3.8.0.115.3
Mapped on: 01/17/17 01:36:37
Mapped on: 01/18/17 01:08:21
 
Design Summary
--------------
34,8 → 34,8
Number used as distributed RAM: 0
Number used as ripple logic: 10
Number used as shift registers: 0
Number of PIO sites used: 20 out of 203 (10%)
Number of PIO sites used for single ended IOs: 18
Number of PIO sites used: 19 out of 203 (9%)
Number of PIO sites used for single ended IOs: 17
Number of PIO sites used for differential IOs: 2 (represented by 1 PIO
comps in NCD)
Number of block RAMs: 0 out of 108 (0%)
66,7 → 66,7
 
 
 
Design: DisplayDriverWrapper Date: 01/17/17 01:36:37
Design: display_driver_wrapper Date: 01/18/17 01:08:22
 
Design Summary (cont)
---------------------
116,7 → 116,7
----------------------
 
WARNING - map: C:/Projects/single-14-segment-display-driver-w-decoder/Project/La
ttice_FPGA_Build/DisplayDriverwDecoder.lpf(21): Semantic error in "USERCODE
ttice_FPGA_Build/DisplayDriverwDecoder.lpf(29): Semantic error in "USERCODE
ASCII "G.L." ; ": Invalid Ascii char <.>.Invalid Ascii char <.>.. This
preference has been disabled.
WARNING - map: Preference parsing results: 1 semantic error detected.
132,7 → 132,7
 
 
 
Design: DisplayDriverWrapper Date: 01/17/17 01:36:37
Design: display_driver_wrapper Date: 01/18/17 01:08:22
 
IO (PIO) Attributes
-------------------
141,40 → 141,38
| IO Name | Direction | Levelmode | IO |
| | | IO_TYPE | Register |
+---------------------+-----------+-----------+------------+
| disp_data[0] | OUTPUT | LVCMOS25 | |
| disp_data_q[0] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| clk | INPUT | LVDS | |
+---------------------+-----------+-----------+------------+
| disp_sel | OUTPUT | LVCMOS25 | |
| disp_data_q[14] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[14] | OUTPUT | LVCMOS25 | |
| disp_data_q[13] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[13] | OUTPUT | LVCMOS25 | |
| disp_data_q[12] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[12] | OUTPUT | LVCMOS25 | |
| disp_data_q[11] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[11] | OUTPUT | LVCMOS25 | |
| disp_data_q[10] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[10] | OUTPUT | LVCMOS25 | |
| disp_data_q[9] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[9] | OUTPUT | LVCMOS25 | |
| disp_data_q[8] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[8] | OUTPUT | LVCMOS25 | |
| disp_data_q[7] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[7] | OUTPUT | LVCMOS25 | |
| disp_data_q[6] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[6] | OUTPUT | LVCMOS25 | |
| disp_data_q[5] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[5] | OUTPUT | LVCMOS25 | |
| disp_data_q[4] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[4] | OUTPUT | LVCMOS25 | |
| disp_data_q[3] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[3] | OUTPUT | LVCMOS25 | |
| disp_data_q[2] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[2] | OUTPUT | LVCMOS25 | |
| disp_data_q[1] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[1] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| button | INPUT | LVCMOS25 | IN |
+---------------------+-----------+-----------+------------+
| n_rst | INPUT | LVCMOS25 | |
183,8 → 181,8
Removed logic
-------------
 
Block GND undriven or does not drive anything - clipped.
Signal n_rst_c_i was merged into signal n_rst_c
Signal GND undriven or does not drive anything - clipped.
Signal VCC undriven or does not drive anything - clipped.
Signal symbol_scan_cntr_cry_0_S0[0] undriven or does not drive anything -
clipped.
192,6 → 190,8
Signal symbol_scan_cntr_s_0_S1[7] undriven or does not drive anything - clipped.
Signal symbol_scan_cntr_s_0_COUT[7] undriven or does not drive anything -
clipped.
Block n_rst_pad_RNIQVTF was optimized away.
 
Page 3
 
198,13 → 198,10
 
 
 
Design: DisplayDriverWrapper Date: 01/17/17 01:36:37
Design: display_driver_wrapper Date: 01/18/17 01:08:22
 
Removed logic (cont)
--------------------
clipped.
Block n_rst_pad_RNIQVTF was optimized away.
Block GND was optimized away.
Block VCC was optimized away.
 
Memory Usage
247,7 → 244,7
-------------------------
 
Total CPU Time: 1 secs
Total REAL Time: 2 secs
Total REAL Time: 3 secs
Peak Memory Usage: 152 MB
 
259,6 → 256,9
 
 
 
 
 
 
Page 4
 
 
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.ncd Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.ngd Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.ngo Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.pad
6,32 → 6,31
PACKAGE: CABGA381
Package Status: Final Version 1.36
 
Tue Jan 17 01:36:59 2017
Wed Jan 18 01:08:45 2017
 
Pinout by Port Name:
+---------------+----------+--------------+-------+-----------+---------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | BC Enable | Properties |
+---------------+----------+--------------+-------+-----------+---------------------------------+
| button | T1/8 | LVCMOS25_IN | PB4B | | PULL:UP CLAMP:ON HYSTERESIS:ON |
| clk | P3/6 | LVDS_IN | PL68C | | CLAMP:ON |
| disp_data[0] | M20/3 | LVCMOS25_OUT | PR35B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[10] | N18/3 | LVCMOS25_OUT | PR41C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[11] | N17/3 | LVCMOS25_OUT | PR44A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[12] | P16/3 | LVCMOS25_OUT | PR44B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[13] | R16/3 | LVCMOS25_OUT | PR44C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[14] | U1/8 | LVCMOS25_OUT | PB6A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[1] | L18/3 | LVCMOS25_OUT | PR38C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[2] | M19/3 | LVCMOS25_OUT | PR35D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[3] | L16/3 | LVCMOS25_OUT | PR38A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[4] | L17/3 | LVCMOS25_OUT | PR38B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[5] | M18/3 | LVCMOS25_OUT | PR38D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[6] | R17/3 | LVCMOS25_OUT | PR44D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[7] | P17/3 | LVCMOS25_OUT | PR41D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[8] | N16/3 | LVCMOS25_OUT | PR41A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[9] | M17/3 | LVCMOS25_OUT | PR41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_sel | J1/6 | LVCMOS25_OUT | PL41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| n_rst | K20/2 | LVCMOS25_IN | PR32D | | PULL:UP CLAMP:ON HYSTERESIS:ON |
+---------------+----------+--------------+-------+-----------+---------------------------------+
+-----------------+----------+--------------+-------+-----------+---------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | BC Enable | Properties |
+-----------------+----------+--------------+-------+-----------+---------------------------------+
| button | T1/8 | LVCMOS25_IN | PB4B | | PULL:UP CLAMP:ON HYSTERESIS:ON |
| clk | P3/6 | LVDS_IN | PL68C | | CLAMP:ON |
| disp_data_q[0] | M20/3 | LVCMOS25_OUT | PR35B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[10] | N18/3 | LVCMOS25_OUT | PR41C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[11] | N17/3 | LVCMOS25_OUT | PR44A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[12] | P16/3 | LVCMOS25_OUT | PR44B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[13] | R16/3 | LVCMOS25_OUT | PR44C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[14] | U1/8 | LVCMOS25_OUT | PB6A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[1] | L18/3 | LVCMOS25_OUT | PR38C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[2] | M19/3 | LVCMOS25_OUT | PR35D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[3] | L16/3 | LVCMOS25_OUT | PR38A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[4] | L17/3 | LVCMOS25_OUT | PR38B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[5] | M18/3 | LVCMOS25_OUT | PR38D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[6] | R17/3 | LVCMOS25_OUT | PR44D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[7] | P17/3 | LVCMOS25_OUT | PR41D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[8] | N16/3 | LVCMOS25_OUT | PR41A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[9] | M17/3 | LVCMOS25_OUT | PR41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| n_rst | K20/2 | LVCMOS25_IN | PR32D | | PULL:UP CLAMP:ON HYSTERESIS:ON |
+-----------------+----------+--------------+-------+-----------+---------------------------------+
 
Vccio by Bank:
+------+-------+
39,7 → 38,7
+------+-------+
| 2 | 2.5V |
| 3 | 2.5V |
| 6 | 2.5V |
| 6 | 1.2V |
| 8 | 2.5V |
+------+-------+
 
175,7 → 174,7
| H17/2 | unused, PULL:DOWN | | | PR20B | RDQ17 | |
| H18/2 | unused, PULL:DOWN | | | PR20A | RDQ17 | |
| H20/2 | unused, PULL:DOWN | | | PR29B | RDQSN29 | |
| J1/6 | disp_sel | LOCATED | LVCMOS25_OUT | PL41B | LDQSN41 | |
| J1/6 | unused, PULL:DOWN | | | PL41B | LDQSN41 | |
| J3/6 | unused, PULL:DOWN | | | PL38C | GR_PCLK6_1/LDQ41 | |
| J4/6 | unused, PULL:DOWN | | | PL38A | GR_PCLK6_0/LDQ41 | |
| J5/6 | unused, PULL:DOWN | | | PL38B | LDQ41 | |
197,9 → 196,9
| L3/6 | unused, PULL:DOWN | | | PL62C | LDQ65 | |
| L4/6 | unused, PULL:DOWN | | | PL44C | LDQ41 | |
| L5/6 | unused, PULL:DOWN | | | PL44D | LDQ41 | |
| L16/3 | disp_data[3] | LOCATED | LVCMOS25_OUT | PR38A | GR_PCLK3_0/RDQ41 | |
| L17/3 | disp_data[4] | LOCATED | LVCMOS25_OUT | PR38B | RDQ41 | |
| L18/3 | disp_data[1] | LOCATED | LVCMOS25_OUT | PR38C | GR_PCLK3_1/RDQ41 | |
| L16/3 | disp_data_q[3] | LOCATED | LVCMOS25_OUT | PR38A | GR_PCLK3_0/RDQ41 | |
| L17/3 | disp_data_q[4] | LOCATED | LVCMOS25_OUT | PR38B | RDQ41 | |
| L18/3 | disp_data_q[1] | LOCATED | LVCMOS25_OUT | PR38C | GR_PCLK3_1/RDQ41 | |
| L19/3 | unused, PULL:DOWN | | | PR35C | PCLKT3_0/RDQ41 | |
| L20/3 | unused, PULL:DOWN | | | PR35A | PCLKT3_1/RDQ41 | |
| M1/6 | unused, PULL:DOWN | | | PL65B | LDQSN65 | |
206,18 → 205,18
| M3/6 | unused, PULL:DOWN | | | PL62B | LDQ65 | |
| M4/6 | unused, PULL:DOWN | | | PL59A | LDQ65 | |
| M5/6 | unused, PULL:DOWN | | | PL53A | LDQS53 | |
| M17/3 | disp_data[9] | LOCATED | LVCMOS25_OUT | PR41B | RDQSN41 | |
| M18/3 | disp_data[5] | LOCATED | LVCMOS25_OUT | PR38D | RDQ41 | |
| M19/3 | disp_data[2] | LOCATED | LVCMOS25_OUT | PR35D | PCLKC3_0/RDQ41 | |
| M20/3 | disp_data[0] | LOCATED | LVCMOS25_OUT | PR35B | PCLKC3_1/RDQ41 | |
| M17/3 | disp_data_q[9] | LOCATED | LVCMOS25_OUT | PR41B | RDQSN41 | |
| M18/3 | disp_data_q[5] | LOCATED | LVCMOS25_OUT | PR38D | RDQ41 | |
| M19/3 | disp_data_q[2] | LOCATED | LVCMOS25_OUT | PR35D | PCLKC3_0/RDQ41 | |
| M20/3 | disp_data_q[0] | LOCATED | LVCMOS25_OUT | PR35B | PCLKC3_1/RDQ41 | |
| N1/6 | unused, PULL:DOWN | | | PL65D | LDQ65 | |
| N2/6 | unused, PULL:DOWN | | | PL65A | LDQS65 | |
| N3/6 | unused, PULL:DOWN | | | PL62A | LDQ65 | |
| N4/6 | unused, PULL:DOWN | | | PL59C | LDQ65 | |
| N5/6 | unused, PULL:DOWN | | | PL59B | LDQ65 | |
| N16/3 | disp_data[8] | LOCATED | LVCMOS25_OUT | PR41A | RDQS41 | |
| N17/3 | disp_data[11] | LOCATED | LVCMOS25_OUT | PR44A | RDQ41 | |
| N18/3 | disp_data[10] | LOCATED | LVCMOS25_OUT | PR41C | RDQ41 | |
| N16/3 | disp_data_q[8] | LOCATED | LVCMOS25_OUT | PR41A | RDQS41 | |
| N17/3 | disp_data_q[11] | LOCATED | LVCMOS25_OUT | PR44A | RDQ41 | |
| N18/3 | disp_data_q[10] | LOCATED | LVCMOS25_OUT | PR41C | RDQ41 | |
| N19/3 | unused, PULL:DOWN | | | PR59A | RDQ65 | |
| N20/3 | unused, PULL:DOWN | | | PR59B | RDQ65 | |
| P1/6 | unused, PULL:DOWN | | | PL68A | LDQ65 | |
225,8 → 224,8
| P3/6 | clk+ | LOCATED | LVDS_IN | PL68C | LLC_GPLL0T_IN/LDQ65 | |
| P4/6 | clk- | | LVDS_IN | PL68D | LLC_GPLL0C_IN/LDQ65 | |
| P5/6 | unused, PULL:DOWN | | | PL59D | LDQ65 | |
| P16/3 | disp_data[12] | LOCATED | LVCMOS25_OUT | PR44B | VREF1_3/RDQ41 | |
| P17/3 | disp_data[7] | LOCATED | LVCMOS25_OUT | PR41D | RDQ41 | |
| P16/3 | disp_data_q[12] | LOCATED | LVCMOS25_OUT | PR44B | VREF1_3/RDQ41 | |
| P17/3 | disp_data_q[7] | LOCATED | LVCMOS25_OUT | PR41D | RDQ41 | |
| P18/3 | unused, PULL:DOWN | | | PR59D | RDQ65 | |
| P19/3 | unused, PULL:DOWN | | | PR59C | RDQ65 | |
| P20/3 | unused, PULL:DOWN | | | PR62A | RDQ65 | |
275,8 → 274,8
| R1/8 | unused, PULL:DOWN | | | PB4A | D7/IO7 | |
| R2/8 | unused, PULL:DOWN | | | PB15A | HOLDN/DI/BUSY/CSSPIN/CEN | |
| R3/8 | unused, PULL:DOWN | | | PB15B | DOUT/CSON | |
| R16/3 | disp_data[13] | LOCATED | LVCMOS25_OUT | PR44C | RDQ41 | |
| R17/3 | disp_data[6] | LOCATED | LVCMOS25_OUT | PR44D | RDQ41 | |
| R16/3 | disp_data_q[13] | LOCATED | LVCMOS25_OUT | PR44C | RDQ41 | |
| R17/3 | disp_data_q[6] | LOCATED | LVCMOS25_OUT | PR44D | RDQ41 | |
| R18/3 | unused, PULL:DOWN | | | PR65B | RDQSN65 | |
| R20/3 | unused, PULL:DOWN | | | PR62B | RDQ65 | |
| T1/8 | button | LOCATED | LVCMOS25_IN | PB4B | D6/IO6 | |
291,7 → 290,7
| TDI/40 | | | | TDI | | |
| TDO/40 | | | | TDO | | |
| TMS/40 | | | | TMS | | |
| U1/8 | disp_data[14] | LOCATED | LVCMOS25_OUT | PB6A | D5/MISO2/IO5 | |
| U1/8 | disp_data_q[14] | LOCATED | LVCMOS25_OUT | PB6A | D5/MISO2/IO5 | |
| U2/8 | unused, PULL:DOWN | | | PB13B | CS1N | |
| U16/3 | unused, PULL:DOWN | | | PR68C | LRC_GPLL0T_IN/RDQ65 | |
| U17/3 | unused, PULL:DOWN | | | PR68B | RDQ65 | |
331,22 → 330,21
 
LOCATE COMP "button" SITE "T1";
LOCATE COMP "clk" SITE "P3";
LOCATE COMP "disp_data[0]" SITE "M20";
LOCATE COMP "disp_data[10]" SITE "N18";
LOCATE COMP "disp_data[11]" SITE "N17";
LOCATE COMP "disp_data[12]" SITE "P16";
LOCATE COMP "disp_data[13]" SITE "R16";
LOCATE COMP "disp_data[14]" SITE "U1";
LOCATE COMP "disp_data[1]" SITE "L18";
LOCATE COMP "disp_data[2]" SITE "M19";
LOCATE COMP "disp_data[3]" SITE "L16";
LOCATE COMP "disp_data[4]" SITE "L17";
LOCATE COMP "disp_data[5]" SITE "M18";
LOCATE COMP "disp_data[6]" SITE "R17";
LOCATE COMP "disp_data[7]" SITE "P17";
LOCATE COMP "disp_data[8]" SITE "N16";
LOCATE COMP "disp_data[9]" SITE "M17";
LOCATE COMP "disp_sel" SITE "J1";
LOCATE COMP "disp_data_q[0]" SITE "M20";
LOCATE COMP "disp_data_q[10]" SITE "N18";
LOCATE COMP "disp_data_q[11]" SITE "N17";
LOCATE COMP "disp_data_q[12]" SITE "P16";
LOCATE COMP "disp_data_q[13]" SITE "R16";
LOCATE COMP "disp_data_q[14]" SITE "U1";
LOCATE COMP "disp_data_q[1]" SITE "L18";
LOCATE COMP "disp_data_q[2]" SITE "M19";
LOCATE COMP "disp_data_q[3]" SITE "L16";
LOCATE COMP "disp_data_q[4]" SITE "L17";
LOCATE COMP "disp_data_q[5]" SITE "M18";
LOCATE COMP "disp_data_q[6]" SITE "R17";
LOCATE COMP "disp_data_q[7]" SITE "P17";
LOCATE COMP "disp_data_q[8]" SITE "N16";
LOCATE COMP "disp_data_q[9]" SITE "M17";
LOCATE COMP "n_rst" SITE "K20";
 
 
359,5 → 357,5
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
Tue Jan 17 01:36:59 2017
Wed Jan 18 01:08:45 2017
 
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.par
4,7 → 4,7
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
Tue Jan 17 01:36:43 2017
Wed Jan 18 01:08:29 2017
 
C:/lscc/diamond/3.8_x64/ispfpga\bin\nt64\par -f DisplayDriverwDecoder_impl1.p2t
DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir
17,17 → 17,17
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 -1.238 7103 0.178 0 26 Complete
5_1 * 0 -1.238 7103 0.178 0 25 Complete
 
 
* : Design saved.
 
Total (real) run time for 1-seed: 26 secs
Total (real) run time for 1-seed: 25 secs
 
par done!
 
Lattice Place and Route Report for Design "DisplayDriverwDecoder_impl1_map.ncd"
Tue Jan 17 01:36:43 2017
Wed Jan 18 01:08:29 2017
 
PAR: Place And Route Diamond (64-bit) 3.8.0.115.3.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir/5_1.ncd DisplayDriverwDecoder_impl1.prf
36,7 → 36,7
Routing Iterations: 6
 
Loading design for application par from file DisplayDriverwDecoder_impl1_map.ncd.
Design name: DisplayDriverWrapper
Design name: display_driver_wrapper
NCD version: 3.3
Vendor: LATTICE
Device: LFE5UM5G-45F
51,8 → 51,8
Ignore Preference Error(s): True
Device utilization summary:
 
PIO (prelim) 20/245 8% used
20/203 9% bonded
PIO (prelim) 19/245 7% used
19/203 9% bonded
IOLOGIC 1/245 <1% used
 
SLICE 65/21924 <1% used
64,7 → 64,7
Number of Connections: 657
 
Pin Constraint Summary:
19 out of 19 pins locked (100% locked).
18 out of 18 pins locked (100% locked).
 
The following 1 signal is selected to use the primary clock routing resources:
clk_c (driver: clk, clk/ce/sr load #: 9/0/0)
124,9 → 124,9
 
+
I/O Usage Summary (final):
20 out of 245 (8.2%) PIO sites used.
20 out of 203 (9.9%) bonded PIO sites used.
Number of PIO comps: 19; differential: 1.
19 out of 245 (7.8%) PIO sites used.
19 out of 203 (9.4%) bonded PIO sites used.
Number of PIO comps: 18; differential: 1.
Number of Vref pins used: 0.
 
I/O Bank Usage Summary:
137,12 → 137,12
| 1 | 0 / 33 ( 0%) | - | - | - |
| 2 | 1 / 32 ( 3%) | 2.5V | - | - |
| 3 | 14 / 33 ( 42%) | 2.5V | - | - |
| 6 | 3 / 33 ( 9%) | 2.5V | - | - |
| 6 | 2 / 33 ( 6%) | 1.2V | - | - |
| 7 | 0 / 32 ( 0%) | - | - | - |
| 8 | 2 / 13 ( 15%) | 2.5V | - | - |
+----------+----------------+------------+------------+------------+
 
Total placer CPU time: 15 secs
Total placer CPU time: 14 secs
 
Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.
 
149,9 → 149,9
0 connections routed; 657 unrouted.
Starting router resource preassignment
 
Completed router resource preassignment. Real time: 23 secs
Completed router resource preassignment. Real time: 22 secs
 
Start NBR router at 01:37:06 01/17/17
Start NBR router at 01:08:51 01/18/17
 
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
166,26 → 166,26
your design.
*****************************************************************
 
Start NBR special constraint process at 01:37:06 01/17/17
Start NBR special constraint process at 01:08:52 01/18/17
 
Start NBR section for initial routing at 01:37:06 01/17/17
Start NBR section for initial routing at 01:08:52 01/18/17
Level 1, iteration 1
0(0.00%) conflict; 544(82.80%) untouched conns; 8380 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.227ns/-8.380ns; real time: 24 secs
Estimated worst slack/total negative slack<setup>: -1.227ns/-8.380ns; real time: 23 secs
Level 2, iteration 1
0(0.00%) conflict; 542(82.50%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 23 secs
Level 3, iteration 1
0(0.00%) conflict; 523(79.60%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 23 secs
Level 4, iteration 1
5(0.00%) conflicts; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 23 secs
 
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
 
Start NBR section for normal routing at 01:37:07 01/17/17
Start NBR section for normal routing at 01:08:53 01/18/17
Level 1, iteration 1
0(0.00%) conflict; 8(1.22%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
199,17 → 199,17
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
 
Start NBR section for performance tuning (iteration 1) at 01:37:07 01/17/17
Start NBR section for performance tuning (iteration 1) at 01:08:53 01/18/17
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
 
Start NBR section for re-routing at 01:37:07 01/17/17
Start NBR section for re-routing at 01:08:53 01/18/17
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
 
Start NBR section for post-routing at 01:37:07 01/17/17
Start NBR section for post-routing at 01:08:53 01/18/17
 
End NBR router with 0 unrouted connection
 
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.prf
1,24 → 1,23
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.8.0.115.3 -- WARNING: Map write only section -- Tue Jan 17 01:36:39 2017
# map: version Diamond (64-bit) 3.8.0.115.3 -- WARNING: Map write only section -- Wed Jan 18 01:08:24 2017
 
SYSCONFIG SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE BACKGROUND_RECONFIG=OFF DONE_EX=OFF DONE_OD=ON DONE_PULL=ON MCCLK_FREQ=2.4 TRANSFR=OFF CONFIG_IOVOLTAGE=2.5 CONFIG_SECURE=OFF WAKE_UP=21 COMPRESS_CONFIG=OFF CONFIG_MODE=JTAG ;
LOCATE COMP "disp_data[0]" SITE "M20" ;
LOCATE COMP "disp_data_q[0]" SITE "M20" ;
LOCATE COMP "clk" SITE "P3" ;
LOCATE COMP "disp_sel" SITE "J1" ;
LOCATE COMP "disp_data[14]" SITE "U1" ;
LOCATE COMP "disp_data[13]" SITE "R16" ;
LOCATE COMP "disp_data[12]" SITE "P16" ;
LOCATE COMP "disp_data[11]" SITE "N17" ;
LOCATE COMP "disp_data[10]" SITE "N18" ;
LOCATE COMP "disp_data[9]" SITE "M17" ;
LOCATE COMP "disp_data[8]" SITE "N16" ;
LOCATE COMP "disp_data[7]" SITE "P17" ;
LOCATE COMP "disp_data[6]" SITE "R17" ;
LOCATE COMP "disp_data[5]" SITE "M18" ;
LOCATE COMP "disp_data[4]" SITE "L17" ;
LOCATE COMP "disp_data[3]" SITE "L16" ;
LOCATE COMP "disp_data[2]" SITE "M19" ;
LOCATE COMP "disp_data[1]" SITE "L18" ;
LOCATE COMP "disp_data_q[14]" SITE "U1" ;
LOCATE COMP "disp_data_q[13]" SITE "R16" ;
LOCATE COMP "disp_data_q[12]" SITE "P16" ;
LOCATE COMP "disp_data_q[11]" SITE "N17" ;
LOCATE COMP "disp_data_q[10]" SITE "N18" ;
LOCATE COMP "disp_data_q[9]" SITE "M17" ;
LOCATE COMP "disp_data_q[8]" SITE "N16" ;
LOCATE COMP "disp_data_q[7]" SITE "P17" ;
LOCATE COMP "disp_data_q[6]" SITE "R17" ;
LOCATE COMP "disp_data_q[5]" SITE "M18" ;
LOCATE COMP "disp_data_q[4]" SITE "L17" ;
LOCATE COMP "disp_data_q[3]" SITE "L16" ;
LOCATE COMP "disp_data_q[2]" SITE "M19" ;
LOCATE COMP "disp_data_q[1]" SITE "L18" ;
LOCATE COMP "button" SITE "T1" ;
LOCATE COMP "n_rst" SITE "K20" ;
SCHEMATIC END ;
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.srd Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.srf
3,7 → 3,7
#OS: Windows 8 6.2
#Hostname: DESKTOP-1AUKF7V
 
# Tue Jan 17 01:19:09 2017
# Wed Jan 18 01:08:13 2017
 
#Implementation: impl1
 
16,43 → 16,39
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
 
@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:28|Top entity is set to display_driver_wrapper.
File C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\ecp5um.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd changed - recompiling
VHDL syntax check successful!
 
Compiler output is up to date. No re-compile necessary
 
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":38:11:38:15|Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":53:11:53:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd":12:7:12:25|Synthesizing work.distromasciidecoder.structure.
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd changed - recompiling
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:28|Synthesizing work.display_driver_wrapper.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":17:7:17:30|Synthesizing work.display_driver_w_decoder.display_driver_w_decoder_arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":42:11:42:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":15:7:15:19|Synthesizing work.ascii_decoder.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\decoder_table_dist_rom_impl\decoder_table_dist_rom\decoder_table_dist_rom.vhd":12:7:12:28|Synthesizing work.decoder_table_dist_rom.structure.
@N: CD630 :"C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd":801:10:801:18|Synthesizing work.rom128x1a.syn_black_box.
Post processing for work.rom128x1a.syn_black_box
Post processing for work.distromasciidecoder.structure
Post processing for work.asciidecoder.arch
Post processing for work.displaydriverwdecoder_top.arch
Post processing for work.displaydriverwrapper.arch
@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_5. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_fifo_5(3 downto 0). Make sure that there are no unused intermediate registers.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":29:8:29:12|Input wr_en is unused.
Post processing for work.decoder_table_dist_rom.structure
Post processing for work.ascii_decoder.arch
Post processing for work.display_driver_w_decoder.display_driver_w_decoder_arch
Post processing for work.display_driver_wrapper.arch
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":23:8:23:12|Input wr_en is unused.
 
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:19:09 2017
# Wed Jan 18 01:08:13 2017
 
###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
@N|Running in 64-bit mode
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling
 
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
59,7 → 55,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:19:09 2017
# Wed Jan 18 01:08:13 2017
 
###########################################################]
@END
69,7 → 65,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:19:09 2017
# Wed Jan 18 01:08:13 2017
 
###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
81,7 → 77,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:19:11 2017
# Wed Jan 18 01:08:14 2017
 
###########################################################]
Pre-mapping Report
112,7 → 108,7
ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed: 0
syn_allowed_resources : blockrams=108 set on top level netlist DisplayDriverWrapper
syn_allowed_resources : blockrams=108 set on top level netlist display_driver_wrapper
 
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
121,13 → 117,14
Clock Summary
*****************
 
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
--------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button 918.9 MHz 1.088 inferred Autoconstr_clkgroup_0 8
========================================================================================================
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
-------------------------------------------------------------------------------------------------------------------------------------------------------------
display_driver_wrapper|bttn_state_derived_clock 1.0 MHz 1000.000 derived (from display_driver_wrapper|clk) Autoconstr_clkgroup_0 8
display_driver_wrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 5
=============================================================================================================================================================
 
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found inferred clock DisplayDriverWrapper|button which controls 8 sequential elements including symbol_scan_cntr[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":52:8:52:9|Found inferred clock display_driver_wrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
 
Finished Pre Mapping Phase.
 
143,7 → 140,7
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 17 01:19:11 2017
# Wed Jan 18 01:08:15 2017
 
###########################################################]
Map & Optimize Report
180,7 → 177,7
 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":74:8:74:9|Found counter in view:work.display_driver_wrapper(arch) inst symbol_scan_cntr[7:0]
 
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
197,7 → 194,7
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
 
 
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
210,17 → 207,14
 
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -0.70ns 1 / 8
2 0h:00m:00s -0.70ns 1 / 8
@N: FX271 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Replicating instance symbol_scan_cntr[0] (in view: work.DisplayDriverWrapper(arch)) with 15 loads 1 time to improve timing.
Timing driven replication report
Added 1 Registers via timing driven replication
Added 0 LUTs via timing driven replication
1 0h:00m:00s -0.76ns 6 / 13
2 0h:00m:00s -0.76ns 6 / 13
 
3 0h:00m:00s -0.64ns 1 / 9
3 0h:00m:00s -0.62ns 7 / 13
 
4 0h:00m:00s -0.64ns 1 / 9
 
4 0h:00m:00s -0.58ns 6 / 13
 
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
227,6 → 221,7
 
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
 
@N: MT611 :|Automatically generated clock display_driver_wrapper|bttn_state_derived_clock is not used and is being removed
 
 
@S |Clock Optimization Summary
234,15 → 229,15
 
#### START OF CLOCK OPTIMIZATION REPORT #####[
 
1 non-gated/non-generated clock tree(s) driving 9 clock pin(s) of sequential element(s)
1 non-gated/non-generated clock tree(s) driving 13 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
8 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
============================= Non-Gated/Non-Generated Clocks ==============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
-------------------------------------------------------------------------------------------
@K:CKID0001 button port 9 symbol_scan_cntr[0]
===========================================================================================
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
@K:CKID0001 clk port 13 bttn_state
=======================================================================================
 
 
##### END OF CLOCK OPTIMIZATION REPORT ######]
252,7 → 247,7
 
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm
 
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 139MB peak: 141MB)
 
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi
259,21 → 254,21
L-2016.03L-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
 
 
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
 
@W: MT420 |Found inferred clock DisplayDriverWrapper|button with period 2.25ns. Please declare a user-defined clock on object "p:button"
@W: MT420 |Found inferred clock display_driver_wrapper|clk with period 2.30ns. Please declare a user-defined clock on object "p:clk"
 
 
##### START OF TIMING REPORT #####[
# Timing Report written on Tue Jan 17 01:19:13 2017
# Timing Report written on Wed Jan 18 01:08:17 2017
#
 
 
Top view: DisplayDriverWrapper
Requested Frequency: 443.5 MHz
Top view: display_driver_wrapper
Requested Frequency: 433.9 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
287,13 → 282,13
*******************
 
 
Worst slack in design: -0.398
Worst slack in design: -0.407
 
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
-------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button 443.5 MHz 377.0 MHz 2.255 2.652 -0.398 inferred Autoconstr_clkgroup_0
=====================================================================================================================================
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
------------------------------------------------------------------------------------------------------------------------------------
display_driver_wrapper|clk 433.9 MHz 368.8 MHz 2.305 2.712 -0.407 inferred Autoconstr_clkgroup_0
====================================================================================================================================
 
 
 
302,12 → 297,12
Clock Relationships
*******************
 
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-------------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-------------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button DisplayDriverWrapper|button | 2.255 -0.398 | No paths - | No paths - | No paths -
=================================================================================================================================================
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-----------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-----------------------------------------------------------------------------------------------------------------------------------------------
display_driver_wrapper|clk display_driver_wrapper|clk | 2.305 -0.407 | No paths - | No paths - | No paths -
===============================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
321,7 → 316,7
 
 
====================================
Detailed Report for Clock: DisplayDriverWrapper|button
Detailed Report for Clock: display_driver_wrapper|clk
====================================
 
 
329,38 → 324,41
Starting Points with Worst Slack
********************************
 
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[1] 0.933 -0.398
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[2] 0.933 -0.398
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[3] 0.933 -0.339
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[4] 0.933 -0.339
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[5] 0.933 -0.280
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[6] 0.933 -0.280
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr_fast[0] 0.753 -0.277
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[7] 0.798 0.570
================================================================================================================================
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[0] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[0] 0.933 -0.407
symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[1] 0.933 -0.348
symbol_scan_cntr[2] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[2] 0.933 -0.348
symbol_scan_cntr[3] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[3] 0.933 -0.289
symbol_scan_cntr[4] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[4] 0.933 -0.289
symbol_scan_cntr[5] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[5] 0.933 -0.230
symbol_scan_cntr[6] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[6] 0.933 -0.230
bttn_state_fifo[3] display_driver_wrapper|clk FD1S3JX Q bttn_state_fifo[3] 0.798 0.123
bttn_state display_driver_wrapper|clk FD1S3AX Q bttn_state_i 0.753 0.168
bttn_state_fifo[1] display_driver_wrapper|clk FD1S3JX Q bttn_state_fifo[1] 0.838 0.606
=====================================================================================================================
 
 
Ending Points with Worst Slack
******************************
 
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[7] 2.044 -0.398
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[5] 2.044 -0.339
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[6] 2.044 -0.339
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[3] 2.044 -0.280
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[4] 2.044 -0.280
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[1] 2.044 -0.100
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[2] 2.044 -0.100
symbol_scan_cntr[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
==============================================================================================================================
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[7] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[7] 2.094 -0.407
symbol_scan_cntr[5] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[5] 2.094 -0.348
symbol_scan_cntr[6] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[6] 2.094 -0.348
symbol_scan_cntr[3] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[3] 2.094 -0.289
symbol_scan_cntr[4] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[4] 2.094 -0.289
symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[1] 2.094 -0.230
symbol_scan_cntr[2] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[2] 2.094 -0.230
symbol_scan_cntr[0] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
symbol_scan_cntr[2] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
==================================================================================================================================
 
 
 
369,64 → 367,67
 
 
Path information for path number 1:
Requested Period: 2.255
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
= Required time: 2.094
 
- Propagation time: 2.442
- Propagation time: 2.501
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.398
= Slack (critical) : -0.407
 
Number of logic level(s): 4
Starting point: symbol_scan_cntr[1] / Q
Number of logic level(s): 5
Starting point: symbol_scan_cntr[0] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[0] Net - - - - 15
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[0] Net - - - - 1
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.894 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.894 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.501 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.501 -
===========================================================================================
 
 
Path information for path number 2:
Requested Period: 2.255
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
= Required time: 2.094
 
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.398
= Slack (non-critical) : -0.348
 
Number of logic level(s): 4
Starting point: symbol_scan_cntr[2] / Q
Starting point: symbol_scan_cntr[1] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[2] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[2] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr[1] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
438,109 → 439,118
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 3:
Requested Period: 2.255
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
= Required time: 2.094
 
- Propagation time: 2.382
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -0.339
= Slack (non-critical) : -0.348
 
Number of logic level(s): 3
Starting point: symbol_scan_cntr[3] / Q
Number of logic level(s): 4
Starting point: symbol_scan_cntr[2] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[3] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[3] Net - - - - 15
symbol_scan_cntr_cry_0[3] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr[2] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[2] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 4:
Requested Period: 2.255
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
= Required time: 2.094
 
- Propagation time: 2.382
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -0.339
= Slack (non-critical) : -0.348
 
Number of logic level(s): 3
Starting point: symbol_scan_cntr[4] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
Number of logic level(s): 4
Starting point: symbol_scan_cntr[0] / Q
Ending point: symbol_scan_cntr[5] / D
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[4] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[4] Net - - - - 15
symbol_scan_cntr_cry_0[3] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[0] Net - - - - 15
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[0] Net - - - - 1
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[5] Net - - - - 1
symbol_scan_cntr[5] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 5:
Requested Period: 2.255
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
= Required time: 2.094
 
- Propagation time: 2.382
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -0.339
= Slack (non-critical) : -0.348
 
Number of logic level(s): 3
Starting point: symbol_scan_cntr[1] / Q
Ending point: symbol_scan_cntr[5] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
Number of logic level(s): 4
Starting point: symbol_scan_cntr[0] / Q
Ending point: symbol_scan_cntr[6] / D
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[0] Net - - - - 15
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[0] Net - - - - 1
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[5] Net - - - - 1
symbol_scan_cntr[5] FD1S3DX D In 0.000 2.382 -
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_cry_0[5] CCU2C S1 Out 0.607 2.442 -
symbol_scan_cntr_s[6] Net - - - - 1
symbol_scan_cntr[6] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
559,7 → 569,7
Resource Usage Report
Part: lfe5um5g_45f-8
 
Register bits: 9 of 43848 (0%)
Register bits: 13 of 43848 (0%)
PIC Latch: 0
I/O cells: 18
 
566,11 → 576,15
 
Details:
CCU2C: 5
FD1S3DX: 9
FD1P3DX: 8
FD1S3AX: 1
FD1S3JX: 3
GSR: 1
IB: 2
INV: 1
OB: 16
IB: 3
IFS1P3JX: 1
INV: 2
OB: 15
ORCALUT4: 4
PUR: 1
ROM128X1A: 14
VHI: 1
580,6 → 594,6
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 17 01:19:13 2017
# Wed Jan 18 01:08:17 2017
 
###########################################################]
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.srm Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.srr
3,7 → 3,7
#OS: Windows 8 6.2
#Hostname: DESKTOP-1AUKF7V
 
# Tue Jan 17 01:19:09 2017
# Wed Jan 18 01:08:13 2017
 
#Implementation: impl1
 
16,43 → 16,39
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
 
@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:28|Top entity is set to display_driver_wrapper.
File C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\ecp5um.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd changed - recompiling
VHDL syntax check successful!
 
Compiler output is up to date. No re-compile necessary
 
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":38:11:38:15|Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":53:11:53:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd":12:7:12:25|Synthesizing work.distromasciidecoder.structure.
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd changed - recompiling
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:28|Synthesizing work.display_driver_wrapper.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":17:7:17:30|Synthesizing work.display_driver_w_decoder.display_driver_w_decoder_arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":42:11:42:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":15:7:15:19|Synthesizing work.ascii_decoder.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\decoder_table_dist_rom_impl\decoder_table_dist_rom\decoder_table_dist_rom.vhd":12:7:12:28|Synthesizing work.decoder_table_dist_rom.structure.
@N: CD630 :"C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd":801:10:801:18|Synthesizing work.rom128x1a.syn_black_box.
Post processing for work.rom128x1a.syn_black_box
Post processing for work.distromasciidecoder.structure
Post processing for work.asciidecoder.arch
Post processing for work.displaydriverwdecoder_top.arch
Post processing for work.displaydriverwrapper.arch
@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_5. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_fifo_5(3 downto 0). Make sure that there are no unused intermediate registers.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":29:8:29:12|Input wr_en is unused.
Post processing for work.decoder_table_dist_rom.structure
Post processing for work.ascii_decoder.arch
Post processing for work.display_driver_w_decoder.display_driver_w_decoder_arch
Post processing for work.display_driver_wrapper.arch
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":23:8:23:12|Input wr_en is unused.
 
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:19:09 2017
# Wed Jan 18 01:08:13 2017
 
###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
@N|Running in 64-bit mode
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling
 
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
59,7 → 55,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:19:09 2017
# Wed Jan 18 01:08:13 2017
 
###########################################################]
@END
69,7 → 65,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:19:09 2017
# Wed Jan 18 01:08:13 2017
 
###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
81,7 → 77,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:19:11 2017
# Wed Jan 18 01:08:14 2017
 
###########################################################]
Pre-mapping Report
112,7 → 108,7
ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed: 0
syn_allowed_resources : blockrams=108 set on top level netlist DisplayDriverWrapper
syn_allowed_resources : blockrams=108 set on top level netlist display_driver_wrapper
 
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
121,13 → 117,14
Clock Summary
*****************
 
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
--------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button 918.9 MHz 1.088 inferred Autoconstr_clkgroup_0 8
========================================================================================================
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
-------------------------------------------------------------------------------------------------------------------------------------------------------------
display_driver_wrapper|bttn_state_derived_clock 1.0 MHz 1000.000 derived (from display_driver_wrapper|clk) Autoconstr_clkgroup_0 8
display_driver_wrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 5
=============================================================================================================================================================
 
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found inferred clock DisplayDriverWrapper|button which controls 8 sequential elements including symbol_scan_cntr[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":52:8:52:9|Found inferred clock display_driver_wrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
 
Finished Pre Mapping Phase.
 
143,7 → 140,7
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 17 01:19:11 2017
# Wed Jan 18 01:08:15 2017
 
###########################################################]
Map & Optimize Report
180,7 → 177,7
 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":74:8:74:9|Found counter in view:work.display_driver_wrapper(arch) inst symbol_scan_cntr[7:0]
 
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
197,7 → 194,7
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
 
 
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
210,17 → 207,14
 
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -0.70ns 1 / 8
2 0h:00m:00s -0.70ns 1 / 8
@N: FX271 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Replicating instance symbol_scan_cntr[0] (in view: work.DisplayDriverWrapper(arch)) with 15 loads 1 time to improve timing.
Timing driven replication report
Added 1 Registers via timing driven replication
Added 0 LUTs via timing driven replication
1 0h:00m:00s -0.76ns 6 / 13
2 0h:00m:00s -0.76ns 6 / 13
 
3 0h:00m:00s -0.64ns 1 / 9
3 0h:00m:00s -0.62ns 7 / 13
 
4 0h:00m:00s -0.64ns 1 / 9
 
4 0h:00m:00s -0.58ns 6 / 13
 
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
227,6 → 221,7
 
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
 
@N: MT611 :|Automatically generated clock display_driver_wrapper|bttn_state_derived_clock is not used and is being removed
 
 
@S |Clock Optimization Summary
234,15 → 229,15
 
#### START OF CLOCK OPTIMIZATION REPORT #####[
 
1 non-gated/non-generated clock tree(s) driving 9 clock pin(s) of sequential element(s)
1 non-gated/non-generated clock tree(s) driving 13 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
8 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
============================= Non-Gated/Non-Generated Clocks ==============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
-------------------------------------------------------------------------------------------
@K:CKID0001 button port 9 symbol_scan_cntr[0]
===========================================================================================
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
@K:CKID0001 clk port 13 bttn_state
=======================================================================================
 
 
##### END OF CLOCK OPTIMIZATION REPORT ######]
252,7 → 247,7
 
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm
 
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 139MB peak: 141MB)
 
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi
259,21 → 254,21
L-2016.03L-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
 
 
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
 
@W: MT420 |Found inferred clock DisplayDriverWrapper|button with period 2.25ns. Please declare a user-defined clock on object "p:button"
@W: MT420 |Found inferred clock display_driver_wrapper|clk with period 2.30ns. Please declare a user-defined clock on object "p:clk"
 
 
##### START OF TIMING REPORT #####[
# Timing Report written on Tue Jan 17 01:19:13 2017
# Timing Report written on Wed Jan 18 01:08:17 2017
#
 
 
Top view: DisplayDriverWrapper
Requested Frequency: 443.5 MHz
Top view: display_driver_wrapper
Requested Frequency: 433.9 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
287,13 → 282,13
*******************
 
 
Worst slack in design: -0.398
Worst slack in design: -0.407
 
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
-------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button 443.5 MHz 377.0 MHz 2.255 2.652 -0.398 inferred Autoconstr_clkgroup_0
=====================================================================================================================================
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
------------------------------------------------------------------------------------------------------------------------------------
display_driver_wrapper|clk 433.9 MHz 368.8 MHz 2.305 2.712 -0.407 inferred Autoconstr_clkgroup_0
====================================================================================================================================
 
 
 
302,12 → 297,12
Clock Relationships
*******************
 
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-------------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-------------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button DisplayDriverWrapper|button | 2.255 -0.398 | No paths - | No paths - | No paths -
=================================================================================================================================================
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-----------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-----------------------------------------------------------------------------------------------------------------------------------------------
display_driver_wrapper|clk display_driver_wrapper|clk | 2.305 -0.407 | No paths - | No paths - | No paths -
===============================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
321,7 → 316,7
 
 
====================================
Detailed Report for Clock: DisplayDriverWrapper|button
Detailed Report for Clock: display_driver_wrapper|clk
====================================
 
 
329,38 → 324,41
Starting Points with Worst Slack
********************************
 
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[1] 0.933 -0.398
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[2] 0.933 -0.398
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[3] 0.933 -0.339
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[4] 0.933 -0.339
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[5] 0.933 -0.280
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[6] 0.933 -0.280
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr_fast[0] 0.753 -0.277
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[7] 0.798 0.570
================================================================================================================================
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[0] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[0] 0.933 -0.407
symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[1] 0.933 -0.348
symbol_scan_cntr[2] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[2] 0.933 -0.348
symbol_scan_cntr[3] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[3] 0.933 -0.289
symbol_scan_cntr[4] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[4] 0.933 -0.289
symbol_scan_cntr[5] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[5] 0.933 -0.230
symbol_scan_cntr[6] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[6] 0.933 -0.230
bttn_state_fifo[3] display_driver_wrapper|clk FD1S3JX Q bttn_state_fifo[3] 0.798 0.123
bttn_state display_driver_wrapper|clk FD1S3AX Q bttn_state_i 0.753 0.168
bttn_state_fifo[1] display_driver_wrapper|clk FD1S3JX Q bttn_state_fifo[1] 0.838 0.606
=====================================================================================================================
 
 
Ending Points with Worst Slack
******************************
 
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[7] 2.044 -0.398
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[5] 2.044 -0.339
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[6] 2.044 -0.339
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[3] 2.044 -0.280
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[4] 2.044 -0.280
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[1] 2.044 -0.100
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[2] 2.044 -0.100
symbol_scan_cntr[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
==============================================================================================================================
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[7] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[7] 2.094 -0.407
symbol_scan_cntr[5] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[5] 2.094 -0.348
symbol_scan_cntr[6] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[6] 2.094 -0.348
symbol_scan_cntr[3] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[3] 2.094 -0.289
symbol_scan_cntr[4] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[4] 2.094 -0.289
symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[1] 2.094 -0.230
symbol_scan_cntr[2] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[2] 2.094 -0.230
symbol_scan_cntr[0] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
symbol_scan_cntr[2] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
==================================================================================================================================
 
 
 
369,64 → 367,67
 
 
Path information for path number 1:
Requested Period: 2.255
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
= Required time: 2.094
 
- Propagation time: 2.442
- Propagation time: 2.501
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.398
= Slack (critical) : -0.407
 
Number of logic level(s): 4
Starting point: symbol_scan_cntr[1] / Q
Number of logic level(s): 5
Starting point: symbol_scan_cntr[0] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[0] Net - - - - 15
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[0] Net - - - - 1
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.894 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.894 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.501 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.501 -
===========================================================================================
 
 
Path information for path number 2:
Requested Period: 2.255
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
= Required time: 2.094
 
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.398
= Slack (non-critical) : -0.348
 
Number of logic level(s): 4
Starting point: symbol_scan_cntr[2] / Q
Starting point: symbol_scan_cntr[1] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[2] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[2] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr[1] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
438,109 → 439,118
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 3:
Requested Period: 2.255
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
= Required time: 2.094
 
- Propagation time: 2.382
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -0.339
= Slack (non-critical) : -0.348
 
Number of logic level(s): 3
Starting point: symbol_scan_cntr[3] / Q
Number of logic level(s): 4
Starting point: symbol_scan_cntr[2] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[3] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[3] Net - - - - 15
symbol_scan_cntr_cry_0[3] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr[2] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[2] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 4:
Requested Period: 2.255
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
= Required time: 2.094
 
- Propagation time: 2.382
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -0.339
= Slack (non-critical) : -0.348
 
Number of logic level(s): 3
Starting point: symbol_scan_cntr[4] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
Number of logic level(s): 4
Starting point: symbol_scan_cntr[0] / Q
Ending point: symbol_scan_cntr[5] / D
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[4] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[4] Net - - - - 15
symbol_scan_cntr_cry_0[3] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[0] Net - - - - 15
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[0] Net - - - - 1
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[5] Net - - - - 1
symbol_scan_cntr[5] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 5:
Requested Period: 2.255
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
= Required time: 2.094
 
- Propagation time: 2.382
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -0.339
= Slack (non-critical) : -0.348
 
Number of logic level(s): 3
Starting point: symbol_scan_cntr[1] / Q
Ending point: symbol_scan_cntr[5] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
Number of logic level(s): 4
Starting point: symbol_scan_cntr[0] / Q
Ending point: symbol_scan_cntr[6] / D
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[0] Net - - - - 15
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[0] Net - - - - 1
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[5] Net - - - - 1
symbol_scan_cntr[5] FD1S3DX D In 0.000 2.382 -
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_cry_0[5] CCU2C S1 Out 0.607 2.442 -
symbol_scan_cntr_s[6] Net - - - - 1
symbol_scan_cntr[6] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
559,7 → 569,7
Resource Usage Report
Part: lfe5um5g_45f-8
 
Register bits: 9 of 43848 (0%)
Register bits: 13 of 43848 (0%)
PIC Latch: 0
I/O cells: 18
 
566,11 → 576,15
 
Details:
CCU2C: 5
FD1S3DX: 9
FD1P3DX: 8
FD1S3AX: 1
FD1S3JX: 3
GSR: 1
IB: 2
INV: 1
OB: 16
IB: 3
IFS1P3JX: 1
INV: 2
OB: 15
ORCALUT4: 4
PUR: 1
ROM128X1A: 14
VHI: 1
580,6 → 594,6
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 17 01:19:13 2017
# Wed Jan 18 01:08:17 2017
 
###########################################################]
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.srs Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.tw1
1,6 → 1,6
 
Loading design for application trce from file displaydriverwdecoder_impl1_map.ncd.
Design name: DisplayDriverWrapper
Design name: display_driver_wrapper
NCD version: 3.3
Vendor: LATTICE
Device: LFE5UM5G-45F
13,7 → 13,7
 
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.8.0.115.3
Tue Jan 17 01:36:41 2017
Wed Jan 18 01:08:27 2017
 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
117,7 → 117,7
 
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.8.0.115.3
Tue Jan 17 01:36:42 2017
Wed Jan 18 01:08:28 2017
 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_bgn.html
100,7 → 100,7
Command: bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g DisableUES:FALSE -g ES:No -e -s C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.sec -k C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.bek -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml DisplayDriverwDecoder_impl1.ncd DisplayDriverwDecoder_impl1.prf
 
Loading design for application Bitgen from file DisplayDriverwDecoder_impl1.ncd.
Design name: DisplayDriverWrapper
Design name: display_driver_wrapper
NCD version: 3.3
Vendor: LATTICE
Device: LFE5UM5G-45F
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_cck.rpt
1,12 → 1,12
# Synopsys Constraint Checker, version maplat, Build 1498R, built Jul 5 2016
# Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
 
# Written on Tue Jan 17 01:19:11 2017
# Written on Wed Jan 18 01:08:15 2017
 
 
##### DESIGN INFO #######################################################
 
Top View: "DisplayDriverWrapper"
Top View: "display_driver_wrapper"
Constraint File(s): (none)
 
 
24,10 → 24,11
Clock Relationships
*******************
 
Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button DisplayDriverWrapper|button | 1.088 | No paths | No paths | No paths
===========================================================================================================================================================================
Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
display_driver_wrapper|clk display_driver_wrapper|clk | 1000.000 | No paths | No paths | No paths
display_driver_wrapper|bttn_state_derived_clock display_driver_wrapper|bttn_state_derived_clock | 1000.000 | No paths | No paths | No paths
===================================================================================================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
35,24 → 36,23
Unconstrained Start/End Points
******************************
 
p:clk
p:disp_data[0]
p:disp_data[1]
p:disp_data[2]
p:disp_data[3]
p:disp_data[4]
p:disp_data[5]
p:disp_data[6]
p:disp_data[7]
p:disp_data[8]
p:disp_data[9]
p:disp_data[10]
p:disp_data[11]
p:disp_data[12]
p:disp_data[13]
p:disp_data[14]
p:disp_sel
p:rst
p:button
p:disp_data_q[0]
p:disp_data_q[1]
p:disp_data_q[2]
p:disp_data_q[3]
p:disp_data_q[4]
p:disp_data_q[5]
p:disp_data_q[6]
p:disp_data_q[7]
p:disp_data_q[8]
p:disp_data_q[9]
p:disp_data_q[10]
p:disp_data_q[11]
p:disp_data_q[12]
p:disp_data_q[13]
p:disp_data_q[14]
p:n_rst
 
 
Inapplicable constraints
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_map.asd
8,9 → 8,9
FF_used = 13;
INPUT_LVCMOS25 = 2;
INPUT_LVDS = 1;
OUTPUT_LVCMOS25 = 16;
OUTPUT_LVCMOS25 = 15;
IO_avail = 203;
IO_used = 20;
IO_used = 19;
EBR_avail = 108;
EBR_used = 0;
;
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_map.cam
2,7 → 2,6
n_rst_c_i n_rst_c
[ END MERGED ]
[ START CLIPPED ]
GND
VCC
symbol_scan_cntr_cry_0_S0[0]
N_1
11,26 → 10,25
[ END CLIPPED ]
[ START DESIGN PREFS ]
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.8.0.115.3 -- WARNING: Map write only section -- Tue Jan 17 01:36:39 2017
# map: version Diamond (64-bit) 3.8.0.115.3 -- WARNING: Map write only section -- Wed Jan 18 01:08:24 2017
 
SYSCONFIG SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE BACKGROUND_RECONFIG=OFF DONE_EX=OFF DONE_OD=ON DONE_PULL=ON MCCLK_FREQ=2.4 TRANSFR=OFF CONFIG_IOVOLTAGE=2.5 CONFIG_SECURE=OFF WAKE_UP=21 COMPRESS_CONFIG=OFF CONFIG_MODE=JTAG ;
LOCATE COMP "disp_data[0]" SITE "M20" ;
LOCATE COMP "disp_data_q[0]" SITE "M20" ;
LOCATE COMP "clk" SITE "P3" ;
LOCATE COMP "disp_sel" SITE "J1" ;
LOCATE COMP "disp_data[14]" SITE "U1" ;
LOCATE COMP "disp_data[13]" SITE "R16" ;
LOCATE COMP "disp_data[12]" SITE "P16" ;
LOCATE COMP "disp_data[11]" SITE "N17" ;
LOCATE COMP "disp_data[10]" SITE "N18" ;
LOCATE COMP "disp_data[9]" SITE "M17" ;
LOCATE COMP "disp_data[8]" SITE "N16" ;
LOCATE COMP "disp_data[7]" SITE "P17" ;
LOCATE COMP "disp_data[6]" SITE "R17" ;
LOCATE COMP "disp_data[5]" SITE "M18" ;
LOCATE COMP "disp_data[4]" SITE "L17" ;
LOCATE COMP "disp_data[3]" SITE "L16" ;
LOCATE COMP "disp_data[2]" SITE "M19" ;
LOCATE COMP "disp_data[1]" SITE "L18" ;
LOCATE COMP "disp_data_q[14]" SITE "U1" ;
LOCATE COMP "disp_data_q[13]" SITE "R16" ;
LOCATE COMP "disp_data_q[12]" SITE "P16" ;
LOCATE COMP "disp_data_q[11]" SITE "N17" ;
LOCATE COMP "disp_data_q[10]" SITE "N18" ;
LOCATE COMP "disp_data_q[9]" SITE "M17" ;
LOCATE COMP "disp_data_q[8]" SITE "N16" ;
LOCATE COMP "disp_data_q[7]" SITE "P17" ;
LOCATE COMP "disp_data_q[6]" SITE "R17" ;
LOCATE COMP "disp_data_q[5]" SITE "M18" ;
LOCATE COMP "disp_data_q[4]" SITE "L17" ;
LOCATE COMP "disp_data_q[3]" SITE "L16" ;
LOCATE COMP "disp_data_q[2]" SITE "M19" ;
LOCATE COMP "disp_data_q[1]" SITE "L18" ;
LOCATE COMP "button" SITE "T1" ;
LOCATE COMP "n_rst" SITE "K20" ;
SCHEMATIC END ;
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_map.hrr
1,6 → 1,6
---------------------------------------------------
Report for cell DisplayDriverWrapper
Instance path: DisplayDriverWrapper
Report for cell display_driver_wrapper
Instance path: display_driver_wrapper
Cell usage:
cell count Res Usage(%)
SLIC 65.00 100.0
7,15 → 7,15
IOLGC 1.00 100.0
LUT4 117.00 100.0
IOREG 1 100.0
IOBUF 19 100.0
IOBUF 18 100.0
PFUREG 12 100.0
RIPPLE 5 100.0
SUB MODULES
cell count SLC Usage(%)
DisplayDriverwDecoder_Top 1 86.2
display_driver_w_decoder 1 86.2
---------------------------------------------------
Report for cell DisplayDriverwDecoder_Top
Instance path: DisplayDriverWrapper/DDwD_Top
Report for cell display_driver_w_decoder
Instance path: display_driver_wrapper/display_driver_with_decoder
Cell usage:
cell count Res Usage(%)
SLIC 56.00 86.2
22,10 → 22,10
LUT4 112.00 95.7
SUB MODULES
cell count SLC Usage(%)
ASCIIDecoder 1 86.2
ascii_decoder 1 86.2
---------------------------------------------------
Report for cell ASCIIDecoder
Instance path: DisplayDriverWrapper/DDwD_Top/ascii_decoder_module
Report for cell ascii_decoder
Instance path: display_driver_wrapper/display_driver_with_decoder/ascii_decoder_module
Cell usage:
cell count Res Usage(%)
SLIC 56.00 86.2
32,10 → 32,10
LUT4 112.00 95.7
SUB MODULES
cell count SLC Usage(%)
DistRomAsciiDecoder 1 86.2
decoder_table_dist_rom 1 86.2
---------------------------------------------------
Report for cell DistRomAsciiDecoder
Instance path: DisplayDriverWrapper/DDwD_Top/ascii_decoder_module/rom_decoding_table
Report for cell decoder_table_dist_rom
Instance path: display_driver_wrapper/display_driver_with_decoder/ascii_decoder_module/rom_decoding_table
Cell usage:
cell count Res Usage(%)
SLIC 56.00 86.2
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_map.ncd Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_mrp.html
91,7 → 91,7
</STYLE>
</HEAD>
<PRE><A name="Mrp"></A>
Lattice Mapping Report File for Design Module 'DisplayDriverWrapper'
Lattice Mapping Report File for Design Module 'display_driver_wrapper'
 
 
 
109,7 → 109,7
Target Device: LFE5UM5G-45FCABGA381
Target Performance: 8
Mapper: sa5p00g, version: Diamond (64-bit) 3.8.0.115.3
Mapped on: 01/17/17 01:36:37
Mapped on: 01/18/17 01:08:21
 
 
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
125,8 → 125,8
Number used as distributed RAM: 0
Number used as ripple logic: 10
Number used as shift registers: 0
Number of PIO sites used: 20 out of 203 (10%)
Number of PIO sites used for single ended IOs: 18
Number of PIO sites used: 19 out of 203 (9%)
Number of PIO sites used for single ended IOs: 17
Number of PIO sites used for differential IOs: 2 (represented by 1 PIO
comps in NCD)
Number of block RAMs: 0 out of 108 (0%)
200,7 → 200,7
<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
 
WARNING - map: C:/Projects/single-14-segment-display-driver-w-decoder/Project/La
ttice_FPGA_Build/DisplayDriverwDecoder.lpf(21): Semantic error in "USERCODE
ttice_FPGA_Build/DisplayDriverwDecoder.lpf(29): Semantic error in "USERCODE
ASCII "G.L." ; ": Invalid Ascii char <.>.Invalid Ascii char <.>.. This
preference has been disabled.
WARNING - map: Preference parsing results: 1 semantic error detected.
219,40 → 219,38
| IO Name | Direction | Levelmode | IO |
| | | IO_TYPE | Register |
+---------------------+-----------+-----------+------------+
| disp_data[0] | OUTPUT | LVCMOS25 | |
| disp_data_q[0] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| clk | INPUT | LVDS | |
+---------------------+-----------+-----------+------------+
| disp_sel | OUTPUT | LVCMOS25 | |
| disp_data_q[14] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[14] | OUTPUT | LVCMOS25 | |
| disp_data_q[13] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[13] | OUTPUT | LVCMOS25 | |
| disp_data_q[12] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[12] | OUTPUT | LVCMOS25 | |
| disp_data_q[11] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[11] | OUTPUT | LVCMOS25 | |
| disp_data_q[10] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[10] | OUTPUT | LVCMOS25 | |
| disp_data_q[9] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[9] | OUTPUT | LVCMOS25 | |
| disp_data_q[8] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[8] | OUTPUT | LVCMOS25 | |
| disp_data_q[7] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[7] | OUTPUT | LVCMOS25 | |
| disp_data_q[6] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[6] | OUTPUT | LVCMOS25 | |
| disp_data_q[5] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[5] | OUTPUT | LVCMOS25 | |
| disp_data_q[4] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[4] | OUTPUT | LVCMOS25 | |
| disp_data_q[3] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[3] | OUTPUT | LVCMOS25 | |
| disp_data_q[2] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[2] | OUTPUT | LVCMOS25 | |
| disp_data_q[1] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data[1] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| button | INPUT | LVCMOS25 | IN |
+---------------------+-----------+-----------+------------+
| n_rst | INPUT | LVCMOS25 | |
262,8 → 260,8
 
<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
 
Block GND undriven or does not drive anything - clipped.
Signal n_rst_c_i was merged into signal n_rst_c
Signal GND undriven or does not drive anything - clipped.
Signal VCC undriven or does not drive anything - clipped.
Signal symbol_scan_cntr_cry_0_S0[0] undriven or does not drive anything -
clipped.
271,10 → 269,9
Signal symbol_scan_cntr_s_0_S1[7] undriven or does not drive anything - clipped.
Signal symbol_scan_cntr_s_0_COUT[7] undriven or does not drive anything -
 
clipped.
Block n_rst_pad_RNIQVTF was optimized away.
Block GND was optimized away.
 
Block VCC was optimized away.
 
 
322,7 → 319,7
-------------------------
 
Total CPU Time: 1 secs
Total REAL Time: 2 secs
Total REAL Time: 3 secs
Peak Memory Usage: 152 MB
 
336,6 → 333,9
 
 
 
 
 
 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_pad.html
98,32 → 98,31
PACKAGE: CABGA381
Package Status: Final Version 1.36
 
Tue Jan 17 01:36:59 2017
Wed Jan 18 01:08:45 2017
 
Pinout by Port Name:
+---------------+----------+--------------+-------+-----------+---------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | BC Enable | Properties |
+---------------+----------+--------------+-------+-----------+---------------------------------+
| button | T1/8 | LVCMOS25_IN | PB4B | | PULL:UP CLAMP:ON HYSTERESIS:ON |
| clk | P3/6 | LVDS_IN | PL68C | | CLAMP:ON |
| disp_data[0] | M20/3 | LVCMOS25_OUT | PR35B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[10] | N18/3 | LVCMOS25_OUT | PR41C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[11] | N17/3 | LVCMOS25_OUT | PR44A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[12] | P16/3 | LVCMOS25_OUT | PR44B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[13] | R16/3 | LVCMOS25_OUT | PR44C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[14] | U1/8 | LVCMOS25_OUT | PB6A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[1] | L18/3 | LVCMOS25_OUT | PR38C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[2] | M19/3 | LVCMOS25_OUT | PR35D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[3] | L16/3 | LVCMOS25_OUT | PR38A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[4] | L17/3 | LVCMOS25_OUT | PR38B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[5] | M18/3 | LVCMOS25_OUT | PR38D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[6] | R17/3 | LVCMOS25_OUT | PR44D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[7] | P17/3 | LVCMOS25_OUT | PR41D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[8] | N16/3 | LVCMOS25_OUT | PR41A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data[9] | M17/3 | LVCMOS25_OUT | PR41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_sel | J1/6 | LVCMOS25_OUT | PL41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| n_rst | K20/2 | LVCMOS25_IN | PR32D | | PULL:UP CLAMP:ON HYSTERESIS:ON |
+---------------+----------+--------------+-------+-----------+---------------------------------+
+-----------------+----------+--------------+-------+-----------+---------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | BC Enable | Properties |
+-----------------+----------+--------------+-------+-----------+---------------------------------+
| button | T1/8 | LVCMOS25_IN | PB4B | | PULL:UP CLAMP:ON HYSTERESIS:ON |
| clk | P3/6 | LVDS_IN | PL68C | | CLAMP:ON |
| disp_data_q[0] | M20/3 | LVCMOS25_OUT | PR35B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[10] | N18/3 | LVCMOS25_OUT | PR41C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[11] | N17/3 | LVCMOS25_OUT | PR44A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[12] | P16/3 | LVCMOS25_OUT | PR44B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[13] | R16/3 | LVCMOS25_OUT | PR44C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[14] | U1/8 | LVCMOS25_OUT | PB6A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[1] | L18/3 | LVCMOS25_OUT | PR38C | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[2] | M19/3 | LVCMOS25_OUT | PR35D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[3] | L16/3 | LVCMOS25_OUT | PR38A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[4] | L17/3 | LVCMOS25_OUT | PR38B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[5] | M18/3 | LVCMOS25_OUT | PR38D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[6] | R17/3 | LVCMOS25_OUT | PR44D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[7] | P17/3 | LVCMOS25_OUT | PR41D | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[8] | N16/3 | LVCMOS25_OUT | PR41A | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| disp_data_q[9] | M17/3 | LVCMOS25_OUT | PR41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW |
| n_rst | K20/2 | LVCMOS25_IN | PR32D | | PULL:UP CLAMP:ON HYSTERESIS:ON |
+-----------------+----------+--------------+-------+-----------+---------------------------------+
 
Vccio by Bank:
+------+-------+
131,7 → 130,7
+------+-------+
| 2 | 2.5V |
| 3 | 2.5V |
| 6 | 2.5V |
| 6 | 1.2V |
| 8 | 2.5V |
+------+-------+
 
268,7 → 267,7
| H17/2 | unused, PULL:DOWN | | | PR20B | RDQ17 | |
| H18/2 | unused, PULL:DOWN | | | PR20A | RDQ17 | |
| H20/2 | unused, PULL:DOWN | | | PR29B | RDQSN29 | |
| J1/6 | disp_sel | LOCATED | LVCMOS25_OUT | PL41B | LDQSN41 | |
| J1/6 | unused, PULL:DOWN | | | PL41B | LDQSN41 | |
| J3/6 | unused, PULL:DOWN | | | PL38C | GR_PCLK6_1/LDQ41 | |
| J4/6 | unused, PULL:DOWN | | | PL38A | GR_PCLK6_0/LDQ41 | |
| J5/6 | unused, PULL:DOWN | | | PL38B | LDQ41 | |
290,9 → 289,9
| L3/6 | unused, PULL:DOWN | | | PL62C | LDQ65 | |
| L4/6 | unused, PULL:DOWN | | | PL44C | LDQ41 | |
| L5/6 | unused, PULL:DOWN | | | PL44D | LDQ41 | |
| L16/3 | disp_data[3] | LOCATED | LVCMOS25_OUT | PR38A | GR_PCLK3_0/RDQ41 | |
| L17/3 | disp_data[4] | LOCATED | LVCMOS25_OUT | PR38B | RDQ41 | |
| L18/3 | disp_data[1] | LOCATED | LVCMOS25_OUT | PR38C | GR_PCLK3_1/RDQ41 | |
| L16/3 | disp_data_q[3] | LOCATED | LVCMOS25_OUT | PR38A | GR_PCLK3_0/RDQ41 | |
| L17/3 | disp_data_q[4] | LOCATED | LVCMOS25_OUT | PR38B | RDQ41 | |
| L18/3 | disp_data_q[1] | LOCATED | LVCMOS25_OUT | PR38C | GR_PCLK3_1/RDQ41 | |
| L19/3 | unused, PULL:DOWN | | | PR35C | PCLKT3_0/RDQ41 | |
| L20/3 | unused, PULL:DOWN | | | PR35A | PCLKT3_1/RDQ41 | |
| M1/6 | unused, PULL:DOWN | | | PL65B | LDQSN65 | |
299,18 → 298,18
| M3/6 | unused, PULL:DOWN | | | PL62B | LDQ65 | |
| M4/6 | unused, PULL:DOWN | | | PL59A | LDQ65 | |
| M5/6 | unused, PULL:DOWN | | | PL53A | LDQS53 | |
| M17/3 | disp_data[9] | LOCATED | LVCMOS25_OUT | PR41B | RDQSN41 | |
| M18/3 | disp_data[5] | LOCATED | LVCMOS25_OUT | PR38D | RDQ41 | |
| M19/3 | disp_data[2] | LOCATED | LVCMOS25_OUT | PR35D | PCLKC3_0/RDQ41 | |
| M20/3 | disp_data[0] | LOCATED | LVCMOS25_OUT | PR35B | PCLKC3_1/RDQ41 | |
| M17/3 | disp_data_q[9] | LOCATED | LVCMOS25_OUT | PR41B | RDQSN41 | |
| M18/3 | disp_data_q[5] | LOCATED | LVCMOS25_OUT | PR38D | RDQ41 | |
| M19/3 | disp_data_q[2] | LOCATED | LVCMOS25_OUT | PR35D | PCLKC3_0/RDQ41 | |
| M20/3 | disp_data_q[0] | LOCATED | LVCMOS25_OUT | PR35B | PCLKC3_1/RDQ41 | |
| N1/6 | unused, PULL:DOWN | | | PL65D | LDQ65 | |
| N2/6 | unused, PULL:DOWN | | | PL65A | LDQS65 | |
| N3/6 | unused, PULL:DOWN | | | PL62A | LDQ65 | |
| N4/6 | unused, PULL:DOWN | | | PL59C | LDQ65 | |
| N5/6 | unused, PULL:DOWN | | | PL59B | LDQ65 | |
| N16/3 | disp_data[8] | LOCATED | LVCMOS25_OUT | PR41A | RDQS41 | |
| N17/3 | disp_data[11] | LOCATED | LVCMOS25_OUT | PR44A | RDQ41 | |
| N18/3 | disp_data[10] | LOCATED | LVCMOS25_OUT | PR41C | RDQ41 | |
| N16/3 | disp_data_q[8] | LOCATED | LVCMOS25_OUT | PR41A | RDQS41 | |
| N17/3 | disp_data_q[11] | LOCATED | LVCMOS25_OUT | PR44A | RDQ41 | |
| N18/3 | disp_data_q[10] | LOCATED | LVCMOS25_OUT | PR41C | RDQ41 | |
| N19/3 | unused, PULL:DOWN | | | PR59A | RDQ65 | |
| N20/3 | unused, PULL:DOWN | | | PR59B | RDQ65 | |
| P1/6 | unused, PULL:DOWN | | | PL68A | LDQ65 | |
318,8 → 317,8
| P3/6 | clk+ | LOCATED | LVDS_IN | PL68C | LLC_GPLL0T_IN/LDQ65 | |
| P4/6 | clk- | | LVDS_IN | PL68D | LLC_GPLL0C_IN/LDQ65 | |
| P5/6 | unused, PULL:DOWN | | | PL59D | LDQ65 | |
| P16/3 | disp_data[12] | LOCATED | LVCMOS25_OUT | PR44B | VREF1_3/RDQ41 | |
| P17/3 | disp_data[7] | LOCATED | LVCMOS25_OUT | PR41D | RDQ41 | |
| P16/3 | disp_data_q[12] | LOCATED | LVCMOS25_OUT | PR44B | VREF1_3/RDQ41 | |
| P17/3 | disp_data_q[7] | LOCATED | LVCMOS25_OUT | PR41D | RDQ41 | |
| P18/3 | unused, PULL:DOWN | | | PR59D | RDQ65 | |
| P19/3 | unused, PULL:DOWN | | | PR59C | RDQ65 | |
| P20/3 | unused, PULL:DOWN | | | PR62A | RDQ65 | |
368,8 → 367,8
| R1/8 | unused, PULL:DOWN | | | PB4A | D7/IO7 | |
| R2/8 | unused, PULL:DOWN | | | PB15A | HOLDN/DI/BUSY/CSSPIN/CEN | |
| R3/8 | unused, PULL:DOWN | | | PB15B | DOUT/CSON | |
| R16/3 | disp_data[13] | LOCATED | LVCMOS25_OUT | PR44C | RDQ41 | |
| R17/3 | disp_data[6] | LOCATED | LVCMOS25_OUT | PR44D | RDQ41 | |
| R16/3 | disp_data_q[13] | LOCATED | LVCMOS25_OUT | PR44C | RDQ41 | |
| R17/3 | disp_data_q[6] | LOCATED | LVCMOS25_OUT | PR44D | RDQ41 | |
| R18/3 | unused, PULL:DOWN | | | PR65B | RDQSN65 | |
| R20/3 | unused, PULL:DOWN | | | PR62B | RDQ65 | |
| T1/8 | button | LOCATED | LVCMOS25_IN | PB4B | D6/IO6 | |
384,7 → 383,7
| TDI/40 | | | | TDI | | |
| TDO/40 | | | | TDO | | |
| TMS/40 | | | | TMS | | |
| U1/8 | disp_data[14] | LOCATED | LVCMOS25_OUT | PB6A | D5/MISO2/IO5 | |
| U1/8 | disp_data_q[14] | LOCATED | LVCMOS25_OUT | PB6A | D5/MISO2/IO5 | |
| U2/8 | unused, PULL:DOWN | | | PB13B | CS1N | |
| U16/3 | unused, PULL:DOWN | | | PR68C | LRC_GPLL0T_IN/RDQ65 | |
| U17/3 | unused, PULL:DOWN | | | PR68B | RDQ65 | |
424,22 → 423,21
 
LOCATE COMP "button" SITE "T1";
LOCATE COMP "clk" SITE "P3";
LOCATE COMP "disp_data[0]" SITE "M20";
LOCATE COMP "disp_data[10]" SITE "N18";
LOCATE COMP "disp_data[11]" SITE "N17";
LOCATE COMP "disp_data[12]" SITE "P16";
LOCATE COMP "disp_data[13]" SITE "R16";
LOCATE COMP "disp_data[14]" SITE "U1";
LOCATE COMP "disp_data[1]" SITE "L18";
LOCATE COMP "disp_data[2]" SITE "M19";
LOCATE COMP "disp_data[3]" SITE "L16";
LOCATE COMP "disp_data[4]" SITE "L17";
LOCATE COMP "disp_data[5]" SITE "M18";
LOCATE COMP "disp_data[6]" SITE "R17";
LOCATE COMP "disp_data[7]" SITE "P17";
LOCATE COMP "disp_data[8]" SITE "N16";
LOCATE COMP "disp_data[9]" SITE "M17";
LOCATE COMP "disp_sel" SITE "J1";
LOCATE COMP "disp_data_q[0]" SITE "M20";
LOCATE COMP "disp_data_q[10]" SITE "N18";
LOCATE COMP "disp_data_q[11]" SITE "N17";
LOCATE COMP "disp_data_q[12]" SITE "P16";
LOCATE COMP "disp_data_q[13]" SITE "R16";
LOCATE COMP "disp_data_q[14]" SITE "U1";
LOCATE COMP "disp_data_q[1]" SITE "L18";
LOCATE COMP "disp_data_q[2]" SITE "M19";
LOCATE COMP "disp_data_q[3]" SITE "L16";
LOCATE COMP "disp_data_q[4]" SITE "L17";
LOCATE COMP "disp_data_q[5]" SITE "M18";
LOCATE COMP "disp_data_q[6]" SITE "R17";
LOCATE COMP "disp_data_q[7]" SITE "P17";
LOCATE COMP "disp_data_q[8]" SITE "N16";
LOCATE COMP "disp_data_q[9]" SITE "M17";
LOCATE COMP "n_rst" SITE "K20";
 
 
452,7 → 450,7
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
Tue Jan 17 01:36:59 2017
Wed Jan 18 01:08:45 2017
 
 
 
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_par.html
96,7 → 96,7
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
Tue Jan 17 01:36:43 2017
Wed Jan 18 01:08:29 2017
 
C:/lscc/diamond/3.8_x64/ispfpga\bin\nt64\par -f DisplayDriverwDecoder_impl1.p2t
DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir
110,17 → 110,17
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 -1.238 7103 0.178 0 26 Complete
5_1 * 0 -1.238 7103 0.178 0 25 Complete
 
 
* : Design saved.
 
Total (real) run time for 1-seed: 26 secs
Total (real) run time for 1-seed: 25 secs
 
par done!
 
Lattice Place and Route Report for Design &quot;DisplayDriverwDecoder_impl1_map.ncd&quot;
Tue Jan 17 01:36:43 2017
Wed Jan 18 01:08:29 2017
 
 
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
131,7 → 131,7
Routing Iterations: 6
 
Loading design for application par from file DisplayDriverwDecoder_impl1_map.ncd.
Design name: DisplayDriverWrapper
Design name: display_driver_wrapper
NCD version: 3.3
Vendor: LATTICE
Device: LFE5UM5G-45F
147,8 → 147,8
 
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
 
PIO (prelim) 20/245 8% used
20/203 9% bonded
PIO (prelim) 19/245 7% used
19/203 9% bonded
IOLOGIC 1/245 &lt;1% used
 
SLICE 65/21924 &lt;1% used
160,7 → 160,7
Number of Connections: 657
 
Pin Constraint Summary:
19 out of 19 pins locked (100% locked).
18 out of 18 pins locked (100% locked).
 
The following 1 signal is selected to use the primary clock routing resources:
clk_c (driver: clk, clk/ce/sr load #: 9/0/0)
221,9 → 221,9
 
+
I/O Usage Summary (final):
20 out of 245 (8.2%) PIO sites used.
20 out of 203 (9.9%) bonded PIO sites used.
Number of PIO comps: 19; differential: 1.
19 out of 245 (7.8%) PIO sites used.
19 out of 203 (9.4%) bonded PIO sites used.
Number of PIO comps: 18; differential: 1.
Number of Vref pins used: 0.
 
I/O Bank Usage Summary:
234,12 → 234,12
| 1 | 0 / 33 ( 0%) | - | - | - |
| 2 | 1 / 32 ( 3%) | 2.5V | - | - |
| 3 | 14 / 33 ( 42%) | 2.5V | - | - |
| 6 | 3 / 33 ( 9%) | 2.5V | - | - |
| 6 | 2 / 33 ( 6%) | 1.2V | - | - |
| 7 | 0 / 32 ( 0%) | - | - | - |
| 8 | 2 / 13 ( 15%) | 2.5V | - | - |
+----------+----------------+------------+------------+------------+
 
Total placer CPU time: 15 secs
Total placer CPU time: 14 secs
 
Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.
 
246,9 → 246,9
0 connections routed; 657 unrouted.
Starting router resource preassignment
 
Completed router resource preassignment. Real time: 23 secs
Completed router resource preassignment. Real time: 22 secs
 
Start NBR router at 01:37:06 01/17/17
Start NBR router at 01:08:51 01/18/17
 
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
263,26 → 263,26
your design.
*****************************************************************
 
Start NBR special constraint process at 01:37:06 01/17/17
Start NBR special constraint process at 01:08:52 01/18/17
 
Start NBR section for initial routing at 01:37:06 01/17/17
Start NBR section for initial routing at 01:08:52 01/18/17
Level 1, iteration 1
0(0.00%) conflict; 544(82.80%) untouched conns; 8380 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: -1.227ns/-8.380ns; real time: 24 secs
Estimated worst slack/total negative slack&lt;setup&gt;: -1.227ns/-8.380ns; real time: 23 secs
Level 2, iteration 1
0(0.00%) conflict; 542(82.50%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: -1.238ns/-8.800ns; real time: 24 secs
Estimated worst slack/total negative slack&lt;setup&gt;: -1.238ns/-8.800ns; real time: 23 secs
Level 3, iteration 1
0(0.00%) conflict; 523(79.60%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: -1.238ns/-8.800ns; real time: 24 secs
Estimated worst slack/total negative slack&lt;setup&gt;: -1.238ns/-8.800ns; real time: 23 secs
Level 4, iteration 1
5(0.00%) conflicts; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: -1.238ns/-8.800ns; real time: 24 secs
Estimated worst slack/total negative slack&lt;setup&gt;: -1.238ns/-8.800ns; real time: 23 secs
 
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
 
Start NBR section for normal routing at 01:37:07 01/17/17
Start NBR section for normal routing at 01:08:53 01/18/17
Level 1, iteration 1
0(0.00%) conflict; 8(1.22%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: -1.238ns/-8.800ns; real time: 24 secs
296,17 → 296,17
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: -1.238ns/-8.800ns; real time: 24 secs
 
Start NBR section for performance tuning (iteration 1) at 01:37:07 01/17/17
Start NBR section for performance tuning (iteration 1) at 01:08:53 01/18/17
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: -1.238ns/-8.800ns; real time: 24 secs
 
Start NBR section for re-routing at 01:37:07 01/17/17
Start NBR section for re-routing at 01:08:53 01/18/17
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: -1.238ns/-8.800ns; real time: 24 secs
 
Start NBR section for post-routing at 01:37:07 01/17/17
Start NBR section for post-routing at 01:08:53 01/18/17
 
End NBR router with 0 unrouted connection
 
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_scck.rpt
1,12 → 1,12
# Synopsys Constraint Checker(syntax only), version maplat, Build 1498R, built Jul 5 2016
# Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
 
# Written on Tue Jan 17 01:19:11 2017
# Written on Wed Jan 18 01:08:15 2017
 
 
##### DESIGN INFO #######################################################
 
Top View: "DisplayDriverWrapper"
Top View: "display_driver_wrapper"
Constraint File(s): (none)
 
#Run constraint checker to find more issues with constraints.
21,8 → 21,9
Clock Summary
*************
 
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
--------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button 918.9 MHz 1.088 inferred Autoconstr_clkgroup_0 8
========================================================================================================
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
-------------------------------------------------------------------------------------------------------------------------------------------------------------
display_driver_wrapper|bttn_state_derived_clock 1.0 MHz 1000.000 derived (from display_driver_wrapper|clk) Autoconstr_clkgroup_0 8
display_driver_wrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 5
=============================================================================================================================================================
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_summary.html
146,7 → 146,7
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2017/01/17 01:51:23</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2017/01/18 01:09:04</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_synplify.html
96,7 → 96,7
#OS: Windows 8 6.2
#Hostname: DESKTOP-1AUKF7V
 
# Tue Jan 17 01:19:09 2017
# Wed Jan 18 01:08:13 2017
 
#Implementation: impl1
 
109,43 → 109,39
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
 
@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:28|Top entity is set to display_driver_wrapper.
File C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\ecp5um.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd changed - recompiling
VHDL syntax check successful!
 
Compiler output is up to date. No re-compile necessary
 
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":38:11:38:15|Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":53:11:53:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd":12:7:12:25|Synthesizing work.distromasciidecoder.structure.
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd changed - recompiling
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:28|Synthesizing work.display_driver_wrapper.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":17:7:17:30|Synthesizing work.display_driver_w_decoder.display_driver_w_decoder_arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":42:11:42:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":15:7:15:19|Synthesizing work.ascii_decoder.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\decoder_table_dist_rom_impl\decoder_table_dist_rom\decoder_table_dist_rom.vhd":12:7:12:28|Synthesizing work.decoder_table_dist_rom.structure.
@N: CD630 :"C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd":801:10:801:18|Synthesizing work.rom128x1a.syn_black_box.
Post processing for work.rom128x1a.syn_black_box
Post processing for work.distromasciidecoder.structure
Post processing for work.asciidecoder.arch
Post processing for work.displaydriverwdecoder_top.arch
Post processing for work.displaydriverwrapper.arch
@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_5. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_fifo_5(3 downto 0). Make sure that there are no unused intermediate registers.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":29:8:29:12|Input wr_en is unused.
Post processing for work.decoder_table_dist_rom.structure
Post processing for work.ascii_decoder.arch
Post processing for work.display_driver_w_decoder.display_driver_w_decoder_arch
Post processing for work.display_driver_wrapper.arch
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":23:8:23:12|Input wr_en is unused.
 
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:19:09 2017
# Wed Jan 18 01:08:13 2017
 
###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
@N|Running in 64-bit mode
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling
 
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
152,7 → 148,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:19:09 2017
# Wed Jan 18 01:08:13 2017
 
###########################################################]
@END
162,7 → 158,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:19:09 2017
# Wed Jan 18 01:08:13 2017
 
###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
174,7 → 170,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:19:11 2017
# Wed Jan 18 01:08:14 2017
 
###########################################################]
Pre-mapping Report
205,7 → 201,7
ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed: 0
syn_allowed_resources : blockrams=108 set on top level netlist DisplayDriverWrapper
syn_allowed_resources : blockrams=108 set on top level netlist display_driver_wrapper
 
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
214,13 → 210,14
Clock Summary
*****************
 
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
--------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button 918.9 MHz 1.088 inferred Autoconstr_clkgroup_0 8
========================================================================================================
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
-------------------------------------------------------------------------------------------------------------------------------------------------------------
display_driver_wrapper|bttn_state_derived_clock 1.0 MHz 1000.000 derived (from display_driver_wrapper|clk) Autoconstr_clkgroup_0 8
display_driver_wrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 5
=============================================================================================================================================================
 
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found inferred clock DisplayDriverWrapper|button which controls 8 sequential elements including symbol_scan_cntr[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":52:8:52:9|Found inferred clock display_driver_wrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
 
Finished Pre Mapping Phase.
 
236,7 → 233,7
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 17 01:19:11 2017
# Wed Jan 18 01:08:15 2017
 
###########################################################]
Map & Optimize Report
273,7 → 270,7
 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":74:8:74:9|Found counter in view:work.display_driver_wrapper(arch) inst symbol_scan_cntr[7:0]
 
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
290,7 → 287,7
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
 
 
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
303,17 → 300,14
 
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -0.70ns 1 / 8
2 0h:00m:00s -0.70ns 1 / 8
@N: FX271 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Replicating instance symbol_scan_cntr[0] (in view: work.DisplayDriverWrapper(arch)) with 15 loads 1 time to improve timing.
Timing driven replication report
Added 1 Registers via timing driven replication
Added 0 LUTs via timing driven replication
1 0h:00m:00s -0.76ns 6 / 13
2 0h:00m:00s -0.76ns 6 / 13
 
3 0h:00m:00s -0.64ns 1 / 9
3 0h:00m:00s -0.62ns 7 / 13
 
4 0h:00m:00s -0.64ns 1 / 9
 
4 0h:00m:00s -0.58ns 6 / 13
 
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
320,6 → 314,7
 
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
 
@N: MT611 :|Automatically generated clock display_driver_wrapper|bttn_state_derived_clock is not used and is being removed
 
 
@S |Clock Optimization Summary
327,15 → 322,15
 
#### START OF CLOCK OPTIMIZATION REPORT #####[
 
1 non-gated/non-generated clock tree(s) driving 9 clock pin(s) of sequential element(s)
1 non-gated/non-generated clock tree(s) driving 13 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
8 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
============================= Non-Gated/Non-Generated Clocks ==============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
-------------------------------------------------------------------------------------------
@K:CKID0001 button port 9 symbol_scan_cntr[0]
===========================================================================================
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
@K:CKID0001 clk port 13 bttn_state
=======================================================================================
 
 
##### END OF CLOCK OPTIMIZATION REPORT ######]
345,7 → 340,7
 
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm
 
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 139MB peak: 141MB)
 
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi
352,21 → 347,21
L-2016.03L-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
 
 
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
 
@W: MT420 |Found inferred clock DisplayDriverWrapper|button with period 2.25ns. Please declare a user-defined clock on object "p:button"
@W: MT420 |Found inferred clock display_driver_wrapper|clk with period 2.30ns. Please declare a user-defined clock on object "p:clk"
 
 
##### START OF TIMING REPORT #####[
# Timing Report written on Tue Jan 17 01:19:13 2017
# Timing Report written on Wed Jan 18 01:08:17 2017
#
 
 
Top view: DisplayDriverWrapper
Requested Frequency: 443.5 MHz
Top view: display_driver_wrapper
Requested Frequency: 433.9 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
380,13 → 375,13
*******************
 
 
Worst slack in design: -0.398
Worst slack in design: -0.407
 
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
-------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button 443.5 MHz 377.0 MHz 2.255 2.652 -0.398 inferred Autoconstr_clkgroup_0
=====================================================================================================================================
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
------------------------------------------------------------------------------------------------------------------------------------
display_driver_wrapper|clk 433.9 MHz 368.8 MHz 2.305 2.712 -0.407 inferred Autoconstr_clkgroup_0
====================================================================================================================================
 
 
 
395,12 → 390,12
Clock Relationships
*******************
 
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-------------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-------------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button DisplayDriverWrapper|button | 2.255 -0.398 | No paths - | No paths - | No paths -
=================================================================================================================================================
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-----------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-----------------------------------------------------------------------------------------------------------------------------------------------
display_driver_wrapper|clk display_driver_wrapper|clk | 2.305 -0.407 | No paths - | No paths - | No paths -
===============================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
414,7 → 409,7
 
 
====================================
Detailed Report for Clock: DisplayDriverWrapper|button
Detailed Report for Clock: display_driver_wrapper|clk
====================================
 
 
422,38 → 417,41
Starting Points with Worst Slack
********************************
 
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[1] 0.933 -0.398
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[2] 0.933 -0.398
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[3] 0.933 -0.339
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[4] 0.933 -0.339
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[5] 0.933 -0.280
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[6] 0.933 -0.280
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr_fast[0] 0.753 -0.277
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[7] 0.798 0.570
================================================================================================================================
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[0] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[0] 0.933 -0.407
symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[1] 0.933 -0.348
symbol_scan_cntr[2] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[2] 0.933 -0.348
symbol_scan_cntr[3] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[3] 0.933 -0.289
symbol_scan_cntr[4] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[4] 0.933 -0.289
symbol_scan_cntr[5] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[5] 0.933 -0.230
symbol_scan_cntr[6] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[6] 0.933 -0.230
bttn_state_fifo[3] display_driver_wrapper|clk FD1S3JX Q bttn_state_fifo[3] 0.798 0.123
bttn_state display_driver_wrapper|clk FD1S3AX Q bttn_state_i 0.753 0.168
bttn_state_fifo[1] display_driver_wrapper|clk FD1S3JX Q bttn_state_fifo[1] 0.838 0.606
=====================================================================================================================
 
 
Ending Points with Worst Slack
******************************
 
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[7] 2.044 -0.398
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[5] 2.044 -0.339
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[6] 2.044 -0.339
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[3] 2.044 -0.280
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[4] 2.044 -0.280
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[1] 2.044 -0.100
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[2] 2.044 -0.100
symbol_scan_cntr[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
==============================================================================================================================
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[7] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[7] 2.094 -0.407
symbol_scan_cntr[5] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[5] 2.094 -0.348
symbol_scan_cntr[6] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[6] 2.094 -0.348
symbol_scan_cntr[3] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[3] 2.094 -0.289
symbol_scan_cntr[4] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[4] 2.094 -0.289
symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[1] 2.094 -0.230
symbol_scan_cntr[2] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[2] 2.094 -0.230
symbol_scan_cntr[0] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
symbol_scan_cntr[2] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
==================================================================================================================================
 
 
 
462,64 → 460,67
 
 
Path information for path number 1:
Requested Period: 2.255
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
= Required time: 2.094
 
- Propagation time: 2.442
- Propagation time: 2.501
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.398
= Slack (critical) : -0.407
 
Number of logic level(s): 4
Starting point: symbol_scan_cntr[1] / Q
Number of logic level(s): 5
Starting point: symbol_scan_cntr[0] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[0] Net - - - - 15
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[0] Net - - - - 1
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.894 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.894 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.501 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.501 -
===========================================================================================
 
 
Path information for path number 2:
Requested Period: 2.255
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
= Required time: 2.094
 
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.398
= Slack (non-critical) : -0.348
 
Number of logic level(s): 4
Starting point: symbol_scan_cntr[2] / Q
Starting point: symbol_scan_cntr[1] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[2] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[2] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr[1] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
531,109 → 532,118
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 3:
Requested Period: 2.255
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
= Required time: 2.094
 
- Propagation time: 2.382
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -0.339
= Slack (non-critical) : -0.348
 
Number of logic level(s): 3
Starting point: symbol_scan_cntr[3] / Q
Number of logic level(s): 4
Starting point: symbol_scan_cntr[2] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[3] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[3] Net - - - - 15
symbol_scan_cntr_cry_0[3] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr[2] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[2] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 4:
Requested Period: 2.255
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
= Required time: 2.094
 
- Propagation time: 2.382
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -0.339
= Slack (non-critical) : -0.348
 
Number of logic level(s): 3
Starting point: symbol_scan_cntr[4] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
Number of logic level(s): 4
Starting point: symbol_scan_cntr[0] / Q
Ending point: symbol_scan_cntr[5] / D
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[4] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[4] Net - - - - 15
symbol_scan_cntr_cry_0[3] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[0] Net - - - - 15
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[0] Net - - - - 1
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[5] Net - - - - 1
symbol_scan_cntr[5] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
Path information for path number 5:
Requested Period: 2.255
Requested Period: 2.305
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
= Required time: 2.094
 
- Propagation time: 2.382
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -0.339
= Slack (non-critical) : -0.348
 
Number of logic level(s): 3
Starting point: symbol_scan_cntr[1] / Q
Ending point: symbol_scan_cntr[5] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
Number of logic level(s): 4
Starting point: symbol_scan_cntr[0] / Q
Ending point: symbol_scan_cntr[6] / D
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
symbol_scan_cntr[0] Net - - - - 15
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[0] Net - - - - 1
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[5] Net - - - - 1
symbol_scan_cntr[5] FD1S3DX D In 0.000 2.382 -
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_cry_0[5] CCU2C S1 Out 0.607 2.442 -
symbol_scan_cntr_s[6] Net - - - - 1
symbol_scan_cntr[6] FD1P3DX D In 0.000 2.442 -
===========================================================================================
 
 
652,7 → 662,7
Resource Usage Report
Part: lfe5um5g_45f-8
 
Register bits: 9 of 43848 (0%)
Register bits: 13 of 43848 (0%)
PIC Latch: 0
I/O cells: 18
 
659,11 → 669,15
 
Details:
CCU2C: 5
FD1S3DX: 9
FD1P3DX: 8
FD1S3AX: 1
FD1S3JX: 3
GSR: 1
IB: 2
INV: 1
OB: 16
IB: 3
IFS1P3JX: 1
INV: 2
OB: 15
ORCALUT4: 4
PUR: 1
ROM128X1A: 14
VHI: 1
673,7 → 687,7
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 17 01:19:13 2017
# Wed Jan 18 01:08:17 2017
 
###########################################################]
 
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_synplify.lpf
3,7 → 3,7
#
 
# Period Constraints
#FREQUENCY PORT "button" 443.5 MHz;
#FREQUENCY PORT "clk" 433.9 MHz;
 
 
# Output Constraints
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_synplify.tcl
44,13 → 44,13
 
#-- add_file options
add_file -vhdl {C:/lscc/diamond/3.8_x64/cae_library/synthesis/vhdl/ecp5um.vhd}
add_file -vhdl -lib "work" {C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd}
add_file -vhdl -lib "work" {C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd}
add_file -vhdl -lib "work" {C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ASCIIDecoder.vhd}
add_file -vhdl -lib "work" {C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd}
add_file -vhdl -lib "work" {C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ascii_decoder.vhd}
add_file -vhdl -lib "work" {C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/display_driver_w_decoder.vhd}
add_file -vhdl -lib "work" {C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/display_driver_wrapper.vhd}
add_file -vhdl -lib "work" {C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd}
 
#-- top module name
set_option -top_module DisplayDriverWrapper
set_option -top_module display_driver_wrapper
 
#-- set result format/file last
project -result_file {C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.edi}
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1_tw1.html
93,7 → 93,7
<PRE><A name="Map_Twr"></A><B><U><big>Map TRACE Report</big></U></B>
 
Loading design for application trce from file displaydriverwdecoder_impl1_map.ncd.
Design name: DisplayDriverWrapper
Design name: display_driver_wrapper
NCD version: 3.3
Vendor: LATTICE
Device: LFE5UM5G-45F
106,7 → 106,7
 
--------------------------------------------------------------------------------
<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.8.0.115.3</big></U></B>
Tue Jan 17 01:36:41 2017
Wed Jan 18 01:08:27 2017
 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
215,7 → 215,7
 
--------------------------------------------------------------------------------
<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.8.0.115.3</big></U></B>
Tue Jan 17 01:36:42 2017
Wed Jan 18 01:08:28 2017
 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/hdla_gen_hierarchy.html
43,78 → 43,78
INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/synattr.vhd(50,9-50,19) (VHDL-1014) analyzing package attributes
(VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v
(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.vhd
(VHDL-1481) Analyzing VHDL file C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(12,8-12,27) (VHDL-1012) analyzing entity distromasciidecoder
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(18,14-18,23) (VHDL-1010) analyzing architecture structure
(VHDL-1481) Analyzing VHDL file C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ASCIIDecoder.vhd
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ASCIIDecoder.vhd(15,8-15,20) (VHDL-1012) analyzing entity asciidecoder
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ASCIIDecoder.vhd(28,14-28,18) (VHDL-1010) analyzing architecture arch
(VHDL-1481) Analyzing VHDL file C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd(16,8-16,33) (VHDL-1012) analyzing entity displaydriverwdecoder_top
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd(51,14-51,18) (VHDL-1010) analyzing architecture arch
(VHDL-1481) Analyzing VHDL file C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd(15,8-15,28) (VHDL-1012) analyzing entity displaydriverwrapper
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd(37,14-37,18) (VHDL-1010) analyzing architecture arch
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd(15,8-15,28) (VHDL-1067) elaborating DisplayDriverWrapper(arch)
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd(16,8-16,33) (VHDL-1067) elaborating DisplayDriverwDecoder_Top_uniq_0(arch)
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ASCIIDecoder.vhd(15,8-15,20) (VHDL-1067) elaborating ASCIIDecoder_uniq_0(arch)
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(12,8-12,27) (VHDL-1067) elaborating DistRomAsciiDecoder_uniq_0(Structure)
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(25,5-29,42) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
(VHDL-1481) Analyzing VHDL file C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(12,8-12,30) (VHDL-1012) analyzing entity decoder_table_dist_rom
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(18,14-18,23) (VHDL-1010) analyzing architecture structure
(VHDL-1481) Analyzing VHDL file C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ascii_decoder.vhd
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ascii_decoder.vhd(15,8-15,21) (VHDL-1012) analyzing entity ascii_decoder
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ascii_decoder.vhd(28,14-28,18) (VHDL-1010) analyzing architecture arch
(VHDL-1481) Analyzing VHDL file C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/display_driver_w_decoder.vhd
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/display_driver_w_decoder.vhd(17,8-17,32) (VHDL-1012) analyzing entity display_driver_w_decoder
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/display_driver_w_decoder.vhd(40,14-40,43) (VHDL-1010) analyzing architecture display_driver_w_decoder_arch
(VHDL-1481) Analyzing VHDL file C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/display_driver_wrapper.vhd
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/display_driver_wrapper.vhd(15,8-15,30) (VHDL-1012) analyzing entity display_driver_wrapper
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/display_driver_wrapper.vhd(32,14-32,18) (VHDL-1010) analyzing architecture arch
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/display_driver_wrapper.vhd(15,8-15,30) (VHDL-1067) elaborating display_driver_wrapper(arch)
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/display_driver_w_decoder.vhd(17,8-17,32) (VHDL-1067) elaborating display_driver_w_decoder_uniq_0(display_driver_w_decoder_arch)
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ascii_decoder.vhd(15,8-15,21) (VHDL-1067) elaborating ascii_decoder_uniq_0(arch)
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(12,8-12,30) (VHDL-1067) elaborating decoder_table_dist_rom_uniq_0(Structure)
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(25,5-29,42) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_1
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_1'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(25,5-29,42) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(31,5-35,42) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(25,5-29,42) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(31,5-35,42) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_2
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_2'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(31,5-35,42) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(37,5-41,42) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(31,5-35,42) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(37,5-41,42) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_3
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_3'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(37,5-41,42) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(43,5-47,42) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(37,5-41,42) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(43,5-47,42) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_4
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_4'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(43,5-47,42) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(49,5-53,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(43,5-47,42) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(49,5-53,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_5
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_5'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(49,5-53,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(55,5-59,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(49,5-53,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(55,5-59,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_6
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_6'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(55,5-59,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(61,5-65,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(55,5-59,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(61,5-65,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_7
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_7'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(61,5-65,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(67,5-71,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(61,5-65,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(67,5-71,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_8
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_8'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(67,5-71,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(73,5-77,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(67,5-71,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(73,5-77,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_9
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_9'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(73,5-77,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(79,5-83,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(73,5-77,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(79,5-83,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_10
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_10'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(79,5-83,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(85,5-89,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(79,5-83,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(85,5-89,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_11
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_11'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(85,5-89,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(91,5-95,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(85,5-89,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(91,5-95,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_12
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_12'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(91,5-95,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(97,5-101,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(91,5-95,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(97,5-101,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_13
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_13'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(97,5-101,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(103,5-107,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(97,5-101,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(103,5-107,41) (VHDL-1399) going to verilog side to elaborate module ROM128X1A
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,8-698,17) (VERI-1018) compiling module ROM128X1A_uniq_14
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_14'
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd(103,5-107,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd(103,5-107,41) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_1'
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_2'
INFO - C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v(698,1-708,10) (VERI-9000) elaborating module 'ROM128X1A_uniq_3'
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/impl1.areasrr
22,12 → 22,12
VLO 1 100.0
SUB MODULES
ASCIIDecoder 1 100.0
DisplayDriverwDecoder_Top 1 100.0
DistRomAsciiDecoder 1 100.0
display_driver_w_decoder 1 100.0
TOTAL 64
----------------------------------------------------------------------
Report for cell DisplayDriverwDecoder_Top.netlist
Report for cell display_driver_w_decoder.netlist
Instance path: DDwD_Top
Cell usage:
cell count Res Usage(%)
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/impl1.edi
4,7 → 4,7
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 2017 1 17 1 29 39)
(timeStamp 2017 1 17 23 41 24)
(author "Synopsys, Inc.")
(program "Synplify Pro" (version "L-2016.03L-1, mapper maplat, Build 1498R"))
)
475,7 → 475,7
(property orig_inst_of (string "ASCIIDecoder"))
)
)
(cell DisplayDriverwDecoder_Top (cellType GENERIC)
(cell display_driver_w_decoder (cellType GENERIC)
(view netlist (viewType NETLIST)
(interface
(port (array (rename symbol_scan_cntr "symbol_scan_cntr(6:0)") 7) (direction INPUT))
569,7 → 569,7
(portRef (member disp_data_c 0))
))
)
(property orig_inst_of (string "DisplayDriverwDecoder_Top"))
(property orig_inst_of (string "display_driver_w_decoder"))
)
)
(cell DisplayDriverWrapper (cellType GENERIC)
677,7 → 677,7
(property INJECT1_0 (string "NO"))
(property INIT1 (string "0x5003"))
)
(instance DDwD_Top (viewRef netlist (cellRef DisplayDriverwDecoder_Top))
(instance DDwD_Top (viewRef netlist (cellRef display_driver_w_decoder))
)
(net (rename symbol_scan_cntr_0 "symbol_scan_cntr[0]") (joined
(portRef Q (instanceRef symbol_scan_cntr_0))
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/impl1.srd Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/impl1.srm Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/impl1.srr
3,7 → 3,7
#OS: Windows 8 6.2
#Hostname: DESKTOP-1AUKF7V
 
# Tue Jan 17 01:29:36 2017
# Tue Jan 17 23:41:19 2017
 
#Implementation: impl1
 
16,23 → 16,26
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
 
@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
Options changed - recompiling
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
File C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\ecp5um.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd changed - recompiling
VHDL syntax check successful!
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":53:11:53:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":17:7:17:30|Synthesizing work.display_driver_w_decoder.display_driver_w_decoder_arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":47:11:47:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd":12:7:12:25|Synthesizing work.distromasciidecoder.structure.
@N: CD630 :"C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd":801:10:801:18|Synthesizing work.rom128x1a.syn_black_box.
Post processing for work.rom128x1a.syn_black_box
Post processing for work.distromasciidecoder.structure
Post processing for work.asciidecoder.arch
Post processing for work.displaydriverwdecoder_top.arch
Post processing for work.display_driver_w_decoder.display_driver_w_decoder_arch
Post processing for work.displaydriverwrapper.arch
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":29:8:29:12|Input wr_en is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":23:8:23:12|Input wr_en is unused.
 
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
 
39,14 → 42,14
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:29:36 2017
# Tue Jan 17 23:41:20 2017
 
###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
@N|Running in 64-bit mode
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
 
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
53,7 → 56,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:29:36 2017
# Tue Jan 17 23:41:20 2017
 
###########################################################]
@END
63,14 → 66,14
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:29:36 2017
# Tue Jan 17 23:41:20 2017
 
###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
@N|Running in 64-bit mode
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_comp.srs changed - recompiling
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
 
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
77,7 → 80,7
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
Process completed successfully.
# Tue Jan 17 01:29:37 2017
# Tue Jan 17 23:41:21 2017
 
###########################################################]
Pre-mapping Report
124,7 → 127,7
DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 5
=========================================================================================================================================================
 
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":57:4:57:5|Found inferred clock DisplayDriverWrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":57:4:57:5|Found inferred clock DisplayDriverWrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
 
Finished Pre Mapping Phase.
 
140,7 → 143,7
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 142MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 17 01:29:38 2017
# Tue Jan 17 23:41:22 2017
 
###########################################################]
Map & Optimize Report
177,7 → 180,7
 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":77:4:77:5|Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":77:4:77:5|Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
 
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
254,7 → 257,7
L-2016.03L-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
 
 
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
263,7 → 266,7
 
 
##### START OF TIMING REPORT #####[
# Timing Report written on Tue Jan 17 01:29:40 2017
# Timing Report written on Tue Jan 17 23:41:24 2017
#
 
 
594,6 → 597,6
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 17 01:29:40 2017
# Tue Jan 17 23:41:24 2017
 
###########################################################]
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/impl1.srs Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/impl1_cck.rpt
1,7 → 1,7
# Synopsys Constraint Checker, version maplat, Build 1498R, built Jul 5 2016
# Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
 
# Written on Tue Jan 17 01:29:38 2017
# Written on Tue Jan 17 23:41:22 2017
 
 
##### DESIGN INFO #######################################################
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/impl1_scck.rpt
1,7 → 1,7
# Synopsys Constraint Checker(syntax only), version maplat, Build 1498R, built Jul 5 2016
# Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
 
# Written on Tue Jan 17 01:29:38 2017
# Written on Tue Jan 17 23:41:22 2017
 
 
##### DESIGN INFO #######################################################
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/impl1_syn.prj
1,15 → 1,15
#-- Synopsys, Inc.
#-- Version L-2016.03L-1
#-- Project file C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_syn.prj
#-- Written on Tue Jan 17 01:28:16 2017
#-- Written on Tue Jan 17 23:37:09 2017
 
 
#project files
add_file -vhdl -lib work "C:/lscc/diamond/3.8_x64/cae_library/synthesis/vhdl/ecp5um.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ASCIIDecoder.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ascii_decoder.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/display_driver_w_decoder.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/display_driver_wrapper.vhd"
 
 
 
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/launch_synplify.tcl
1,6 → 1,6
#-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/launch_synplify.tcl
#-- Written on Tue Jan 17 01:28:15 2017
#-- Written on Tue Jan 17 23:37:07 2017
 
project -close
set filename "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/impl1_syn.prj"
45,10 → 45,10
}
#-- add_file options
add_file -vhdl "C:/lscc/diamond/3.8_x64/cae_library/synthesis/vhdl/ecp5um.vhd"
add_file -vhdl -lib "work" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd"
add_file -vhdl -lib "work" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd"
add_file -vhdl -lib "work" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ASCIIDecoder.vhd"
add_file -vhdl -lib "work" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd"
add_file -vhdl -lib "work" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ascii_decoder.vhd"
add_file -vhdl -lib "work" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/display_driver_w_decoder.vhd"
add_file -vhdl -lib "work" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/display_driver_wrapper.vhd"
#-- top module name
set_option -top_module {}
project -result_file {C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/impl1.edi}
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/message.xml
4,10 → 4,10
<Message>
<ID>1101672</ID>
<Severity>Warning</Severity>
<Dynamic>C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.lpf(21): Semantic error in &quot;USERCODE ASCII &quot;G.L.&quot; ; &quot;: </Dynamic>
<Dynamic>C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.lpf(29): Semantic error in &quot;USERCODE ASCII &quot;G.L.&quot; ; &quot;: </Dynamic>
<Dynamic>Invalid Ascii char &lt;.&gt;.Invalid Ascii char &lt;.&gt;.</Dynamic>
<Navigation>C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.lpf</Navigation>
<Navigation>21</Navigation>
<Navigation>29</Navigation>
</Message>
<Message>
<ID>1104062</ID>
169,24 → 169,12
<Message>
<ID>2019991</ID>
<Severity>Warning</Severity>
<Dynamic>CD638 :&quot;C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd&quot;:38:11:38:15|Signal empty is undriven. Either assign the signal a value or remove the signal declaration.</Dynamic>
<Dynamic>CD638 :&quot;C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd&quot;:42:11:42:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.</Dynamic>
<Navigation>CD638</Navigation>
<Navigation>C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd</Navigation>
<Navigation>38</Navigation>
<Navigation>C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd</Navigation>
<Navigation>42</Navigation>
<Navigation>11</Navigation>
<Navigation>38</Navigation>
<Navigation>15</Navigation>
<Navigation>Signal empty is undriven. Either assign the signal a value or remove the signal declaration.</Navigation>
</Message>
<Message>
<ID>2019991</ID>
<Severity>Warning</Severity>
<Dynamic>CD638 :&quot;C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd&quot;:53:11:53:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.</Dynamic>
<Navigation>CD638</Navigation>
<Navigation>C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd</Navigation>
<Navigation>53</Navigation>
<Navigation>11</Navigation>
<Navigation>53</Navigation>
<Navigation>42</Navigation>
<Navigation>19</Navigation>
<Navigation>Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.</Navigation>
</Message>
193,45 → 181,21
<Message>
<ID>2019991</ID>
<Severity>Warning</Severity>
<Dynamic>CL169 :&quot;C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd&quot;:54:4:54:5|Pruning unused register bttn_state_5. Make sure that there are no unused intermediate registers.</Dynamic>
<Navigation>CL169</Navigation>
<Navigation>C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd</Navigation>
<Navigation>54</Navigation>
<Navigation>4</Navigation>
<Navigation>54</Navigation>
<Navigation>5</Navigation>
<Navigation>Pruning unused register bttn_state_5. Make sure that there are no unused intermediate registers.</Navigation>
</Message>
<Message>
<ID>2019991</ID>
<Severity>Warning</Severity>
<Dynamic>CL169 :&quot;C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd&quot;:54:4:54:5|Pruning unused register bttn_state_fifo_5(3 downto 0). Make sure that there are no unused intermediate registers.</Dynamic>
<Navigation>CL169</Navigation>
<Navigation>C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd</Navigation>
<Navigation>54</Navigation>
<Navigation>4</Navigation>
<Navigation>54</Navigation>
<Navigation>5</Navigation>
<Navigation>Pruning unused register bttn_state_fifo_5(3 downto 0). Make sure that there are no unused intermediate registers.</Navigation>
</Message>
<Message>
<ID>2019991</ID>
<Severity>Warning</Severity>
<Dynamic>MT529 :&quot;c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd&quot;:74:4:74:5|Found inferred clock DisplayDriverWrapper|button which controls 8 sequential elements including symbol_scan_cntr[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.</Dynamic>
<Dynamic>MT529 :&quot;c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd&quot;:52:8:52:9|Found inferred clock display_driver_wrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.</Dynamic>
<Navigation>MT529</Navigation>
<Navigation>c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd</Navigation>
<Navigation>74</Navigation>
<Navigation>4</Navigation>
<Navigation>74</Navigation>
<Navigation>5</Navigation>
<Navigation>Found inferred clock DisplayDriverWrapper|button which controls 8 sequential elements including symbol_scan_cntr[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </Navigation>
<Navigation>c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd</Navigation>
<Navigation>52</Navigation>
<Navigation>8</Navigation>
<Navigation>52</Navigation>
<Navigation>9</Navigation>
<Navigation>Found inferred clock display_driver_wrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </Navigation>
</Message>
<Message>
<ID>2019993</ID>
<Severity>Warning</Severity>
<Dynamic>MT420 |Found inferred clock DisplayDriverWrapper|button with period 2.25ns. Please declare a user-defined clock on object &quot;p:button&quot;</Dynamic>
<Dynamic>MT420 |Found inferred clock display_driver_wrapper|clk with period 2.30ns. Please declare a user-defined clock on object &quot;p:clk&quot;</Dynamic>
<Navigation>MT420</Navigation>
<Navigation>Found inferred clock DisplayDriverWrapper|button with period 2.25ns. Please declare a user-defined clock on object &quot;p:button&quot;</Navigation>
<Navigation>Found inferred clock display_driver_wrapper|clk with period 2.30ns. Please declare a user-defined clock on object &quot;p:clk&quot;</Navigation>
</Message>
</Task>
</BaliMessageLog>
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/run_options.txt
4,10 → 4,10
 
#project files
add_file -vhdl -lib work "C:/lscc/diamond/3.8_x64/cae_library/synthesis/vhdl/ecp5um.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ASCIIDecoder.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ascii_decoder.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/display_driver_w_decoder.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/display_driver_wrapper.vhd"
 
 
 
17,7 → 17,7
#
#implementation attributes
 
set_option -vlog_std sysv
set_option -vlog_std v2001
set_option -project_relative_includes 1
 
#device options
28,6 → 28,7
set_option -part_companion ""
 
#compilation/mapping options
set_option -top_module "display_driver_wrapper"
 
# hdl_compiler_options
set_option -distributed_compile 0
41,11 → 42,11
set_option -write_vhdl 0
 
# Lattice XP
set_option -maxfan 100
set_option -maxfan 1000
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -pipe 1
set_option -forcegsr no
set_option -forcegsr false
set_option -fix_gated_and_generated_clocks 1
set_option -rw_check_on_ram 1
set_option -update_models_cp 0
70,5 → 71,8
set_option -write_apr_constraint 1
 
#set result format/file last
project -result_file "./impl1.edi"
project -result_file "./DisplayDriverwDecoder_impl1.edi"
 
#set log file
set_option log_file "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.srf"
impl -active "impl1"
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/scratchproject.prs
4,10 → 4,10
 
#project files
add_file -vhdl -lib work "C:/lscc/diamond/3.8_x64/cae_library/synthesis/vhdl/ecp5um.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ASCIIDecoder.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ascii_decoder.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/display_driver_w_decoder.vhd"
add_file -vhdl -lib work "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/display_driver_wrapper.vhd"
 
 
 
17,7 → 17,7
#
#implementation attributes
 
set_option -vlog_std sysv
set_option -vlog_std v2001
set_option -project_relative_includes 1
set_option -include_path {C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/}
 
29,6 → 29,7
set_option -part_companion ""
 
#compilation/mapping options
set_option -top_module "display_driver_wrapper"
 
# hdl_compiler_options
set_option -distributed_compile 0
42,11 → 43,11
set_option -write_vhdl 0
 
# Lattice XP
set_option -maxfan 100
set_option -maxfan 1000
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -pipe 1
set_option -forcegsr no
set_option -forcegsr false
set_option -fix_gated_and_generated_clocks 1
set_option -rw_check_on_ram 1
set_option -update_models_cp 0
71,5 → 72,8
set_option -write_apr_constraint 1
 
#set result format/file last
project -result_file "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/impl1.edi"
project -result_file "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.edi"
 
#set log file
set_option log_file "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/DisplayDriverwDecoder_impl1.srf"
impl -active "impl1"
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/impl1/synlog.tcl
1,7 → 1,8
source "C:/Users/GL/AppData/Local/Synplicity/scm_perforce.tcl"
history clear
run_tcl -fg C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/launch_synplify.tcl
project -run
project -run
project -run
project -close C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/impl1_syn.prj
run_tcl -fg DisplayDriverwDecoder_impl1_synplify.tcl
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.ldf
1,18 → 1,20
<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="DisplayDriverwDecoder" device="LFE5UM5G-45F-8BG381C" default_implementation="impl1">
<Options/>
<Options>
<Option name="HDL type" value="VHDL"/>
</Options>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
<Options def_top="DisplayDriverWrapper"/>
<Source name="../Sources/DisplayDriverwDecoder_Top.vhd" type="VHDL" type_short="VHDL">
<Options def_top="display_driver_wrapper"/>
<Source name="../Sources/ascii_decoder.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../Sources/DisplayDriverWrapper.vhd" type="VHDL" type_short="VHDL">
<Options top_module="DisplayDriverWrapper"/>
</Source>
<Source name="../Sources/ASCIIDecoder.vhd" type="VHDL" type_short="VHDL">
<Source name="../Sources/display_driver_w_decoder.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd" type="VHDL" type_short="VHDL">
<Source name="../Sources/display_driver_wrapper.vhd" type="VHDL" type_short="VHDL">
<Options top_module="display_driver_wrapper"/>
</Source>
<Source name="../Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="DisplayDriverwDecoder.lpf" type="Logic Preference" type_short="LPF">
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.lpf
1,25 → 1,29
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
LOCATE COMP "disp_data[0]" SITE "M20" ;
LOCATE COMP "disp_data[1]" SITE "L18" ;
LOCATE COMP "disp_data[2]" SITE "M19" ;
LOCATE COMP "disp_data[3]" SITE "L16" ;
LOCATE COMP "disp_data[4]" SITE "L17" ;
LOCATE COMP "disp_data[6]" SITE "R17" ;
LOCATE COMP "disp_data[5]" SITE "M18" ;
LOCATE COMP "disp_data[7]" SITE "P17" ;
LOCATE COMP "disp_data[8]" SITE "N16" ;
 
LOCATE COMP "clk" SITE "P3" ;
IOBUF PORT "clk" IO_TYPE=LVDS ;
LOCATE COMP "disp_sel" SITE "J1" ;
LOCATE COMP "disp_data[10]" SITE "N18" ;
LOCATE COMP "disp_data[11]" SITE "N17" ;
LOCATE COMP "disp_data[12]" SITE "P16" ;
LOCATE COMP "disp_data[14]" SITE "U1" ;
LOCATE COMP "disp_data[9]" SITE "M17" ;
LOCATE COMP "disp_data[13]" SITE "R16" ;
USERCODE ASCII "G.L." ;
IOBUF PORT "button" PULLMODE=UP IO_TYPE=LVCMOS25 ;
 
LOCATE COMP "n_rst" SITE "K20" ;
IOBUF PORT "n_rst" PULLMODE=UP IO_TYPE=LVCMOS25 ;
 
LOCATE COMP "button" SITE "T1" ;
IOBUF PORT "button" PULLMODE=UP IO_TYPE=LVCMOS25 ;
 
LOCATE COMP "disp_data_q[0]" SITE "M20" ;
LOCATE COMP "disp_data_q[1]" SITE "L18" ;
LOCATE COMP "disp_data_q[2]" SITE "M19" ;
LOCATE COMP "disp_data_q[3]" SITE "L16" ;
LOCATE COMP "disp_data_q[4]" SITE "L17" ;
LOCATE COMP "disp_data_q[5]" SITE "M18" ;
LOCATE COMP "disp_data_q[6]" SITE "R17" ;
LOCATE COMP "disp_data_q[7]" SITE "P17" ;
LOCATE COMP "disp_data_q[8]" SITE "N16" ;
LOCATE COMP "disp_data_q[9]" SITE "M17" ;
LOCATE COMP "disp_data_q[10]" SITE "N18" ;
LOCATE COMP "disp_data_q[11]" SITE "N17" ;
LOCATE COMP "disp_data_q[12]" SITE "P16" ;
LOCATE COMP "disp_data_q[13]" SITE "R16" ;
LOCATE COMP "disp_data_q[14]" SITE "U1" ;
 
USERCODE ASCII "G.L." ;
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/DisplayDriverwDecoder_tcl.html
156,6 → 156,60
 
 
 
<A name="pn170117235933"></A><B><U><big>pn170117235933</big></U></B>
#Start recording tcl command: 1/17/2017 23:33:55
#Project Location: C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build; Project name: DisplayDriverwDecoder
prj_project open "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.ldf"
prj_src add "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ascii_decoder.vhd" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/display_driver_w_decoder.vhd" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/display_driver_wrapper.vhd"
prj_src remove "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd"
prj_src remove "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd"
prj_src remove "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ASCIIDecoder.vhd"
prj_run Translate -impl impl1
launch_synplify_prj impl1
prj_project save
prj_run Translate -impl impl1
#Stop recording: 1/17/2017 23:59:33
 
 
 
<A name="pn170118004206"></A><B><U><big>pn170118004206</big></U></B>
#Start recording tcl command: 1/18/2017 00:39:07
#Project Location: C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build; Project name: DisplayDriverwDecoder
prj_project open "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.ldf"
prj_run Translate -impl impl1
sbp_design open -dsgn "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.sbx"
set currentPath [pwd];set tmp_autopath $auto_path
cd "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder"
source "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/generate_core.tcl"
set auto_path $tmp_autopath;cd $currentPath
prj_src add "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.sbx"
sbp_design open -dsgn "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.sbx"
#Stop recording: 1/18/2017 00:42:06
 
 
 
<A name="pn170118005400"></A><B><U><big>pn170118005400</big></U></B>
#Start recording tcl command: 1/18/2017 00:43:34
#Project Location: C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build; Project name: DisplayDriverwDecoder
prj_project open "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.ldf"
sbp_design new -dsgn "decoder_table_dist_rom_impl" -path "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl" -device "LFE5UM5G-45F-8BG381C"
set currentPath [pwd];set tmp_autopath $auto_path
cd "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom"
source "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/generate_core.tcl"
set auto_path $tmp_autopath;cd $currentPath
set currentPath [pwd];set tmp_autopath $auto_path
cd "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom"
source "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/generate_ngd.tcl"
set auto_path $tmp_autopath;cd $currentPath
sbp_builder export_add -comp {decoder_table_dist_rom_impl/decoder_table_dist_rom}
prj_src remove "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.sbx"
prj_src remove "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd"
prj_src add "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd"
prj_run Translate -impl impl1
#Stop recording: 1/18/2017 00:54:00
 
 
 
<BR>
<BR>
<BR>
/single-14-segment-display-driver-w-decoder/trunk/Project/Lattice_FPGA_Build/promote.xml
1,5 → 1,5
<?xml version="1.0" encoding="UTF-8"?>
<userSetting name="C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml" version="Diamond (64-bit) 3.8.0.115.3" date="Tue Jan 17 01:51:32 2017" vendor="Lattice Semiconductor Corporation" >
<userSetting name="C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml" version="Diamond (64-bit) 3.8.0.115.3" date="Wed Jan 18 01:09:15 2017" vendor="Lattice Semiconductor Corporation" >
<msg mid="35921504" type="Info" />
<msg mid="35921205" type="Warning" />
</userSetting>
/single-14-segment-display-driver-w-decoder/trunk/Project/Sources/DisplayDriverwDecoder_Top.vhd File deleted
single-14-segment-display-driver-w-decoder/trunk/Project/Sources/DisplayDriverwDecoder_Top.vhd Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/RomInitValsBin.mem =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/RomInitValsBin.mem (revision 8) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/RomInitValsBin.mem (nonexistent) @@ -1,128 +0,0 @@ -01101111000000 -11111111111001 -11111100100100 -11111101110000 -11111100011001 -11011110010110 -11111100000010 -11111111111000 -11111100000000 -11111100010000 -11111100001000 -10110101110000 -11111111000110 -10110111110000 -11111100000110 -11111110001110 -11111111111111 -11111111111111 -11111111111111 -11111111111111 -11111111111111 -11111111111111 -11111111111111 -11111111111111 -10110100110110 -10101000111111 -10110100000110 -11111100011100 -11101011001111 -10110100110111 -00010111111111 -10100011111111 -11111111111111 -11111111111001 -11110111011111 -00000000000000 -10110100010010 -01001000011011 -01001011110010 -11101111111111 -11001111111111 -01111011111111 -00000000111111 -10110100111111 -01111111111111 -11111100111111 -10111110100111 -01101111111111 -01101111000000 -11111111111001 -11111100100100 -11111101110000 -11111100011001 -11011110010110 -11111100000010 -11111111111000 -11111100000000 -11111100010000 -10110111111111 -01110111111111 -11001111111111 -11111100110111 -01111011111111 -10111101111100 -11110101000100 -11111100001000 -10110101110000 -11111111000110 -10110111110000 -11111100000110 -11111110001110 -11111101000010 -11111100001001 -10110111111111 -11111111100001 -11001110001111 -11111111000111 -11101011001001 -11011011001001 -11111111000000 -11111100001100 -11011111000000 -11011100001100 -11111100010010 -10110111111110 -11111111000001 -01101111001111 -01011111001001 -01001011111111 -10101011111111 -01101111110110 -11111111000110 -11011011111111 -11111111110000 -01101111111100 -11111111110111 -11111011111111 -11111100001000 -10110101110000 -11111111000110 -10110111110000 -11111100000110 -11111110001110 -11111101000010 -11111100001001 -10110111111111 -11111111100001 -11001110001111 -11111111000111 -11101011001001 -11011011001001 -11111111000000 -11111100001100 -11011111000000 -11011100001100 -11111100010010 -10110111111110 -11111111000001 -01101111001111 -01011111001001 -01001011111111 -10101011111111 -01101111110110 -11001110111111 -10110111111111 -01111001111111 -11111100101101 -11111111000000 \ No newline at end of file Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_Init_Vals.csv =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_Init_Vals.csv (revision 8) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_Init_Vals.csv (nonexistent) @@ -1,128 +0,0 @@ -00,01101111000000 -01,11111111111001 -02,11111100100100 -03,11111101110000 -04,11111100011001 -05,11011110010110 -06,11111100000010 -07,11111111111000 -08,11111100000000 -09,11111100010000 -0A,11111100001000 -0B,10110101110000 -0C,11111111000110 -0D,10110111110000 -0E,11111100000110 -0F,11111110001110 -10,11111111111111 -11,11111111111111 -12,11111111111111 -13,11111111111111 -14,11111111111111 -15,11111111111111 -16,11111111111111 -17,11111111111111 -18,10110100110110 -19,10101000111111 -1A,10110100000110 -1B,11111100011100 -1C,11101011001111 -1D,10110100110111 -1E,00010111111111 -1F,10100011111111 -20,11111111111111 -21,11111111111001 -22,11110111011111 -23,00000000000000 -24,10110100010010 -25,01001000011011 -26,01001011110010 -27,11101111111111 -28,11001111111111 -29,01111011111111 -2A,00000000111111 -2B,10110100111111 -2C,01111111111111 -2D,11111100111111 -2E,10111110100111 -2F,01101111111111 -30,01101111000000 -31,11111111111001 -32,11111100100100 -33,11111101110000 -34,11111100011001 -35,11011110010110 -36,11111100000010 -37,11111111111000 -38,11111100000000 -39,11111100010000 -3A,10110111111111 -3B,01110111111111 -3C,11001111111111 -3D,11111100110111 -3E,01111011111111 -3F,10111101111100 -40,11110101000100 -41,11111100001000 -42,10110101110000 -43,11111111000110 -44,10110111110000 -45,11111100000110 -46,11111110001110 -47,11111101000010 -48,11111100001001 -49,10110111111111 -4A,11111111100001 -4B,11001110001111 -4C,11111111000111 -4D,11101011001001 -4E,11011011001001 -4F,11111111000000 -50,11111100001100 -51,11011111000000 -52,11011100001100 -53,11111100010010 -54,10110111111110 -55,11111111000001 -56,01101111001111 -57,01011111001001 -58,01001011111111 -59,10101011111111 -5A,01101111110110 -5B,11111111000110 -5C,11011011111111 -5D,11111111110000 -5E,01101111111100 -5F,11111111110111 -60,11111011111111 -61,11111100001000 -62,10110101110000 -63,11111111000110 -64,10110111110000 -65,11111100000110 -66,11111110001110 -67,11111101000010 -68,11111100001001 -69,10110111111111 -6A,11111111100001 -6B,11001110001111 -6C,11111111000111 -6D,11101011001001 -6E,11011011001001 -6F,11111111000000 -70,11111100001100 -71,11011111000000 -72,11011100001100 -73,11111100010010 -74,10110111111110 -75,11111111000001 -76,01101111001111 -77,01011111001001 -78,01001011111111 -79,10101011111111 -7A,01101111110110 -7B,11001110111111 -7C,10110111111111 -7D,01111001111111 -7E,11111100101101 -7F,11111111000000 \ No newline at end of file Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/Dist_ROM_ASCII_Decoder.lpc =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/Dist_ROM_ASCII_Decoder.lpc (revision 8) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/Dist_ROM_ASCII_Decoder.lpc (nonexistent) @@ -1,40 +0,0 @@ -[Device] -Family=ecp5um5g -PartType=LFE5UM5G-45F -PartName=LFE5UM5G-45F-8BG381C -SpeedGrade=8 -Package=CABGA381 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=Distributed_ROM -CoreRevision=2.8 -ModuleName=Dist_ROM_ASCII_Decoder -SourceFormat=vhdl -ParameterFileVersion=1.0 -Date=01/13/2017 -Time=23:10:29 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -Addresses=127 -Data=14 -LUT=0 -MemFile=c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem -MemFormat=bin - -[FilesGenerated] -c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem=mem - -[Command] -cmd_line= -w -n Dist_ROM_ASCII_Decoder -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -dram -type romblk -addr_width 7 -num_words 127 -data_width 14 -outdata UNREGISTERED -memfile c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem -memformat bin Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/tb_DistRomAsciiDecoder_tmpl.vhd =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/tb_DistRomAsciiDecoder_tmpl.vhd (revision 8) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/tb_DistRomAsciiDecoder_tmpl.vhd (nonexistent) @@ -1,42 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.8.0.115.3 -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -use IEEE.math_real.all; - -use IEEE.numeric_std.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component DistRomAsciiDecoder - port (Address : in std_logic_vector(6 downto 0); - Q : out std_logic_vector(13 downto 0) - ); - end component; - - signal Address : std_logic_vector(6 downto 0) := (others => '0'); - signal Q : std_logic_vector(13 downto 0); -begin - u1 : DistRomAsciiDecoder - port map (Address => Address, Q => Q - ); - - process - - begin - Address <= (others => '0') ; - wait for 100 ns; - wait for 10 ns; - for i in 0 to 131 loop - wait for 10 ns; - Address <= Address + '1' ; - end loop; - wait; - end process; - -end architecture test;
single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/tb_DistRomAsciiDecoder_tmpl.vhd Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.naf =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.naf (revision 8) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.naf (nonexistent) @@ -1,2 +0,0 @@ -Address i -Q o Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.srp =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.srp (revision 8) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.srp (nonexistent) @@ -1,30 +0,0 @@ -SCUBA, Version Diamond (64-bit) 3.8.0.115.3 -Fri Jan 13 23:14:11 2017 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : C:\lscc\diamond\3.8_x64\ispfpga\bin\nt64\scuba.exe -w -n DistRomAsciiDecoder -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -dram -type romblk -addr_width 7 -num_words 128 -data_width 14 -outdata UNREGISTERED -memfile c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem -memformat bin -fdc C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.fdc - Circuit name : DistRomAsciiDecoder - Module type : rom - Module Version : 2.8 - Address width : 7 - Ports : - Inputs : Address[6:0] - Outputs : Q[13:0] - I/O buffer : not inserted - Memory file : c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem - EDIF output : DistRomAsciiDecoder.edn - VHDL output : DistRomAsciiDecoder.vhd - VHDL template : DistRomAsciiDecoder_tmpl.vhd - VHDL testbench : tb_DistRomAsciiDecoder_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : DistRomAsciiDecoder.srp - Element Usage : - ROM128X1A : 14 - Estimated Resource Usage: - LUT : 56 Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/generate_core.tcl =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/generate_core.tcl (revision 8) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/generate_core.tcl (nonexistent) @@ -1,100 +0,0 @@ -#!/usr/local/bin/wish - -proc GetPlatform {} { - global tcl_platform - - set cpu $tcl_platform(machine) - - switch $cpu { - intel - - i*86* { - set cpu ix86 - } - x86_64 { - if {$tcl_platform(wordSize) == 4} { - set cpu ix86 - } - } - } - - switch $tcl_platform(platform) { - windows { - if {$cpu == "amd64"} { - # Do not check wordSize, win32-x64 is an IL32P64 platform. - set cpu x86_64 - } - if {$cpu == "x86_64"} { - return "nt64" - } else { - return "nt" - } - } - unix { - if {$tcl_platform(os) == "Linux"} { - if {$cpu == "x86_64"} { - return "lin64" - } else { - return "lin" - } - } else { - return "sol" - } - } - } - return "nt" -} - -proc GetCmdLine {lpcfile} { - global Para - - if [catch {open $lpcfile r} fileid] { - puts "Cannot open $para_file file!" - exit -1 - } - - seek $fileid 0 start - set default_match 0 - while {[gets $fileid line] >= 0} { - if {[string first "\[Command\]" $line] == 0} { - set default_match 1 - continue - } - if {[string first "\[" $line] == 0} { - set default_match 0 - } - if {$default_match == 1} { - if [regexp {([^=]*)=(.*)} $line match parameter value] { - if [regexp {([ |\t]*;)} $parameter match] {continue} - if [regexp {(.*)[ |\t]*;} $value match temp] { - set Para($parameter) $temp - } else { - set Para($parameter) $value - } - } - } - } - set default_match 0 - close $fileid - - return $Para(cmd_line) -} - -set platformpath [GetPlatform] -set Para(sbp_path) [file dirname [info script]] -set Para(install_dir) $env(TOOLRTF) -set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" - -set scuba "$Para(FPGAPath)/scuba" -set modulename "DistRomAsciiDecoder" -set lang "vhdl" -set lpcfile "$Para(sbp_path)/$modulename.lpc" -set arch "sa5p00g" -set cmd_line [GetCmdLine $lpcfile] -set fdcfile "$Para(sbp_path)/$modulename.fdc" -if {[file exists $fdcfile] == 0} { - append scuba " " $cmd_line -} else { - append scuba " " $cmd_line " " -fdc " " \"$fdcfile\" -} -set Para(result) [catch {eval exec "$scuba"} msg] -#puts $msg Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.jhd =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.jhd (revision 8) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.jhd (nonexistent) @@ -1,2 +0,0 @@ -VHDL_ENTITY_ONLY DistRomAsciiDecoder DEFIN DistRomAsciiDecoder.vhd -MODULE DistRomAsciiDecoder DEFIN DistRomAsciiDecoder.vhd Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.edn =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.edn (revision 8) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.edn (nonexistent) @@ -1,294 +0,0 @@ -(edif DistRomAsciiDecoder - (edifVersion 2 0 0) - (edifLevel 0) - (keywordMap (keywordLevel 0)) - (status - (written - (timestamp 2017 1 13 23 14 11) - (program "SCUBA" (version "Diamond (64-bit) 3.8.0.115.3")))) - (comment "C:\lscc\diamond\3.8_x64\ispfpga\bin\nt64\scuba.exe -w -n DistRomAsciiDecoder -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -type rom -addr_width 7 -num_rows 128 -data_width 14 -outdata UNREGISTERED -memfile c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem -memformat bin -fdc C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.fdc ") - (library ORCLIB - (edifLevel 0) - (technology - (numberDefinition)) - (cell ROM128X1A - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port AD6 - (direction INPUT)) - (port AD5 - (direction INPUT)) - (port AD4 - (direction INPUT)) - (port AD3 - (direction INPUT)) - (port AD2 - (direction INPUT)) - (port AD1 - (direction INPUT)) - (port AD0 - (direction INPUT)) - (port DO0 - (direction OUTPUT))))) - (cell DistRomAsciiDecoder - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port (array (rename Address "Address(6:0)") 7) - (direction INPUT)) - (port (array (rename Q "Q(13:0)") 14) - (direction OUTPUT))) - (property NGD_DRC_MASK (integer 1)) - (contents - (instance mem_0_13 - (viewRef view1 - (cellRef ROM128X1A)) - (property initval - (string "0xDA3FFFFFBA3FFFFFB7FE6997BFFFFFFE"))) - (instance mem_0_12 - (viewRef view1 - (cellRef ROM128X1A)) - (property initval - (string "0xEDEFFDEBFDEFFDEB7BFFB3E718FFD7FF"))) - (instance mem_0_11 - (viewRef view1 - (cellRef ROM128X1A)) - (property initval - (string "0xF679B7FFEE79B7FFEFDFFA97BFFFFFDF"))) - (instance mem_0_10 - (viewRef view1 - (cellRef ROM128X1A)) - (property initval - (string "0xF0BFD7FFB8BFD7FFEFFE7A176DFFFFFE"))) - (instance mem_0_9 - (viewRef view1 - (cellRef ROM128X1A)) - (property initval - (string "0xEFEFFDEBFFEFFDEAF3FFF3E31AFFD7FF"))) - (instance mem_0_8 - (viewRef view1 - (cellRef ROM128X1A)) - (property initval - (string "0xDCFF9FFEECFF9FFFBFFFF9976DFFFFFF"))) - (instance mem_0_7 - (viewRef view1 - (cellRef ROM128X1A)) - (property initval - (string "0x9FF2FE59FFF2FE585CA3D3C7D0FFB0A3"))) - (instance mem_0_6 - (viewRef view1 - (cellRef ROM128X1A)) - (property initval - (string "0xB7F2F69DFFF2F69DDC8B93C7D0FF388B"))) - (instance mem_0_5 - (viewRef view1 - (cellRef ROM128X1A)) - (property initval - (string "0x7F100615F7100614FC8EFFC3E3FF288E"))) - (instance mem_0_4 - (viewRef view1 - (cellRef ROM128X1A)) - (property initval - (string "0x3F180215F7180214FEBABFF7EBFF2ABA"))) - (instance mem_0_3 - (viewRef view1 - (cellRef ROM128X1A)) - (property initval - (string "0x7BD56B4353D56B42DC92BFA7DAFF8492"))) - (instance mem_0_2 - (viewRef view1 - (cellRef ROM128X1A)) - (property initval - (string "0x7F551A69DF551A69FC24FF85FFFFD024"))) - (instance mem_0_1 - (viewRef view1 - (cellRef ROM128X1A)) - (property initval - (string "0x3F581AE99F581AE87C60FFF5F7FFD060"))) - (instance mem_0_0 - (viewRef view1 - (cellRef ROM128X1A)) - (property initval - (string "0x7BE07F0193E07F007C12FFA7F2FF0012"))) - (net qdataout13 - (joined - (portRef (member Q 0)) - (portRef DO0 (instanceRef mem_0_13)))) - (net qdataout12 - (joined - (portRef (member Q 1)) - (portRef DO0 (instanceRef mem_0_12)))) - (net qdataout11 - (joined - (portRef (member Q 2)) - (portRef DO0 (instanceRef mem_0_11)))) - (net qdataout10 - (joined - (portRef (member Q 3)) - (portRef DO0 (instanceRef mem_0_10)))) - (net qdataout9 - (joined - (portRef (member Q 4)) - (portRef DO0 (instanceRef mem_0_9)))) - (net qdataout8 - (joined - (portRef (member Q 5)) - (portRef DO0 (instanceRef mem_0_8)))) - (net qdataout7 - (joined - (portRef (member Q 6)) - (portRef DO0 (instanceRef mem_0_7)))) - (net qdataout6 - (joined - (portRef (member Q 7)) - (portRef DO0 (instanceRef mem_0_6)))) - (net qdataout5 - (joined - (portRef (member Q 8)) - (portRef DO0 (instanceRef mem_0_5)))) - (net qdataout4 - (joined - (portRef (member Q 9)) - (portRef DO0 (instanceRef mem_0_4)))) - (net qdataout3 - (joined - (portRef (member Q 10)) - (portRef DO0 (instanceRef mem_0_3)))) - (net qdataout2 - (joined - (portRef (member Q 11)) - (portRef DO0 (instanceRef mem_0_2)))) - (net qdataout1 - (joined - (portRef (member Q 12)) - (portRef DO0 (instanceRef mem_0_1)))) - (net qdataout0 - (joined - (portRef (member Q 13)) - (portRef DO0 (instanceRef mem_0_0)))) - (net addr6 - (joined - (portRef (member Address 0)) - (portRef AD6 (instanceRef mem_0_13)) - (portRef AD6 (instanceRef mem_0_12)) - (portRef AD6 (instanceRef mem_0_11)) - (portRef AD6 (instanceRef mem_0_10)) - (portRef AD6 (instanceRef mem_0_9)) - (portRef AD6 (instanceRef mem_0_8)) - (portRef AD6 (instanceRef mem_0_7)) - (portRef AD6 (instanceRef mem_0_6)) - (portRef AD6 (instanceRef mem_0_5)) - (portRef AD6 (instanceRef mem_0_4)) - (portRef AD6 (instanceRef mem_0_3)) - (portRef AD6 (instanceRef mem_0_2)) - (portRef AD6 (instanceRef mem_0_1)) - (portRef AD6 (instanceRef mem_0_0)))) - (net addr5 - (joined - (portRef (member Address 1)) - (portRef AD5 (instanceRef mem_0_13)) - (portRef AD5 (instanceRef mem_0_12)) - (portRef AD5 (instanceRef mem_0_11)) - (portRef AD5 (instanceRef mem_0_10)) - (portRef AD5 (instanceRef mem_0_9)) - (portRef AD5 (instanceRef mem_0_8)) - (portRef AD5 (instanceRef mem_0_7)) - (portRef AD5 (instanceRef mem_0_6)) - (portRef AD5 (instanceRef mem_0_5)) - (portRef AD5 (instanceRef mem_0_4)) - (portRef AD5 (instanceRef mem_0_3)) - (portRef AD5 (instanceRef mem_0_2)) - (portRef AD5 (instanceRef mem_0_1)) - (portRef AD5 (instanceRef mem_0_0)))) - (net addr4 - (joined - (portRef (member Address 2)) - (portRef AD4 (instanceRef mem_0_13)) - (portRef AD4 (instanceRef mem_0_12)) - (portRef AD4 (instanceRef mem_0_11)) - (portRef AD4 (instanceRef mem_0_10)) - (portRef AD4 (instanceRef mem_0_9)) - (portRef AD4 (instanceRef mem_0_8)) - (portRef AD4 (instanceRef mem_0_7)) - (portRef AD4 (instanceRef mem_0_6)) - (portRef AD4 (instanceRef mem_0_5)) - (portRef AD4 (instanceRef mem_0_4)) - (portRef AD4 (instanceRef mem_0_3)) - (portRef AD4 (instanceRef mem_0_2)) - (portRef AD4 (instanceRef mem_0_1)) - (portRef AD4 (instanceRef mem_0_0)))) - (net addr3 - (joined - (portRef (member Address 3)) - (portRef AD3 (instanceRef mem_0_13)) - (portRef AD3 (instanceRef mem_0_12)) - (portRef AD3 (instanceRef mem_0_11)) - (portRef AD3 (instanceRef mem_0_10)) - (portRef AD3 (instanceRef mem_0_9)) - (portRef AD3 (instanceRef mem_0_8)) - (portRef AD3 (instanceRef mem_0_7)) - (portRef AD3 (instanceRef mem_0_6)) - (portRef AD3 (instanceRef mem_0_5)) - (portRef AD3 (instanceRef mem_0_4)) - (portRef AD3 (instanceRef mem_0_3)) - (portRef AD3 (instanceRef mem_0_2)) - (portRef AD3 (instanceRef mem_0_1)) - (portRef AD3 (instanceRef mem_0_0)))) - (net addr2 - (joined - (portRef (member Address 4)) - (portRef AD2 (instanceRef mem_0_13)) - (portRef AD2 (instanceRef mem_0_12)) - (portRef AD2 (instanceRef mem_0_11)) - (portRef AD2 (instanceRef mem_0_10)) - (portRef AD2 (instanceRef mem_0_9)) - (portRef AD2 (instanceRef mem_0_8)) - (portRef AD2 (instanceRef mem_0_7)) - (portRef AD2 (instanceRef mem_0_6)) - (portRef AD2 (instanceRef mem_0_5)) - (portRef AD2 (instanceRef mem_0_4)) - (portRef AD2 (instanceRef mem_0_3)) - (portRef AD2 (instanceRef mem_0_2)) - (portRef AD2 (instanceRef mem_0_1)) - (portRef AD2 (instanceRef mem_0_0)))) - (net addr1 - (joined - (portRef (member Address 5)) - (portRef AD1 (instanceRef mem_0_13)) - (portRef AD1 (instanceRef mem_0_12)) - (portRef AD1 (instanceRef mem_0_11)) - (portRef AD1 (instanceRef mem_0_10)) - (portRef AD1 (instanceRef mem_0_9)) - (portRef AD1 (instanceRef mem_0_8)) - (portRef AD1 (instanceRef mem_0_7)) - (portRef AD1 (instanceRef mem_0_6)) - (portRef AD1 (instanceRef mem_0_5)) - (portRef AD1 (instanceRef mem_0_4)) - (portRef AD1 (instanceRef mem_0_3)) - (portRef AD1 (instanceRef mem_0_2)) - (portRef AD1 (instanceRef mem_0_1)) - (portRef AD1 (instanceRef mem_0_0)))) - (net addr0 - (joined - (portRef (member Address 6)) - (portRef AD0 (instanceRef mem_0_13)) - (portRef AD0 (instanceRef mem_0_12)) - (portRef AD0 (instanceRef mem_0_11)) - (portRef AD0 (instanceRef mem_0_10)) - (portRef AD0 (instanceRef mem_0_9)) - (portRef AD0 (instanceRef mem_0_8)) - (portRef AD0 (instanceRef mem_0_7)) - (portRef AD0 (instanceRef mem_0_6)) - (portRef AD0 (instanceRef mem_0_5)) - (portRef AD0 (instanceRef mem_0_4)) - (portRef AD0 (instanceRef mem_0_3)) - (portRef AD0 (instanceRef mem_0_2)) - (portRef AD0 (instanceRef mem_0_1)) - (portRef AD0 (instanceRef mem_0_0)))))))) - (design DistRomAsciiDecoder - (cellRef DistRomAsciiDecoder - (libraryRef ORCLIB))) -) Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.sym =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.sym =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.sym (revision 8) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.sym (nonexistent)
single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.sym Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder_tmpl.vhd =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder_tmpl.vhd (revision 8) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder_tmpl.vhd (nonexistent) @@ -1,13 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.8.0.115.3 --- Module Version: 2.8 --- Fri Jan 13 23:14:11 2017 - --- parameterized module component declaration -component DistRomAsciiDecoder - port (Address: in std_logic_vector(6 downto 0); - Q: out std_logic_vector(13 downto 0)); -end component; - --- parameterized module component instance -__ : DistRomAsciiDecoder - port map (Address(6 downto 0)=>__, Q(13 downto 0)=>__);
single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder_tmpl.vhd Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.lpc =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.lpc (revision 8) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.lpc (nonexistent) @@ -1,40 +0,0 @@ -[Device] -Family=ecp5um5g -PartType=LFE5UM5G-45F -PartName=LFE5UM5G-45F-8BG381C -SpeedGrade=8 -Package=CABGA381 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=Distributed_ROM -CoreRevision=2.8 -ModuleName=DistRomAsciiDecoder -SourceFormat=vhdl -ParameterFileVersion=1.0 -Date=01/13/2017 -Time=23:14:03 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -Addresses=128 -Data=14 -LUT=0 -MemFile=c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem -MemFormat=bin - -[FilesGenerated] -c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem=mem - -[Command] -cmd_line= -w -n DistRomAsciiDecoder -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -dram -type romblk -addr_width 7 -num_words 128 -data_width 14 -outdata UNREGISTERED -memfile c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem -memformat bin Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd (revision 8) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd (nonexistent) @@ -1,109 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond (64-bit) 3.8.0.115.3 --- Module Version: 2.8 ---C:\lscc\diamond\3.8_x64\ispfpga\bin\nt64\scuba.exe -w -n DistRomAsciiDecoder -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -type rom -addr_width 7 -num_rows 128 -data_width 14 -outdata UNREGISTERED -memfile c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem -memformat bin -fdc C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.fdc - --- Fri Jan 13 23:14:11 2017 - -library IEEE; -use IEEE.std_logic_1164.all; -library ecp5um; -use ecp5um.components.all; - -entity DistRomAsciiDecoder is - port ( - Address: in std_logic_vector(6 downto 0); - Q: out std_logic_vector(13 downto 0)); -end DistRomAsciiDecoder; - -architecture Structure of DistRomAsciiDecoder is - - attribute NGD_DRC_MASK : integer; - attribute NGD_DRC_MASK of Structure : architecture is 1; - -begin - -- component instantiation statements - mem_0_13: ROM128X1A - generic map (initval=> X"DA3FFFFFBA3FFFFFB7FE6997BFFFFFFE") - port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), - AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), - AD0=>Address(0), DO0=>Q(13)); - - mem_0_12: ROM128X1A - generic map (initval=> X"EDEFFDEBFDEFFDEB7BFFB3E718FFD7FF") - port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), - AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), - AD0=>Address(0), DO0=>Q(12)); - - mem_0_11: ROM128X1A - generic map (initval=> X"F679B7FFEE79B7FFEFDFFA97BFFFFFDF") - port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), - AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), - AD0=>Address(0), DO0=>Q(11)); - - mem_0_10: ROM128X1A - generic map (initval=> X"F0BFD7FFB8BFD7FFEFFE7A176DFFFFFE") - port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), - AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), - AD0=>Address(0), DO0=>Q(10)); - - mem_0_9: ROM128X1A - generic map (initval=> X"EFEFFDEBFFEFFDEAF3FFF3E31AFFD7FF") - port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), - AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), - AD0=>Address(0), DO0=>Q(9)); - - mem_0_8: ROM128X1A - generic map (initval=> X"DCFF9FFEECFF9FFFBFFFF9976DFFFFFF") - port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), - AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), - AD0=>Address(0), DO0=>Q(8)); - - mem_0_7: ROM128X1A - generic map (initval=> X"9FF2FE59FFF2FE585CA3D3C7D0FFB0A3") - port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), - AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), - AD0=>Address(0), DO0=>Q(7)); - - mem_0_6: ROM128X1A - generic map (initval=> X"B7F2F69DFFF2F69DDC8B93C7D0FF388B") - port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), - AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), - AD0=>Address(0), DO0=>Q(6)); - - mem_0_5: ROM128X1A - generic map (initval=> X"7F100615F7100614FC8EFFC3E3FF288E") - port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), - AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), - AD0=>Address(0), DO0=>Q(5)); - - mem_0_4: ROM128X1A - generic map (initval=> X"3F180215F7180214FEBABFF7EBFF2ABA") - port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), - AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), - AD0=>Address(0), DO0=>Q(4)); - - mem_0_3: ROM128X1A - generic map (initval=> X"7BD56B4353D56B42DC92BFA7DAFF8492") - port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), - AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), - AD0=>Address(0), DO0=>Q(3)); - - mem_0_2: ROM128X1A - generic map (initval=> X"7F551A69DF551A69FC24FF85FFFFD024") - port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), - AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), - AD0=>Address(0), DO0=>Q(2)); - - mem_0_1: ROM128X1A - generic map (initval=> X"3F581AE99F581AE87C60FFF5F7FFD060") - port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), - AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), - AD0=>Address(0), DO0=>Q(1)); - - mem_0_0: ROM128X1A - generic map (initval=> X"7BE07F0193E07F007C12FFA7F2FF0012") - port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), - AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), - AD0=>Address(0), DO0=>Q(0)); - -end Structure;
single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/generate_ngd.tcl =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/generate_ngd.tcl (revision 8) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/generate_ngd.tcl (nonexistent) @@ -1,74 +0,0 @@ -#!/usr/local/bin/wish - -proc GetPlatform {} { - global tcl_platform - - set cpu $tcl_platform(machine) - - switch $cpu { - intel - - i*86* { - set cpu ix86 - } - x86_64 { - if {$tcl_platform(wordSize) == 4} { - set cpu ix86 - } - } - } - - switch $tcl_platform(platform) { - windows { - if {$cpu == "amd64"} { - # Do not check wordSize, win32-x64 is an IL32P64 platform. - set cpu x86_64 - } - if {$cpu == "x86_64"} { - return "nt64" - } else { - return "nt" - } - } - unix { - if {$tcl_platform(os) == "Linux"} { - if {$cpu == "x86_64"} { - return "lin64" - } else { - return "lin" - } - } else { - return "sol" - } - } - } - return "nt" -} - -set platformpath [GetPlatform] -set Para(sbp_path) [file dirname [info script]] -set Para(install_dir) $env(TOOLRTF) -set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" -set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]" - -set Para(ModuleName) "DistRomAsciiDecoder" -set Para(Module) "Distributed_ROM" -set Para(libname) ecp5um5g -set Para(arch_name) sa5p00g -set Para(PartType) "LFE5UM5G-45F" - -set Para(tech_syn) ecp5um5g -set Para(tech_cae) ecp5um5g -set Para(Package) "CABGA381" -set Para(SpeedGrade) "8" -set Para(FMax) "100" -set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc" - -#edif2ngd -set edif2ngd "$Para(FPGAPath)/edif2ngd" -set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn $Para(ModuleName).edn $Para(ModuleName).ngo} msg] -#puts $msg - -#ngdbuild -set ngdbuild "$Para(FPGAPath)/ngdbuild" -set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg] -#puts $msg Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/._Real_._Math_.vhd =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/._Real_._Math_.vhd (revision 8) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/._Real_._Math_.vhd (nonexistent) @@ -1,2574 +0,0 @@ - - ------------------------------------------------------------------------- --- --- Copyright 1996 by IEEE. All rights reserved. --- --- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard --- VHDL Mathematical Packages. This source file may not be copied, sold, or --- included with software that is sold without written permission from the IEEE --- Standards Department. This source file may be used to implement this standard --- and may be distributed in compiled form in any manner so long as the --- compiled form does not allow direct decompilation of the original source file. --- This source file may be copied for individual use between licensed users. --- This source file is provided on an AS IS basis. The IEEE disclaims ANY --- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY --- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source --- file shall indemnify and hold IEEE harmless from any damages or liability --- arising out of the use thereof. --- --- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, --- MATH_REAL) --- --- Library: This package shall be compiled into a library --- symbolically named IEEE. --- --- Developers: IEEE DASC VHDL Mathematical Packages Working Group --- --- Purpose: This package defines a standard for designers to use in --- describing VHDL models that make use of common REAL constants --- and common REAL elementary mathematical functions. --- --- Limitation: The values generated by the functions in this package may --- vary from platform to platform, and the precision of results --- is only guaranteed to be the minimum required by IEEE Std 1076- --- 1993. --- --- Notes: --- No declarations or definitions shall be included in, or --- excluded from, this package. --- The "package declaration" defines the types, subtypes, and --- declarations of MATH_REAL. --- The standard mathematical definition and conventional meaning --- of the mathematical functions that are part of this standard --- represent the formal semantics of the implementation of the --- MATH_REAL package declaration. The purpose of the MATH_REAL --- package body is to provide a guideline for implementations to --- verify their implementation of MATH_REAL. Tool developers may --- choose to implement the package body in the most efficient --- manner available to them. --- --- ----------------------------------------------------------------------------- --- Version : 1.5 --- Date : 24 July 1996 --- ----------------------------------------------------------------------------- - -package MATH_REAL is - constant CopyRightNotice: STRING - := "Copyright 1996 IEEE. All rights reserved."; - - -- - -- Constant Definitions - -- - constant MATH_E : REAL := 2.71828_18284_59045_23536; - -- Value of e - constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160; - -- Value of 1/e - constant MATH_PI : REAL := 3.14159_26535_89793_23846; - -- Value of pi - constant MATH_2_PI : REAL := 6.28318_53071_79586_47693; - -- Value of 2*pi - constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154; - -- Value of 1/pi - constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923; - -- Value of pi/2 - constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615; - -- Value of pi/3 - constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962; - -- Value of pi/4 - constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769; - -- Value 3*pi/2 - constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942; - -- Natural log of 2 - constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402; - -- Natural log of 10 - constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074; - -- Log base 2 of e - constant MATH_LOG10_OF_E: REAL := 0.43429_44819_03251_82765; - -- Log base 10 of e - constant MATH_SQRT_2: REAL := 1.41421_35623_73095_04880; - -- square root of 2 - constant MATH_1_OVER_SQRT_2: REAL := 0.70710_67811_86547_52440; - -- square root of 1/2 - constant MATH_SQRT_PI: REAL := 1.77245_38509_05516_02730; - -- square root of pi - constant MATH_DEG_TO_RAD: REAL := 0.01745_32925_19943_29577; - -- Conversion factor from degree to radian - constant MATH_RAD_TO_DEG: REAL := 57.29577_95130_82320_87680; - -- Conversion factor from radian to degree - - -- - -- Function Declarations - -- - function SIGN (X: in REAL ) return REAL; - -- Purpose: - -- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0 - -- Special values: - -- None - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ABS(SIGN(X)) <= 1.0 - -- Notes: - -- None - - function CEIL (X : in REAL ) return REAL; - -- Purpose: - -- Returns smallest INTEGER value (as REAL) not less than X - -- Special values: - -- None - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- CEIL(X) is mathematically unbounded - -- Notes: - -- a) Implementations have to support at least the domain - -- ABS(X) < REAL(INTEGER'HIGH) - - function FLOOR (X : in REAL ) return REAL; - -- Purpose: - -- Returns largest INTEGER value (as REAL) not greater than X - -- Special values: - -- FLOOR(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- FLOOR(X) is mathematically unbounded - -- Notes: - -- a) Implementations have to support at least the domain - -- ABS(X) < REAL(INTEGER'HIGH) - - function ROUND (X : in REAL ) return REAL; - -- Purpose: - -- Rounds X to the nearest integer value (as real). If X is - -- halfway between two integers, rounding is away from 0.0 - -- Special values: - -- ROUND(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ROUND(X) is mathematically unbounded - -- Notes: - -- a) Implementations have to support at least the domain - -- ABS(X) < REAL(INTEGER'HIGH) - - function TRUNC (X : in REAL ) return REAL; - -- Purpose: - -- Truncates X towards 0.0 and returns truncated value - -- Special values: - -- TRUNC(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- TRUNC(X) is mathematically unbounded - -- Notes: - -- a) Implementations have to support at least the domain - -- ABS(X) < REAL(INTEGER'HIGH) - - function "MOD" (X, Y: in REAL ) return REAL; - -- Purpose: - -- Returns floating point modulus of X/Y, with the same sign as - -- Y, and absolute value less than the absolute value of Y, and - -- for some INTEGER value N the result satisfies the relation - -- X = Y*N + MOD(X,Y) - -- Special values: - -- None - -- Domain: - -- X in REAL; Y in REAL and Y /= 0.0 - -- Error conditions: - -- Error if Y = 0.0 - -- Range: - -- ABS(MOD(X,Y)) < ABS(Y) - -- Notes: - -- None - - function REALMAX (X, Y : in REAL ) return REAL; - -- Purpose: - -- Returns the algebraically larger of X and Y - -- Special values: - -- REALMAX(X,Y) = X when X = Y - -- Domain: - -- X in REAL; Y in REAL - -- Error conditions: - -- None - -- Range: - -- REALMAX(X,Y) is mathematically unbounded - -- Notes: - -- None - - function REALMIN (X, Y : in REAL ) return REAL; - -- Purpose: - -- Returns the algebraically smaller of X and Y - -- Special values: - -- REALMIN(X,Y) = X when X = Y - -- Domain: - -- X in REAL; Y in REAL - -- Error conditions: - -- None - -- Range: - -- REALMIN(X,Y) is mathematically unbounded - -- Notes: - -- None - - procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE; variable X:out REAL); - -- Purpose: - -- Returns, in X, a pseudo-random number with uniform - -- distribution in the open interval (0.0, 1.0). - -- Special values: - -- None - -- Domain: - -- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398 - -- Error conditions: - -- Error if SEED1 or SEED2 outside of valid domain - -- Range: - -- 0.0 < X < 1.0 - -- Notes: - -- a) The semantics for this function are described by the - -- algorithm published by Pierre L'Ecuyer in "Communications - -- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774. - -- The algorithm is based on the combination of two - -- multiplicative linear congruential generators for 32-bit - -- platforms. - -- - -- b) Before the first call to UNIFORM, the seed values - -- (SEED1, SEED2) have to be initialized to values in the range - -- [1, 2147483562] and [1, 2147483398] respectively. The - -- seed values are modified after each call to UNIFORM. - -- - -- c) This random number generator is portable for 32-bit - -- computers, and it has a period of ~2.30584*(10**18) for each - -- set of seed values. - -- - -- d) For information on spectral tests for the algorithm, refer - -- to the L'Ecuyer article. - - function SQRT (X : in REAL ) return REAL; - -- Purpose: - -- Returns square root of X - -- Special values: - -- SQRT(0.0) = 0.0 - -- SQRT(1.0) = 1.0 - -- Domain: - -- X >= 0.0 - -- Error conditions: - -- Error if X < 0.0 - -- Range: - -- SQRT(X) >= 0.0 - -- Notes: - -- a) The upper bound of the reachable range of SQRT is - -- approximately given by: - -- SQRT(X) <= SQRT(REAL'HIGH) - - function CBRT (X : in REAL ) return REAL; - -- Purpose: - -- Returns cube root of X - -- Special values: - -- CBRT(0.0) = 0.0 - -- CBRT(1.0) = 1.0 - -- CBRT(-1.0) = -1.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- CBRT(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of CBRT is approximately given by: - -- ABS(CBRT(X)) <= CBRT(REAL'HIGH) - - function "**" (X : in INTEGER; Y : in REAL) return REAL; - -- Purpose: - -- Returns Y power of X ==> X**Y - -- Special values: - -- X**0.0 = 1.0; X /= 0 - -- 0**Y = 0.0; Y > 0.0 - -- X**1.0 = REAL(X); X >= 0 - -- 1**Y = 1.0 - -- Domain: - -- X > 0 - -- X = 0 for Y > 0.0 - -- X < 0 for Y = 0.0 - -- Error conditions: - -- Error if X < 0 and Y /= 0.0 - -- Error if X = 0 and Y <= 0.0 - -- Range: - -- X**Y >= 0.0 - -- Notes: - -- a) The upper bound of the reachable range for "**" is - -- approximately given by: - -- X**Y <= REAL'HIGH - - function "**" (X : in REAL; Y : in REAL) return REAL; - -- Purpose: - -- Returns Y power of X ==> X**Y - -- Special values: - -- X**0.0 = 1.0; X /= 0.0 - -- 0.0**Y = 0.0; Y > 0.0 - -- X**1.0 = X; X >= 0.0 - -- 1.0**Y = 1.0 - -- Domain: - -- X > 0.0 - -- X = 0.0 for Y > 0.0 - -- X < 0.0 for Y = 0.0 - -- Error conditions: - -- Error if X < 0.0 and Y /= 0.0 - -- Error if X = 0.0 and Y <= 0.0 - -- Range: - -- X**Y >= 0.0 - -- Notes: - -- a) The upper bound of the reachable range for "**" is - -- approximately given by: - -- X**Y <= REAL'HIGH - - function EXP (X : in REAL ) return REAL; - -- Purpose: - -- Returns e**X; where e = MATH_E - -- Special values: - -- EXP(0.0) = 1.0 - -- EXP(1.0) = MATH_E - -- EXP(-1.0) = MATH_1_OVER_E - -- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH) - -- Domain: - -- X in REAL such that EXP(X) <= REAL'HIGH - -- Error conditions: - -- Error if X > LOG(REAL'HIGH) - -- Range: - -- EXP(X) >= 0.0 - -- Notes: - -- a) The usable domain of EXP is approximately given by: - -- X <= LOG(REAL'HIGH) - - function LOG (X : in REAL ) return REAL; - -- Purpose: - -- Returns natural logarithm of X - -- Special values: - -- LOG(1.0) = 0.0 - -- LOG(MATH_E) = 1.0 - -- Domain: - -- X > 0.0 - -- Error conditions: - -- Error if X <= 0.0 - -- Range: - -- LOG(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of LOG is approximately given by: - -- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH) - - function LOG2 (X : in REAL ) return REAL; - -- Purpose: - -- Returns logarithm base 2 of X - -- Special values: - -- LOG2(1.0) = 0.0 - -- LOG2(2.0) = 1.0 - -- Domain: - -- X > 0.0 - -- Error conditions: - -- Error if X <= 0.0 - -- Range: - -- LOG2(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of LOG2 is approximately given by: - -- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH) - - function LOG10 (X : in REAL ) return REAL; - -- Purpose: - -- Returns logarithm base 10 of X - -- Special values: - -- LOG10(1.0) = 0.0 - -- LOG10(10.0) = 1.0 - -- Domain: - -- X > 0.0 - -- Error conditions: - -- Error if X <= 0.0 - -- Range: - -- LOG10(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of LOG10 is approximately given by: - -- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH) - - function LOG (X: in REAL; BASE: in REAL) return REAL; - -- Purpose: - -- Returns logarithm base BASE of X - -- Special values: - -- LOG(1.0, BASE) = 0.0 - -- LOG(BASE, BASE) = 1.0 - -- Domain: - -- X > 0.0 - -- BASE > 0.0 - -- BASE /= 1.0 - -- Error conditions: - -- Error if X <= 0.0 - -- Error if BASE <= 0.0 - -- Error if BASE = 1.0 - -- Range: - -- LOG(X, BASE) is mathematically unbounded - -- Notes: - -- a) When BASE > 1.0, the reachable range of LOG is - -- approximately given by: - -- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE) - -- b) When 0.0 < BASE < 1.0, the reachable range of LOG is - -- approximately given by: - -- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE) - - function SIN (X : in REAL ) return REAL; - -- Purpose: - -- Returns sine of X; X in radians - -- Special values: - -- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER - -- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an - -- INTEGER - -- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an - -- INTEGER - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ABS(SIN(X)) <= 1.0 - -- Notes: - -- a) For larger values of ABS(X), degraded accuracy is allowed. - - function COS ( X : in REAL ) return REAL; - -- Purpose: - -- Returns cosine of X; X in radians - -- Special values: - -- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an - -- INTEGER - -- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER - -- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ABS(COS(X)) <= 1.0 - -- Notes: - -- a) For larger values of ABS(X), degraded accuracy is allowed. - - function TAN (X : in REAL ) return REAL; - -- Purpose: - -- Returns tangent of X; X in radians - -- Special values: - -- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER - -- Domain: - -- X in REAL and - -- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER - -- Error conditions: - -- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an - -- INTEGER - -- Range: - -- TAN(X) is mathematically unbounded - -- Notes: - -- a) For larger values of ABS(X), degraded accuracy is allowed. - - function ARCSIN (X : in REAL ) return REAL; - -- Purpose: - -- Returns inverse sine of X - -- Special values: - -- ARCSIN(0.0) = 0.0 - -- ARCSIN(1.0) = MATH_PI_OVER_2 - -- ARCSIN(-1.0) = -MATH_PI_OVER_2 - -- Domain: - -- ABS(X) <= 1.0 - -- Error conditions: - -- Error if ABS(X) > 1.0 - -- Range: - -- ABS(ARCSIN(X) <= MATH_PI_OVER_2 - -- Notes: - -- None - - function ARCCOS (X : in REAL ) return REAL; - -- Purpose: - -- Returns inverse cosine of X - -- Special values: - -- ARCCOS(1.0) = 0.0 - -- ARCCOS(0.0) = MATH_PI_OVER_2 - -- ARCCOS(-1.0) = MATH_PI - -- Domain: - -- ABS(X) <= 1.0 - -- Error conditions: - -- Error if ABS(X) > 1.0 - -- Range: - -- 0.0 <= ARCCOS(X) <= MATH_PI - -- Notes: - -- None - - function ARCTAN (Y : in REAL) return REAL; - -- Purpose: - -- Returns the value of the angle in radians of the point - -- (1.0, Y), which is in rectangular coordinates - -- Special values: - -- ARCTAN(0.0) = 0.0 - -- Domain: - -- Y in REAL - -- Error conditions: - -- None - -- Range: - -- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2 - -- Notes: - -- None - - function ARCTAN (Y : in REAL; X : in REAL) return REAL; - -- Purpose: - -- Returns the principal value of the angle in radians of - -- the point (X, Y), which is in rectangular coordinates - -- Special values: - -- ARCTAN(0.0, X) = 0.0 if X > 0.0 - -- ARCTAN(0.0, X) = MATH_PI if X < 0.0 - -- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0 - -- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0 - -- Domain: - -- Y in REAL - -- X in REAL, X /= 0.0 when Y = 0.0 - -- Error conditions: - -- Error if X = 0.0 and Y = 0.0 - -- Range: - -- -MATH_PI < ARCTAN(Y,X) <= MATH_PI - -- Notes: - -- None - - function SINH (X : in REAL) return REAL; - -- Purpose: - -- Returns hyperbolic sine of X - -- Special values: - -- SINH(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- SINH(X) is mathematically unbounded - -- Notes: - -- a) The usable domain of SINH is approximately given by: - -- ABS(X) <= LOG(REAL'HIGH) - - - function COSH (X : in REAL) return REAL; - -- Purpose: - -- Returns hyperbolic cosine of X - -- Special values: - -- COSH(0.0) = 1.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- COSH(X) >= 1.0 - -- Notes: - -- a) The usable domain of COSH is approximately given by: - -- ABS(X) <= LOG(REAL'HIGH) - - function TANH (X : in REAL) return REAL; - -- Purpose: - -- Returns hyperbolic tangent of X - -- Special values: - -- TANH(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ABS(TANH(X)) <= 1.0 - -- Notes: - -- None - - function ARCSINH (X : in REAL) return REAL; - -- Purpose: - -- Returns inverse hyperbolic sine of X - -- Special values: - -- ARCSINH(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ARCSINH(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of ARCSINH is approximately given by: - -- ABS(ARCSINH(X)) <= LOG(REAL'HIGH) - - function ARCCOSH (X : in REAL) return REAL; - -- Purpose: - -- Returns inverse hyperbolic cosine of X - -- Special values: - -- ARCCOSH(1.0) = 0.0 - -- Domain: - -- X >= 1.0 - -- Error conditions: - -- Error if X < 1.0 - -- Range: - -- ARCCOSH(X) >= 0.0 - -- Notes: - -- a) The upper bound of the reachable range of ARCCOSH is - -- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH) - - function ARCTANH (X : in REAL) return REAL; - -- Purpose: - -- Returns inverse hyperbolic tangent of X - -- Special values: - -- ARCTANH(0.0) = 0.0 - -- Domain: - -- ABS(X) < 1.0 - -- Error conditions: - -- Error if ABS(X) >= 1.0 - -- Range: - -- ARCTANH(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of ARCTANH is approximately given by: - -- ABS(ARCTANH(X)) < LOG(REAL'HIGH) - -end MATH_REAL; - - - ------------------------------------------------------------------------- --- --- Copyright 1996 by IEEE. All rights reserved. - --- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard --- VHDL Mathematical Packages. This source file may not be copied, sold, or --- included with software that is sold without written permission from the IEEE --- Standards Department. This source file may be used to implement this standard --- and may be distributed in compiled form in any manner so long as the --- compiled form does not allow direct decompilation of the original source file. --- This source file may be copied for individual use between licensed users. --- This source file is provided on an AS IS basis. The IEEE disclaims ANY --- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY --- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source --- file shall indemnify and hold IEEE harmless from any damages or liability --- arising out of the use thereof. - --- --- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, --- MATH_REAL) --- --- Library: This package shall be compiled into a library --- symbolically named IEEE. --- --- Developers: IEEE DASC VHDL Mathematical Packages Working Group --- --- Purpose: This package body is a nonnormative implementation of the --- functionality defined in the MATH_REAL package declaration. --- --- Limitation: The values generated by the functions in this package may --- vary from platform to platform, and the precision of results --- is only guaranteed to be the minimum required by IEEE Std 1076 --- -1993. --- --- Notes: --- The "package declaration" defines the types, subtypes, and --- declarations of MATH_REAL. --- The standard mathematical definition and conventional meaning --- of the mathematical functions that are part of this standard --- represent the formal semantics of the implementation of the --- MATH_REAL package declaration. The purpose of the MATH_REAL --- package body is to clarify such semantics and provide a --- guideline for implementations to verify their implementation --- of MATH_REAL. Tool developers may choose to implement --- the package body in the most efficient manner available to them. --- --- ----------------------------------------------------------------------------- --- Version : 1.5 --- Date : 24 July 1996 --- ----------------------------------------------------------------------------- - -package body MATH_REAL is - - -- - -- Local Constants for Use in the Package Body Only - -- - constant MATH_E_P2 : REAL := 7.38905_60989_30650; -- e**2 - constant MATH_E_P10 : REAL := 22026.46579_48067_17; -- e**10 - constant MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi - constant MAX_ITER: INTEGER := 27; -- Maximum precision factor for cordic - constant MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries - constant BASE_EPS: REAL := 0.00001; -- Factor for convergence criteria - constant KC : REAL := 6.0725293500888142e-01; -- Constant for cordic - - -- - -- Local Type Declarations for Cordic Operations - -- - type REAL_VECTOR is array (NATURAL range <>) of REAL; - type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL; - subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER); - subtype REAL_ARR_2 is REAL_VECTOR (0 to 1); - subtype REAL_ARR_3 is REAL_VECTOR (0 to 2); - subtype QUADRANT is INTEGER range 0 to 3; - type CORDIC_MODE_TYPE is (ROTATION, VECTORING); - - -- - -- Auxiliary Functions for Cordic Algorithms - -- - function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL; - NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is - -- Description: - -- Returns power of two for a vector of values - -- Notes: - -- None - -- - variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES); - variable TEMP : REAL := INITIAL_VALUE; - variable FLAG : BOOLEAN := TRUE; - begin - for I in 0 to NUMBER_OF_VALUES loop - V(I) := TEMP; - for P in D'RANGE loop - if I = D(P) then - FLAG := FALSE; - exit; - end if; - end loop; - if FLAG then - TEMP := TEMP/2.0; - end if; - FLAG := TRUE; - end loop; - return V; - end POWER_OF_2_SERIES; - - - constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES( - NATURAL_VECTOR'(100, 90),1.0, - MAX_ITER); - - constant EPSILON : REAL_VECTOR_N := ( - 7.8539816339744827e-01, - 4.6364760900080606e-01, - 2.4497866312686413e-01, - 1.2435499454676144e-01, - 6.2418809995957351e-02, - 3.1239833430268277e-02, - 1.5623728620476830e-02, - 7.8123410601011116e-03, - 3.9062301319669717e-03, - 1.9531225164788189e-03, - 9.7656218955931937e-04, - 4.8828121119489829e-04, - 2.4414062014936175e-04, - 1.2207031189367021e-04, - 6.1035156174208768e-05, - 3.0517578115526093e-05, - 1.5258789061315760e-05, - 7.6293945311019699e-06, - 3.8146972656064960e-06, - 1.9073486328101870e-06, - 9.5367431640596080e-07, - 4.7683715820308876e-07, - 2.3841857910155801e-07, - 1.1920928955078067e-07, - 5.9604644775390553e-08, - 2.9802322387695303e-08, - 1.4901161193847654e-08, - 7.4505805969238281e-09 - ); - - function CORDIC ( X0 : in REAL; - Y0 : in REAL; - Z0 : in REAL; - N : in NATURAL; -- Precision factor - CORDIC_MODE : in CORDIC_MODE_TYPE -- Rotation (Z -> 0) - -- or vectoring (Y -> 0) - ) return REAL_ARR_3 is - -- Description: - -- Compute cordic values - -- Notes: - -- None - variable X : REAL := X0; - variable Y : REAL := Y0; - variable Z : REAL := Z0; - variable X_TEMP : REAL; - begin - if CORDIC_MODE = ROTATION then - for K in 0 to N loop - X_TEMP := X; - if ( Z >= 0.0) then - X := X - Y * TWO_AT_MINUS(K); - Y := Y + X_TEMP * TWO_AT_MINUS(K); - Z := Z - EPSILON(K); - else - X := X + Y * TWO_AT_MINUS(K); - Y := Y - X_TEMP * TWO_AT_MINUS(K); - Z := Z + EPSILON(K); - end if; - end loop; - else - for K in 0 to N loop - X_TEMP := X; - if ( Y < 0.0) then - X := X - Y * TWO_AT_MINUS(K); - Y := Y + X_TEMP * TWO_AT_MINUS(K); - Z := Z - EPSILON(K); - else - X := X + Y * TWO_AT_MINUS(K); - Y := Y - X_TEMP * TWO_AT_MINUS(K); - Z := Z + EPSILON(K); - end if; - end loop; - end if; - return REAL_ARR_3'(X, Y, Z); - end CORDIC; - - -- - -- Bodies for Global Mathematical Functions Start Here - -- - function SIGN (X: in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- None - begin - if ( X > 0.0 ) then - return 1.0; - elsif ( X < 0.0 ) then - return -1.0; - else - return 0.0; - end if; - end SIGN; - - function CEIL (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) No conversion to an INTEGER type is expected, so truncate - -- cannot overflow for large arguments - -- b) The domain supported by this function is X <= LARGE - -- c) Returns X if ABS(X) >= LARGE - - constant LARGE: REAL := REAL(INTEGER'HIGH); - variable RD: REAL; - - begin - if ABS(X) >= LARGE then - return X; - end if; - - RD := REAL ( INTEGER(X)); - if RD = X then - return X; - end if; - - if X > 0.0 then - if RD >= X then - return RD; - else - return RD + 1.0; - end if; - elsif X = 0.0 then - return 0.0; - else - if RD <= X then - return RD + 1.0; - else - return RD; - end if; - end if; - end CEIL; - - function FLOOR (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) No conversion to an INTEGER type is expected, so truncate - -- cannot overflow for large arguments - -- b) The domain supported by this function is ABS(X) <= LARGE - -- c) Returns X if ABS(X) >= LARGE - - constant LARGE: REAL := REAL(INTEGER'HIGH); - variable RD: REAL; - - begin - if ABS( X ) >= LARGE then - return X; - end if; - - RD := REAL ( INTEGER(X)); - if RD = X then - return X; - end if; - - if X > 0.0 then - if RD <= X then - return RD; - else - return RD - 1.0; - end if; - elsif X = 0.0 then - return 0.0; - else - if RD >= X then - return RD - 1.0; - else - return RD; - end if; - end if; - end FLOOR; - - function ROUND (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 if X = 0.0 - -- b) Returns FLOOR(X + 0.5) if X > 0 - -- c) Returns CEIL(X - 0.5) if X < 0 - - begin - if X > 0.0 then - return FLOOR(X + 0.5); - elsif X < 0.0 then - return CEIL( X - 0.5); - else - return 0.0; - end if; - end ROUND; - - function TRUNC (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 if X = 0.0 - -- b) Returns FLOOR(X) if X > 0 - -- c) Returns CEIL(X) if X < 0 - - begin - if X > 0.0 then - return FLOOR(X); - elsif X < 0.0 then - return CEIL( X); - else - return 0.0; - end if; - end TRUNC; - - - - - function "MOD" (X, Y: in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error - - variable XNEGATIVE : BOOLEAN := X < 0.0; - variable YNEGATIVE : BOOLEAN := Y < 0.0; - variable VALUE : REAL; - begin - -- Check validity of input arguments - if (Y = 0.0) then - assert FALSE - report "MOD(X, 0.0) is undefined" - severity ERROR; - return 0.0; - end if; - - -- Compute value - if ( XNEGATIVE ) then - if ( YNEGATIVE ) then - VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); - else - VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y); - end if; - else - if ( YNEGATIVE ) then - VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y); - else - VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); - end if; - end if; - - return VALUE; - end "MOD"; - - - function REALMAX (X, Y : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) REALMAX(X,Y) = X when X = Y - -- - begin - if X >= Y then - return X; - else - return Y; - end if; - end REALMAX; - - function REALMIN (X, Y : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) REALMIN(X,Y) = X when X = Y - -- - begin - if X <= Y then - return X; - else - return Y; - end if; - end REALMIN; - - - procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL) - is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error - -- - variable Z, K: INTEGER; - variable TSEED1 : INTEGER := INTEGER'(SEED1); - variable TSEED2 : INTEGER := INTEGER'(SEED2); - begin - -- Check validity of arguments - if SEED1 > 2147483562 then - assert FALSE - report "SEED1 > 2147483562 in UNIFORM" - severity ERROR; - X := 0.0; - return; - end if; - - if SEED2 > 2147483398 then - assert FALSE - report "SEED2 > 2147483398 in UNIFORM" - severity ERROR; - X := 0.0; - return; - end if; - - -- Compute new seed values and pseudo-random number - K := TSEED1/53668; - TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211; - - if TSEED1 < 0 then - TSEED1 := TSEED1 + 2147483563; - end if; - - K := TSEED2/52774; - TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791; - - if TSEED2 < 0 then - TSEED2 := TSEED2 + 2147483399; - end if; - - Z := TSEED1 - TSEED2; - if Z < 1 then - Z := Z + 2147483562; - end if; - - -- Get output values - SEED1 := POSITIVE'(TSEED1); - SEED2 := POSITIVE'(TSEED2); - X := REAL(Z)*4.656613e-10; - end UNIFORM; - - - - function SQRT (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Uses the Newton-Raphson approximation: - -- F(n+1) = 0.5*[F(n) + x/F(n)] - -- b) Returns 0.0 on error - -- - - constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor - - variable INIVAL: REAL; - variable OLDVAL : REAL ; - variable NEWVAL : REAL ; - variable COUNT : INTEGER := 1; - - begin - -- Check validity of argument - if ( X < 0.0 ) then - assert FALSE - report "X < 0.0 in SQRT(X)" - severity ERROR; - return 0.0; - end if; - - -- Get the square root for special cases - if X = 0.0 then - return 0.0; - else - if ( X = 1.0 ) then - return 1.0; - end if; - end if; - - -- Get the square root for general cases - INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise - OLDVAL := INIVAL; - NEWVAL := (X/OLDVAL + OLDVAL)*0.5; - - -- Check for relative and absolute error and max count - while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR - (ABS(NEWVAL - OLDVAL) > EPS) ) AND - (COUNT < MAX_COUNT) ) loop - OLDVAL := NEWVAL; - NEWVAL := (X/OLDVAL + OLDVAL)*0.5; - COUNT := COUNT + 1; - end loop; - return NEWVAL; - end SQRT; - - function CBRT (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Uses the Newton-Raphson approximation: - -- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2]; - -- - constant EPS : REAL := BASE_EPS*BASE_EPS; - - variable INIVAL: REAL; - variable XLOCAL : REAL := X; - variable NEGATIVE : BOOLEAN := X < 0.0; - variable OLDVAL : REAL ; - variable NEWVAL : REAL ; - variable COUNT : INTEGER := 1; - - begin - - -- Compute root for special cases - if X = 0.0 then - return 0.0; - elsif ( X = 1.0 ) then - return 1.0; - else - if X = -1.0 then - return -1.0; - end if; - end if; - - -- Compute root for general cases - if NEGATIVE then - XLOCAL := -X; - end if; - - INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but - -- imprecise - OLDVAL := INIVAL; - NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; - - -- Check for relative and absolute errors and max count - while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR - (ABS(NEWVAL - OLDVAL) > EPS ) ) AND - ( COUNT < MAX_COUNT ) ) loop - OLDVAL := NEWVAL; - NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; - COUNT := COUNT + 1; - end loop; - - if NEGATIVE then - NEWVAL := -NEWVAL; - end if; - - return NEWVAL; - end CBRT; - - function "**" (X : in INTEGER; Y : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error condition - - begin - -- Check validity of argument - if ( ( X < 0 ) and ( Y /= 0.0 ) ) then - assert FALSE - report "X < 0 and Y /= 0.0 in X**Y" - severity ERROR; - return 0.0; - end if; - - if ( ( X = 0 ) and ( Y <= 0.0 ) ) then - assert FALSE - report "X = 0 and Y <= 0.0 in X**Y" - severity ERROR; - return 0.0; - end if; - - -- Get value for special cases - if ( X = 0 and Y > 0.0 ) then - return 0.0; - end if; - - if ( X = 1 ) then - return 1.0; - end if; - - if ( Y = 0.0 and X /= 0 ) then - return 1.0; - end if; - - if ( Y = 1.0) then - return (REAL(X)); - end if; - - -- Get value for general case - return EXP (Y * LOG (REAL(X))); - end "**"; - - function "**" (X : in REAL; Y : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error condition - - begin - -- Check validity of argument - if ( ( X < 0.0 ) and ( Y /= 0.0 ) ) then - assert FALSE - report "X < 0.0 and Y /= 0.0 in X**Y" - severity ERROR; - return 0.0; - end if; - - if ( ( X = 0.0 ) and ( Y <= 0.0 ) ) then - assert FALSE - report "X = 0.0 and Y <= 0.0 in X**Y" - severity ERROR; - return 0.0; - end if; - - -- Get value for special cases - if ( X = 0.0 and Y > 0.0 ) then - return 0.0; - end if; - - if ( X = 1.0 ) then - return 1.0; - end if; - - if ( Y = 0.0 and X /= 0.0 ) then - return 1.0; - end if; - - if ( Y = 1.0) then - return (X); - end if; - - -- Get value for general case - return EXP (Y * LOG (X)); - end "**"; - - function EXP (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) This function computes the exponential using the following - -- series: - -- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0 - -- and reduces argument X to take advantage of exp(x+y) = - -- exp(x)*exp(y) - -- - -- b) This implementation limits X to be less than LOG(REAL'HIGH) - -- to avoid overflow. Returns REAL'HIGH when X reaches that - -- limit - -- - constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria - - variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument - variable XLOCAL : REAL := ABS(X); -- Use positive value - variable OLDVAL: REAL ; - variable COUNT: INTEGER ; - variable NEWVAL: REAL ; - variable LAST_TERM: REAL ; - variable FACTOR : REAL := 1.0; - - begin - -- Compute value for special cases - if X = 0.0 then - return 1.0; - end if; - - if XLOCAL = 1.0 then - if RECIPROCAL then - return MATH_1_OVER_E; - else - return MATH_E; - end if; - end if; - - if XLOCAL = 2.0 then - if RECIPROCAL then - return 1.0/MATH_E_P2; - else - return MATH_E_P2; - end if; - end if; - - if XLOCAL = 10.0 then - if RECIPROCAL then - return 1.0/MATH_E_P10; - else - return MATH_E_P10; - end if; - end if; - - if XLOCAL > LOG(REAL'HIGH) then - if RECIPROCAL then - return 0.0; - else - assert FALSE - report "X > LOG(REAL'HIGH) in EXP(X)" - severity NOTE; - return REAL'HIGH; - end if; - end if; - - -- Reduce argument to ABS(X) < 1.0 - while XLOCAL > 10.0 loop - XLOCAL := XLOCAL - 10.0; - FACTOR := FACTOR*MATH_E_P10; - end loop; - - while XLOCAL > 1.0 loop - XLOCAL := XLOCAL - 1.0; - FACTOR := FACTOR*MATH_E; - end loop; - - -- Compute value for case 0 < XLOCAL < 1 - OLDVAL := 1.0; - LAST_TERM := XLOCAL; - NEWVAL:= OLDVAL + LAST_TERM; - COUNT := 2; - - -- Check for relative and absolute errors and max count - while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR - (ABS(NEWVAL - OLDVAL) > EPS) ) AND - (COUNT < MAX_COUNT ) ) loop - OLDVAL := NEWVAL; - LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT))); - NEWVAL := OLDVAL + LAST_TERM; - COUNT := COUNT + 1; - end loop; - - -- Compute final value using exp(x+y) = exp(x)*exp(y) - NEWVAL := NEWVAL*FACTOR; - - if RECIPROCAL then - NEWVAL := 1.0/NEWVAL; - end if; - - return NEWVAL; - end EXP; - - - -- - -- Auxiliary Functions to Compute LOG - -- - function ILOGB(X: in REAL) return INTEGER IS - -- Description: - -- Returns n such that -1 <= ABS(X)/2^n < 2 - -- Notes: - -- None - - variable N: INTEGER := 0; - variable Y: REAL := ABS(X); - - begin - if(Y = 1.0 or Y = 0.0) then - return 0; - end if; - - if( Y > 1.0) then - while Y >= 2.0 loop - Y := Y/2.0; - N := N+1; - end loop; - return N; - end if; - - -- O < Y < 1 - while Y < 1.0 loop - Y := Y*2.0; - N := N -1; - end loop; - return N; - end ILOGB; - - function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS - -- Description: - -- Returns X*2^n - -- Notes: - -- None - begin - return X*(2.0 ** N); - end LDEXP; - - function LOG (X : in REAL ) return REAL IS - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- - -- Notes: - -- a) Returns REAL'LOW on error - -- - -- Copyright (c) 1992 Regents of the University of California. - -- All rights reserved. - -- - -- Redistribution and use in source and binary forms, with or without - -- modification, are permitted provided that the following conditions - -- are met: - -- 1. Redistributions of source code must retain the above copyright - -- notice, this list of conditions and the following disclaimer. - -- 2. Redistributions in binary form must reproduce the above copyright - -- notice, this list of conditions and the following disclaimer in the - -- documentation and/or other materials provided with the distribution. - -- 3. All advertising materials mentioning features or use of this - -- software must display the following acknowledgement: - -- This product includes software developed by the University of - -- California, Berkeley and its contributors. - -- 4. Neither the name of the University nor the names of its - -- contributors may be used to endorse or promote products derived - -- from this software without specific prior written permission. - -- - -- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' - -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR - -- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - -- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - -- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY - -- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - -- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - -- DAMAGE. - -- - -- NOTE: This VHDL version was generated using the C version of the - -- original function by the IEEE VHDL Mathematical Package - -- Working Group (CS/JT) - - constant N: INTEGER := 128; - - -- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128. - -- Used for generation of extend precision logarithms. - -- The constant 35184372088832 is 2^45, so the divide is exact. - -- It ensures correct reading of logF_head, even for inaccurate - -- decimal-to-binary conversion routines. (Everybody gets the - -- right answer for INTEGERs less than 2^53.) - -- Values for LOG(F) were generated using error < 10^-57 absolute - -- with the bc -l package. - - type REAL_VECTOR is array (NATURAL range <>) of REAL; - - constant A1:REAL := 0.08333333333333178827; - constant A2:REAL := 0.01250000000377174923; - constant A3:REAL := 0.002232139987919447809; - constant A4:REAL := 0.0004348877777076145742; - - constant LOGF_HEAD: REAL_VECTOR(0 TO N) := ( - 0.0, - 0.007782140442060381246, - 0.015504186535963526694, - 0.023167059281547608406, - 0.030771658666765233647, - 0.038318864302141264488, - 0.045809536031242714670, - 0.053244514518837604555, - 0.060624621816486978786, - 0.067950661908525944454, - 0.075223421237524235039, - 0.082443669210988446138, - 0.089612158689760690322, - 0.096729626458454731618, - 0.103796793681567578460, - 0.110814366340264314203, - 0.117783035656430001836, - 0.124703478501032805070, - 0.131576357788617315236, - 0.138402322859292326029, - 0.145182009844575077295, - 0.151916042025732167530, - 0.158605030176659056451, - 0.165249572895390883786, - 0.171850256926518341060, - 0.178407657472689606947, - 0.184922338493834104156, - 0.191394852999565046047, - 0.197825743329758552135, - 0.204215541428766300668, - 0.210564769107350002741, - 0.216873938300523150246, - 0.223143551314024080056, - 0.229374101064877322642, - 0.235566071312860003672, - 0.241719936886966024758, - 0.247836163904594286577, - 0.253915209980732470285, - 0.259957524436686071567, - 0.265963548496984003577, - 0.271933715484010463114, - 0.277868451003087102435, - 0.283768173130738432519, - 0.289633292582948342896, - 0.295464212893421063199, - 0.301261330578199704177, - 0.307025035294827830512, - 0.312755710004239517729, - 0.318453731118097493890, - 0.324119468654316733591, - 0.329753286372579168528, - 0.335355541920762334484, - 0.340926586970454081892, - 0.346466767346100823488, - 0.351976423156884266063, - 0.357455888922231679316, - 0.362905493689140712376, - 0.368325561158599157352, - 0.373716409793814818840, - 0.379078352934811846353, - 0.384411698910298582632, - 0.389716751140440464951, - 0.394993808240542421117, - 0.400243164127459749579, - 0.405465108107819105498, - 0.410659924985338875558, - 0.415827895143593195825, - 0.420969294644237379543, - 0.426084395310681429691, - 0.431173464818130014464, - 0.436236766774527495726, - 0.441274560805140936281, - 0.446287102628048160113, - 0.451274644139630254358, - 0.456237433481874177232, - 0.461175715122408291790, - 0.466089729924533457960, - 0.470979715219073113985, - 0.475845904869856894947, - 0.480688529345570714212, - 0.485507815781602403149, - 0.490303988045525329653, - 0.495077266798034543171, - 0.499827869556611403822, - 0.504556010751912253908, - 0.509261901790523552335, - 0.513945751101346104405, - 0.518607764208354637958, - 0.523248143765158602036, - 0.527867089620485785417, - 0.532464798869114019908, - 0.537041465897345915436, - 0.541597282432121573947, - 0.546132437597407260909, - 0.550647117952394182793, - 0.555141507540611200965, - 0.559615787935399566777, - 0.564070138285387656651, - 0.568504735352689749561, - 0.572919753562018740922, - 0.577315365035246941260, - 0.581691739635061821900, - 0.586049045003164792433, - 0.590387446602107957005, - 0.594707107746216934174, - 0.599008189645246602594, - 0.603290851438941899687, - 0.607555250224322662688, - 0.611801541106615331955, - 0.616029877215623855590, - 0.620240409751204424537, - 0.624433288012369303032, - 0.628608659422752680256, - 0.632766669570628437213, - 0.636907462236194987781, - 0.641031179420679109171, - 0.645137961373620782978, - 0.649227946625615004450, - 0.653301272011958644725, - 0.657358072709030238911, - 0.661398482245203922502, - 0.665422632544505177065, - 0.669430653942981734871, - 0.673422675212350441142, - 0.677398823590920073911, - 0.681359224807238206267, - 0.685304003098281100392, - 0.689233281238557538017, - 0.693147180560117703862); - - constant LOGF_TAIL: REAL_VECTOR(0 TO N) := ( - 0.0, - -0.00000000000000543229938420049, - 0.00000000000000172745674997061, - -0.00000000000001323017818229233, - -0.00000000000001154527628289872, - -0.00000000000000466529469958300, - 0.00000000000005148849572685810, - -0.00000000000002532168943117445, - -0.00000000000005213620639136504, - -0.00000000000001819506003016881, - 0.00000000000006329065958724544, - 0.00000000000008614512936087814, - -0.00000000000007355770219435028, - 0.00000000000009638067658552277, - 0.00000000000007598636597194141, - 0.00000000000002579999128306990, - -0.00000000000004654729747598444, - -0.00000000000007556920687451336, - 0.00000000000010195735223708472, - -0.00000000000017319034406422306, - -0.00000000000007718001336828098, - 0.00000000000010980754099855238, - -0.00000000000002047235780046195, - -0.00000000000008372091099235912, - 0.00000000000014088127937111135, - 0.00000000000012869017157588257, - 0.00000000000017788850778198106, - 0.00000000000006440856150696891, - 0.00000000000016132822667240822, - -0.00000000000007540916511956188, - -0.00000000000000036507188831790, - 0.00000000000009120937249914984, - 0.00000000000018567570959796010, - -0.00000000000003149265065191483, - -0.00000000000009309459495196889, - 0.00000000000017914338601329117, - -0.00000000000001302979717330866, - 0.00000000000023097385217586939, - 0.00000000000023999540484211737, - 0.00000000000015393776174455408, - -0.00000000000036870428315837678, - 0.00000000000036920375082080089, - -0.00000000000009383417223663699, - 0.00000000000009433398189512690, - 0.00000000000041481318704258568, - -0.00000000000003792316480209314, - 0.00000000000008403156304792424, - -0.00000000000034262934348285429, - 0.00000000000043712191957429145, - -0.00000000000010475750058776541, - -0.00000000000011118671389559323, - 0.00000000000037549577257259853, - 0.00000000000013912841212197565, - 0.00000000000010775743037572640, - 0.00000000000029391859187648000, - -0.00000000000042790509060060774, - 0.00000000000022774076114039555, - 0.00000000000010849569622967912, - -0.00000000000023073801945705758, - 0.00000000000015761203773969435, - 0.00000000000003345710269544082, - -0.00000000000041525158063436123, - 0.00000000000032655698896907146, - -0.00000000000044704265010452446, - 0.00000000000034527647952039772, - -0.00000000000007048962392109746, - 0.00000000000011776978751369214, - -0.00000000000010774341461609578, - 0.00000000000021863343293215910, - 0.00000000000024132639491333131, - 0.00000000000039057462209830700, - -0.00000000000026570679203560751, - 0.00000000000037135141919592021, - -0.00000000000017166921336082431, - -0.00000000000028658285157914353, - -0.00000000000023812542263446809, - 0.00000000000006576659768580062, - -0.00000000000028210143846181267, - 0.00000000000010701931762114254, - 0.00000000000018119346366441110, - 0.00000000000009840465278232627, - -0.00000000000033149150282752542, - -0.00000000000018302857356041668, - -0.00000000000016207400156744949, - 0.00000000000048303314949553201, - -0.00000000000071560553172382115, - 0.00000000000088821239518571855, - -0.00000000000030900580513238244, - -0.00000000000061076551972851496, - 0.00000000000035659969663347830, - 0.00000000000035782396591276383, - -0.00000000000046226087001544578, - 0.00000000000062279762917225156, - 0.00000000000072838947272065741, - 0.00000000000026809646615211673, - -0.00000000000010960825046059278, - 0.00000000000002311949383800537, - -0.00000000000058469058005299247, - -0.00000000000002103748251144494, - -0.00000000000023323182945587408, - -0.00000000000042333694288141916, - -0.00000000000043933937969737844, - 0.00000000000041341647073835565, - 0.00000000000006841763641591466, - 0.00000000000047585534004430641, - 0.00000000000083679678674757695, - -0.00000000000085763734646658640, - 0.00000000000021913281229340092, - -0.00000000000062242842536431148, - -0.00000000000010983594325438430, - 0.00000000000065310431377633651, - -0.00000000000047580199021710769, - -0.00000000000037854251265457040, - 0.00000000000040939233218678664, - 0.00000000000087424383914858291, - 0.00000000000025218188456842882, - -0.00000000000003608131360422557, - -0.00000000000050518555924280902, - 0.00000000000078699403323355317, - -0.00000000000067020876961949060, - 0.00000000000016108575753932458, - 0.00000000000058527188436251509, - -0.00000000000035246757297904791, - -0.00000000000018372084495629058, - 0.00000000000088606689813494916, - 0.00000000000066486268071468700, - 0.00000000000063831615170646519, - 0.00000000000025144230728376072, - -0.00000000000017239444525614834); - - variable M, J:INTEGER; - variable F1, F2, G, Q, U, U2, V: REAL; - variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs - variable ONE: REAL := 1.0; --Made variable so no constant folding occurs - - -- double logb(), ldexp(); - - variable U1:REAL; - - begin - - -- Check validity of argument - if ( X <= 0.0 ) then - assert FALSE - report "X <= 0.0 in LOG(X)" - severity ERROR; - return(REAL'LOW); - end if; - - -- Compute value for special cases - if ( X = 1.0 ) then - return 0.0; - end if; - - if ( X = MATH_E ) then - return 1.0; - end if; - - -- Argument reduction: 1 <= g < 2; x/2^m = g; - -- y = F*(1 + f/F) for |f| <= 2^-8 - - M := ILOGB(X); - G := LDEXP(X, -M); - J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding - F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512] - F2 := G - F1; - - -- Approximate expansion for log(1+f2/F1) ~= u + q - G := 1.0/(2.0*F1+F2); - U := 2.0*F2*G; - V := U*U; - Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4))); - - -- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8, - -- u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits. - -- It also adds exactly to |m*log2_hi + log_F_head[j] | < 750. - -- - if ( J /= 0 or M /= 0) then - U1 := U + 513.0; - U1 := U1 - 513.0; - - -- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero - -- u1 = u to 24 bits. - -- - else - U1 := U; - --TRUNC(U1); --In c this is u1 = (double) (float) (u1) - end if; - - U2 := (2.0*(F2 - F1*U1) - U1*F2) * G; - -- u1 + u2 = 2f/(2F+f) to extra precision. - - -- log(x) = log(2^m*F1*(1+f2/F1)) = - -- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q); - -- (exact) + (tiny) - - U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J); -- Exact - U2 := (U2 + LOGF_TAIL(J)) + Q; -- Tiny - U2 := U2 + LOGF_TAIL(N)*REAL(M); - return (U1 + U2); - end LOG; - - - function LOG2 (X: in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns REAL'LOW on error - begin - -- Check validity of arguments - if ( X <= 0.0 ) then - assert FALSE - report "X <= 0.0 in LOG2(X)" - severity ERROR; - return(REAL'LOW); - end if; - - -- Compute value for special cases - if ( X = 1.0 ) then - return 0.0; - end if; - - if ( X = 2.0 ) then - return 1.0; - end if; - - -- Compute value for general case - return ( MATH_LOG2_OF_E*LOG(X) ); - end LOG2; - - - function LOG10 (X: in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns REAL'LOW on error - begin - -- Check validity of arguments - if ( X <= 0.0 ) then - assert FALSE - report "X <= 0.0 in LOG10(X)" - severity ERROR; - return(REAL'LOW); - end if; - - -- Compute value for special cases - if ( X = 1.0 ) then - return 0.0; - end if; - - if ( X = 10.0 ) then - return 1.0; - end if; - - -- Compute value for general case - return ( MATH_LOG10_OF_E*LOG(X) ); - end LOG10; - - - function LOG (X: in REAL; BASE: in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns REAL'LOW on error - begin - -- Check validity of arguments - if ( X <= 0.0 ) then - assert FALSE - report "X <= 0.0 in LOG(X, BASE)" - severity ERROR; - return(REAL'LOW); - end if; - - if ( BASE <= 0.0 or BASE = 1.0 ) then - assert FALSE - report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)" - severity ERROR; - return(REAL'LOW); - end if; - - -- Compute value for special cases - if ( X = 1.0 ) then - return 0.0; - end if; - - if ( X = BASE ) then - return 1.0; - end if; - - -- Compute value for general case - return ( LOG(X)/LOG(BASE)); - end LOG; - - - function SIN (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) SIN(-X) = -SIN(X) - -- b) SIN(X) = X if ABS(X) < EPS - -- c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS - -- d) SIN(MATH_PI_OVER_2 - X) = COS(X) - -- e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS - -- f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if - -- EPS< ABS(X) MATH_2_PI then - TEMP := FLOOR(XLOCAL/MATH_2_PI); - XLOCAL := XLOCAL - TEMP*MATH_2_PI; - end if; - - if XLOCAL < 0.0 then - assert FALSE - report "XLOCAL <= 0.0 after reduction in SIN(X)" - severity ERROR; - XLOCAL := -XLOCAL; - end if; - - -- Compute value for special cases - if XLOCAL = 0.0 or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI then - return 0.0; - end if; - - if XLOCAL = MATH_PI_OVER_2 then - if NEGATIVE then - return -1.0; - else - return 1.0; - end if; - end if; - - if XLOCAL = MATH_3_PI_OVER_2 then - if NEGATIVE then - return 1.0; - else - return -1.0; - end if; - end if; - - if XLOCAL < EPS then - if NEGATIVE then - return -XLOCAL; - else - return XLOCAL; - end if; - else - if XLOCAL < BASE_EPS then - TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0; - if NEGATIVE then - return -TEMP; - else - return TEMP; - end if; - end if; - end if; - - TEMP := MATH_PI - XLOCAL; - if ABS(TEMP) < EPS then - if NEGATIVE then - return -TEMP; - else - return TEMP; - end if; - else - if ABS(TEMP) < BASE_EPS then - TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; - if NEGATIVE then - return -TEMP; - else - return TEMP; - end if; - end if; - end if; - - TEMP := MATH_2_PI - XLOCAL; - if ABS(TEMP) < EPS then - if NEGATIVE then - return TEMP; - else - return -TEMP; - end if; - else - if ABS(TEMP) < BASE_EPS then - TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; - if NEGATIVE then - return TEMP; - else - return -TEMP; - end if; - end if; - end if; - - TEMP := ABS(MATH_PI_OVER_2 - XLOCAL); - if TEMP < EPS then - TEMP := 1.0 - TEMP*TEMP*0.5; - if NEGATIVE then - return -TEMP; - else - return TEMP; - end if; - else - if TEMP < BASE_EPS then - TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; - if NEGATIVE then - return -TEMP; - else - return TEMP; - end if; - end if; - end if; - - TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL); - if TEMP < EPS then - TEMP := 1.0 - TEMP*TEMP*0.5; - if NEGATIVE then - return TEMP; - else - return -TEMP; - end if; - else - if TEMP < BASE_EPS then - TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; - if NEGATIVE then - return TEMP; - else - return -TEMP; - end if; - end if; - end if; - - -- Compute value for general cases - if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then - VALUE:= CORDIC( KC, 0.0, x, 27, ROTATION)(1); - end if; - - N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2)); - case QUADRANT( N mod 4) is - when 0 => - VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1); - when 1 => - VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27, - ROTATION)(0); - when 2 => - VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1); - when 3 => - VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27, - ROTATION)(0); - end case; - - if NEGATIVE then - return -VALUE; - else - return VALUE; - end if; - end SIN; - - - function COS (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) COS(-X) = COS(X) - -- b) COS(X) = SIN(MATH_PI_OVER_2 - X) - -- c) COS(MATH_PI + X) = -COS(X) - -- d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS - -- e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if - -- EPS< ABS(X) MATH_2_PI then - TEMP := FLOOR(XLOCAL/MATH_2_PI); - XLOCAL := XLOCAL - TEMP*MATH_2_PI; - end if; - - if XLOCAL < 0.0 then - assert FALSE - report "XLOCAL <= 0.0 after reduction in COS(X)" - severity ERROR; - XLOCAL := -XLOCAL; - end if; - - -- Compute value for special cases - if XLOCAL = 0.0 or XLOCAL = MATH_2_PI then - return 1.0; - end if; - - if XLOCAL = MATH_PI then - return -1.0; - end if; - - if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then - return 0.0; - end if; - - TEMP := ABS(XLOCAL); - if ( TEMP < EPS) then - return (1.0 - 0.5*TEMP*TEMP); - else - if (TEMP < BASE_EPS) then - return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); - end if; - end if; - - TEMP := ABS(XLOCAL -MATH_2_PI); - if ( TEMP < EPS) then - return (1.0 - 0.5*TEMP*TEMP); - else - if (TEMP < BASE_EPS) then - return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); - end if; - end if; - - TEMP := ABS (XLOCAL - MATH_PI); - if TEMP < EPS then - return (-1.0 + 0.5*TEMP*TEMP); - else - if (TEMP < BASE_EPS) then - return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0); - end if; - end if; - - -- Compute value for general cases - return SIN(MATH_PI_OVER_2 - XLOCAL); - end COS; - - function TAN (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) TAN(0.0) = 0.0 - -- b) TAN(-X) = -TAN(X) - -- c) Returns REAL'LOW on error if X < 0.0 - -- d) Returns REAL'HIGH on error if X > 0.0 - - variable NEGATIVE : BOOLEAN := X < 0.0; - variable XLOCAL : REAL := ABS(X) ; - variable VALUE: REAL; - variable TEMP : REAL; - - begin - -- Make 0.0 <= XLOCAL <= MATH_2_PI - if XLOCAL > MATH_2_PI then - TEMP := FLOOR(XLOCAL/MATH_2_PI); - XLOCAL := XLOCAL - TEMP*MATH_2_PI; - end if; - - if XLOCAL < 0.0 then - assert FALSE - report "XLOCAL <= 0.0 after reduction in TAN(X)" - severity ERROR; - XLOCAL := -XLOCAL; - end if; - - -- Check validity of argument - if XLOCAL = MATH_PI_OVER_2 then - assert FALSE - report "X is a multiple of MATH_PI_OVER_2 in TAN(X)" - severity ERROR; - if NEGATIVE then - return(REAL'LOW); - else - return(REAL'HIGH); - end if; - end if; - - if XLOCAL = MATH_3_PI_OVER_2 then - assert FALSE - report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)" - severity ERROR; - if NEGATIVE then - return(REAL'HIGH); - else - return(REAL'LOW); - end if; - end if; - - -- Compute value for special cases - if XLOCAL = 0.0 or XLOCAL = MATH_PI then - return 0.0; - end if; - - -- Compute value for general cases - VALUE := SIN(XLOCAL)/COS(XLOCAL); - if NEGATIVE then - return -VALUE; - else - return VALUE; - end if; - end TAN; - - function ARCSIN (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) ARCSIN(-X) = -ARCSIN(X) - -- b) Returns X on error - - variable NEGATIVE : BOOLEAN := X < 0.0; - variable XLOCAL : REAL := ABS(X); - variable VALUE : REAL; - - begin - -- Check validity of arguments - if XLOCAL > 1.0 then - assert FALSE - report "ABS(X) > 1.0 in ARCSIN(X)" - severity ERROR; - return X; - end if; - - -- Compute value for special cases - if XLOCAL = 0.0 then - return 0.0; - elsif XLOCAL = 1.0 then - if NEGATIVE then - return -MATH_PI_OVER_2; - else - return MATH_PI_OVER_2; - end if; - end if; - - -- Compute value for general cases - if XLOCAL < 0.9 then - VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL))); - else - VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); - end if; - - if NEGATIVE then - VALUE := -VALUE; - end if; - - return VALUE; - end ARCSIN; - - function ARCCOS (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) ARCCOS(-X) = MATH_PI - ARCCOS(X) - -- b) Returns X on error - - variable NEGATIVE : BOOLEAN := X < 0.0; - variable XLOCAL : REAL := ABS(X); - variable VALUE : REAL; - - begin - -- Check validity of argument - if XLOCAL > 1.0 then - assert FALSE - report "ABS(X) > 1.0 in ARCCOS(X)" - severity ERROR; - return X; - end if; - - -- Compute value for special cases - if X = 1.0 then - return 0.0; - elsif X = 0.0 then - return MATH_PI_OVER_2; - elsif X = -1.0 then - return MATH_PI; - end if; - - -- Compute value for general cases - if XLOCAL > 0.9 then - VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); - else - VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL)); - end if; - - - if NEGATIVE then - VALUE := MATH_PI - VALUE; - end if; - - return VALUE; - end ARCCOS; - - - function ARCTAN (Y : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) ARCTAN(-Y) = -ARCTAN(Y) - -- b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0 - -- c) ARCTAN(Y) = Y for |Y| < EPS - - constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS; - - variable NEGATIVE : BOOLEAN := Y < 0.0; - variable RECIPROCAL : BOOLEAN; - variable YLOCAL : REAL := ABS(Y); - variable VALUE : REAL; - - begin - -- Make argument |Y| <=1.0 - if YLOCAL > 1.0 then - YLOCAL := 1.0/YLOCAL; - RECIPROCAL := TRUE; - else - RECIPROCAL := FALSE; - end if; - - -- Compute value for special cases - if YLOCAL = 0.0 then - if RECIPROCAL then - if NEGATIVE then - return (-MATH_PI_OVER_2); - else - return (MATH_PI_OVER_2); - end if; - else - return 0.0; - end if; - end if; - - if YLOCAL < EPS then - if NEGATIVE then - if RECIPROCAL then - return (-MATH_PI_OVER_2 + YLOCAL); - else - return -YLOCAL; - end if; - else - if RECIPROCAL then - return (MATH_PI_OVER_2 - YLOCAL); - else - return YLOCAL; - end if; - end if; - end if; - - -- Compute value for general cases - VALUE := CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2); - - if RECIPROCAL then - VALUE := MATH_PI_OVER_2 - VALUE; - end if; - - if NEGATIVE then - VALUE := -VALUE; - end if; - - return VALUE; - end ARCTAN; - - - function ARCTAN (Y : in REAL; X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error - - variable YLOCAL : REAL; - variable VALUE : REAL; - begin - - -- Check validity of arguments - if (Y = 0.0 and X = 0.0 ) then - assert FALSE report - "ARCTAN(0.0, 0.0) is undetermined" - severity ERROR; - return 0.0; - end if; - - -- Compute value for special cases - if Y = 0.0 then - if X > 0.0 then - return 0.0; - else - return MATH_PI; - end if; - end if; - - if X = 0.0 then - if Y > 0.0 then - return MATH_PI_OVER_2; - else - return -MATH_PI_OVER_2; - end if; - end if; - - - -- Compute value for general cases - YLOCAL := ABS(Y/X); - - VALUE := ARCTAN(YLOCAL); - - if X < 0.0 then - VALUE := MATH_PI - VALUE; - end if; - - if Y < 0.0 then - VALUE := -VALUE; - end if; - - return VALUE; - end ARCTAN; - - - function SINH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns (EXP(X) - EXP(-X))/2.0 - -- b) SINH(-X) = SINH(X) - - variable NEGATIVE : BOOLEAN := X < 0.0; - variable XLOCAL : REAL := ABS(X); - variable TEMP : REAL; - variable VALUE : REAL; - - begin - -- Compute value for special cases - if XLOCAL = 0.0 then - return 0.0; - end if; - - -- Compute value for general cases - TEMP := EXP(XLOCAL); - VALUE := (TEMP - 1.0/TEMP)*0.5; - - if NEGATIVE then - VALUE := -VALUE; - end if; - - return VALUE; - end SINH; - - function COSH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns (EXP(X) + EXP(-X))/2.0 - -- b) COSH(-X) = COSH(X) - - variable XLOCAL : REAL := ABS(X); - variable TEMP : REAL; - variable VALUE : REAL; - begin - -- Compute value for special cases - if XLOCAL = 0.0 then - return 1.0; - end if; - - - -- Compute value for general cases - TEMP := EXP(XLOCAL); - VALUE := (TEMP + 1.0/TEMP)*0.5; - - return VALUE; - end COSH; - - function TANH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X)) - -- b) TANH(-X) = -TANH(X) - - variable NEGATIVE : BOOLEAN := X < 0.0; - variable XLOCAL : REAL := ABS(X); - variable TEMP : REAL; - variable VALUE : REAL; - - begin - -- Compute value for special cases - if XLOCAL = 0.0 then - return 0.0; - end if; - - -- Compute value for general cases - TEMP := EXP(XLOCAL); - VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP); - - if NEGATIVE then - return -VALUE; - else - return VALUE; - end if; - end TANH; - - function ARCSINH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns LOG( X + SQRT( X*X + 1.0)) - - begin - -- Compute value for special cases - if X = 0.0 then - return 0.0; - end if; - - -- Compute value for general cases - return ( LOG( X + SQRT( X*X + 1.0)) ); - end ARCSINH; - - - - function ARCCOSH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns LOG( X + SQRT( X*X - 1.0)); X >= 1.0 - -- b) Returns X on error - - begin - -- Check validity of arguments - if X < 1.0 then - assert FALSE - report "X < 1.0 in ARCCOSH(X)" - severity ERROR; - return X; - end if; - - -- Compute value for special cases - if X = 1.0 then - return 0.0; - end if; - - -- Compute value for general cases - return ( LOG( X + SQRT( X*X - 1.0))); - end ARCCOSH; - - function ARCTANH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0 - -- b) Returns X on error - begin - -- Check validity of arguments - if ABS(X) >= 1.0 then - assert FALSE - report "ABS(X) >= 1.0 in ARCTANH(X)" - severity ERROR; - return X; - end if; - - -- Compute value for special cases - if X = 0.0 then - return 0.0; - end if; - - -- Compute value for general cases - return( 0.5*LOG( (1.0+X)/(1.0-X) ) ); - end ARCTANH; - -end MATH_REAL;
single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/._Real_._Math_.vhd Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.sort =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.sort (revision 8) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.sort (nonexistent) @@ -1 +0,0 @@ -DistRomAsciiDecoder.vhd Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.fdc =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.fdc (revision 8) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.fdc (nonexistent) @@ -1,2 +0,0 @@ -###==== Start Configuration - Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.sbx =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.sbx (revision 8) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.sbx (nonexistent) @@ -1,205 +0,0 @@ - - - - Lattice Semiconductor Corporation - LEGACY - Distributed_ROM - 2.8 - - - Diamond_Simulation - simulation - - ./DistRomAsciiDecoder.vhd - vhdlSource - - - - Diamond_Synthesis - synthesis - - ./DistRomAsciiDecoder.vhd - vhdlSource - - - - - - Configuration - none - ${sbp_path}/generate_core.tcl - CONFIG - - - - - - - - LFE5UM5G-45F-8BG381C - synplify - 2017-01-13.23:14:11 - 2017-01-13.23:14:11 - 3.8.0.115.3 - VHDL - - false - false - false - false - false - false - false - false - false - false - LPM - PRIMARY - PRIMARY - false - false - - - - - - Family - ecp5um5g - - - OperatingCondition - COM - - - Package - CABGA381 - - - PartName - LFE5UM5G-45F-8BG381C - - - PartType - LFE5UM5G-45F - - - SpeedGrade - 8 - - - Status - P - - - - CoreName - Distributed_ROM - - - CoreRevision - 2.8 - - - CoreStatus - Demo - - - CoreType - LPM - - - Date - 01/13/2017 - - - ModuleName - DistRomAsciiDecoder - - - ParameterFileVersion - 1.0 - - - SourceFormat - vhdl - - - Time - 23:14:03 - - - VendorName - Lattice Semiconductor Corporation - - - - Addresses - 128 - - - Data - 14 - - - Destination - Synplicity - - - EDIF - 1 - - - Expression - BusA(0 to 7) - - - IO - 0 - - - LUT - 0 - - - MemFile - c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem - - - MemFormat - bin - - - Order - Big Endian [MSB:LSB] - - - VHDL - 1 - - - Verilog - 0 - - - - c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem - mem - - - - cmd_line - -w -n DistRomAsciiDecoder -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -dram -type romblk -addr_width 7 -num_words 128 -data_width 14 -outdata UNREGISTERED -memfile c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem -memformat bin - - - - - - - LATTICE - LOCAL - DistRomAsciiDecoder - 1.0 - - - - Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/Dist_ROM_ASCII_Decoder.srp =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/Dist_ROM_ASCII_Decoder.srp (revision 8) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/Dist_ROM_ASCII_Decoder.srp (nonexistent) @@ -1,10 +0,0 @@ -SCUBA, Version Diamond (64-bit) 3.8.0.115.3 -Fri Jan 13 23:10:29 2017 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : C:\lscc\diamond\3.8_x64\ispfpga\bin\nt64\scuba.exe -w -n Dist_ROM_ASCII_Decoder -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -dram -type romblk -addr_width 7 -num_words 127 -data_width 14 -outdata UNREGISTERED -memfile c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/rominitvalsbin.mem -memformat bin Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/Dist_ROM_ASCII_Decoder.cst =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/Dist_ROM_ASCII_Decoder.cst (revision 8) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/Dist_ROM_ASCII_Decoder.cst (nonexistent) @@ -1,3 +0,0 @@ -Date=01/13/2017 -Time=23:10:29 - Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/archv/decoder_table_dist_rom.zip =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/archv/decoder_table_dist_rom.zip =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/archv/decoder_table_dist_rom.zip (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/archv/decoder_table_dist_rom.zip (revision 9)
single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/archv/decoder_table_dist_rom.zip Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/._Real_._Math_.vhd =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/._Real_._Math_.vhd (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/._Real_._Math_.vhd (revision 9) @@ -0,0 +1,2574 @@ + + +------------------------------------------------------------------------ +-- +-- Copyright 1996 by IEEE. All rights reserved. +-- +-- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard +-- VHDL Mathematical Packages. This source file may not be copied, sold, or +-- included with software that is sold without written permission from the IEEE +-- Standards Department. This source file may be used to implement this standard +-- and may be distributed in compiled form in any manner so long as the +-- compiled form does not allow direct decompilation of the original source file. +-- This source file may be copied for individual use between licensed users. +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source +-- file shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. +-- +-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, +-- MATH_REAL) +-- +-- Library: This package shall be compiled into a library +-- symbolically named IEEE. +-- +-- Developers: IEEE DASC VHDL Mathematical Packages Working Group +-- +-- Purpose: This package defines a standard for designers to use in +-- describing VHDL models that make use of common REAL constants +-- and common REAL elementary mathematical functions. +-- +-- Limitation: The values generated by the functions in this package may +-- vary from platform to platform, and the precision of results +-- is only guaranteed to be the minimum required by IEEE Std 1076- +-- 1993. +-- +-- Notes: +-- No declarations or definitions shall be included in, or +-- excluded from, this package. +-- The "package declaration" defines the types, subtypes, and +-- declarations of MATH_REAL. +-- The standard mathematical definition and conventional meaning +-- of the mathematical functions that are part of this standard +-- represent the formal semantics of the implementation of the +-- MATH_REAL package declaration. The purpose of the MATH_REAL +-- package body is to provide a guideline for implementations to +-- verify their implementation of MATH_REAL. Tool developers may +-- choose to implement the package body in the most efficient +-- manner available to them. +-- +-- ----------------------------------------------------------------------------- +-- Version : 1.5 +-- Date : 24 July 1996 +-- ----------------------------------------------------------------------------- + +package MATH_REAL is + constant CopyRightNotice: STRING + := "Copyright 1996 IEEE. All rights reserved."; + + -- + -- Constant Definitions + -- + constant MATH_E : REAL := 2.71828_18284_59045_23536; + -- Value of e + constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160; + -- Value of 1/e + constant MATH_PI : REAL := 3.14159_26535_89793_23846; + -- Value of pi + constant MATH_2_PI : REAL := 6.28318_53071_79586_47693; + -- Value of 2*pi + constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154; + -- Value of 1/pi + constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923; + -- Value of pi/2 + constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615; + -- Value of pi/3 + constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962; + -- Value of pi/4 + constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769; + -- Value 3*pi/2 + constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942; + -- Natural log of 2 + constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402; + -- Natural log of 10 + constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074; + -- Log base 2 of e + constant MATH_LOG10_OF_E: REAL := 0.43429_44819_03251_82765; + -- Log base 10 of e + constant MATH_SQRT_2: REAL := 1.41421_35623_73095_04880; + -- square root of 2 + constant MATH_1_OVER_SQRT_2: REAL := 0.70710_67811_86547_52440; + -- square root of 1/2 + constant MATH_SQRT_PI: REAL := 1.77245_38509_05516_02730; + -- square root of pi + constant MATH_DEG_TO_RAD: REAL := 0.01745_32925_19943_29577; + -- Conversion factor from degree to radian + constant MATH_RAD_TO_DEG: REAL := 57.29577_95130_82320_87680; + -- Conversion factor from radian to degree + + -- + -- Function Declarations + -- + function SIGN (X: in REAL ) return REAL; + -- Purpose: + -- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0 + -- Special values: + -- None + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(SIGN(X)) <= 1.0 + -- Notes: + -- None + + function CEIL (X : in REAL ) return REAL; + -- Purpose: + -- Returns smallest INTEGER value (as REAL) not less than X + -- Special values: + -- None + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- CEIL(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function FLOOR (X : in REAL ) return REAL; + -- Purpose: + -- Returns largest INTEGER value (as REAL) not greater than X + -- Special values: + -- FLOOR(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- FLOOR(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function ROUND (X : in REAL ) return REAL; + -- Purpose: + -- Rounds X to the nearest integer value (as real). If X is + -- halfway between two integers, rounding is away from 0.0 + -- Special values: + -- ROUND(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ROUND(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function TRUNC (X : in REAL ) return REAL; + -- Purpose: + -- Truncates X towards 0.0 and returns truncated value + -- Special values: + -- TRUNC(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- TRUNC(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function "MOD" (X, Y: in REAL ) return REAL; + -- Purpose: + -- Returns floating point modulus of X/Y, with the same sign as + -- Y, and absolute value less than the absolute value of Y, and + -- for some INTEGER value N the result satisfies the relation + -- X = Y*N + MOD(X,Y) + -- Special values: + -- None + -- Domain: + -- X in REAL; Y in REAL and Y /= 0.0 + -- Error conditions: + -- Error if Y = 0.0 + -- Range: + -- ABS(MOD(X,Y)) < ABS(Y) + -- Notes: + -- None + + function REALMAX (X, Y : in REAL ) return REAL; + -- Purpose: + -- Returns the algebraically larger of X and Y + -- Special values: + -- REALMAX(X,Y) = X when X = Y + -- Domain: + -- X in REAL; Y in REAL + -- Error conditions: + -- None + -- Range: + -- REALMAX(X,Y) is mathematically unbounded + -- Notes: + -- None + + function REALMIN (X, Y : in REAL ) return REAL; + -- Purpose: + -- Returns the algebraically smaller of X and Y + -- Special values: + -- REALMIN(X,Y) = X when X = Y + -- Domain: + -- X in REAL; Y in REAL + -- Error conditions: + -- None + -- Range: + -- REALMIN(X,Y) is mathematically unbounded + -- Notes: + -- None + + procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE; variable X:out REAL); + -- Purpose: + -- Returns, in X, a pseudo-random number with uniform + -- distribution in the open interval (0.0, 1.0). + -- Special values: + -- None + -- Domain: + -- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398 + -- Error conditions: + -- Error if SEED1 or SEED2 outside of valid domain + -- Range: + -- 0.0 < X < 1.0 + -- Notes: + -- a) The semantics for this function are described by the + -- algorithm published by Pierre L'Ecuyer in "Communications + -- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774. + -- The algorithm is based on the combination of two + -- multiplicative linear congruential generators for 32-bit + -- platforms. + -- + -- b) Before the first call to UNIFORM, the seed values + -- (SEED1, SEED2) have to be initialized to values in the range + -- [1, 2147483562] and [1, 2147483398] respectively. The + -- seed values are modified after each call to UNIFORM. + -- + -- c) This random number generator is portable for 32-bit + -- computers, and it has a period of ~2.30584*(10**18) for each + -- set of seed values. + -- + -- d) For information on spectral tests for the algorithm, refer + -- to the L'Ecuyer article. + + function SQRT (X : in REAL ) return REAL; + -- Purpose: + -- Returns square root of X + -- Special values: + -- SQRT(0.0) = 0.0 + -- SQRT(1.0) = 1.0 + -- Domain: + -- X >= 0.0 + -- Error conditions: + -- Error if X < 0.0 + -- Range: + -- SQRT(X) >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range of SQRT is + -- approximately given by: + -- SQRT(X) <= SQRT(REAL'HIGH) + + function CBRT (X : in REAL ) return REAL; + -- Purpose: + -- Returns cube root of X + -- Special values: + -- CBRT(0.0) = 0.0 + -- CBRT(1.0) = 1.0 + -- CBRT(-1.0) = -1.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- CBRT(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of CBRT is approximately given by: + -- ABS(CBRT(X)) <= CBRT(REAL'HIGH) + + function "**" (X : in INTEGER; Y : in REAL) return REAL; + -- Purpose: + -- Returns Y power of X ==> X**Y + -- Special values: + -- X**0.0 = 1.0; X /= 0 + -- 0**Y = 0.0; Y > 0.0 + -- X**1.0 = REAL(X); X >= 0 + -- 1**Y = 1.0 + -- Domain: + -- X > 0 + -- X = 0 for Y > 0.0 + -- X < 0 for Y = 0.0 + -- Error conditions: + -- Error if X < 0 and Y /= 0.0 + -- Error if X = 0 and Y <= 0.0 + -- Range: + -- X**Y >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range for "**" is + -- approximately given by: + -- X**Y <= REAL'HIGH + + function "**" (X : in REAL; Y : in REAL) return REAL; + -- Purpose: + -- Returns Y power of X ==> X**Y + -- Special values: + -- X**0.0 = 1.0; X /= 0.0 + -- 0.0**Y = 0.0; Y > 0.0 + -- X**1.0 = X; X >= 0.0 + -- 1.0**Y = 1.0 + -- Domain: + -- X > 0.0 + -- X = 0.0 for Y > 0.0 + -- X < 0.0 for Y = 0.0 + -- Error conditions: + -- Error if X < 0.0 and Y /= 0.0 + -- Error if X = 0.0 and Y <= 0.0 + -- Range: + -- X**Y >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range for "**" is + -- approximately given by: + -- X**Y <= REAL'HIGH + + function EXP (X : in REAL ) return REAL; + -- Purpose: + -- Returns e**X; where e = MATH_E + -- Special values: + -- EXP(0.0) = 1.0 + -- EXP(1.0) = MATH_E + -- EXP(-1.0) = MATH_1_OVER_E + -- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH) + -- Domain: + -- X in REAL such that EXP(X) <= REAL'HIGH + -- Error conditions: + -- Error if X > LOG(REAL'HIGH) + -- Range: + -- EXP(X) >= 0.0 + -- Notes: + -- a) The usable domain of EXP is approximately given by: + -- X <= LOG(REAL'HIGH) + + function LOG (X : in REAL ) return REAL; + -- Purpose: + -- Returns natural logarithm of X + -- Special values: + -- LOG(1.0) = 0.0 + -- LOG(MATH_E) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG is approximately given by: + -- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH) + + function LOG2 (X : in REAL ) return REAL; + -- Purpose: + -- Returns logarithm base 2 of X + -- Special values: + -- LOG2(1.0) = 0.0 + -- LOG2(2.0) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG2(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG2 is approximately given by: + -- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH) + + function LOG10 (X : in REAL ) return REAL; + -- Purpose: + -- Returns logarithm base 10 of X + -- Special values: + -- LOG10(1.0) = 0.0 + -- LOG10(10.0) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG10(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG10 is approximately given by: + -- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH) + + function LOG (X: in REAL; BASE: in REAL) return REAL; + -- Purpose: + -- Returns logarithm base BASE of X + -- Special values: + -- LOG(1.0, BASE) = 0.0 + -- LOG(BASE, BASE) = 1.0 + -- Domain: + -- X > 0.0 + -- BASE > 0.0 + -- BASE /= 1.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Error if BASE <= 0.0 + -- Error if BASE = 1.0 + -- Range: + -- LOG(X, BASE) is mathematically unbounded + -- Notes: + -- a) When BASE > 1.0, the reachable range of LOG is + -- approximately given by: + -- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE) + -- b) When 0.0 < BASE < 1.0, the reachable range of LOG is + -- approximately given by: + -- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE) + + function SIN (X : in REAL ) return REAL; + -- Purpose: + -- Returns sine of X; X in radians + -- Special values: + -- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER + -- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(SIN(X)) <= 1.0 + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function COS ( X : in REAL ) return REAL; + -- Purpose: + -- Returns cosine of X; X in radians + -- Special values: + -- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER + -- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(COS(X)) <= 1.0 + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function TAN (X : in REAL ) return REAL; + -- Purpose: + -- Returns tangent of X; X in radians + -- Special values: + -- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER + -- Domain: + -- X in REAL and + -- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER + -- Error conditions: + -- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an + -- INTEGER + -- Range: + -- TAN(X) is mathematically unbounded + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function ARCSIN (X : in REAL ) return REAL; + -- Purpose: + -- Returns inverse sine of X + -- Special values: + -- ARCSIN(0.0) = 0.0 + -- ARCSIN(1.0) = MATH_PI_OVER_2 + -- ARCSIN(-1.0) = -MATH_PI_OVER_2 + -- Domain: + -- ABS(X) <= 1.0 + -- Error conditions: + -- Error if ABS(X) > 1.0 + -- Range: + -- ABS(ARCSIN(X) <= MATH_PI_OVER_2 + -- Notes: + -- None + + function ARCCOS (X : in REAL ) return REAL; + -- Purpose: + -- Returns inverse cosine of X + -- Special values: + -- ARCCOS(1.0) = 0.0 + -- ARCCOS(0.0) = MATH_PI_OVER_2 + -- ARCCOS(-1.0) = MATH_PI + -- Domain: + -- ABS(X) <= 1.0 + -- Error conditions: + -- Error if ABS(X) > 1.0 + -- Range: + -- 0.0 <= ARCCOS(X) <= MATH_PI + -- Notes: + -- None + + function ARCTAN (Y : in REAL) return REAL; + -- Purpose: + -- Returns the value of the angle in radians of the point + -- (1.0, Y), which is in rectangular coordinates + -- Special values: + -- ARCTAN(0.0) = 0.0 + -- Domain: + -- Y in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2 + -- Notes: + -- None + + function ARCTAN (Y : in REAL; X : in REAL) return REAL; + -- Purpose: + -- Returns the principal value of the angle in radians of + -- the point (X, Y), which is in rectangular coordinates + -- Special values: + -- ARCTAN(0.0, X) = 0.0 if X > 0.0 + -- ARCTAN(0.0, X) = MATH_PI if X < 0.0 + -- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0 + -- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0 + -- Domain: + -- Y in REAL + -- X in REAL, X /= 0.0 when Y = 0.0 + -- Error conditions: + -- Error if X = 0.0 and Y = 0.0 + -- Range: + -- -MATH_PI < ARCTAN(Y,X) <= MATH_PI + -- Notes: + -- None + + function SINH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic sine of X + -- Special values: + -- SINH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- SINH(X) is mathematically unbounded + -- Notes: + -- a) The usable domain of SINH is approximately given by: + -- ABS(X) <= LOG(REAL'HIGH) + + + function COSH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic cosine of X + -- Special values: + -- COSH(0.0) = 1.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- COSH(X) >= 1.0 + -- Notes: + -- a) The usable domain of COSH is approximately given by: + -- ABS(X) <= LOG(REAL'HIGH) + + function TANH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic tangent of X + -- Special values: + -- TANH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(TANH(X)) <= 1.0 + -- Notes: + -- None + + function ARCSINH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic sine of X + -- Special values: + -- ARCSINH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ARCSINH(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of ARCSINH is approximately given by: + -- ABS(ARCSINH(X)) <= LOG(REAL'HIGH) + + function ARCCOSH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic cosine of X + -- Special values: + -- ARCCOSH(1.0) = 0.0 + -- Domain: + -- X >= 1.0 + -- Error conditions: + -- Error if X < 1.0 + -- Range: + -- ARCCOSH(X) >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range of ARCCOSH is + -- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH) + + function ARCTANH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic tangent of X + -- Special values: + -- ARCTANH(0.0) = 0.0 + -- Domain: + -- ABS(X) < 1.0 + -- Error conditions: + -- Error if ABS(X) >= 1.0 + -- Range: + -- ARCTANH(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of ARCTANH is approximately given by: + -- ABS(ARCTANH(X)) < LOG(REAL'HIGH) + +end MATH_REAL; + + + +------------------------------------------------------------------------ +-- +-- Copyright 1996 by IEEE. All rights reserved. + +-- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard +-- VHDL Mathematical Packages. This source file may not be copied, sold, or +-- included with software that is sold without written permission from the IEEE +-- Standards Department. This source file may be used to implement this standard +-- and may be distributed in compiled form in any manner so long as the +-- compiled form does not allow direct decompilation of the original source file. +-- This source file may be copied for individual use between licensed users. +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source +-- file shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. + +-- +-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, +-- MATH_REAL) +-- +-- Library: This package shall be compiled into a library +-- symbolically named IEEE. +-- +-- Developers: IEEE DASC VHDL Mathematical Packages Working Group +-- +-- Purpose: This package body is a nonnormative implementation of the +-- functionality defined in the MATH_REAL package declaration. +-- +-- Limitation: The values generated by the functions in this package may +-- vary from platform to platform, and the precision of results +-- is only guaranteed to be the minimum required by IEEE Std 1076 +-- -1993. +-- +-- Notes: +-- The "package declaration" defines the types, subtypes, and +-- declarations of MATH_REAL. +-- The standard mathematical definition and conventional meaning +-- of the mathematical functions that are part of this standard +-- represent the formal semantics of the implementation of the +-- MATH_REAL package declaration. The purpose of the MATH_REAL +-- package body is to clarify such semantics and provide a +-- guideline for implementations to verify their implementation +-- of MATH_REAL. Tool developers may choose to implement +-- the package body in the most efficient manner available to them. +-- +-- ----------------------------------------------------------------------------- +-- Version : 1.5 +-- Date : 24 July 1996 +-- ----------------------------------------------------------------------------- + +package body MATH_REAL is + + -- + -- Local Constants for Use in the Package Body Only + -- + constant MATH_E_P2 : REAL := 7.38905_60989_30650; -- e**2 + constant MATH_E_P10 : REAL := 22026.46579_48067_17; -- e**10 + constant MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi + constant MAX_ITER: INTEGER := 27; -- Maximum precision factor for cordic + constant MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries + constant BASE_EPS: REAL := 0.00001; -- Factor for convergence criteria + constant KC : REAL := 6.0725293500888142e-01; -- Constant for cordic + + -- + -- Local Type Declarations for Cordic Operations + -- + type REAL_VECTOR is array (NATURAL range <>) of REAL; + type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL; + subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER); + subtype REAL_ARR_2 is REAL_VECTOR (0 to 1); + subtype REAL_ARR_3 is REAL_VECTOR (0 to 2); + subtype QUADRANT is INTEGER range 0 to 3; + type CORDIC_MODE_TYPE is (ROTATION, VECTORING); + + -- + -- Auxiliary Functions for Cordic Algorithms + -- + function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL; + NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is + -- Description: + -- Returns power of two for a vector of values + -- Notes: + -- None + -- + variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES); + variable TEMP : REAL := INITIAL_VALUE; + variable FLAG : BOOLEAN := TRUE; + begin + for I in 0 to NUMBER_OF_VALUES loop + V(I) := TEMP; + for P in D'RANGE loop + if I = D(P) then + FLAG := FALSE; + exit; + end if; + end loop; + if FLAG then + TEMP := TEMP/2.0; + end if; + FLAG := TRUE; + end loop; + return V; + end POWER_OF_2_SERIES; + + + constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES( + NATURAL_VECTOR'(100, 90),1.0, + MAX_ITER); + + constant EPSILON : REAL_VECTOR_N := ( + 7.8539816339744827e-01, + 4.6364760900080606e-01, + 2.4497866312686413e-01, + 1.2435499454676144e-01, + 6.2418809995957351e-02, + 3.1239833430268277e-02, + 1.5623728620476830e-02, + 7.8123410601011116e-03, + 3.9062301319669717e-03, + 1.9531225164788189e-03, + 9.7656218955931937e-04, + 4.8828121119489829e-04, + 2.4414062014936175e-04, + 1.2207031189367021e-04, + 6.1035156174208768e-05, + 3.0517578115526093e-05, + 1.5258789061315760e-05, + 7.6293945311019699e-06, + 3.8146972656064960e-06, + 1.9073486328101870e-06, + 9.5367431640596080e-07, + 4.7683715820308876e-07, + 2.3841857910155801e-07, + 1.1920928955078067e-07, + 5.9604644775390553e-08, + 2.9802322387695303e-08, + 1.4901161193847654e-08, + 7.4505805969238281e-09 + ); + + function CORDIC ( X0 : in REAL; + Y0 : in REAL; + Z0 : in REAL; + N : in NATURAL; -- Precision factor + CORDIC_MODE : in CORDIC_MODE_TYPE -- Rotation (Z -> 0) + -- or vectoring (Y -> 0) + ) return REAL_ARR_3 is + -- Description: + -- Compute cordic values + -- Notes: + -- None + variable X : REAL := X0; + variable Y : REAL := Y0; + variable Z : REAL := Z0; + variable X_TEMP : REAL; + begin + if CORDIC_MODE = ROTATION then + for K in 0 to N loop + X_TEMP := X; + if ( Z >= 0.0) then + X := X - Y * TWO_AT_MINUS(K); + Y := Y + X_TEMP * TWO_AT_MINUS(K); + Z := Z - EPSILON(K); + else + X := X + Y * TWO_AT_MINUS(K); + Y := Y - X_TEMP * TWO_AT_MINUS(K); + Z := Z + EPSILON(K); + end if; + end loop; + else + for K in 0 to N loop + X_TEMP := X; + if ( Y < 0.0) then + X := X - Y * TWO_AT_MINUS(K); + Y := Y + X_TEMP * TWO_AT_MINUS(K); + Z := Z - EPSILON(K); + else + X := X + Y * TWO_AT_MINUS(K); + Y := Y - X_TEMP * TWO_AT_MINUS(K); + Z := Z + EPSILON(K); + end if; + end loop; + end if; + return REAL_ARR_3'(X, Y, Z); + end CORDIC; + + -- + -- Bodies for Global Mathematical Functions Start Here + -- + function SIGN (X: in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + begin + if ( X > 0.0 ) then + return 1.0; + elsif ( X < 0.0 ) then + return -1.0; + else + return 0.0; + end if; + end SIGN; + + function CEIL (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) No conversion to an INTEGER type is expected, so truncate + -- cannot overflow for large arguments + -- b) The domain supported by this function is X <= LARGE + -- c) Returns X if ABS(X) >= LARGE + + constant LARGE: REAL := REAL(INTEGER'HIGH); + variable RD: REAL; + + begin + if ABS(X) >= LARGE then + return X; + end if; + + RD := REAL ( INTEGER(X)); + if RD = X then + return X; + end if; + + if X > 0.0 then + if RD >= X then + return RD; + else + return RD + 1.0; + end if; + elsif X = 0.0 then + return 0.0; + else + if RD <= X then + return RD + 1.0; + else + return RD; + end if; + end if; + end CEIL; + + function FLOOR (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) No conversion to an INTEGER type is expected, so truncate + -- cannot overflow for large arguments + -- b) The domain supported by this function is ABS(X) <= LARGE + -- c) Returns X if ABS(X) >= LARGE + + constant LARGE: REAL := REAL(INTEGER'HIGH); + variable RD: REAL; + + begin + if ABS( X ) >= LARGE then + return X; + end if; + + RD := REAL ( INTEGER(X)); + if RD = X then + return X; + end if; + + if X > 0.0 then + if RD <= X then + return RD; + else + return RD - 1.0; + end if; + elsif X = 0.0 then + return 0.0; + else + if RD >= X then + return RD - 1.0; + else + return RD; + end if; + end if; + end FLOOR; + + function ROUND (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 if X = 0.0 + -- b) Returns FLOOR(X + 0.5) if X > 0 + -- c) Returns CEIL(X - 0.5) if X < 0 + + begin + if X > 0.0 then + return FLOOR(X + 0.5); + elsif X < 0.0 then + return CEIL( X - 0.5); + else + return 0.0; + end if; + end ROUND; + + function TRUNC (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 if X = 0.0 + -- b) Returns FLOOR(X) if X > 0 + -- c) Returns CEIL(X) if X < 0 + + begin + if X > 0.0 then + return FLOOR(X); + elsif X < 0.0 then + return CEIL( X); + else + return 0.0; + end if; + end TRUNC; + + + + + function "MOD" (X, Y: in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + + variable XNEGATIVE : BOOLEAN := X < 0.0; + variable YNEGATIVE : BOOLEAN := Y < 0.0; + variable VALUE : REAL; + begin + -- Check validity of input arguments + if (Y = 0.0) then + assert FALSE + report "MOD(X, 0.0) is undefined" + severity ERROR; + return 0.0; + end if; + + -- Compute value + if ( XNEGATIVE ) then + if ( YNEGATIVE ) then + VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); + else + VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y); + end if; + else + if ( YNEGATIVE ) then + VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y); + else + VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); + end if; + end if; + + return VALUE; + end "MOD"; + + + function REALMAX (X, Y : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) REALMAX(X,Y) = X when X = Y + -- + begin + if X >= Y then + return X; + else + return Y; + end if; + end REALMAX; + + function REALMIN (X, Y : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) REALMIN(X,Y) = X when X = Y + -- + begin + if X <= Y then + return X; + else + return Y; + end if; + end REALMIN; + + + procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL) + is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + -- + variable Z, K: INTEGER; + variable TSEED1 : INTEGER := INTEGER'(SEED1); + variable TSEED2 : INTEGER := INTEGER'(SEED2); + begin + -- Check validity of arguments + if SEED1 > 2147483562 then + assert FALSE + report "SEED1 > 2147483562 in UNIFORM" + severity ERROR; + X := 0.0; + return; + end if; + + if SEED2 > 2147483398 then + assert FALSE + report "SEED2 > 2147483398 in UNIFORM" + severity ERROR; + X := 0.0; + return; + end if; + + -- Compute new seed values and pseudo-random number + K := TSEED1/53668; + TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211; + + if TSEED1 < 0 then + TSEED1 := TSEED1 + 2147483563; + end if; + + K := TSEED2/52774; + TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791; + + if TSEED2 < 0 then + TSEED2 := TSEED2 + 2147483399; + end if; + + Z := TSEED1 - TSEED2; + if Z < 1 then + Z := Z + 2147483562; + end if; + + -- Get output values + SEED1 := POSITIVE'(TSEED1); + SEED2 := POSITIVE'(TSEED2); + X := REAL(Z)*4.656613e-10; + end UNIFORM; + + + + function SQRT (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Uses the Newton-Raphson approximation: + -- F(n+1) = 0.5*[F(n) + x/F(n)] + -- b) Returns 0.0 on error + -- + + constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor + + variable INIVAL: REAL; + variable OLDVAL : REAL ; + variable NEWVAL : REAL ; + variable COUNT : INTEGER := 1; + + begin + -- Check validity of argument + if ( X < 0.0 ) then + assert FALSE + report "X < 0.0 in SQRT(X)" + severity ERROR; + return 0.0; + end if; + + -- Get the square root for special cases + if X = 0.0 then + return 0.0; + else + if ( X = 1.0 ) then + return 1.0; + end if; + end if; + + -- Get the square root for general cases + INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise + OLDVAL := INIVAL; + NEWVAL := (X/OLDVAL + OLDVAL)*0.5; + + -- Check for relative and absolute error and max count + while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR + (ABS(NEWVAL - OLDVAL) > EPS) ) AND + (COUNT < MAX_COUNT) ) loop + OLDVAL := NEWVAL; + NEWVAL := (X/OLDVAL + OLDVAL)*0.5; + COUNT := COUNT + 1; + end loop; + return NEWVAL; + end SQRT; + + function CBRT (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Uses the Newton-Raphson approximation: + -- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2]; + -- + constant EPS : REAL := BASE_EPS*BASE_EPS; + + variable INIVAL: REAL; + variable XLOCAL : REAL := X; + variable NEGATIVE : BOOLEAN := X < 0.0; + variable OLDVAL : REAL ; + variable NEWVAL : REAL ; + variable COUNT : INTEGER := 1; + + begin + + -- Compute root for special cases + if X = 0.0 then + return 0.0; + elsif ( X = 1.0 ) then + return 1.0; + else + if X = -1.0 then + return -1.0; + end if; + end if; + + -- Compute root for general cases + if NEGATIVE then + XLOCAL := -X; + end if; + + INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but + -- imprecise + OLDVAL := INIVAL; + NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; + + -- Check for relative and absolute errors and max count + while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR + (ABS(NEWVAL - OLDVAL) > EPS ) ) AND + ( COUNT < MAX_COUNT ) ) loop + OLDVAL := NEWVAL; + NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; + COUNT := COUNT + 1; + end loop; + + if NEGATIVE then + NEWVAL := -NEWVAL; + end if; + + return NEWVAL; + end CBRT; + + function "**" (X : in INTEGER; Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error condition + + begin + -- Check validity of argument + if ( ( X < 0 ) and ( Y /= 0.0 ) ) then + assert FALSE + report "X < 0 and Y /= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + if ( ( X = 0 ) and ( Y <= 0.0 ) ) then + assert FALSE + report "X = 0 and Y <= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + -- Get value for special cases + if ( X = 0 and Y > 0.0 ) then + return 0.0; + end if; + + if ( X = 1 ) then + return 1.0; + end if; + + if ( Y = 0.0 and X /= 0 ) then + return 1.0; + end if; + + if ( Y = 1.0) then + return (REAL(X)); + end if; + + -- Get value for general case + return EXP (Y * LOG (REAL(X))); + end "**"; + + function "**" (X : in REAL; Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error condition + + begin + -- Check validity of argument + if ( ( X < 0.0 ) and ( Y /= 0.0 ) ) then + assert FALSE + report "X < 0.0 and Y /= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + if ( ( X = 0.0 ) and ( Y <= 0.0 ) ) then + assert FALSE + report "X = 0.0 and Y <= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + -- Get value for special cases + if ( X = 0.0 and Y > 0.0 ) then + return 0.0; + end if; + + if ( X = 1.0 ) then + return 1.0; + end if; + + if ( Y = 0.0 and X /= 0.0 ) then + return 1.0; + end if; + + if ( Y = 1.0) then + return (X); + end if; + + -- Get value for general case + return EXP (Y * LOG (X)); + end "**"; + + function EXP (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) This function computes the exponential using the following + -- series: + -- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0 + -- and reduces argument X to take advantage of exp(x+y) = + -- exp(x)*exp(y) + -- + -- b) This implementation limits X to be less than LOG(REAL'HIGH) + -- to avoid overflow. Returns REAL'HIGH when X reaches that + -- limit + -- + constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria + + variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument + variable XLOCAL : REAL := ABS(X); -- Use positive value + variable OLDVAL: REAL ; + variable COUNT: INTEGER ; + variable NEWVAL: REAL ; + variable LAST_TERM: REAL ; + variable FACTOR : REAL := 1.0; + + begin + -- Compute value for special cases + if X = 0.0 then + return 1.0; + end if; + + if XLOCAL = 1.0 then + if RECIPROCAL then + return MATH_1_OVER_E; + else + return MATH_E; + end if; + end if; + + if XLOCAL = 2.0 then + if RECIPROCAL then + return 1.0/MATH_E_P2; + else + return MATH_E_P2; + end if; + end if; + + if XLOCAL = 10.0 then + if RECIPROCAL then + return 1.0/MATH_E_P10; + else + return MATH_E_P10; + end if; + end if; + + if XLOCAL > LOG(REAL'HIGH) then + if RECIPROCAL then + return 0.0; + else + assert FALSE + report "X > LOG(REAL'HIGH) in EXP(X)" + severity NOTE; + return REAL'HIGH; + end if; + end if; + + -- Reduce argument to ABS(X) < 1.0 + while XLOCAL > 10.0 loop + XLOCAL := XLOCAL - 10.0; + FACTOR := FACTOR*MATH_E_P10; + end loop; + + while XLOCAL > 1.0 loop + XLOCAL := XLOCAL - 1.0; + FACTOR := FACTOR*MATH_E; + end loop; + + -- Compute value for case 0 < XLOCAL < 1 + OLDVAL := 1.0; + LAST_TERM := XLOCAL; + NEWVAL:= OLDVAL + LAST_TERM; + COUNT := 2; + + -- Check for relative and absolute errors and max count + while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR + (ABS(NEWVAL - OLDVAL) > EPS) ) AND + (COUNT < MAX_COUNT ) ) loop + OLDVAL := NEWVAL; + LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT))); + NEWVAL := OLDVAL + LAST_TERM; + COUNT := COUNT + 1; + end loop; + + -- Compute final value using exp(x+y) = exp(x)*exp(y) + NEWVAL := NEWVAL*FACTOR; + + if RECIPROCAL then + NEWVAL := 1.0/NEWVAL; + end if; + + return NEWVAL; + end EXP; + + + -- + -- Auxiliary Functions to Compute LOG + -- + function ILOGB(X: in REAL) return INTEGER IS + -- Description: + -- Returns n such that -1 <= ABS(X)/2^n < 2 + -- Notes: + -- None + + variable N: INTEGER := 0; + variable Y: REAL := ABS(X); + + begin + if(Y = 1.0 or Y = 0.0) then + return 0; + end if; + + if( Y > 1.0) then + while Y >= 2.0 loop + Y := Y/2.0; + N := N+1; + end loop; + return N; + end if; + + -- O < Y < 1 + while Y < 1.0 loop + Y := Y*2.0; + N := N -1; + end loop; + return N; + end ILOGB; + + function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS + -- Description: + -- Returns X*2^n + -- Notes: + -- None + begin + return X*(2.0 ** N); + end LDEXP; + + function LOG (X : in REAL ) return REAL IS + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- + -- Notes: + -- a) Returns REAL'LOW on error + -- + -- Copyright (c) 1992 Regents of the University of California. + -- All rights reserved. + -- + -- Redistribution and use in source and binary forms, with or without + -- modification, are permitted provided that the following conditions + -- are met: + -- 1. Redistributions of source code must retain the above copyright + -- notice, this list of conditions and the following disclaimer. + -- 2. Redistributions in binary form must reproduce the above copyright + -- notice, this list of conditions and the following disclaimer in the + -- documentation and/or other materials provided with the distribution. + -- 3. All advertising materials mentioning features or use of this + -- software must display the following acknowledgement: + -- This product includes software developed by the University of + -- California, Berkeley and its contributors. + -- 4. Neither the name of the University nor the names of its + -- contributors may be used to endorse or promote products derived + -- from this software without specific prior written permission. + -- + -- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' + -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR + -- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + -- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + -- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY + -- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + -- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + -- DAMAGE. + -- + -- NOTE: This VHDL version was generated using the C version of the + -- original function by the IEEE VHDL Mathematical Package + -- Working Group (CS/JT) + + constant N: INTEGER := 128; + + -- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128. + -- Used for generation of extend precision logarithms. + -- The constant 35184372088832 is 2^45, so the divide is exact. + -- It ensures correct reading of logF_head, even for inaccurate + -- decimal-to-binary conversion routines. (Everybody gets the + -- right answer for INTEGERs less than 2^53.) + -- Values for LOG(F) were generated using error < 10^-57 absolute + -- with the bc -l package. + + type REAL_VECTOR is array (NATURAL range <>) of REAL; + + constant A1:REAL := 0.08333333333333178827; + constant A2:REAL := 0.01250000000377174923; + constant A3:REAL := 0.002232139987919447809; + constant A4:REAL := 0.0004348877777076145742; + + constant LOGF_HEAD: REAL_VECTOR(0 TO N) := ( + 0.0, + 0.007782140442060381246, + 0.015504186535963526694, + 0.023167059281547608406, + 0.030771658666765233647, + 0.038318864302141264488, + 0.045809536031242714670, + 0.053244514518837604555, + 0.060624621816486978786, + 0.067950661908525944454, + 0.075223421237524235039, + 0.082443669210988446138, + 0.089612158689760690322, + 0.096729626458454731618, + 0.103796793681567578460, + 0.110814366340264314203, + 0.117783035656430001836, + 0.124703478501032805070, + 0.131576357788617315236, + 0.138402322859292326029, + 0.145182009844575077295, + 0.151916042025732167530, + 0.158605030176659056451, + 0.165249572895390883786, + 0.171850256926518341060, + 0.178407657472689606947, + 0.184922338493834104156, + 0.191394852999565046047, + 0.197825743329758552135, + 0.204215541428766300668, + 0.210564769107350002741, + 0.216873938300523150246, + 0.223143551314024080056, + 0.229374101064877322642, + 0.235566071312860003672, + 0.241719936886966024758, + 0.247836163904594286577, + 0.253915209980732470285, + 0.259957524436686071567, + 0.265963548496984003577, + 0.271933715484010463114, + 0.277868451003087102435, + 0.283768173130738432519, + 0.289633292582948342896, + 0.295464212893421063199, + 0.301261330578199704177, + 0.307025035294827830512, + 0.312755710004239517729, + 0.318453731118097493890, + 0.324119468654316733591, + 0.329753286372579168528, + 0.335355541920762334484, + 0.340926586970454081892, + 0.346466767346100823488, + 0.351976423156884266063, + 0.357455888922231679316, + 0.362905493689140712376, + 0.368325561158599157352, + 0.373716409793814818840, + 0.379078352934811846353, + 0.384411698910298582632, + 0.389716751140440464951, + 0.394993808240542421117, + 0.400243164127459749579, + 0.405465108107819105498, + 0.410659924985338875558, + 0.415827895143593195825, + 0.420969294644237379543, + 0.426084395310681429691, + 0.431173464818130014464, + 0.436236766774527495726, + 0.441274560805140936281, + 0.446287102628048160113, + 0.451274644139630254358, + 0.456237433481874177232, + 0.461175715122408291790, + 0.466089729924533457960, + 0.470979715219073113985, + 0.475845904869856894947, + 0.480688529345570714212, + 0.485507815781602403149, + 0.490303988045525329653, + 0.495077266798034543171, + 0.499827869556611403822, + 0.504556010751912253908, + 0.509261901790523552335, + 0.513945751101346104405, + 0.518607764208354637958, + 0.523248143765158602036, + 0.527867089620485785417, + 0.532464798869114019908, + 0.537041465897345915436, + 0.541597282432121573947, + 0.546132437597407260909, + 0.550647117952394182793, + 0.555141507540611200965, + 0.559615787935399566777, + 0.564070138285387656651, + 0.568504735352689749561, + 0.572919753562018740922, + 0.577315365035246941260, + 0.581691739635061821900, + 0.586049045003164792433, + 0.590387446602107957005, + 0.594707107746216934174, + 0.599008189645246602594, + 0.603290851438941899687, + 0.607555250224322662688, + 0.611801541106615331955, + 0.616029877215623855590, + 0.620240409751204424537, + 0.624433288012369303032, + 0.628608659422752680256, + 0.632766669570628437213, + 0.636907462236194987781, + 0.641031179420679109171, + 0.645137961373620782978, + 0.649227946625615004450, + 0.653301272011958644725, + 0.657358072709030238911, + 0.661398482245203922502, + 0.665422632544505177065, + 0.669430653942981734871, + 0.673422675212350441142, + 0.677398823590920073911, + 0.681359224807238206267, + 0.685304003098281100392, + 0.689233281238557538017, + 0.693147180560117703862); + + constant LOGF_TAIL: REAL_VECTOR(0 TO N) := ( + 0.0, + -0.00000000000000543229938420049, + 0.00000000000000172745674997061, + -0.00000000000001323017818229233, + -0.00000000000001154527628289872, + -0.00000000000000466529469958300, + 0.00000000000005148849572685810, + -0.00000000000002532168943117445, + -0.00000000000005213620639136504, + -0.00000000000001819506003016881, + 0.00000000000006329065958724544, + 0.00000000000008614512936087814, + -0.00000000000007355770219435028, + 0.00000000000009638067658552277, + 0.00000000000007598636597194141, + 0.00000000000002579999128306990, + -0.00000000000004654729747598444, + -0.00000000000007556920687451336, + 0.00000000000010195735223708472, + -0.00000000000017319034406422306, + -0.00000000000007718001336828098, + 0.00000000000010980754099855238, + -0.00000000000002047235780046195, + -0.00000000000008372091099235912, + 0.00000000000014088127937111135, + 0.00000000000012869017157588257, + 0.00000000000017788850778198106, + 0.00000000000006440856150696891, + 0.00000000000016132822667240822, + -0.00000000000007540916511956188, + -0.00000000000000036507188831790, + 0.00000000000009120937249914984, + 0.00000000000018567570959796010, + -0.00000000000003149265065191483, + -0.00000000000009309459495196889, + 0.00000000000017914338601329117, + -0.00000000000001302979717330866, + 0.00000000000023097385217586939, + 0.00000000000023999540484211737, + 0.00000000000015393776174455408, + -0.00000000000036870428315837678, + 0.00000000000036920375082080089, + -0.00000000000009383417223663699, + 0.00000000000009433398189512690, + 0.00000000000041481318704258568, + -0.00000000000003792316480209314, + 0.00000000000008403156304792424, + -0.00000000000034262934348285429, + 0.00000000000043712191957429145, + -0.00000000000010475750058776541, + -0.00000000000011118671389559323, + 0.00000000000037549577257259853, + 0.00000000000013912841212197565, + 0.00000000000010775743037572640, + 0.00000000000029391859187648000, + -0.00000000000042790509060060774, + 0.00000000000022774076114039555, + 0.00000000000010849569622967912, + -0.00000000000023073801945705758, + 0.00000000000015761203773969435, + 0.00000000000003345710269544082, + -0.00000000000041525158063436123, + 0.00000000000032655698896907146, + -0.00000000000044704265010452446, + 0.00000000000034527647952039772, + -0.00000000000007048962392109746, + 0.00000000000011776978751369214, + -0.00000000000010774341461609578, + 0.00000000000021863343293215910, + 0.00000000000024132639491333131, + 0.00000000000039057462209830700, + -0.00000000000026570679203560751, + 0.00000000000037135141919592021, + -0.00000000000017166921336082431, + -0.00000000000028658285157914353, + -0.00000000000023812542263446809, + 0.00000000000006576659768580062, + -0.00000000000028210143846181267, + 0.00000000000010701931762114254, + 0.00000000000018119346366441110, + 0.00000000000009840465278232627, + -0.00000000000033149150282752542, + -0.00000000000018302857356041668, + -0.00000000000016207400156744949, + 0.00000000000048303314949553201, + -0.00000000000071560553172382115, + 0.00000000000088821239518571855, + -0.00000000000030900580513238244, + -0.00000000000061076551972851496, + 0.00000000000035659969663347830, + 0.00000000000035782396591276383, + -0.00000000000046226087001544578, + 0.00000000000062279762917225156, + 0.00000000000072838947272065741, + 0.00000000000026809646615211673, + -0.00000000000010960825046059278, + 0.00000000000002311949383800537, + -0.00000000000058469058005299247, + -0.00000000000002103748251144494, + -0.00000000000023323182945587408, + -0.00000000000042333694288141916, + -0.00000000000043933937969737844, + 0.00000000000041341647073835565, + 0.00000000000006841763641591466, + 0.00000000000047585534004430641, + 0.00000000000083679678674757695, + -0.00000000000085763734646658640, + 0.00000000000021913281229340092, + -0.00000000000062242842536431148, + -0.00000000000010983594325438430, + 0.00000000000065310431377633651, + -0.00000000000047580199021710769, + -0.00000000000037854251265457040, + 0.00000000000040939233218678664, + 0.00000000000087424383914858291, + 0.00000000000025218188456842882, + -0.00000000000003608131360422557, + -0.00000000000050518555924280902, + 0.00000000000078699403323355317, + -0.00000000000067020876961949060, + 0.00000000000016108575753932458, + 0.00000000000058527188436251509, + -0.00000000000035246757297904791, + -0.00000000000018372084495629058, + 0.00000000000088606689813494916, + 0.00000000000066486268071468700, + 0.00000000000063831615170646519, + 0.00000000000025144230728376072, + -0.00000000000017239444525614834); + + variable M, J:INTEGER; + variable F1, F2, G, Q, U, U2, V: REAL; + variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs + variable ONE: REAL := 1.0; --Made variable so no constant folding occurs + + -- double logb(), ldexp(); + + variable U1:REAL; + + begin + + -- Check validity of argument + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = MATH_E ) then + return 1.0; + end if; + + -- Argument reduction: 1 <= g < 2; x/2^m = g; + -- y = F*(1 + f/F) for |f| <= 2^-8 + + M := ILOGB(X); + G := LDEXP(X, -M); + J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding + F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512] + F2 := G - F1; + + -- Approximate expansion for log(1+f2/F1) ~= u + q + G := 1.0/(2.0*F1+F2); + U := 2.0*F2*G; + V := U*U; + Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4))); + + -- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8, + -- u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits. + -- It also adds exactly to |m*log2_hi + log_F_head[j] | < 750. + -- + if ( J /= 0 or M /= 0) then + U1 := U + 513.0; + U1 := U1 - 513.0; + + -- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero + -- u1 = u to 24 bits. + -- + else + U1 := U; + --TRUNC(U1); --In c this is u1 = (double) (float) (u1) + end if; + + U2 := (2.0*(F2 - F1*U1) - U1*F2) * G; + -- u1 + u2 = 2f/(2F+f) to extra precision. + + -- log(x) = log(2^m*F1*(1+f2/F1)) = + -- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q); + -- (exact) + (tiny) + + U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J); -- Exact + U2 := (U2 + LOGF_TAIL(J)) + Q; -- Tiny + U2 := U2 + LOGF_TAIL(N)*REAL(M); + return (U1 + U2); + end LOG; + + + function LOG2 (X: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG2(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = 2.0 ) then + return 1.0; + end if; + + -- Compute value for general case + return ( MATH_LOG2_OF_E*LOG(X) ); + end LOG2; + + + function LOG10 (X: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG10(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = 10.0 ) then + return 1.0; + end if; + + -- Compute value for general case + return ( MATH_LOG10_OF_E*LOG(X) ); + end LOG10; + + + function LOG (X: in REAL; BASE: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG(X, BASE)" + severity ERROR; + return(REAL'LOW); + end if; + + if ( BASE <= 0.0 or BASE = 1.0 ) then + assert FALSE + report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = BASE ) then + return 1.0; + end if; + + -- Compute value for general case + return ( LOG(X)/LOG(BASE)); + end LOG; + + + function SIN (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) SIN(-X) = -SIN(X) + -- b) SIN(X) = X if ABS(X) < EPS + -- c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS + -- d) SIN(MATH_PI_OVER_2 - X) = COS(X) + -- e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS + -- f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if + -- EPS< ABS(X) MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + assert FALSE + report "XLOCAL <= 0.0 after reduction in SIN(X)" + severity ERROR; + XLOCAL := -XLOCAL; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI then + return 0.0; + end if; + + if XLOCAL = MATH_PI_OVER_2 then + if NEGATIVE then + return -1.0; + else + return 1.0; + end if; + end if; + + if XLOCAL = MATH_3_PI_OVER_2 then + if NEGATIVE then + return 1.0; + else + return -1.0; + end if; + end if; + + if XLOCAL < EPS then + if NEGATIVE then + return -XLOCAL; + else + return XLOCAL; + end if; + else + if XLOCAL < BASE_EPS then + TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := MATH_PI - XLOCAL; + if ABS(TEMP) < EPS then + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + else + if ABS(TEMP) < BASE_EPS then + TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := MATH_2_PI - XLOCAL; + if ABS(TEMP) < EPS then + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + else + if ABS(TEMP) < BASE_EPS then + TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + end if; + end if; + + TEMP := ABS(MATH_PI_OVER_2 - XLOCAL); + if TEMP < EPS then + TEMP := 1.0 - TEMP*TEMP*0.5; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + else + if TEMP < BASE_EPS then + TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL); + if TEMP < EPS then + TEMP := 1.0 - TEMP*TEMP*0.5; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + else + if TEMP < BASE_EPS then + TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + end if; + end if; + + -- Compute value for general cases + if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then + VALUE:= CORDIC( KC, 0.0, x, 27, ROTATION)(1); + end if; + + N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2)); + case QUADRANT( N mod 4) is + when 0 => + VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1); + when 1 => + VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27, + ROTATION)(0); + when 2 => + VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1); + when 3 => + VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27, + ROTATION)(0); + end case; + + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end SIN; + + + function COS (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) COS(-X) = COS(X) + -- b) COS(X) = SIN(MATH_PI_OVER_2 - X) + -- c) COS(MATH_PI + X) = -COS(X) + -- d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS + -- e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if + -- EPS< ABS(X) MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + assert FALSE + report "XLOCAL <= 0.0 after reduction in COS(X)" + severity ERROR; + XLOCAL := -XLOCAL; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_2_PI then + return 1.0; + end if; + + if XLOCAL = MATH_PI then + return -1.0; + end if; + + if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then + return 0.0; + end if; + + TEMP := ABS(XLOCAL); + if ( TEMP < EPS) then + return (1.0 - 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + TEMP := ABS(XLOCAL -MATH_2_PI); + if ( TEMP < EPS) then + return (1.0 - 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + TEMP := ABS (XLOCAL - MATH_PI); + if TEMP < EPS then + return (-1.0 + 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + -- Compute value for general cases + return SIN(MATH_PI_OVER_2 - XLOCAL); + end COS; + + function TAN (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) TAN(0.0) = 0.0 + -- b) TAN(-X) = -TAN(X) + -- c) Returns REAL'LOW on error if X < 0.0 + -- d) Returns REAL'HIGH on error if X > 0.0 + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X) ; + variable VALUE: REAL; + variable TEMP : REAL; + + begin + -- Make 0.0 <= XLOCAL <= MATH_2_PI + if XLOCAL > MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + assert FALSE + report "XLOCAL <= 0.0 after reduction in TAN(X)" + severity ERROR; + XLOCAL := -XLOCAL; + end if; + + -- Check validity of argument + if XLOCAL = MATH_PI_OVER_2 then + assert FALSE + report "X is a multiple of MATH_PI_OVER_2 in TAN(X)" + severity ERROR; + if NEGATIVE then + return(REAL'LOW); + else + return(REAL'HIGH); + end if; + end if; + + if XLOCAL = MATH_3_PI_OVER_2 then + assert FALSE + report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)" + severity ERROR; + if NEGATIVE then + return(REAL'HIGH); + else + return(REAL'LOW); + end if; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_PI then + return 0.0; + end if; + + -- Compute value for general cases + VALUE := SIN(XLOCAL)/COS(XLOCAL); + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end TAN; + + function ARCSIN (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCSIN(-X) = -ARCSIN(X) + -- b) Returns X on error + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable VALUE : REAL; + + begin + -- Check validity of arguments + if XLOCAL > 1.0 then + assert FALSE + report "ABS(X) > 1.0 in ARCSIN(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + elsif XLOCAL = 1.0 then + if NEGATIVE then + return -MATH_PI_OVER_2; + else + return MATH_PI_OVER_2; + end if; + end if; + + -- Compute value for general cases + if XLOCAL < 0.9 then + VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL))); + else + VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); + end if; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end ARCSIN; + + function ARCCOS (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCCOS(-X) = MATH_PI - ARCCOS(X) + -- b) Returns X on error + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable VALUE : REAL; + + begin + -- Check validity of argument + if XLOCAL > 1.0 then + assert FALSE + report "ABS(X) > 1.0 in ARCCOS(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 1.0 then + return 0.0; + elsif X = 0.0 then + return MATH_PI_OVER_2; + elsif X = -1.0 then + return MATH_PI; + end if; + + -- Compute value for general cases + if XLOCAL > 0.9 then + VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); + else + VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL)); + end if; + + + if NEGATIVE then + VALUE := MATH_PI - VALUE; + end if; + + return VALUE; + end ARCCOS; + + + function ARCTAN (Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCTAN(-Y) = -ARCTAN(Y) + -- b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0 + -- c) ARCTAN(Y) = Y for |Y| < EPS + + constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS; + + variable NEGATIVE : BOOLEAN := Y < 0.0; + variable RECIPROCAL : BOOLEAN; + variable YLOCAL : REAL := ABS(Y); + variable VALUE : REAL; + + begin + -- Make argument |Y| <=1.0 + if YLOCAL > 1.0 then + YLOCAL := 1.0/YLOCAL; + RECIPROCAL := TRUE; + else + RECIPROCAL := FALSE; + end if; + + -- Compute value for special cases + if YLOCAL = 0.0 then + if RECIPROCAL then + if NEGATIVE then + return (-MATH_PI_OVER_2); + else + return (MATH_PI_OVER_2); + end if; + else + return 0.0; + end if; + end if; + + if YLOCAL < EPS then + if NEGATIVE then + if RECIPROCAL then + return (-MATH_PI_OVER_2 + YLOCAL); + else + return -YLOCAL; + end if; + else + if RECIPROCAL then + return (MATH_PI_OVER_2 - YLOCAL); + else + return YLOCAL; + end if; + end if; + end if; + + -- Compute value for general cases + VALUE := CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2); + + if RECIPROCAL then + VALUE := MATH_PI_OVER_2 - VALUE; + end if; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end ARCTAN; + + + function ARCTAN (Y : in REAL; X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + + variable YLOCAL : REAL; + variable VALUE : REAL; + begin + + -- Check validity of arguments + if (Y = 0.0 and X = 0.0 ) then + assert FALSE report + "ARCTAN(0.0, 0.0) is undetermined" + severity ERROR; + return 0.0; + end if; + + -- Compute value for special cases + if Y = 0.0 then + if X > 0.0 then + return 0.0; + else + return MATH_PI; + end if; + end if; + + if X = 0.0 then + if Y > 0.0 then + return MATH_PI_OVER_2; + else + return -MATH_PI_OVER_2; + end if; + end if; + + + -- Compute value for general cases + YLOCAL := ABS(Y/X); + + VALUE := ARCTAN(YLOCAL); + + if X < 0.0 then + VALUE := MATH_PI - VALUE; + end if; + + if Y < 0.0 then + VALUE := -VALUE; + end if; + + return VALUE; + end ARCTAN; + + + function SINH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) - EXP(-X))/2.0 + -- b) SINH(-X) = SINH(X) + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP - 1.0/TEMP)*0.5; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end SINH; + + function COSH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) + EXP(-X))/2.0 + -- b) COSH(-X) = COSH(X) + + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 1.0; + end if; + + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP + 1.0/TEMP)*0.5; + + return VALUE; + end COSH; + + function TANH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X)) + -- b) TANH(-X) = -TANH(X) + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP); + + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end TANH; + + function ARCSINH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns LOG( X + SQRT( X*X + 1.0)) + + begin + -- Compute value for special cases + if X = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + return ( LOG( X + SQRT( X*X + 1.0)) ); + end ARCSINH; + + + + function ARCCOSH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns LOG( X + SQRT( X*X - 1.0)); X >= 1.0 + -- b) Returns X on error + + begin + -- Check validity of arguments + if X < 1.0 then + assert FALSE + report "X < 1.0 in ARCCOSH(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 1.0 then + return 0.0; + end if; + + -- Compute value for general cases + return ( LOG( X + SQRT( X*X - 1.0))); + end ARCCOSH; + + function ARCTANH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0 + -- b) Returns X on error + begin + -- Check validity of arguments + if ABS(X) >= 1.0 then + assert FALSE + report "ABS(X) >= 1.0 in ARCTANH(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + return( 0.5*LOG( (1.0+X)/(1.0-X) ) ); + end ARCTANH; + +end MATH_REAL;
single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/._Real_._Math_.vhd Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.cst =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.cst (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.cst (revision 9) @@ -0,0 +1,3 @@ +Date=01/18/2017 +Time=00:48:24 + Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.edn =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.edn (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.edn (revision 9) @@ -0,0 +1,294 @@ +(edif decoder_table_dist_rom + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2017 1 18 0 48 29) + (program "SCUBA" (version "Diamond (64-bit) 3.8.0.115.3")))) + (comment "C:\lscc\diamond\3.8_x64\ispfpga\bin\nt64\scuba.exe -w -n decoder_table_dist_rom -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -type rom -addr_width 7 -num_rows 128 -data_width 14 -outdata UNREGISTERED -memfile c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/decoder_table_init_binary.mem -memformat bin -fdc C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.fdc ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell ROM128X1A + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port AD6 + (direction INPUT)) + (port AD5 + (direction INPUT)) + (port AD4 + (direction INPUT)) + (port AD3 + (direction INPUT)) + (port AD2 + (direction INPUT)) + (port AD1 + (direction INPUT)) + (port AD0 + (direction INPUT)) + (port DO0 + (direction OUTPUT))))) + (cell decoder_table_dist_rom + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename Address "Address(6:0)") 7) + (direction INPUT)) + (port (array (rename Q "Q(13:0)") 14) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance mem_0_13 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0xDA3FFFFFBA3FFFFFB7FE6997BFFFFFFE"))) + (instance mem_0_12 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0xEDEFFDEBFDEFFDEB7BFFB3E718FFD7FF"))) + (instance mem_0_11 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0xF679B7FFEE79B7FFEFDFFA97BFFFFFDF"))) + (instance mem_0_10 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0xF0BFD7FFB8BFD7FFEFFE7A176DFFFFFE"))) + (instance mem_0_9 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0xEFEFFDEBFFEFFDEAF3FFF3E31AFFD7FF"))) + (instance mem_0_8 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0xDCFF9FFEECFF9FFFBFFFF9976DFFFFFF"))) + (instance mem_0_7 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0x9FF2FE59FFF2FE585CA3D3C7D0FFB0A3"))) + (instance mem_0_6 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0xB7F2F69DFFF2F69DDC8B93C7D0FF388B"))) + (instance mem_0_5 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0x7F100615F7100614FC8EFFC3E3FF288E"))) + (instance mem_0_4 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0x3F180215F7180214FEBABFF7EBFF2ABA"))) + (instance mem_0_3 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0x7BD56B4353D56B42DC92BFA7DAFF8492"))) + (instance mem_0_2 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0x7F551A69DF551A69FC24FF85FFFFD024"))) + (instance mem_0_1 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0x3F581AE99F581AE87C60FFF5F7FFD060"))) + (instance mem_0_0 + (viewRef view1 + (cellRef ROM128X1A)) + (property initval + (string "0x7BE07F0193E07F007C12FFA7F2FF0012"))) + (net qdataout13 + (joined + (portRef (member Q 0)) + (portRef DO0 (instanceRef mem_0_13)))) + (net qdataout12 + (joined + (portRef (member Q 1)) + (portRef DO0 (instanceRef mem_0_12)))) + (net qdataout11 + (joined + (portRef (member Q 2)) + (portRef DO0 (instanceRef mem_0_11)))) + (net qdataout10 + (joined + (portRef (member Q 3)) + (portRef DO0 (instanceRef mem_0_10)))) + (net qdataout9 + (joined + (portRef (member Q 4)) + (portRef DO0 (instanceRef mem_0_9)))) + (net qdataout8 + (joined + (portRef (member Q 5)) + (portRef DO0 (instanceRef mem_0_8)))) + (net qdataout7 + (joined + (portRef (member Q 6)) + (portRef DO0 (instanceRef mem_0_7)))) + (net qdataout6 + (joined + (portRef (member Q 7)) + (portRef DO0 (instanceRef mem_0_6)))) + (net qdataout5 + (joined + (portRef (member Q 8)) + (portRef DO0 (instanceRef mem_0_5)))) + (net qdataout4 + (joined + (portRef (member Q 9)) + (portRef DO0 (instanceRef mem_0_4)))) + (net qdataout3 + (joined + (portRef (member Q 10)) + (portRef DO0 (instanceRef mem_0_3)))) + (net qdataout2 + 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(instanceRef mem_0_11)) + (portRef AD5 (instanceRef mem_0_10)) + (portRef AD5 (instanceRef mem_0_9)) + (portRef AD5 (instanceRef mem_0_8)) + (portRef AD5 (instanceRef mem_0_7)) + (portRef AD5 (instanceRef mem_0_6)) + (portRef AD5 (instanceRef mem_0_5)) + (portRef AD5 (instanceRef mem_0_4)) + (portRef AD5 (instanceRef mem_0_3)) + (portRef AD5 (instanceRef mem_0_2)) + (portRef AD5 (instanceRef mem_0_1)) + (portRef AD5 (instanceRef mem_0_0)))) + (net addr4 + (joined + (portRef (member Address 2)) + (portRef AD4 (instanceRef mem_0_13)) + (portRef AD4 (instanceRef mem_0_12)) + (portRef AD4 (instanceRef mem_0_11)) + (portRef AD4 (instanceRef mem_0_10)) + (portRef AD4 (instanceRef mem_0_9)) + (portRef AD4 (instanceRef mem_0_8)) + (portRef AD4 (instanceRef mem_0_7)) + (portRef AD4 (instanceRef mem_0_6)) + (portRef AD4 (instanceRef mem_0_5)) + (portRef AD4 (instanceRef mem_0_4)) + (portRef AD4 (instanceRef mem_0_3)) + (portRef AD4 (instanceRef mem_0_2)) + (portRef AD4 (instanceRef mem_0_1)) + (portRef AD4 (instanceRef mem_0_0)))) + (net addr3 + (joined + (portRef (member Address 3)) + (portRef AD3 (instanceRef mem_0_13)) + (portRef AD3 (instanceRef mem_0_12)) + (portRef AD3 (instanceRef mem_0_11)) + (portRef AD3 (instanceRef mem_0_10)) + (portRef AD3 (instanceRef mem_0_9)) + (portRef AD3 (instanceRef mem_0_8)) + (portRef AD3 (instanceRef mem_0_7)) + (portRef AD3 (instanceRef mem_0_6)) + (portRef AD3 (instanceRef mem_0_5)) + (portRef AD3 (instanceRef mem_0_4)) + (portRef AD3 (instanceRef mem_0_3)) + (portRef AD3 (instanceRef mem_0_2)) + (portRef AD3 (instanceRef mem_0_1)) + (portRef AD3 (instanceRef mem_0_0)))) + (net addr2 + (joined + (portRef (member Address 4)) + (portRef AD2 (instanceRef mem_0_13)) + (portRef AD2 (instanceRef mem_0_12)) + (portRef AD2 (instanceRef mem_0_11)) + (portRef AD2 (instanceRef mem_0_10)) + (portRef AD2 (instanceRef mem_0_9)) + (portRef AD2 (instanceRef mem_0_8)) + (portRef AD2 (instanceRef mem_0_7)) + (portRef AD2 (instanceRef mem_0_6)) + (portRef AD2 (instanceRef mem_0_5)) + (portRef AD2 (instanceRef mem_0_4)) + (portRef AD2 (instanceRef mem_0_3)) + (portRef AD2 (instanceRef mem_0_2)) + (portRef AD2 (instanceRef mem_0_1)) + (portRef AD2 (instanceRef mem_0_0)))) + (net addr1 + (joined + (portRef (member Address 5)) + (portRef AD1 (instanceRef mem_0_13)) + (portRef AD1 (instanceRef mem_0_12)) + (portRef AD1 (instanceRef mem_0_11)) + (portRef AD1 (instanceRef mem_0_10)) + (portRef AD1 (instanceRef mem_0_9)) + (portRef AD1 (instanceRef mem_0_8)) + (portRef AD1 (instanceRef mem_0_7)) + (portRef AD1 (instanceRef mem_0_6)) + (portRef AD1 (instanceRef mem_0_5)) + (portRef AD1 (instanceRef mem_0_4)) + (portRef AD1 (instanceRef mem_0_3)) + (portRef AD1 (instanceRef mem_0_2)) + (portRef AD1 (instanceRef mem_0_1)) + (portRef AD1 (instanceRef mem_0_0)))) + (net addr0 + (joined + (portRef (member Address 6)) + (portRef AD0 (instanceRef mem_0_13)) + (portRef AD0 (instanceRef mem_0_12)) + (portRef AD0 (instanceRef mem_0_11)) + (portRef AD0 (instanceRef mem_0_10)) + (portRef AD0 (instanceRef mem_0_9)) + (portRef AD0 (instanceRef mem_0_8)) + (portRef AD0 (instanceRef mem_0_7)) + (portRef AD0 (instanceRef mem_0_6)) + (portRef AD0 (instanceRef mem_0_5)) + (portRef AD0 (instanceRef mem_0_4)) + (portRef AD0 (instanceRef mem_0_3)) + (portRef AD0 (instanceRef mem_0_2)) + (portRef AD0 (instanceRef mem_0_1)) + (portRef AD0 (instanceRef mem_0_0)))))))) + (design decoder_table_dist_rom + (cellRef decoder_table_dist_rom + (libraryRef ORCLIB))) +) Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.fdc =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.fdc (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.fdc (revision 9) @@ -0,0 +1,2 @@ +###==== Start Configuration + Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.jhd =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.jhd (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.jhd (revision 9) @@ -0,0 +1,2 @@ +VHDL_ENTITY_ONLY decoder_table_dist_rom DEFIN decoder_table_dist_rom.vhd +MODULE decoder_table_dist_rom DEFIN decoder_table_dist_rom.vhd Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.lpc =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.lpc (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.lpc (revision 9) @@ -0,0 +1,40 @@ +[Device] +Family=ecp5um5g +PartType=LFE5UM5G-45F +PartName=LFE5UM5G-45F-8BG381C +SpeedGrade=8 +Package=CABGA381 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=Distributed_ROM +CoreRevision=2.8 +ModuleName=decoder_table_dist_rom +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=01/18/2017 +Time=00:48:24 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Addresses=128 +Data=14 +LUT=0 +MemFile=c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/decoder_table_init_binary.mem +MemFormat=bin + +[FilesGenerated] +c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/decoder_table_init_binary.mem=mem + +[Command] +cmd_line= -w -n decoder_table_dist_rom -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -dram -type romblk -addr_width 7 -num_words 128 -data_width 14 -outdata UNREGISTERED -memfile c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/decoder_table_init_binary.mem -memformat bin Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.naf =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.naf (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.naf (revision 9) @@ -0,0 +1,2 @@ +Address i +Q o Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.ngd =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.ngd =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.ngd (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.ngd (revision 9)
single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.ngd Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.ngo =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.ngo =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.ngo (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.ngo (revision 9)
single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.ngo Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.sort =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.sort (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.sort (revision 9) @@ -0,0 +1 @@ +decoder_table_dist_rom.vhd Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.srp =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.srp (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.srp (revision 9) @@ -0,0 +1,30 @@ +SCUBA, Version Diamond (64-bit) 3.8.0.115.3 +Wed Jan 18 00:48:29 2017 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : C:\lscc\diamond\3.8_x64\ispfpga\bin\nt64\scuba.exe -w -n decoder_table_dist_rom -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -dram -type romblk -addr_width 7 -num_words 128 -data_width 14 -outdata UNREGISTERED -memfile c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/decoder_table_init_binary.mem -memformat bin -fdc C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.fdc + Circuit name : decoder_table_dist_rom + Module type : rom + Module Version : 2.8 + Address width : 7 + Ports : + Inputs : Address[6:0] + Outputs : Q[13:0] + I/O buffer : not inserted + Memory file : c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/decoder_table_init_binary.mem + EDIF output : decoder_table_dist_rom.edn + VHDL output : decoder_table_dist_rom.vhd + VHDL template : decoder_table_dist_rom_tmpl.vhd + VHDL testbench : tb_decoder_table_dist_rom_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : decoder_table_dist_rom.srp + Element Usage : + ROM128X1A : 14 + Estimated Resource Usage: + LUT : 56 Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.sym =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.sym =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.sym (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.sym (revision 9)
single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.sym Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd (revision 9) @@ -0,0 +1,109 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.8.0.115.3 +-- Module Version: 2.8 +--C:\lscc\diamond\3.8_x64\ispfpga\bin\nt64\scuba.exe -w -n decoder_table_dist_rom -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -type rom -addr_width 7 -num_rows 128 -data_width 14 -outdata UNREGISTERED -memfile c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/decoder_table_init_binary.mem -memformat bin -fdc C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.fdc + +-- Wed Jan 18 00:48:29 2017 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity decoder_table_dist_rom is + port ( + Address: in std_logic_vector(6 downto 0); + Q: out std_logic_vector(13 downto 0)); +end decoder_table_dist_rom; + +architecture Structure of decoder_table_dist_rom is + + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + mem_0_13: ROM128X1A + generic map (initval=> X"DA3FFFFFBA3FFFFFB7FE6997BFFFFFFE") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(13)); + + mem_0_12: ROM128X1A + generic map (initval=> X"EDEFFDEBFDEFFDEB7BFFB3E718FFD7FF") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(12)); + + mem_0_11: ROM128X1A + generic map (initval=> X"F679B7FFEE79B7FFEFDFFA97BFFFFFDF") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(11)); + + mem_0_10: ROM128X1A + generic map (initval=> X"F0BFD7FFB8BFD7FFEFFE7A176DFFFFFE") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(10)); + + mem_0_9: ROM128X1A + generic map (initval=> X"EFEFFDEBFFEFFDEAF3FFF3E31AFFD7FF") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(9)); + + mem_0_8: ROM128X1A + generic map (initval=> X"DCFF9FFEECFF9FFFBFFFF9976DFFFFFF") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(8)); + + mem_0_7: ROM128X1A + generic map (initval=> X"9FF2FE59FFF2FE585CA3D3C7D0FFB0A3") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(7)); + + mem_0_6: ROM128X1A + generic map (initval=> X"B7F2F69DFFF2F69DDC8B93C7D0FF388B") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(6)); + + mem_0_5: ROM128X1A + generic map (initval=> X"7F100615F7100614FC8EFFC3E3FF288E") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(5)); + + mem_0_4: ROM128X1A + generic map (initval=> X"3F180215F7180214FEBABFF7EBFF2ABA") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(4)); + + mem_0_3: ROM128X1A + generic map (initval=> X"7BD56B4353D56B42DC92BFA7DAFF8492") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(3)); + + mem_0_2: ROM128X1A + generic map (initval=> X"7F551A69DF551A69FC24FF85FFFFD024") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(2)); + + mem_0_1: ROM128X1A + generic map (initval=> X"3F581AE99F581AE87C60FFF5F7FFD060") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(1)); + + mem_0_0: ROM128X1A + generic map (initval=> X"7BE07F0193E07F007C12FFA7F2FF0012") + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(0)); + +end Structure;
single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom_ngd.asd =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom_ngd.asd (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom_ngd.asd (revision 9) @@ -0,0 +1 @@ +[ActiveSupport NGD] Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom_tmpl.vhd =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom_tmpl.vhd (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom_tmpl.vhd (revision 9) @@ -0,0 +1,13 @@ +-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.8.0.115.3 +-- Module Version: 2.8 +-- Wed Jan 18 00:48:29 2017 + +-- parameterized module component declaration +component decoder_table_dist_rom + port (Address: in std_logic_vector(6 downto 0); + Q: out std_logic_vector(13 downto 0)); +end component; + +-- parameterized module component instance +__ : decoder_table_dist_rom + port map (Address(6 downto 0)=>__, Q(13 downto 0)=>__);
single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom_tmpl.vhd Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/generate_core.tcl =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/generate_core.tcl (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/generate_core.tcl (revision 9) @@ -0,0 +1,100 @@ +#!/usr/local/bin/wish + +proc GetPlatform {} { + global tcl_platform + + set cpu $tcl_platform(machine) + + switch $cpu { + intel - + i*86* { + set cpu ix86 + } + x86_64 { + if {$tcl_platform(wordSize) == 4} { + set cpu ix86 + } + } + } + + switch $tcl_platform(platform) { + windows { + if {$cpu == "amd64"} { + # Do not check wordSize, win32-x64 is an IL32P64 platform. + set cpu x86_64 + } + if {$cpu == "x86_64"} { + return "nt64" + } else { + return "nt" + } + } + unix { + if {$tcl_platform(os) == "Linux"} { + if {$cpu == "x86_64"} { + return "lin64" + } else { + return "lin" + } + } else { + return "sol" + } + } + } + return "nt" +} + +proc GetCmdLine {lpcfile} { + global Para + + if [catch {open $lpcfile r} fileid] { + puts "Cannot open $para_file file!" + exit -1 + } + + seek $fileid 0 start + set default_match 0 + while {[gets $fileid line] >= 0} { + if {[string first "\[Command\]" $line] == 0} { + set default_match 1 + continue + } + if {[string first "\[" $line] == 0} { + set default_match 0 + } + if {$default_match == 1} { + if [regexp {([^=]*)=(.*)} $line match parameter value] { + if [regexp {([ |\t]*;)} $parameter match] {continue} + if [regexp {(.*)[ |\t]*;} $value match temp] { + set Para($parameter) $temp + } else { + set Para($parameter) $value + } + } + } + } + set default_match 0 + close $fileid + + return $Para(cmd_line) +} + +set platformpath [GetPlatform] +set Para(sbp_path) [file dirname [info script]] +set Para(install_dir) $env(TOOLRTF) +set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" + +set scuba "$Para(FPGAPath)/scuba" +set modulename "decoder_table_dist_rom" +set lang "vhdl" +set lpcfile "$Para(sbp_path)/$modulename.lpc" +set arch "sa5p00g" +set cmd_line [GetCmdLine $lpcfile] +set fdcfile "$Para(sbp_path)/$modulename.fdc" +if {[file exists $fdcfile] == 0} { + append scuba " " $cmd_line +} else { + append scuba " " $cmd_line " " -fdc " " \"$fdcfile\" +} +set Para(result) [catch {eval exec "$scuba"} msg] +#puts $msg Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/generate_ngd.tcl =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/generate_ngd.tcl (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/generate_ngd.tcl (revision 9) @@ -0,0 +1,74 @@ +#!/usr/local/bin/wish + +proc GetPlatform {} { + global tcl_platform + + set cpu $tcl_platform(machine) + + switch $cpu { + intel - + i*86* { + set cpu ix86 + } + x86_64 { + if {$tcl_platform(wordSize) == 4} { + set cpu ix86 + } + } + } + + switch $tcl_platform(platform) { + windows { + if {$cpu == "amd64"} { + # Do not check wordSize, win32-x64 is an IL32P64 platform. + set cpu x86_64 + } + if {$cpu == "x86_64"} { + return "nt64" + } else { + return "nt" + } + } + unix { + if {$tcl_platform(os) == "Linux"} { + if {$cpu == "x86_64"} { + return "lin64" + } else { + return "lin" + } + } else { + return "sol" + } + } + } + return "nt" +} + +set platformpath [GetPlatform] +set Para(sbp_path) [file dirname [info script]] +set Para(install_dir) $env(TOOLRTF) +set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" +set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]" + +set Para(ModuleName) "decoder_table_dist_rom" +set Para(Module) "Distributed_ROM" +set Para(libname) ecp5um5g +set Para(arch_name) sa5p00g +set Para(PartType) "LFE5UM5G-45F" + +set Para(tech_syn) ecp5um5g +set Para(tech_cae) ecp5um5g +set Para(Package) "CABGA381" +set Para(SpeedGrade) "8" +set Para(FMax) "100" +set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc" + +#edif2ngd +set edif2ngd "$Para(FPGAPath)/edif2ngd" +set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn $Para(ModuleName).edn $Para(ModuleName).ngo} msg] +#puts $msg + +#ngdbuild +set ngdbuild "$Para(FPGAPath)/ngdbuild" +set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg] +#puts $msg Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/tb_decoder_table_dist_rom_tmpl.vhd =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/tb_decoder_table_dist_rom_tmpl.vhd (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/tb_decoder_table_dist_rom_tmpl.vhd (revision 9) @@ -0,0 +1,42 @@ +-- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.8.0.115.3 +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +use IEEE.math_real.all; + +use IEEE.numeric_std.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component decoder_table_dist_rom + port (Address : in std_logic_vector(6 downto 0); + Q : out std_logic_vector(13 downto 0) + ); + end component; + + signal Address : std_logic_vector(6 downto 0) := (others => '0'); + signal Q : std_logic_vector(13 downto 0); +begin + u1 : decoder_table_dist_rom + port map (Address => Address, Q => Q + ); + + process + + begin + Address <= (others => '0') ; + wait for 100 ns; + wait for 10 ns; + for i in 0 to 131 loop + wait for 10 ns; + Address <= Address + '1' ; + end loop; + wait; + end process; + +end architecture test;
single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/tb_decoder_table_dist_rom_tmpl.vhd Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom_impl.sbx =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom_impl.sbx (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom_impl.sbx (revision 9) @@ -0,0 +1,451 @@ + + + + LATTICE + LOCAL + decoder_table_dist_rom_impl + 1.0 + + + Diamond_Synthesis + synthesis + + + Diamond_Simulation + simulation + + + + + + + + decoder_table_dist_rom_Address + decoder_table_dist_rom_Address + + in + + 6 + 0 + + + + + decoder_table_dist_rom.Address + + + + + decoder_table_dist_rom_Q + decoder_table_dist_rom_Q + + out + + 13 + 0 + + + + + decoder_table_dist_rom.Q + + + + + + + LFE5UM5G-45F-8BG381C + synplify + 2017-01-18.00:46:05 + 2017-01-18.00:53:23 + 3.8.0.115.3 + VHDL + + true + false + false + true + false + false + false + false + false + false + false + + + + + + + + LATTICE + LOCAL + decoder_table_dist_rom_impl + 1.0 + + + decoder_table_dist_rom + + Lattice Semiconductor Corporation + LEGACY + Distributed_ROM + 2.8 + + + Diamond_Simulation + simulation + + ./decoder_table_dist_rom/decoder_table_dist_rom.vhd + vhdlSource + + + + Diamond_Synthesis + synthesis + + ./decoder_table_dist_rom/decoder_table_dist_rom.vhd + vhdlSource + + + + + + Configuration + none + ${sbp_path}/${instance}/generate_core.tcl + CONFIG + + + CreateNGD + none + ${sbp_path}/${instance}/generate_ngd.tcl + CONFIG + + + + + + + Address + Address + + in + + 6 + 0 + + + + + Q + Q + + out + + 13 + 0 + + + + + + + synplify + 2017-01-18.00:53:23 + + false + false + false + false + false + false + false + false + false + false + LPM + PRIMARY + PRIMARY + false + false + + + + + + Family + ecp5um5g + + + OperatingCondition + COM + + + Package + CABGA381 + + + PartName + LFE5UM5G-45F-8BG381C + + + PartType + LFE5UM5G-45F + + + SpeedGrade + 8 + + + Status + P + + + + CoreName + Distributed_ROM + + + CoreRevision + 2.8 + + + CoreStatus + Demo + + + CoreType + LPM + + + Date + 01/18/2017 + + + ModuleName + decoder_table_dist_rom + + + ParameterFileVersion + 1.0 + + + SourceFormat + vhdl + + + Time + 00:48:24 + + + VendorName + Lattice Semiconductor Corporation + + + + Addresses + 128 + + + Data + 14 + + + Destination + Synplicity + + + EDIF + 1 + + + Expression + BusA(0 to 7) + + + IO + 0 + + + LUT + 0 + + + MemFile + c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/decoder_table_init_binary.mem + + + MemFormat + bin + + + Order + Big Endian [MSB:LSB] + + + VHDL + 1 + + + Verilog + 0 + + + + c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/decoder_table_init_binary.mem + mem + + + + cmd_line + -w -n decoder_table_dist_rom -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -dram -type romblk -addr_width 7 -num_words 128 -data_width 14 -outdata UNREGISTERED -memfile c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/decoder_table_init_binary.mem -memformat bin + + + + + + + + + + decoder_table_dist_rom_Address + decoder_table_dist_rom_Address + + + + + decoder_table_dist_rom_Address[0] + decoder_table_dist_rom_Address[0] + + + + + decoder_table_dist_rom_Address[1] + decoder_table_dist_rom_Address[1] + + + + + decoder_table_dist_rom_Address[2] + decoder_table_dist_rom_Address[2] + + + + + decoder_table_dist_rom_Address[3] + decoder_table_dist_rom_Address[3] + + + + + decoder_table_dist_rom_Address[4] + decoder_table_dist_rom_Address[4] + + + + + decoder_table_dist_rom_Address[5] + decoder_table_dist_rom_Address[5] + + + + + decoder_table_dist_rom_Address[6] + decoder_table_dist_rom_Address[6] + + + + + decoder_table_dist_rom_Q + decoder_table_dist_rom_Q + + + + + decoder_table_dist_rom_Q[0] + decoder_table_dist_rom_Q[0] + + + + + decoder_table_dist_rom_Q[10] + decoder_table_dist_rom_Q[10] + + + + + decoder_table_dist_rom_Q[11] + decoder_table_dist_rom_Q[11] + + + + + decoder_table_dist_rom_Q[12] + decoder_table_dist_rom_Q[12] + + + + + decoder_table_dist_rom_Q[13] + decoder_table_dist_rom_Q[13] + + + + + decoder_table_dist_rom_Q[1] + decoder_table_dist_rom_Q[1] + + + + + decoder_table_dist_rom_Q[2] + decoder_table_dist_rom_Q[2] + + + + + decoder_table_dist_rom_Q[3] + decoder_table_dist_rom_Q[3] + + + + + decoder_table_dist_rom_Q[4] + decoder_table_dist_rom_Q[4] + + + + + decoder_table_dist_rom_Q[5] + decoder_table_dist_rom_Q[5] + + + + + decoder_table_dist_rom_Q[6] + decoder_table_dist_rom_Q[6] + + + + + decoder_table_dist_rom_Q[7] + decoder_table_dist_rom_Q[7] + + + + + decoder_table_dist_rom_Q[8] + decoder_table_dist_rom_Q[8] + + + + + decoder_table_dist_rom_Q[9] + decoder_table_dist_rom_Q[9] + + + + + + Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/14-segment display ascii decoder.xlsx =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/14-segment display ascii decoder.xlsx =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/14-segment display ascii decoder.xlsx (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/14-segment display ascii decoder.xlsx (revision 9)
single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/14-segment display ascii decoder.xlsx Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/decoder_table_init_binary.mem =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/decoder_table_init_binary.mem (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/Decoding_Table/decoder_table_init_binary.mem (revision 9) @@ -0,0 +1,128 @@ +01101111000000 +11111111111001 +11111100100100 +11111101110000 +11111100011001 +11011110010110 +11111100000010 +11111111111000 +11111100000000 +11111100010000 +11111100001000 +10110101110000 +11111111000110 +10110111110000 +11111100000110 +11111110001110 +11111111111111 +11111111111111 +11111111111111 +11111111111111 +11111111111111 +11111111111111 +11111111111111 +11111111111111 +10110100110110 +10101000111111 +10110100000110 +11111100011100 +11101011001111 +10110100110111 +00010111111111 +10100011111111 +11111111111111 +11111111111001 +11110111011111 +00000000000000 +10110100010010 +01001000011011 +01001011110010 +11101111111111 +11001111111111 +01111011111111 +00000000111111 +10110100111111 +01111111111111 +11111100111111 +10111110100111 +01101111111111 +01101111000000 +11111111111001 +11111100100100 +11111101110000 +11111100011001 +11011110010110 +11111100000010 +11111111111000 +11111100000000 +11111100010000 +10110111111111 +01110111111111 +11001111111111 +11111100110111 +01111011111111 +10111101111100 +11110101000100 +11111100001000 +10110101110000 +11111111000110 +10110111110000 +11111100000110 +11111110001110 +11111101000010 +11111100001001 +10110111111111 +11111111100001 +11001110001111 +11111111000111 +11101011001001 +11011011001001 +11111111000000 +11111100001100 +11011111000000 +11011100001100 +11111100010010 +10110111111110 +11111111000001 +01101111001111 +01011111001001 +01001011111111 +10101011111111 +01101111110110 +11111111000110 +11011011111111 +11111111110000 +01101111111100 +11111111110111 +11111011111111 +11111100001000 +10110101110000 +11111111000110 +10110111110000 +11111100000110 +11111110001110 +11111101000010 +11111100001001 +10110111111111 +11111111100001 +11001110001111 +11111111000111 +11101011001001 +11011011001001 +11111111000000 +11111100001100 +11011111000000 +11011100001100 +11111100010010 +10110111111110 +11111111000001 +01101111001111 +01011111001001 +01001011111111 +10101011111111 +01101111110110 +11001110111111 +10110111111111 +01111001111111 +11111100101101 +11111111000000 \ No newline at end of file Index: single-14-segment-display-driver-w-decoder/trunk/Project/Sources/ascii_decoder.vhd =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Project/Sources/ascii_decoder.vhd (revision 8) +++ single-14-segment-display-driver-w-decoder/trunk/Project/Sources/ascii_decoder.vhd (revision 9) @@ -1,5 +1,5 @@ -------------------------------------------------------------------------------- --- Entity: ASCIIDecoder +-- Entity: ascii_decoder -- Date:2017-01-07 -- Author: GL -- @@ -12,27 +12,27 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; -entity ASCIIDecoder is +entity ascii_decoder is port ( - clk : in std_logic; -- input clock, xx MHz. + clk : in std_logic; --! input clock, xx MHz. reset : in std_logic; --! ascii_in(7) represents the DP state so it is not decoded. --! Symbol codes from 0x00 to 0x7F are without DP lit. Symbol codes from 0x80 to 0xFF have DP lit. - ascii_in: in std_logic_vector(7 downto 0); + ascii_in: in std_logic_vector(7 downto 0); --! input ascii code to be displayed - disp_data_q : out std_logic_vector(14 downto 0) + disp_data_q : out std_logic_vector(14 downto 0) --! decoded ascii code output with symbol bit map ); -end ASCIIDecoder; +end ascii_decoder; -architecture arch of ASCIIDecoder is +architecture arch of ascii_decoder is --! Q represents the symbol's bit mapping overlay over the 14-segment display. signal Q : std_logic_vector(13 downto 0); begin ---! @details Decoding table -rom_decoding_table: entity work.DistRomAsciiDecoder +--! @brief Decoding table handling all symbols except the DP +rom_decoding_table: entity work.decoder_table_dist_rom port map( Address => ascii_in(6 downto 0), Q => Q
/single-14-segment-display-driver-w-decoder/trunk/Project/Sources/display_driver_w_decoder.vhd
23,7 → 23,7
wr_en : in std_logic; --! active high write enable to store the ASCII code in a register
--! Typically the data fed to display (single or multiple) is provided for single display at a time.
--! If multiple displays are required disp_sel signal must be provided (according typical dynamic display indication).
--! If multiple displays are required scan signal must be additionally provided (according typical dynamic display indication).
--!
--! \section disp_data_bit_mapping Display Segment Bit Mapping
--! |Bit Number | 14| 13| 12| 11| 10| 9| 8| 7| 6| 5| 4| 3| 2| 1|0 |
31,12 → 31,7
--! |Display Segment| dp| m| l| k| j| i| h| g2| g1| f| e| d| c| b|a |
--! Note that there is no standard way to name the segments.
--! Current data bits correspondt to display segments according this picture: @image html https://www.maximintegrated.com/en/images/appnotes/3211/3211Fig02.gif
disp_data_q : out std_logic_vector(14 downto 0);
--! If more displays needs to be fed change disp_sel to vector with length equal to number of displays.
--! Use principles of the standard dynamic indication: provide data then enable the displays sequentially.
--! If brightness control is desired just AND the selector and the PWM controller output.
disp_sel : out std_logic
disp_data_q : out std_logic_vector(14 downto 0)
);
end display_driver_w_decoder;
 
67,10 → 62,6
--! source: https://datasheets.maximintegrated.com/en/ds/MAX6955.pdf
--!
--! \section port_disp_data Display Data Out
--!
--! Typically the data fed to display (single or multiple) is provided for single display at a time.
--! If multiple displays are required disp_sel signal must be provided (according typical dynamic display indication) to determine
--! for which display is the data targeted.
--!
--! \subsection disp_data_bit_mapping Display Segment Bit Mapping
--! |Bit Number | 14| 13| 12| 11| 10| 9| 8| 7| 6| 5| 4| 3| 2| 1|0 |
79,7 → 70,7
--! Note that there is no standard way to name the segments.
--! Current data bits correspondt to display segments according this picture: @image html https://www.maximintegrated.com/en/images/appnotes/3211/3211Fig02.gif
 
ascii_decoder_module:entity work.ASCIIDecoder
ascii_decoder_module:entity work.ascii_decoder
port map(
clk => clk,
reset => reset,
87,7 → 78,5
disp_data_q => disp_data_q
);
disp_sel <= '0'; -- TODO: implement this correctly
 
end display_driver_w_decoder_arch;
 
/single-14-segment-display-driver-w-decoder/trunk/Project/Sources/display_driver_wrapper.vhd
1,5 → 1,5
--------------------------------------------------------------------------------
-- Entity: DisplayDriverWrapper
-- Entity: display_driver_wrapper
-- Date:2017-01-06
-- Author: GL
--
12,7 → 12,7
--! @file
--! @brief Top wrapper for design FPGA prove.
--! @details This wrapper is designed for Lattice ECP5-5G Versa Development Kit.
entity DisplayDriverWrapper is
entity display_driver_wrapper is
port (
clk : in std_logic; --! input clock, xx MHz.
n_rst : in std_logic; --! active low on board. active high in design.
21,20 → 21,15
--! Typically the data fed to display (single or multiple) is provided for single display at a time.
--! If multiple displays are required together with data goes display select (according typical dynamic display indication).
disp_data : out std_logic_vector(14 downto 0);
--! If more displays needs to be fed change disp_sel to vector with length equal to number of displays.
--! Use principles of the standard dynamic indication: provide data then enable the displays sequentially.
--! If brightness control is desired just AND the selector and the PWM controller output.
disp_sel : out std_logic
disp_data_q : out std_logic_vector(14 downto 0)
);
attribute syn_force_pad: boolean;
attribute syn_force_pad of clk, n_rst, button, disp_sel, disp_data: signal is true;
end DisplayDriverWrapper;
attribute syn_force_pad of clk, n_rst, button, disp_data_q: signal is true;
end display_driver_wrapper;
 
--! @details The architecture consists of the DisplayDriverwDecoder_Top itself (as DUT) plus
--! @details The architecture consists of the display_driver_w_decoder itself (as DUT) plus
--! sample symbol generator triggered by the button on the dev board
architecture arch of DisplayDriverWrapper is
architecture arch of display_driver_wrapper is
signal rst: std_logic;
--! Debounce the glitches shorter than 4 clock cycles. Expand at will according the clock speed and glitch duration to filter.
49,50 → 44,49
signal symbol_scan_cntr: unsigned(7 downto 0);
begin
 
--! invert n_rst to make it active high on design recommendation
rst <= not n_rst;
 
BtnDebouncer:process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
bttn_state_fifo <= (others=>'1'); -- active low
bttn_state <= '0'; -- active high
else
bttn_state_fifo <= shift_left(bttn_state_fifo,1);
bttn_state_fifo(bttn_state_fifo'right) <= button;
if bttn_state_fifo = "0000" then -- button actuated for more than X clocks and no bounces present
bttn_state <= '1'; -- report button is actuated
--! invert n_rst to make it active high on design recommendation
rst <= not n_rst;
button_debouncer: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
bttn_state_fifo <= (others=>'1'); -- active low
bttn_state <= '0'; -- active high
else
bttn_state <= '0';
bttn_state_fifo <= shift_left(bttn_state_fifo,1);
bttn_state_fifo(bttn_state_fifo'right) <= button;
if bttn_state_fifo = "0000" then -- button actuated for more than X clocks and no bounces present
bttn_state <= '1'; -- report button is actuated
else
bttn_state <= '0';
end if;
end if;
end if;
end if;
end process;
end process; -- button_debouncer
--! @brief User control counter to emulate ASCII codes input
--! @details Counter that goes through values from 0x00 to 0xFF in steps of 0x01 and then rolls naturally to 0x00.
--! With the counter output hex ASCII codes are emulated. The counter is incremented by clicking SW3 on ECP5-5G Versa Board.
address_scan_counter: process(rst,bttn_state)
begin
if rst='1' then
symbol_scan_cntr <= (others=>'0');
elsif rising_edge(bttn_state) then -- TODO: Fix this to edge detector implementation
symbol_scan_cntr <= symbol_scan_cntr + 1; -- I count ont the natural rolloff of this counter
end if;
end process; -- address_scan_counter
display_driver_with_decoder: entity work.display_driver_w_decoder
port map(
clk => clk,
reset => rst,
ascii_in => std_logic_vector(symbol_scan_cntr),
wr_en => '0',
disp_data_q => disp_data_q
);
 
 
AddrScanCntr:process(rst,bttn_state)
begin
if rst='1' then
symbol_scan_cntr <= (others=>'0');
elsif rising_edge(bttn_state) then -- TODO: Fix this to edge detector implementation
symbol_scan_cntr <= symbol_scan_cntr + 1; -- I count ont the natural rolloff of this counter
end if;
end process;
 
 
DDwD_Top:entity work.DisplayDriverwDecoder_Top
port map(
clk => clk,
reset => rst,
ascii_in => std_logic_vector(symbol_scan_cntr),
wr_en => '0',
disp_data => disp_data,
disp_sel => disp_sel
);
 
--disp_sel <= '1' when button = '1';
 
end arch;
 

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