OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 8 to Rev 9
    ↔ Reverse comparison
  •

Rev 8 → Rev 9

/socgen/trunk/bin/Makefile.root
84,8 → 84,16
################################################################################
 
 
.PHONY clean_sims:
clean_sims:
(\
rm -f $(CUR_DIR)/../out/*;\
rm -f $(CUR_DIR)/../log/*;\
)
 
 
.PHONY run_sims:
run_sims:
run_sims: clean_sims
@for VARIENT_PROG in `ls $(CUR_DIR)/../run`; do \
echo "################################################################################"; \
echo; \
98,7 → 106,7
done; \
 
 
 
.PHONY sim:
sim:
(\
iverilog -D VCD ../../bench/verilog/TestBench;\
151,11 → 159,11
cd xilinx;\
echo "run -ifn ../filelist -ifmt mixed -top " $(board)_$(Design) " -ofn " $(board)_$(Design)".ngc -ofmt NGC -p " $(Part) "-opt_mode Speed -opt_level 1" > Xst;\
xst -ifn ./Xst -ofn $(board)_$(Design).log;\
ngdbuild -uc ../targets/$(board)/$(board).ucf $(board)_$(Design);\
ngdbuild -uc ../target/$(board).ucf $(board)_$(Design);\
map -p $(Part) -cm area -pr b -k 4 -c 100 -o $(board)_$(Design)_map.ncd $(board)_$(Design).ngd $(board)_$(Design).pcf;\
par -w -ol std -t 1 $(board)_$(Design)_map.ncd $(board)_$(Design).ncd $(board)_$(Design).pcf ;\
trce -e 3 -s 5 -xml $(board)_$(Design) $(board)_$(Design).ncd -o $(board)_$(Design).twr $(board)_$(Design).pcf -ucf ../targets/$(board)/$(board).ucf ;\
bitgen -f ../targets/$(board)/jtag.ut $(board)_$(Design).ncd;\
trce -e 3 -s 5 -xml $(board)_$(Design) $(board)_$(Design).ncd -o $(board)_$(Design).twr $(board)_$(Design).pcf -ucf ../target/$(board).ucf ;\
bitgen -f ../target/jtag.ut $(board)_$(Design).ncd;\
mv $(board)_$(Design).bit $(board)_$(Design)_jtag.bit ;\
bit_2_svf $(board)_$(Design)_jtag.bit ;\
cp $(board)_$(Design)_jtag.svf ../debug/bitstream.svf ;\
/socgen/trunk/bin/hex2abs12
70,7 → 70,7
## Help option
##############################################################################
if ( ($opt_h eq "1") )
{ print "\n type> hex2abs12 prog_name ( no extension)";
{ print "\n type test filename ( no extension)";
print "\n";
exit 1;
}
/socgen/trunk/bin/hex2abs16
70,7 → 70,7
## Help option
##############################################################################
if ( ($opt_h eq "1") )
{ print "\n type> hex2abs16 prog_name ( no extension)";
{ print "\n type test filename ( no extension)";
print "\n";
exit 1;
}
/socgen/trunk/bin/hex2abs_split
0,0 → 1,215
eval 'exec `which perl` -S $0 ${1+"$@"}'
if 0;
 
#/**********************************************************************/
#/* */
#/* ------- */
#/* / SOC \ */
#/* / GEN \ */
#/* / TOOL \ */
#/* ============== */
#/* | | */
#/* |____________| */
#/* */
#/* Converts a intel hex file into a 16 bit verilog readmemh format */
#/* split into 8 bit even and 8 bit odd files */
#/* */
#/* Author(s): */
#/* - John Eaton, jt_eaton@opencores.org */
#/* */
#/**********************************************************************/
#/* */
#/* Copyright (C) <2010> <Ouabache Design Works> */
#/* */
#/* This source file may be used and distributed without */
#/* restriction provided that this copyright statement is not */
#/* removed from the file and that any derivative work contains */
#/* the original copyright notice and the associated disclaimer. */
#/* */
#/* This source file is free software; you can redistribute it */
#/* and/or modify it under the terms of the GNU Lesser General */
#/* Public License as published by the Free Software Foundation; */
#/* either version 2.1 of the License, or (at your option) any */
#/* later version. */
#/* */
#/* This source is distributed in the hope that it will be */
#/* useful, but WITHOUT ANY WARRANTY; without even the implied */
#/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
#/* PURPOSE. See the GNU Lesser General Public License for more */
#/* details. */
#/* */
#/* You should have received a copy of the GNU Lesser General */
#/* Public License along with this source; if not, download it */
#/* from http://www.opencores.org/lgpl.shtml */
#/* */
#/**********************************************************************/
 
# ToDO: add handling unaligned words
 
 
############################################################################
# General PERL config
############################################################################
use Getopt::Long;
use English;
use File::Basename;
 
$OUTPUT_AUTOFLUSH = 1; # set autoflush of stdout to TRUE.
 
 
############################################################################
### Process the options
############################################################################
 
Getopt::Long::config("require_order", "prefix=-");
GetOptions("h"
) || die "(use '$program_name -h' for help)";
 
 
##############################################################################
## Help option
##############################################################################
if ( ($opt_h eq "1") )
{ print "\n type test filename ( no extension)";
print "\n";
exit 1;
}
 
 
 
#############################################################################
##
## open intel hex file and read into array
##
#############################################################################
 
my $prog_name = $ARGV[0];
 
my $input_file = ${prog_name}.".hex";
my $output_file_e = ${prog_name}.".absE";
my $output_file_o = ${prog_name}.".absO";
 
print "Reading hex File $input_file\n";
print "Writing abs File $output_file_e\n";
print "Writing abs File $output_file_o\n";
 
open VERILOG_E , "> $output_file_e";
open VERILOG_O , "> $output_file_o";
open FILE, $input_file;
 
open DEFINES , "> ROM_defines.v";
 
while(<FILE>){push @intel_hex, $_ ;}
 
 
#############################################################################
##
## Clear a storage area for the 16 bit words
##
#############################################################################
 
 
my $x=0;
while( $x <= 65535)
{
@Mem_e[$x] = "00";
@Mem_o[$x] = "00";
$x = $x+1;
}
 
 
#############################################################################
##
## Parse Data into storage converting from 8 bit bytes to 16 bit words
##
#############################################################################
my $pointer = 0;
my $max_pointer = 0;
my $start_address = 65536;
 
 
foreach $line (@intel_hex)
{
$colon = substr($line, 0,1);
$length = (cvt(substr($line, 1,1))* 16) + cvt(substr($line, 2,1));
$address = cvt(substr($line, 3,1));
$address = cvt(substr($line, 4,1))+($address *16) ;
$address = cvt(substr($line, 5,1))+($address *16) ;
$address = cvt(substr($line, 6,1))+($address *16) ;
$type = substr($line, 7,2);
 
 
 
if(($type eq "00") )
 
{
if( $address <= $start_address) {$start_address = $address;}
$x=9;
while( $x <= 7+($length *2))
{
$value_E = substr($line, $x,2);
$value_O = substr($line, $x+2,2);
$pointer = (($address/2) +($x-9)/4);
if( $pointer > $max_pointer ) {$max_pointer = $pointer}
@Mem_e[$pointer] = $value_E;
@Mem_o[$pointer] = $value_O;
$x= $x+4;
}
 
 
}
 
 
 
 
}
 
 
#############################################################################
##
## dump out up to the last word, undefined space is 000
##
#############################################################################
 
$x = ($start_address/2);
while( $x <= ($max_pointer))
{
printf VERILOG_E (" %s\n",@Mem_e[$x]);
printf VERILOG_O (" %s\n",@Mem_o[$x]);
$x = $x+1;
}
 
 
$words = ($max_pointer) - ($start_address/2)+1;
printf DEFINES ("`define PROG_FILE /${prog_name}.abs16\n" );
printf DEFINES ("`define ROM_WIDTH 16\n" );
printf DEFINES ("`define ROM_WORDS $words \n" );
 
 
#############################################################################
##
## convert 0-9,A-F to decimal or 0 if out of range
##
#############################################################################
 
 
sub cvt {
 
$temp = ord($_[0]);
if( $temp <= 48) { return 0 }
if( $temp <= 58) { return $temp - 48 }
if( $temp <= 64) { return 0 }
if( $temp <= 70) { return ($temp - 65)+10 }
return 0;
 
 
 
}
 
 
 
 
1
 
 
/socgen/trunk/bin/hex2abs
0,0 → 1,210
eval 'exec `which perl` -S $0 ${1+"$@"}'
if 0;
 
#/**********************************************************************/
#/* */
#/* ------- */
#/* / SOC \ */
#/* / GEN \ */
#/* / TOOL \ */
#/* ============== */
#/* | | */
#/* |____________| */
#/* */
#/* Converts a intel hex file into a 8 bit verilog readmemh format */
#/* */
#/* */
#/* Author(s): */
#/* - John Eaton, jt_eaton@opencores.org */
#/* */
#/**********************************************************************/
#/* */
#/* Copyright (C) <2010> <Ouabache Design Works> */
#/* */
#/* This source file may be used and distributed without */
#/* restriction provided that this copyright statement is not */
#/* removed from the file and that any derivative work contains */
#/* the original copyright notice and the associated disclaimer. */
#/* */
#/* This source file is free software; you can redistribute it */
#/* and/or modify it under the terms of the GNU Lesser General */
#/* Public License as published by the Free Software Foundation; */
#/* either version 2.1 of the License, or (at your option) any */
#/* later version. */
#/* */
#/* This source is distributed in the hope that it will be */
#/* useful, but WITHOUT ANY WARRANTY; without even the implied */
#/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
#/* PURPOSE. See the GNU Lesser General Public License for more */
#/* details. */
#/* */
#/* You should have received a copy of the GNU Lesser General */
#/* Public License along with this source; if not, download it */
#/* from http://www.opencores.org/lgpl.shtml */
#/* */
#/**********************************************************************/
 
# ToDO: add handling unaligned words
 
 
############################################################################
# General PERL config
############################################################################
use Getopt::Long;
use English;
use File::Basename;
 
$OUTPUT_AUTOFLUSH = 1; # set autoflush of stdout to TRUE.
 
 
############################################################################
### Process the options
############################################################################
 
Getopt::Long::config("require_order", "prefix=-");
GetOptions("h"
) || die "(use '$program_name -h' for help)";
 
 
##############################################################################
## Help option
##############################################################################
if ( ($opt_h eq "1") )
{ print "\n type test filename ( no extension)";
print "\n";
exit 1;
}
 
 
 
#############################################################################
##
## open intel hex file and read into array
##
#############################################################################
 
my $prog_name = $ARGV[0];
 
my $input_file = ${prog_name}.".hex";
my $output_file = ${prog_name}.".abs";
 
 
print "Reading hex File $input_file\n";
print "Writing abs File $output_file\n";
 
 
open VERILOG , "> $output_file";
open FILE, $input_file;
 
open DEFINES , "> ROM_defines.v";
 
while(<FILE>){push @intel_hex, $_ ;}
 
 
#############################################################################
##
## Clear a storage area for the 8 bit words
##
#############################################################################
 
 
my $x=0;
while( $x <= 65535)
{
@Mem[$x] = "0000";
$x = $x+1;
}
 
 
#############################################################################
##
## Parse Data into storage
##
#############################################################################
my $pointer = 0;
my $max_pointer = 0;
my $start_address = 65536;
 
 
foreach $line (@intel_hex)
{
$colon = substr($line, 0,1);
$length = (cvt(substr($line, 1,1))* 16) + cvt(substr($line, 2,1));
$address = cvt(substr($line, 3,1));
$address = cvt(substr($line, 4,1))+($address *16) ;
$address = cvt(substr($line, 5,1))+($address *16) ;
$address = cvt(substr($line, 6,1))+($address *16) ;
$type = substr($line, 7,2);
 
 
 
if(($type eq "00") )
 
{
if( $address <= $start_address) {$start_address = $address;}
$x=9;
while( $x <= 7+($length *2))
{
$value = substr($line, $x,2);
$pointer = (($address ) +(($x-9)/2));
if( $pointer > $max_pointer ) {$max_pointer = $pointer}
@Mem[$pointer] = $value;
$x= $x+2;
}
 
 
}
 
 
 
 
}
 
 
#############################################################################
##
## dump out up to the last word, undefined space is 000
##
#############################################################################
 
$x = ($start_address);
while( $x <= ($max_pointer))
{
printf VERILOG (" %s\n",@Mem[$x]);
$x = $x+1;
}
 
 
$words = ($max_pointer) - ($start_address)+1;
printf DEFINES ("`define PROG_FILE /${prog_name}.abs\n" );
printf DEFINES ("`define ROM_WIDTH 8\n" );
printf DEFINES ("`define ROM_WORDS $words \n" );
 
 
#############################################################################
##
## convert 0-9,A-F to decimal or 0 if out of range
##
#############################################################################
 
 
sub cvt {
 
$temp = ord($_[0]);
if( $temp <= 48) { return 0 }
if( $temp <= 58) { return $temp - 48 }
if( $temp <= 64) { return 0 }
if( $temp <= 70) { return ($temp - 65)+10 }
return 0;
 
 
 
}
 
 
 
 
1
 
 
/socgen/trunk/bin/build_cmp
119,15 → 119,10
chomp($project);
$cmd = "mkdir ${home}/${design}_cmp/projects/${project} > /dev/null " ;
if (system($cmd)) {die "Failed ";}
print ("$cmd \n");
$cmd = "lndir -silent ${home}/${design}/projects/${project} ${home}/${design}_cmp/projects/${project} " ;
if (system($cmd)) {die "Failed ";}
print ("$cmd \n");
$cmd = "ln -s ${home}/${design}/bin/Makefile.root ${home}/${design}_cmp/projects/${project}"."/bin " ;
if (system($cmd)) {die "Failed ";}
print ("$cmd \n");
 
my @components = qx(ls ${home}/${design}/projects/${project}/ip );
foreach my $component (@components)
{
135,66 → 130,51
 
$cmd = "mkdir ${home}/${design}_cmp/projects/${project}/ip/${component}/sim/bench " ;
if (system($cmd)) {}
print ("$cmd \n");
$cmd = "mkdir ${home}/${design}_cmp/projects/${project}/ip/${component}/sim/lib " ;
if (system($cmd)) {}
print ("$cmd \n");
$cmd =
"lndir -silent ${home}/${design}/bench ${home}/${design}_cmp/projects/${project}/ip/${component}/sim/bench " ;
if (system($cmd)) {die "Failed ";}
print ("$cmd \n");
$cmd =
"lndir -silent ${home}/${design}/lib ${home}/${design}_cmp/projects/${project}/ip/${component}/sim/lib " ;
if (system($cmd)) {die "Failed ";}
print ("$cmd \n");
 
 
 
 
 
 
 
 
 
 
my @syns = qx(ls ${home}/${design}/projects/${project}/ip/${component}/syn );
foreach my $syn (@syns)
{
chomp($syn);
print ("SYN $syn \n");
chomp($syn);
print ("SYN $syn \n");
 
my @targets = qx(ls ${home}/${design}/projects/${project}/ip/${component}/syn/${syn}/target );
 
$cmd = "mkdir ${home}/${design}_cmp/projects/${project}/ip/${component}/syn/${syn}/targets " ;
if (system($cmd)) {}
print ("$cmd \n");
$cmd =
"lndir -silent ${home}/${design}/targets ${home}/${design}_cmp/projects/${project}/ip/${component}/syn/${syn}/targets " ;
if (system($cmd)) {}
print ("$cmd \n");
$cmd =
"lndir -silent ${home}/${design}/lib ${home}/${design}_cmp/projects/${project}/ip/${component}/syn/${syn}/targets/Basys/lib/syn" ;
if (system($cmd)) {}
print ("$cmd \n");
$cmd =
"lndir -silent ${home}/${design}/lib ${home}/${design}_cmp/projects/${project}/ip/${component}/syn/${syn}/targets/Nexys/lib/syn" ;
if (system($cmd)) { }
print ("$cmd \n");
foreach my $target (@targets)
{
chomp($target);
print ("TARGET $target \n");
 
$cmd =
"lndir -silent ${home}/${design}/targets/${target} ${home}/${design}_cmp/projects/${project}/ip/${component}/syn/${syn}/target " ;
if (system($cmd)) {}
 
}
$cmd =
"lndir -silent ${home}/${design}/lib ${home}/${design}_cmp/projects/${project}/ip/${component}/syn/${syn}/target/lib/syn" ;
if (system($cmd)) {}
 
$cmd =
"rmdir ${home}/${design}_cmp/projects/${project}/ip/${component}/syn/${syn}/target/${target}" ;
if (system($cmd)) {}
 
 
 
 
}
 
 
 
}
 
 
 
 
 
}
 
 
210,27 → 190,16
 
$cmd = "mkdir ${home}/${design}_cmp/projects/${project}/children/${child}/bin " ;
if (system($cmd)) {die "Failed ";}
print ("$cmd \n");
$cmd = "ln -s ${home}/${design}/bin/Makefile.root ${home}/${design}_cmp/projects/${project}/children/${child}/bin " ;
if (system($cmd)) {die "Failed ";}
$cmd = "ln -s ${home}/${design}/bin/Makefile ${home}/${design}_cmp/projects/${project}/children/${child}/bin " ;
if (system($cmd)) {die "Failed ";}
print ("$cmd \n");
 
$cmd = "mkdir ${home}/${design}_cmp/projects/${project}/children/${child}/sw " ;
if (system($cmd)) {die "Failed ";}
print ("$cmd \n");
$cmd = "lndir -silent ${home}/${design}/projects/${child}/sw ${home}/${design}_cmp/projects/${project}/children/${child}/sw " ;
if (system($cmd)) {}
print ("$cmd \n");
 
 
 
 
 
 
 
 
my @grand_children = qx(ls ${home}/${design}/projects/${project}/children/${child}/ip );
foreach my $grand_child (@grand_children)
{
238,15 → 207,8
$cmd =
"lndir -silent ${home}/${design}/projects/${child}/ip/${grand_child} ${home}/${design}_cmp/projects/${project}/children/${child}/ip/${grand_child} " ;
if (system($cmd)) {die "Failed ";}
print ("$cmd \n");
}
 
 
 
 
 
 
 
}
 
}
255,10 → 217,6
 
 
 
 
 
 
 
1
 
 
/socgen/trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/debug/fpga_load
1,4 → 1,4
bsdl path ../bsdl;../targets/Basys;
bsdl path ../bsdl;../target/bsdl;
cable usbblaster
detect
part 1
/socgen/trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/filelist
1,11 → 1,11
verilog work ./targets/Basys/Pad_Ring.v
verilog work ./target/Pad_Ring.v
verilog work ../../../../../ip/mrisc/rtl/gen/syn/mrisc.v
verilog work ../../../../../children/logic/ip/disp_io/rtl/gen/syn/disp_io.v
 
verilog work ./targets/Basys/lib/syn/cde_pads/cde_pad_se_dig.v
verilog work ./targets/Basys/lib/syn/cde_clock_sys/cde_clock_sys.v
verilog work ./targets/Basys/lib/syn/cde_jtag/cde_jtag.v
verilog work ./targets/Basys/lib/syn/cde_jtag/cde_jtag_rpc_reg.v
verilog work ./targets/Basys/lib/syn/cde_sram/cde_sram.v
verilog work ./target/lib/syn/cde_pads/cde_pad_se_dig.v
verilog work ./target/lib/syn/cde_clock_sys/cde_clock_sys.v
verilog work ./target/lib/syn/cde_jtag/cde_jtag.v
verilog work ./target/lib/syn/cde_jtag/cde_jtag_rpc_reg.v
verilog work ./target/lib/syn/cde_sram/cde_sram.v
 
 
/socgen/trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/core.v
78,9 → 78,9
.inst_addr (inst_addr),
.inst_data (inst_data),
 
.portain (portain),
.portbin (portbin),
.portcin (portcin),
.portain (portaout),
.portbin (portbout),
.portcin (portcout),
 
.portaout (portaout),
.portbout (portbout),
91,7 → 91,7
.trisc (trisc),
.tcki (1'b0),
.wdt_en (1'b1)
.wdt_en (1'b0)
 
);
 
126,7 → 126,7
assign ps2_clk_pad_oe = 1'b0;
 
 
assign PosD = {trisa[4:0],inst_addr};
assign PosD = {portcout,portbout};
assign PosL = portaout;
 
 
/socgen/trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/Makefile
1,4 → 1,4
include ../../../../bin/Makefile.root
include ./targets/Basys/Makefile.brd
include ./target/Makefile.brd
Design=loop
 
/socgen/trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/def_file
1,8 → 1,7
`define SYNTHESIS
`define ROM_FILE "../../../../../../../projects/pic_micro/sw/loop/loop.abs12"
`define ROM_WORDS 27
`define ROM_FILE "../../../../../../../projects/pic_micro/sw/loop/loop.abs12"
`include "../../../../../../../projects/pic_micro/sw/loop/ROM_defines.v"
`define ROM_ADDR 11
`define ROM_WIDTH 12
`define MODULE_NAME Basys_loop
 
 
/socgen/trunk/projects/pic_micro/sw/sanity2/sanity2.asm
66,6 → 66,7
 
; SETUP all ports
; Tristate all ports
sleep
clrw
movwf FSR
movwf PORTA
74,8 → 75,28
tris PORTA
tris PORTB
tris PORTC
clrwdt
clrw
xorlw 0x01
option
movwf TMR0
xorlw 0x03
sleep
option
xorlw 0x0f
option
xorlw 0x1f
option
movwf TMR0
xorlw 0x3f
option
xorlw 0xff
option
clrwdt
 
 
 
; -------------------------------
; ---- Test the PLC register ----
; -------------------------------
/socgen/trunk/targets/Basys/Pad_Ring.ucf
0,0 → 1,87
# clock pin for Basys Board
NET "A_CLK" LOC = "p53" ; # oscillator 48 Mhz
NET "B_CLK" LOC = "p54" ; # resonator 100/50/25
 
 
 
# Pin assignment for DispCtl
# Connected to Basys onBoard 7seg display
 
NET "SEG<0>" LOC = "p25" ; # Signal name = CA
NET "SEG<1>" LOC = "p16" ; # Signal name = CB
NET "SEG<2>" LOC = "p23" ; # Signal name = CC
NET "SEG<3>" LOC = "p21" ; # Signal name = CD
NET "SEG<4>" LOC = "p20" ; # Signal name = CE
NET "SEG<5>" LOC = "p17" ; # Signal name = CF
NET "SEG<6>" LOC = "p83" ; # Signal name = CG
NET "DP" LOC = "p22" ; # Signal name = DP
 
NET "AN<3>" LOC = "p26" ; # Signal name = AN3
NET "AN<2>" LOC = "p32" ; # Signal name = AN2
NET "AN<1>" LOC = "p33" ; # Signal name = AN1
NET "AN<0>" LOC = "p34" ; # Signal name = AN0
 
# Pin assignment for LEDs
NET "LED<7>" LOC = "p2" ; # Bank = 3, Signal name = LD7
NET "LED<6>" LOC = "p3" ; # Bank = 3, Signal name = LD6
NET "LED<5>" LOC = "p4" ; # Bank = 3, Signal name = LD5
NET "LED<4>" LOC = "p5" ; # Bank = 3, Signal name = LD4
NET "LED<3>" LOC = "p7" ; # Bank = 3, Signal name = LD3
NET "LED<2>" LOC = "p8" ; # Bank = 3, Signal name = LD2
NET "LED<1>" LOC = "p14" ; # Bank = 3, Signal name = LD1
NET "LED<0>" LOC = "p15" ; # Bank = 3, Signal name = LD0
 
# Pin assignment for SWs
NET "SW<7>" LOC = "p6" ; # Bank = 3, Signal name = SW7
NET "SW<6>" LOC = "p10" ; # Bank = 3, Signal name = SW6
NET "SW<5>" LOC = "p12" ; # Bank = 3, Signal name = SW5
NET "SW<4>" LOC = "p18" ; # Bank = 3, Signal name = SW4
NET "SW<3>" LOC = "p24" ; # Bank = 3, Signal name = SW3
NET "SW<2>" LOC = "p29" ; # Bank = 3, Signal name = SW2
NET "SW<1>" LOC = "p36" ; # Bank = 3, Signal name = SW1
NET "SW<0>" LOC = "p38" ; # Bank = 2, Signal name = SW0
 
# Pin assignment for BTNs
NET "BTN<3>" LOC = "p41" ; # Bank = 2, Signal name = BTN3
NET "BTN<2>" LOC = "p47" ; # Bank = 2, Signal name = BTN2
NET "BTN<1>" LOC = "p48" ; # Bank = 2, Signal name = BTN1
NET "BTN<0>" LOC = "p69" ; # Bank = 2, Signal name = BTN0
 
# Loop back/demo signals
# Pin assignment for PS2
NET "PS2C" LOC = "p96" | DRIVE = 2 | PULLUP ; # Bank = 1, Signal name = PS2C
NET "PS2D" LOC = "p97" | DRIVE = 2 | PULLUP ; # Bank = 1, Signal name = PS2D
 
# Pin assignment for VGA
NET "HSYNC" LOC = "p39" | DRIVE = 2 ; # Bank = 2, Signal name = HSYNC
NET "VSYNC" LOC = "p35" | DRIVE = 2 ; # Bank = 3, Signal name = VSYNC
NET "VGARED<2>" LOC = "p67" | DRIVE = 2 ; # Bank = 2, Signal name = RED2
NET "VGARED<1>" LOC = "p68" | DRIVE = 2 ; # Bank = 2, Signal name = RED1
NET "VGARED<0>" LOC = "p70" | DRIVE = 2 ; # Bank = 2, Signal name = RED0
NET "VGAGREEN<2>" LOC = "p50" | DRIVE = 2 ; # Bank = 2, Signal name = GRN2
NET "VGAGREEN<1>" LOC = "p51" | DRIVE = 2 ; # Bank = 2, Signal name = GRN1
NET "VGAGREEN<0>" LOC = "p52" | DRIVE = 2 ; # Bank = 2, Signal name = GRN0
NET "VGABLUE<1>" LOC = "p43" | DRIVE = 2 ; # Bank = 2, Signal name = BLU2
NET "VGABLUE<0>" LOC = "p44" | DRIVE = 2 ; # Bank = 2, Signal name = BLU1
 
# Pin assignment for Expansion Ports
 
NET "JA_1" LOC = "p81" | DRIVE = 6 ;
NET "JA_2" LOC = "p91" | DRIVE = 6 ;
NET "JA_3" LOC = "p82" | DRIVE = 6 ;
NET "JA_4" LOC = "p92" | DRIVE = 6 ;
 
NET "JB_1" LOC = "p87" ;
NET "JB_2" LOC = "p93" ;
NET "JB_3" LOC = "p88" ;
NET "JB_4" LOC = "p94" ;
 
NET "JC_1" LOC = "p77" ;
NET "JC_2" LOC = "p86" ;
NET "JC_3" LOC = "p76" ;
NET "JC_4" LOC = "p85" ;
 
NET "RTS" LOC = "p75" ;
NET "CTS" LOC = "p59" ;
NET "RXD" LOC = "p74" ;
NET "TXD" LOC = "p58" ;

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