URL
https://opencores.org/ocsvn/usb_phy/usb_phy/trunk
Subversion Repositories usb_phy
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 8 to Rev 9
- ↔ Reverse comparison
Rev 8 → Rev 9
/trunk/rtl/verilog/usb_tx_phy.v
39,10 → 39,10
|
// CVS Log |
// |
// $Id: usb_tx_phy.v,v 1.2 2003-10-19 17:40:13 rudi Exp $ |
// $Id: usb_tx_phy.v,v 1.3 2003-10-21 05:58:41 rudi Exp $ |
// |
// $Date: 2003-10-19 17:40:13 $ |
// $Revision: 1.2 $ |
// $Date: 2003-10-21 05:58:41 $ |
// $Revision: 1.3 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
49,6 → 49,11
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2003/10/19 17:40:13 rudi |
// - Made core more robust against line noise |
// - Added Error Checking and Reporting |
// (See README.txt for more info) |
// |
// Revision 1.1.1.1 2002/09/16 14:27:02 rudi |
// Created Directory Structure |
// |
399,15 → 404,12
|
case(state) // synopsys full_case parallel_case |
IDLE: |
begin |
if(TxValid_i) |
begin |
ld_sop_d = 1'b1; |
next_state = SOP; |
end |
end |
SOP: |
begin |
if(sft_done_e) |
begin |
tx_ready_d = 1'b1; |
414,7 → 416,6
ld_data_d = 1'b1; |
next_state = DATA; |
end |
end |
DATA: |
begin |
if(!data_done && sft_done_e) |
430,17 → 431,11
end |
end |
EOP1: |
begin |
if(eop_done) next_state = EOP2; |
end |
EOP2: |
begin |
if(!eop_done && fs_ce) next_state = WAIT; |
end |
WAIT: |
begin |
if(fs_ce) next_state = IDLE; |
end |
endcase |
end |
|
/trunk/rtl/verilog/usb_phy.v
38,10 → 38,10
|
// CVS Log |
// |
// $Id: usb_phy.v,v 1.3 2003-10-19 17:40:13 rudi Exp $ |
// $Id: usb_phy.v,v 1.4 2003-10-21 05:58:40 rudi Exp $ |
// |
// $Date: 2003-10-19 17:40:13 $ |
// $Revision: 1.3 $ |
// $Date: 2003-10-21 05:58:40 $ |
// $Revision: 1.4 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
48,6 → 48,11
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2003/10/19 17:40:13 rudi |
// - Made core more robust against line noise |
// - Added Error Checking and Reporting |
// (See README.txt for more info) |
// |
// Revision 1.2 2002/09/16 16:06:37 rudi |
// Changed top level name to be consistent ... |
// |
97,7 → 102,8
|
reg [4:0] rst_cnt; |
reg usb_rst; |
wire reset; |
wire fs_ce; |
wire rst; |
|
/////////////////////////////////////////////////////////////////// |
// |
104,8 → 110,6
// Misc Logic |
// |
|
assign reset = rst & ~usb_rst; |
|
/////////////////////////////////////////////////////////////////// |
// |
// TX Phy |
113,7 → 117,7
|
usb_tx_phy i_tx_phy( |
.clk( clk ), |
.rst( reset ), |
.rst( rst ), |
.fs_ce( fs_ce ), |
.phy_mode( phy_tx_mode ), |
|
135,7 → 139,7
|
usb_rx_phy i_rx_phy( |
.clk( clk ), |
.rst( reset ), |
.rst( rst ), |
.fs_ce( fs_ce ), |
|
// Transciever Interface |
157,7 → 161,11
// Generate an USB Reset is we see SE0 for at least 2.5uS |
// |
|
`ifdef USB_ASYNC_REST |
always @(posedge clk or negedge rst) |
`else |
always @(posedge clk) |
`endif |
if(!rst) rst_cnt <= 5'h0; |
else |
if(LineState_o != 2'h0) rst_cnt <= 5'h0; |