URL
https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk
Subversion Repositories vga_lcd
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 8 to Rev 9
- ↔ Reverse comparison
Rev 8 → Rev 9
/trunk/counter.vhd
7,6 → 7,10
-- rev. 1.1 april 26th, 2001. Changed SYNCH_RCO (component ud_cnt) from string to bit. Fixed problems with Synplify |
-- rev. 1.2 may 11th, 2001. Fixed incomplete sensitivity list warning |
-- rev. 1.3 june 18th, 2001. Changed module order, they are now in compilation order. |
-- rev. 1.4 june 27th, 2001. Removed 'SYNCH_RCO' parameter, simplifies conversion to verilog. |
-- Fixed a potential bug in "ro_cnt" where 'rci' was not related to 'cnt_en'. |
-- Changed "val" signal generation from process to "when..else.." statement |
-- |
|
|
library ieee; |
17,7 → 21,6
-- general purpose up-down counter |
component ud_cnt is |
generic( |
SYNCH_RCO : bit := '0'; -- NO |
SIZE : natural := 8 |
); |
port( |
66,7 → 69,6
|
entity ud_cnt is |
generic( |
SYNCH_RCO : bit := '0'; -- NO |
SIZE : natural := 8 |
); |
port( |
91,14 → 93,7
signal Qi : unsigned(SIZE -1 downto 0); |
signal val : unsigned(SIZE downto 0); |
begin |
nval: process(rci, ud, Qi) |
begin |
if (ud = '1') then |
val <= ('0' & Qi) + rci; |
else |
val <= ('0' & Qi) - rci; |
end if; |
end process nval; |
val <= ( ('0' & Qi) + rci) when (ud = '1') else ( ('0' & Qi) - rci); |
|
regs: process(clk, nReset, resD) |
begin |
119,28 → 114,7
|
-- assign outputs |
Q <= Qi; |
|
gen_rco: |
if (SYNCH_RCO = '0') generate |
rco <= val(SIZE); |
end generate; |
gen_srco: |
if (SYNCH_RCO = '1') generate |
process(clk, nReset) |
begin |
if (nReset = '0') then |
rco <= '0'; |
elsif (clk'event and clk = '1') then |
if (rst = '1') then |
rco <= '0'; |
else |
if (cnt_en = '1') then |
rco <= val(SIZE); |
end if; |
end if; |
end if; |
end process; |
end generate; |
rco <= val(SIZE); |
end architecture structural; |
|
|
171,7 → 145,6
architecture structural of ro_cnt is |
component ud_cnt is |
generic( |
SYNCH_RCO : bit := '0'; -- NO |
SIZE : natural := 8 |
); |
port( |
201,7 → 174,7
elsif (clk'event and clk = '1') then |
if (rst = '1') then |
rci <= '0'; |
else |
elsif (cnt_en = '1' ) then |
rci <= (go or rci) and not rco; |
end if; |
end if; |
211,9 → 184,10
|
-- hookup counter |
cnt : ud_cnt |
generic map (SIZE => SIZE, SYNCH_RCO => '0') |
generic map (SIZE => SIZE) |
port map (clk => clk, nReset => nReset, rst => rst, cnt_en => cnt_en, nld => nld, D => D, Q => Q, |
resD => ID, rci => rci, rco => rco); |
|
done <= rco; |
end architecture structural; |
|