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Rev 8 → Rev 9

/trunk/bench/verilog/wb_mast_model.v
11,7 → 11,7
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
37,10 → 37,10
 
// CVS Log
//
// $Id: wb_mast_model.v,v 1.1 2001-07-29 08:57:02 rudi Exp $
// $Id: wb_mast_model.v,v 1.2 2001-09-07 15:34:36 rudi Exp $
//
// $Date: 2001-07-29 08:57:02 $
// $Revision: 1.1 $
// $Date: 2001-09-07 15:34:36 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,11 → 47,17
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.1.1.1 2001/03/19 13:11:34 rudi
// Initial Release
//
//
//
//
 
`include "wb_model_defines.v"
 
71,6 → 77,8
// Local Wires
//
 
parameter mem_size = 4096;
 
reg [31:0] adr;
reg [31:0] dout;
reg cyc, stb;
77,6 → 85,11
reg [3:0] sel;
reg we;
 
reg [31:0] rd_mem[mem_size:0];
reg [31:0] wr_mem[mem_size:0];
integer rd_cnt;
integer wr_cnt;
 
////////////////////////////////////////////////////////////////////
//
// Memory Logic
92,10 → 105,28
stb = 0;
sel = 4'hx;
we = 1'hx;
rd_cnt = 0;
wr_cnt = 0;
#1;
$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
end
 
 
 
task mem_fill;
 
integer n;
begin
rd_cnt = 0;
wr_cnt = 0;
for(n=0;n<mem_size;n=n+1)
begin
rd_mem[n] = $random;
wr_mem[n] = $random;
end
end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Write 1 Word Task
118,20 → 149,20
sel = s;
 
@(posedge clk);
while(~ack) @(posedge clk);
while(~ack & ~err) @(posedge clk);
#1;
cyc=0;
stb=0;
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
//adr = 0;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
//@(posedge clk);
end
endtask
 
 
////////////////////////////////////////////////////////////////////
//
// Write 4 Words Task
164,7 → 195,7
dout = d1;
stb = 1;
we=1;
while(~ack) @(posedge clk);
while(~ack & ~err) @(posedge clk);
#2;
stb=0;
we=1'bx;
181,7 → 212,7
dout = d2;
we=1;
@(posedge clk);
while(~ack) @(posedge clk);
while(~ack & ~err) @(posedge clk);
#2;
stb=0;
we=1'bx;
197,7 → 228,7
dout = d3;
we=1;
@(posedge clk);
while(~ack) @(posedge clk);
while(~ack & ~err) @(posedge clk);
#2;
stb=0;
we=1'bx;
213,12 → 244,14
dout = d4;
we=1;
@(posedge clk);
while(~ack) @(posedge clk);
while(~ack & ~err) @(posedge clk);
#1;
stb=0;
cyc=0;
 
adr = 32'hxxxx_xxxx;
//adr = 0;
//adr = 32'hffff_ffff;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
227,6 → 260,240
endtask
 
 
task wb_wr_mult;
input [31:0] a;
input [3:0] s;
input delay;
input count;
 
integer delay;
integer count;
integer n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
 
for(n=0;n<count;n=n+1)
begin
repeat(delay)
begin
@(posedge clk);
#1;
end
adr = a + (n*4);
dout = wr_mem[n + wr_cnt];
stb = 1;
we=1;
sel = s;
if(n!=0) @(posedge clk);
while(~ack & ~err) @(posedge clk);
#2;
stb=0;
we=1'bx;
sel = 4'hx;
dout = 32'hxxxx_xxxx;
adr = 32'hxxxx_xxxx;
end
 
cyc=0;
 
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
 
wr_cnt = wr_cnt + count;
end
endtask
 
 
task wb_rmw;
input [31:0] a;
input [3:0] s;
input delay;
input rcount;
input wcount;
 
integer delay;
integer rcount;
integer wcount;
integer n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay) @(posedge clk);
 
for(n=0;n<rcount-1;n=n+1)
begin
adr = a + (n*4);
stb = 1;
while(~ack & ~err) @(posedge clk);
rd_mem[n + rd_cnt] = din;
//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
repeat(delay)
begin
@(posedge clk);
#1;
end
we = 0;
sel = s;
end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
rd_mem[n + rd_cnt] = din;
//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
#1;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
 
rd_cnt = rd_cnt + rcount;
 
//@(posedge clk);
 
 
for(n=0;n<wcount;n=n+1)
begin
repeat(delay)
begin
@(posedge clk);
#1;
end
adr = a + (n*4);
dout = wr_mem[n + wr_cnt];
stb = 1;
we=1;
sel = s;
// if(n!=0)
@(posedge clk);
while(~ack & ~err) @(posedge clk);
#2;
stb=0;
we=1'bx;
sel = 4'hx;
dout = 32'hxxxx_xxxx;
adr = 32'hxxxx_xxxx;
end
 
cyc=0;
 
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
 
wr_cnt = wr_cnt + wcount;
end
endtask
 
 
 
 
task wb_wmr;
input [31:0] a;
input [3:0] s;
input delay;
input rcount;
input wcount;
 
integer delay;
integer rcount;
integer wcount;
integer n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 1'bx;
sel = 4'hx;
sel = s;
 
for(n=0;n<wcount;n=n+1)
begin
repeat(delay)
begin
@(posedge clk);
#1;
end
adr = a + (n*4);
dout = wr_mem[n + wr_cnt];
stb = 1;
we=1;
sel = s;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
#2;
stb=0;
we=1'bx;
sel = 4'hx;
dout = 32'hxxxx_xxxx;
adr = 32'hxxxx_xxxx;
end
 
wr_cnt = wr_cnt + wcount;
stb=0;
repeat(delay) @(posedge clk);
#1;
 
sel = s;
we = 0;
for(n=0;n<rcount-1;n=n+1)
begin
adr = a + (n*4);
stb = 1;
while(~ack & ~err) @(posedge clk);
rd_mem[n + rd_cnt] = din;
//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
repeat(delay)
begin
@(posedge clk);
#1;
end
we = 0;
sel = s;
end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
rd_mem[n + rd_cnt] = din;
rd_cnt = rd_cnt + rcount;
//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
#1;
 
cyc = 0;
stb = 0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
 
end
endtask
 
 
 
 
////////////////////////////////////////////////////////////////////
//
// Read 1 Word Task
248,7 → 515,7
sel = s;
 
//@(posedge clk);
while(~ack) @(posedge clk);
while(~ack & ~err) @(posedge clk);
d = din;
#1;
cyc=0;
291,7 → 558,7
 
adr = a;
stb = 1;
while(~ack) @(posedge clk);
while(~ack & ~err) @(posedge clk);
d1 = din;
#2;
stb=0;
308,7 → 575,7
adr = a+4;
stb = 1;
@(posedge clk);
while(~ack) @(posedge clk);
while(~ack & ~err) @(posedge clk);
d2 = din;
#2;
stb=0;
326,7 → 593,7
adr = a+8;
stb = 1;
@(posedge clk);
while(~ack) @(posedge clk);
while(~ack & ~err) @(posedge clk);
d3 = din;
#2;
stb=0;
343,7 → 610,7
adr = a+12;
stb = 1;
@(posedge clk);
while(~ack) @(posedge clk);
while(~ack & ~err) @(posedge clk);
d4 = din;
#1;
stb=0;
355,4 → 622,61
endtask
 
 
 
task wb_rd_mult;
input [31:0] a;
input [3:0] s;
input delay;
input count;
 
integer delay;
integer count;
integer n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay) @(posedge clk);
 
for(n=0;n<count-1;n=n+1)
begin
adr = a + (n*4);
stb = 1;
while(~ack & ~err) @(posedge clk);
rd_mem[n + rd_cnt] = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
repeat(delay)
begin
@(posedge clk);
#1;
end
we = 0;
sel = s;
end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
rd_mem[n + rd_cnt] = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hffff_ffff;
adr = 32'hxxxx_xxxx;
 
rd_cnt = rd_cnt + count;
end
endtask
 
endmodule
/trunk/bench/verilog/test_bench_top.v
37,10 → 37,10
 
// CVS Log
//
// $Id: test_bench_top.v,v 1.2 2001-08-15 05:40:29 rudi Exp $
// $Id: test_bench_top.v,v 1.3 2001-09-07 15:34:36 rudi Exp $
//
// $Date: 2001-08-15 05:40:29 $
// $Revision: 1.2 $
// $Date: 2001-09-07 15:34:36 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,12
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/08/15 05:40:29 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Added Section 3.10, describing DMA restart.
//
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
135,7 → 141,7
 
 
`define MEM 32'h0002_0000
`define REG_BASE 32'hff00_0000
`define REG_BASE 32'hb000_0000
 
`define COR 8'h0
`define INT_MASKA 8'h4
199,17 → 205,21
ack_cnt_clr = 0;
error_cnt = 0;
clk = 0;
rst = 0;
rst = 1;
rest_i = 0;
 
repeat(10) @(posedge clk);
rst = 1;
rst = 0;
repeat(10) @(posedge clk);
 
// HERE IS WHERE THE TEST CASES GO ...
 
if(1) // Full Regression Run
if(0) // Full Regression Run
begin
$display(" ......................................................");
$display(" : :");
$display(" : Long Regression Run ... :");
$display(" :....................................................:");
pt10_rd;
pt01_wr;
pt01_rd;
226,6 → 236,10
else
if(1) // Quick Regression Run
begin
$display(" ......................................................");
$display(" : :");
$display(" : Short Regression Run ... :");
$display(" :....................................................:");
pt10_rd;
pt01_wr;
pt01_rd;
245,8 → 259,9
//
// TEST DEVELOPMENT AREA
//
sw_dma1(3);
 
arb_test1;
//arb_test1;
 
repeat(100) @(posedge clk);
 
348,7 → 363,7
 
wb_slv #(14) s0(
.clk( clk ),
.rst( rst ),
.rst( ~rst ),
.adr( wb0_addr_o ),
.din( wb0s_data_o ),
.dout( wb0s_data_i ),
363,7 → 378,7
 
wb_slv #(14) s1(
.clk( clk ),
.rst( rst ),
.rst( ~rst ),
.adr( wb1_addr_o ),
.din( wb1s_data_o ),
.dout( wb1s_data_i ),
378,7 → 393,7
 
wb_mast m0(
.clk( clk ),
.rst( rst ),
.rst( ~rst ),
.adr( wb0_addr_i ),
.din( wb0m_data_o ),
.dout( wb0m_data_i ),
393,7 → 408,7
 
wb_mast m1(
.clk( clk ),
.rst( rst ),
.rst( ~rst ),
.adr( wb1_addr_i ),
.din( wb1m_data_o ),
.dout( wb1m_data_i ),
/trunk/bench/verilog/tests.v
37,10 → 37,10
 
// CVS Log
//
// $Id: tests.v,v 1.2 2001-08-15 05:40:29 rudi Exp $
// $Id: tests.v,v 1.3 2001-09-07 15:34:36 rudi Exp $
//
// $Date: 2001-08-15 05:40:29 $
// $Revision: 1.2 $
// $Date: 2001-09-07 15:34:36 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,12
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/08/15 05:40:29 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Added Section 3.10, describing DMA restart.
//
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
76,10 → 82,10
$display("*** SW DMA No Buffer Ext. Descr LL ... ***");
$display("*****************************************************\n");
 
rst = 1;
repeat(10) @(posedge clk);
rst = 0;
repeat(10) @(posedge clk);
rst = 1;
repeat(10) @(posedge clk);
 
if(quick)
begin
/trunk/rtl/verilog/wb_dma_top.v
37,10 → 37,10
 
// CVS Log
//
// $Id: wb_dma_top.v,v 1.2 2001-08-15 05:40:30 rudi Exp $
// $Id: wb_dma_top.v,v 1.3 2001-09-07 15:34:38 rudi Exp $
//
// $Date: 2001-08-15 05:40:30 $
// $Revision: 1.2 $
// $Date: 2001-09-07 15:34:38 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,12
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/08/15 05:40:30 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Added Section 3.10, describing DMA restart.
//
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
300,7 → 306,7
 
wb_dma_rf u0(
.clk( clk_i ),
.rst( rst_i ),
.rst( ~rst_i ),
.wb_rf_adr( slv0_adr[9:2] ),
.wb_rf_din( slv0_dout ),
.wb_rf_dout( slv0_din ),
581,7 → 587,7
// Channel Select
wb_dma_ch_sel u1(
.clk( clk_i ),
.rst( rst_i ),
.rst( ~rst_i ),
.req_i( dma_req ),
.ack_o( dma_ack ),
.nd_i( dma_nd ),
856,7 → 862,7
// DMA Engine
wb_dma_de u2(
.clk( clk_i ),
.rst( rst_i ),
.rst( ~rst_i ),
.mast0_go( mast0_go ),
.mast0_we( mast0_we ),
.mast0_adr( mast0_adr ),
907,7 → 913,7
// Wishbone Interface 0
wb_dma_wb_if u3(
.clk( clk_i ),
.rst( rst_i ),
.rst( ~rst_i ),
.wbs_data_i( wb0s_data_i ),
.wbs_data_o( wb0s_data_o ),
.wb_addr_i( wb0_addr_i ),
952,7 → 958,7
// Wishbone Interface 1
wb_dma_wb_if u4(
.clk( clk_i ),
.rst( rst_i ),
.rst( ~rst_i ),
.wbs_data_i( wb1s_data_i ),
.wbs_data_o( wb1s_data_o ),
.wb_addr_i( wb1_addr_i ),
/trunk/rtl/verilog/wb_dma_defines.v
37,10 → 37,10
 
// CVS Log
//
// $Id: wb_dma_defines.v,v 1.2 2001-08-15 05:40:30 rudi Exp $
// $Id: wb_dma_defines.v,v 1.3 2001-09-07 15:34:38 rudi Exp $
//
// $Date: 2001-08-15 05:40:30 $
// $Revision: 1.2 $
// $Date: 2001-09-07 15:34:38 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,12
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/08/15 05:40:30 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Added Section 3.10, describing DMA restart.
//
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
223,7 → 229,8
// the higher will be the initial delay when pass-through mode is selected.
// Here we look at the top 8 address bit. If they are all 1, the
// register file is selected. Use this with caution !!!
`define WDMA_REG_SEL (wb_addr_i[31:24] == 8'hff)
//`define WDMA_REG_SEL (wb_addr_i[31:24] == 8'hff)
`define WDMA_REG_SEL (wb_addr_i[31:28] == 4'hb)
 
 
// CSR Bits
/trunk/sim/rtl_sim/bin/Makefile
43,6 → 43,8
INCDIR="-INCDIR ./$(DUT_SRC_DIR)/ -INCDIR ./$(TB_SRC_DIR)/"
LOGF=-LOGFILE .nclog
NCCOMMON=-CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var -NOCOPYRIGHT
UMC_LIB=/tools/dc_libraries/virtual_silicon/umc_lib.v
GATE_NETLIST = ../../../syn/out/wb_dma_top_ps.v
 
##########################################################################
#
77,6 → 79,26
@$(MAKE) $(MS) ncsim TOP=$(_TOP_)
@echo ""
 
gatew:
@$(MAKE) -s gate ACCESS="-ACCESS +r " WAVES="-DEFINE WAVES"
 
gate:
@echo ""
@echo "----- Running NCVLOG ... ----------"
@$(MAKE) $(MS) vlog \
TARGETS="$(UMC_LIB) $(GATE_NETLIST)" \
TB="$(_TB_)" \
INCDIR=$(INCDIR) \
WAVES="$(WAVES)"
@echo ""
@echo "----- Running NCELAB ... ----------"
@$(MAKE) $(MS) elab \
ACCESS="$(ACCESS)" TOP=$(_TOP_)
@echo ""
@echo "----- Running NCSIM ... ----------"
@$(MAKE) $(MS) ncsim TOP=$(_TOP_)
@echo ""
 
hal:
@echo ""
@echo "----- Running HAL ... ----------"
/trunk/syn/bin/comp.dc
63,14 → 63,14
 
echo "+++++++++ Setting up Clocks ..." >> $log_file
 
set_drive 0 [find port {*clk}]
set_drive 0 [find port {clk_i}]
# !!! WISHBONE Clock !!!
set clock_period 5
create_clock -period $clock_period clk
set_clock_skew -uncertainty 0.1 clk
set_clock_transition 0.5 clk
set_dont_touch_network clk
create_clock -period $clock_period clk_i
set_clock_skew -uncertainty 0.2 clk_i
set_clock_transition 0.2 clk_i
set_dont_touch_network clk_i
# !!! Reset !!!
set_drive 0 [find port {rst*}]
86,12 → 86,13
set_driving_cell -cell NAND2D2 -pin Z [all_inputs] >> $junk_file
set_load 0.2 [all_outputs]
 
set_input_delay -max 1 -clock clk [all_inputs]
set_output_delay -max 1 -clock clk [all_outputs]
set_input_delay 2.0 -clock clk_i [all_inputs]
set_output_delay 2.0 -clock clk_i [all_outputs]
 
# ==============================================
# Setup Area Constrains
set_max_area 0.0
set compile_sequential_area_recovery true
 
# ==============================================
# Force Ultra
101,17 → 102,15
# Compile Design
 
echo "+++++++++ Starting Compile ..." >> $log_file
#compile -map_effort medium -area_effort medium -ungroup_all >> $log_file
compile -map_effort low -area_effort low >> $log_file
#compile -map_effort high -area_effort high -ungroup_all >> $log_file
#compile -map_effort high -area_effort high -auto_ungroup >> $log_file
#compile -map_effort low -area_effort low >> $log_file
compile -map_effort high -area_effort high -boundary_optimization -auto_ungroup >> $log_file
 
# ==============================================
# Write Out the optimized design
 
echo "+++++++++ Saving Optimized Design ..." >> $log_file
write_file -format verilog -output $post_syn_verilog_file
write_file -hierarchy -format db -output $post_comp_db_file
write_file -hierarchy -format verilog -output $post_syn_verilog_file
write_file -hierarchy -format db -output $post_comp_db_file
 
# ==============================================
# Create Some Basic Reports
/trunk/syn/bin/lib_spec.dc
15,7 → 15,7
# Setup Libraries
 
set search_path [list $search_path . \
/tools/dc_libraries/umc/umc_0.18/UMCL18U250D2_2.1/design_compiler/ \
/tools/dc_libraries/virtual_silicon/UMCL18U250D2_2.2/design_compiler/ \
$hdl_src_dir]
 
set snps [getenv "SYNOPSYS"]

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