OpenCores
URL https://opencores.org/ocsvn/zet86/zet86/trunk

Subversion Repositories zet86

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 8 to Rev 9
    ↔ Reverse comparison
  •

Rev 8 → Rev 9

/trunk/impl/virtex4-ml403ep/rtl/mem_ctrl.v File deleted \ No newline at end of file
/trunk/impl/virtex4-ml403ep/memory/clock.v
0,0 → 1,40
module clock (
input sys_clk_in_,
output clk,
output clk_100M,
output vdu_clk,
output rst
);
 
// Register declarations
reg [6:0] count;
reg [2:0] clock;
 
// Net declarations
wire lock;
wire clk_60M;
wire clk_7M;
 
// Module instantiations
clocks c0 (
.CLKIN_IN (sys_clk_in_),
.CLKDV_OUT (vdu_clk),
.CLK0_OUT (clk_100M),
.CLKFX_OUT (clk_60M),
.LOCKED_OUT (lock)
);
 
// Continuous assignments
assign rst = (count!=7'h7f);
assign clk_7M = clock[2];
assign clk = clk_7M;
 
// Behavioral description
// count
always @(posedge clk_60M)
if (!lock) count <= 7'b0;
else count <= (count==7'h7f || clock!=3'b111) ? count : (count + 7'h1);
 
// clock
always @(posedge clk_60M) clock <= clock + 3'd1;
endmodule
/trunk/impl/virtex4-ml403ep/memory/mem_map.v
0,0 → 1,88
`timescale 1ns/10ps
 
module mem_map (
// Wishbone signals
input clk_i,
input rst_i,
input [19:0] adr_i,
input [15:0] dat_i,
output [15:0] dat_o,
input we_i,
output ack_o,
input stb_i,
input byte_i,
 
// Pad signals - Flash / SRAM
output sram_clk_,
output [20:0] sram_flash_addr_,
inout [15:0] sram_flash_data_,
output sram_flash_oe_n_,
output sram_flash_we_n_,
output [ 3:0] sram_bw_,
output sram_cen_,
output flash_ce2_,
 
// VGA pad signals
input vdu_clk, // 25MHz VDU clock
output vga_red_o,
output vga_green_o,
output vga_blue_o,
output horiz_sync,
output vert_sync
);
 
// Net declarations
wire [15:0] dat_mem_o, dat_vdu_o;
wire ack_mem_o, ack_vdu_o;
wire stb_mem_i, stb_vdu_i;
 
// Module instantiations
mem_ctrl mem_ctrl0 (
.clk_i (clk_i),
.rst_i (rst_i),
.adr_i (adr_i),
.dat_i (dat_i),
.dat_o (dat_mem_o),
.we_i (we_i),
.ack_o (ack_mem_o),
.stb_i (stb_mem_i),
.byte_i (byte_i),
 
// Pad signals - Flash / SRAM
.sram_clk_ (sram_clk_),
.sram_flash_addr_ (sram_flash_addr_),
.sram_flash_data_ (sram_flash_data_),
.sram_flash_oe_n_ (sram_flash_oe_n_),
.sram_flash_we_n_ (sram_flash_we_n_),
.sram_bw_ (sram_bw_),
.sram_cen_ (sram_cen_),
.flash_ce2_ (flash_ce2_)
);
 
vdu vdu0 (
// Wishbone signals
.clk_i (clk_i),
.rst_i (rst_i),
.stb_i (stb_vdu_i),
.we_i (we_i),
.adr_i (adr_i[11:0]),
.dat_i (dat_i),
.dat_o (dat_vdu_o),
.ack_o (ack_vdu_o),
.byte_i (byte_i),
 
// VGA pad signals
.vdu_clk (vdu_clk),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (vert_sync)
);
 
// Continuous assignments
assign stb_vdu_i = (adr_i[19:13]==7'b1011_100) & stb_i;
assign stb_mem_i = (adr_i[19:13]!=7'b1011_100) & stb_i;
assign ack_o = stb_vdu_i ? ack_vdu_o : ack_mem_o;
assign dat_o = stb_vdu_i ? dat_vdu_o : dat_mem_o;
endmodule
/trunk/impl/virtex4-ml403ep/memory/ml403-with-tft.ucf
0,0 → 1,104
NET sys_clk_in_ TNM_NET = "sys_clk_in_";
TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in_" 9.9 ns HIGH 50 %;
 
NET sys_clk_in_ LOC = AE14;
NET sys_clk_in_ IOSTANDARD = LVCMOS33;
 
#NET trx LOC = W1;
NET sram_clk_ LOC = AF7 ;
 
#NET sram_flash_addr_[24] LOC = T21;
#NET sram_flash_addr_[23] LOC = U20;
#NET sram_flash_addr_[22] LOC = T19;
NET sram_flash_addr_[20] LOC = AC5;
NET sram_flash_addr_[19] LOC = AB5;
NET sram_flash_addr_[18] LOC = AC4;
NET sram_flash_addr_[17] LOC = AB4;
NET sram_flash_addr_[16] LOC = AB3;
NET sram_flash_addr_[15] LOC = AA4;
NET sram_flash_addr_[14] LOC = AA3;
NET sram_flash_addr_[13] LOC = W5;
NET sram_flash_addr_[12] LOC = W6;
NET sram_flash_addr_[11] LOC = W3;
NET sram_flash_addr_[10] LOC = AF3;
NET sram_flash_addr_[9] LOC = AE3;
NET sram_flash_addr_[8] LOC = AD2;
NET sram_flash_addr_[7] LOC = AD1;
NET sram_flash_addr_[6] LOC = AC2;
NET sram_flash_addr_[5] LOC = AC1;
NET sram_flash_addr_[4] LOC = AB2;
NET sram_flash_addr_[3] LOC = AB1;
NET sram_flash_addr_[2] LOC = AA1;
NET sram_flash_addr_[1] LOC = Y2;
NET sram_flash_addr_[0] LOC = Y1;
#NET sram_flash_addr_[0] LOC = T20;
 
NET sram_flash_data_[15] LOC = AA14;
NET sram_flash_data_[14] LOC = AB14;
NET sram_flash_data_[13] LOC = AC12;
NET sram_flash_data_[12] LOC = AC11;
NET sram_flash_data_[11] LOC = AA16;
NET sram_flash_data_[10] LOC = AA15;
NET sram_flash_data_[9] LOC = AB13;
NET sram_flash_data_[8] LOC = AA13;
NET sram_flash_data_[7] LOC = AC14;
NET sram_flash_data_[6] LOC = AD14;
NET sram_flash_data_[5] LOC = AA12;
NET sram_flash_data_[4] LOC = AA11;
NET sram_flash_data_[3] LOC = AC16;
NET sram_flash_data_[2] LOC = AC15;
NET sram_flash_data_[1] LOC = AC13;
NET sram_flash_data_[0] LOC = AD13;
 
NET sram_flash_oe_n_ LOC = AC6;
NET sram_flash_we_n_ LOC = AB6;
 
NET sram_bw_[3] LOC = Y3; #Y4;
NET sram_bw_[2] LOC = Y4; #Y3;
NET sram_bw_[1] LOC = Y5; #Y6;
NET sram_bw_[0] LOC = Y6; #Y5;
 
NET sram_cen_ LOC = V7;
 
NET flash_ce2_ LOC = W7;
 
#NET flash_byte_n LOC = N22;
#NET flash_audio_reset_n LOC = AD10;
 
NET tft_lcd_clk_ LOC = AF8;
NET tft_lcd_r_ LOC = E6; # VGA_R7
NET tft_lcd_g_ LOC = C1; # VGA_G7
NET tft_lcd_b_ LOC = F8; # VGA_B7
NET tft_lcd_hsync_ LOC = C10;
NET tft_lcd_vsync_ LOC = A8;
 
NET tft_lcd_clk_ SLEW = FAST;
NET tft_lcd_clk_ DRIVE = 8;
 
NET tft_lcd_r_ SLEW = FAST;
NET tft_lcd_r_ DRIVE = 8;
 
NET tft_lcd_g_ SLEW = FAST;
NET tft_lcd_g_ DRIVE = 8;
 
NET tft_lcd_b_ SLEW = FAST;
NET tft_lcd_b_ DRIVE = 8;
 
NET tft_lcd_hsync_ SLEW = FAST;
NET tft_lcd_hsync_ DRIVE = 8;
 
NET tft_lcd_vsync_ SLEW = FAST;
NET tft_lcd_vsync_ DRIVE = 8;
 
 
#NET leds_[0] LOC = G5; #GPLED0
#NET leds_[1] LOC = G6; #GPLED1
#NET leds_[2] LOC = A11; #GPLED2
#NET leds_[3] LOC = A12; #GPLED3
 
# North-East-South-West-Center LEDs
#NET leds_[4] LOC = C6; # C LED
#NET leds_[5] LOC = F9; # W LED
#NET leds_[6] LOC = A5; # S LED
#NET leds_[7] LOC = E10; # E LED
#NET leds_[8] LOC = E2; # N LED
/trunk/impl/virtex4-ml403ep/memory/mem_cntrlr_test.v
0,0 → 1,325
//
// Memory controller test. It testes all kind of memory accesses in
// different RAM / ROM areas. RAM contents at the end:
//
// Mem[01:00] = xx34
// Mem[03:02] = 1234
// Mem[05:04] = Mem[09:08]
// Mem[07:06] = 0a0b
// Mem[0d:0c] = 12xx
// Mem[0f:0e] = xxMem[08]
// Mem[11:10] = ff83
// Mem[13:12] = 0034
// Mem[15:14] = 0062
// Mem[17:16] = ext(Mem[09])
// Mem[19:18] = Mem[09]xx
// Mem[1b:1a] = 0b06
// Mem[1d:1c] = Mem[08]12
//
 
module mem_cntrlr_test (
input sys_clk_in_,
 
output sram_clk_,
output [20:0] sram_flash_addr_,
inout [15:0] sram_flash_data_,
output sram_flash_oe_n_,
output sram_flash_we_n_,
output [ 3:0] sram_bw_,
output sram_cen_,
output flash_ce2_,
 
output [ 8:0] leds_
);
 
// Net declarations
wire rst;
wire clk;
wire [15:0] dada_ent;
wire ack;
 
// Register declarations
reg [ 7:0] estat;
reg [15:0] dada_sor;
reg [15:0] dada1;
reg [15:0] dada2;
reg [19:0] adr;
reg we;
reg stb;
reg byte_o;
 
// Module instantiations
clock c0 (
.sys_clk_in_ (sys_clk_in_),
.clk (clk),
.rst (rst)
);
 
mem_ctrl mem_ctrl0 (
// Wishbone signals
.clk_i (clk),
.rst_i (rst),
.adr_i (adr),
.dat_i (dada_sor),
.dat_o (dada_ent),
.we_i (we),
.ack_o (ack),
.stb_i (stb),
.byte_i (byte_o),
 
// Pad signals
.sram_clk_ (sram_clk_),
.sram_flash_addr_ (sram_flash_addr_),
.sram_flash_data_ (sram_flash_data_),
.sram_flash_oe_n_ (sram_flash_oe_n_),
.sram_flash_we_n_ (sram_flash_we_n_),
.sram_bw_ (sram_bw_),
.sram_cen_ (sram_cen_),
.flash_ce2_ (flash_ce2_)
);
 
assign leds_[7:0] = estat;
 
// Behavioral description
always @(posedge clk)
if (rst)
begin // ROM word read (dada1 = 1234)
estat <= 8'h10;
dada_sor <= 16'd0;
dada1 <= 16'h1234;
dada2 <= 16'h6789;
adr <= 21'hc0002;
we <= 1'd0;
stb <= 1'd0;
byte_o <= 1'd0;
end
else
case (estat)
8'h10:
begin // ROM word read (dada2 = 0a0b)
estat <= 8'h20;
dada_sor <= dada_sor;
dada1 <= dada1;
dada2 <= dada2;
adr <= 20'hc0004;
we <= 1'd0;
stb <= 1'd1;
byte_o <= 1'd0;
end
8'h20:
if (ack) begin // RAM word read (@4)
estat <= 8'h30;
dada_sor <= dada_sor;
dada1 <= dada1;
dada2 <= dada_ent;
adr <= 20'h8;
we <= 1'd0;
stb <= 1'd1;
byte_o <= 1'd0;
end
8'h30:
if (ack) begin // RAM write (@2 = @4)
estat <= 8'h40;
dada_sor <= dada_ent;
dada1 <= dada1;
dada2 <= dada2;
adr <= 20'h4;
we <= 1'd1;
stb <= 1'd1;
byte_o <= 1'd0;
end
8'h40:
if (ack) begin // RAM write (@3 = 0a0b)
estat <= 8'h50;
dada_sor <= dada2;
dada1 <= dada1;
dada2 <= dada2;
adr <= 20'h6;
we <= 1'd1;
stb <= 1'd1;
byte_o <= 1'd0;
end
8'h50:
if (ack) begin // RAM write (@1 = 1234)
estat <= 8'h60;
dada_sor <= dada1;
dada1 <= dada1;
dada2 <= dada2;
adr <= 20'h2;
we <= 1'd1;
stb <= 1'd1;
byte_o <= 1'd0;
end
8'h60:
if (ack) begin // ROM read byte (83)
estat <= 8'h62;
dada_sor <= dada_sor;
dada1 <= dada1;
dada2 <= dada2;
adr <= 20'hc0040;
we <= 1'd0;
stb <= 1'd1;
byte_o <= 1'd1;
end
8'h62:
if (ack) begin // RAM word write (@8 = ff83)
estat <= 8'h65;
dada_sor <= dada_ent;
dada1 <= dada1;
dada2 <= dada2;
adr <= 20'h10;
we <= 1'd1;
stb <= 1'd1;
byte_o <= 1'd0;
end
8'h65:
if (ack) begin // RAM byte read (07)
estat <= 8'h70;
dada_sor <= dada_sor;
dada1 <= dada1;
dada2 <= dada2;
adr <= 20'h2;
we <= 1'd0;
stb <= 1'd1;
byte_o <= 1'd1;
end
8'h70:
if (ack) begin // RAM word write (@9 = 0034)
estat <= 8'h75;
dada_sor <= dada_ent;
dada1 <= dada1;
dada2 <= dada2;
adr <= 20'h12;
we <= 1'd1;
stb <= 1'd1;
byte_o <= 1'd0;
end
8'h75:
if (ack) begin // RAM byte write (@0 = 34)
estat <= 8'h80;
dada_sor <= dada_sor;
dada1 <= dada1;
dada2 <= dada2;
adr <= 20'h0;
we <= 1'd1;
stb <= 1'd1;
byte_o <= 1'd1;
end
8'h80:
if (ack) begin // ROM read byte odd (62)
estat <= 8'h90;
dada_sor <= dada_sor;
dada1 <= dada1;
dada2 <= dada2;
adr <= 20'hc0031;
we <= 1'd0;
stb <= 1'd1;
byte_o <= 1'd1;
end
8'h90:
if (ack) begin // RAM word write (@10 = 0062)
estat <= 8'h95;
dada_sor <= dada_ent;
dada1 <= dada1;
dada2 <= dada2;
adr <= 20'h14;
we <= 1'd1;
stb <= 1'd1;
byte_o <= 1'd0;
end
8'h95:
if (ack) begin // RAM byte read odd (8c)
estat <= 8'ha0;
dada_sor <= dada_sor;
dada1 <= dada1;
dada2 <= dada2;
adr <= 20'h9;
we <= 1'd0;
stb <= 1'd1;
byte_o <= 1'd1;
end
8'ha0:
if (ack) begin // RAM word write (@11 = ff8c)
estat <= 8'hb0;
dada_sor <= dada_ent;
dada1 <= dada1;
dada2 <= dada2;
adr <= 20'h16;
we <= 1'd1;
stb <= 1'd1;
byte_o <= 1'd0;
end
8'hb0:
if (ack) begin // RAM byte write odd (@12 = 8cxx)
estat <= 8'hc0;
dada_sor <= dada_sor;
dada1 <= dada1;
dada2 <= dada2;
adr <= 20'h19;
we <= 1'd1;
stb <= 1'd1;
byte_o <= 1'd1;
end
8'hc0:
if (ack) begin // ROM word read odd (0b06)
estat <= 8'hd0;
dada_sor <= dada_sor;
dada1 <= dada1;
dada2 <= dada2;
adr <= 20'hc0003;
we <= 1'd0;
stb <= 1'd1;
byte_o <= 1'd0;
end
8'hd0:
if (ack) begin // RAM word write (@13 = 0b06)
estat <= 8'he0;
dada_sor <= dada_ent;
dada1 <= dada1;
dada2 <= dada2;
adr <= 20'h1a;
we <= 1'd1;
stb <= 1'd1;
byte_o <= 1'd0;
end
8'he0:
if (ack) begin // RAM word read (odd)
estat <= 8'he7;
dada_sor <= dada_sor;
dada1 <= dada1;
dada2 <= dada2;
adr <= 20'h3;
we <= 1'd0;
stb <= 1'd1;
byte_o <= 1'd0;
end
8'he7:
if (ack) begin // RAM word write (even)
estat <= 8'he9;
dada_sor <= dada_ent;
dada1 <= dada_ent;
dada2 <= dada2;
adr <= 20'h1c;
we <= 1'd1;
stb <= 1'd1;
byte_o <= 1'd0;
end
8'he9:
if (ack) begin // RAM word write (odd)
estat <= 8'hf0;
dada_sor <= dada1;
dada1 <= dada1;
dada2 <= dada2;
adr <= 20'd13;
we <= 1'd1;
stb <= 1'd1;
byte_o <= 1'd0;
end
8'hf0:
if (ack) begin
estat <= 8'hf5;
we <= 1'b0;
stb <= 1'b0;
end
endcase
endmodule
/trunk/impl/virtex4-ml403ep/memory/mem_ctrl.v
0,0 → 1,93
`timescale 1ns/10ps
 
module mem_ctrl (
// Wishbone signals
input clk_i,
input rst_i,
input [19:0] adr_i,
input [15:0] dat_i,
output [15:0] dat_o,
input we_i,
output ack_o,
input stb_i,
input byte_i,
 
// Pad signals
output sram_clk_,
output [20:0] sram_flash_addr_,
inout [15:0] sram_flash_data_,
output sram_flash_oe_n_,
output sram_flash_we_n_,
output [ 3:0] sram_bw_,
output sram_cen_,
output flash_ce2_
);
 
// Net declarations
wire rom_area;
wire [ 5:0] high_flash;
wire [ 5:0] high_addr;
wire [ 1:0] be; // byte enable
wire a0; // address 0 bit
wire [15:0] wr; // word from memory read
wire [15:0] ww; // word to memory write
wire [15:0] bhr; // byte high read, sign extended
wire [15:0] blr; // byte low read, sign extended
wire [19:0] adr_1; // next address
wire odd_word; // Word odd operation
wire [19:0] adr; // address
wire next_cnd; // Next byte condition
 
// Register declarations
reg [1:0] cnt;
reg next;
reg [7:0] bhr_l;
 
// Continous assignments
assign sram_clk_ = clk_i;
assign sram_flash_addr_ = { high_addr, adr[15:1] };
assign sram_flash_we_n_ = cnt != 2'b00 | !stb_i | !we_i | rom_area;
assign sram_flash_oe_n_ = !rom_area & we_i;
assign sram_bw_ = { 2'b11, be };
assign sram_cen_ = rom_area | !stb_i;
assign flash_ce2_ = rom_area & stb_i;
 
assign sram_flash_data_ = we_i ? ww : 16'hzzzz;
 
assign rom_area = (adr[19:16]==4'hc || adr[19:16]==4'hf);
assign high_flash = { 5'b0, adr[17] };
assign high_addr = rom_area ? high_flash : { 2'b0, adr[19:16] };
assign be = byte_i ? (a0 ? 2'b01 : 2'b10)
: (a0 ? (next ? 2'b10 : 2'b01) : 2'b00);
assign a0 = adr_i[0];
assign wr = sram_flash_data_;
assign bhr = { {8{wr[15]}}, wr[15:8] };
assign blr = { {8{wr[7]}}, wr[7:0] };
assign ww = a0 ? { dat_i[7:0], dat_i[15:8] } : dat_i;
 
assign adr_1 = adr_i + 20'd1;
assign odd_word = a0 & !byte_i;
assign adr = (next && stb_i && odd_word) ? adr_1 : adr_i;
assign ack_o = stb_i & (rom_area ? (!odd_word | next)
: (cnt==2'b10 & (!odd_word | next)));
assign dat_o = byte_i ? (a0 ? bhr : blr)
: (a0 ? { wr[7:0], bhr_l } : wr);
assign next_cnd = stb_i & odd_word &
(next ? (rom_area ? 1'b0 : (cnt==2'b10 ? 1'b0 : 1'b1 ))
: (rom_area ? 1'b1 : (cnt==2'b10 ? 1'b1 : 1'b0)));
 
// Behavioral description
// cnt
always @(posedge clk_i)
if (rst_i) cnt <= 2'd0;
else cnt <= (stb_i && !rom_area) ?
((cnt==2'b10) ? 2'd0 : cnt + 2'b1) : 2'd0;
 
// next
always @(posedge clk_i)
if (rst_i) next <= 1'b0;
else next <= next_cnd;
 
// bhr_l
always @(posedge clk_i) bhr_l <= next_cnd ? wr[15:8] : bhr_l;
endmodule
/trunk/impl/virtex4-ml403ep/memory/ml403.ucf
0,0 → 1,79
NET sys_clk_in_ TNM_NET = "sys_clk_in_";
TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in_" 9.9 ns HIGH 50 %;
 
NET sys_clk_in_ LOC = AE14;
NET sys_clk_in_ IOSTANDARD = LVCMOS33;
 
#NET trx LOC = W1;
NET sram_clk_ LOC = AF7 ;
 
#NET sram_flash_addr_[24] LOC = T21;
#NET sram_flash_addr_[23] LOC = U20;
#NET sram_flash_addr_[22] LOC = T19;
NET sram_flash_addr_[20] LOC = AC5;
NET sram_flash_addr_[19] LOC = AB5;
NET sram_flash_addr_[18] LOC = AC4;
NET sram_flash_addr_[17] LOC = AB4;
NET sram_flash_addr_[16] LOC = AB3;
NET sram_flash_addr_[15] LOC = AA4;
NET sram_flash_addr_[14] LOC = AA3;
NET sram_flash_addr_[13] LOC = W5;
NET sram_flash_addr_[12] LOC = W6;
NET sram_flash_addr_[11] LOC = W3;
NET sram_flash_addr_[10] LOC = AF3;
NET sram_flash_addr_[9] LOC = AE3;
NET sram_flash_addr_[8] LOC = AD2;
NET sram_flash_addr_[7] LOC = AD1;
NET sram_flash_addr_[6] LOC = AC2;
NET sram_flash_addr_[5] LOC = AC1;
NET sram_flash_addr_[4] LOC = AB2;
NET sram_flash_addr_[3] LOC = AB1;
NET sram_flash_addr_[2] LOC = AA1;
NET sram_flash_addr_[1] LOC = Y2;
NET sram_flash_addr_[0] LOC = Y1;
#NET sram_flash_addr_[0] LOC = T20;
 
NET sram_flash_data_[15] LOC = AA14;
NET sram_flash_data_[14] LOC = AB14;
NET sram_flash_data_[13] LOC = AC12;
NET sram_flash_data_[12] LOC = AC11;
NET sram_flash_data_[11] LOC = AA16;
NET sram_flash_data_[10] LOC = AA15;
NET sram_flash_data_[9] LOC = AB13;
NET sram_flash_data_[8] LOC = AA13;
NET sram_flash_data_[7] LOC = AC14;
NET sram_flash_data_[6] LOC = AD14;
NET sram_flash_data_[5] LOC = AA12;
NET sram_flash_data_[4] LOC = AA11;
NET sram_flash_data_[3] LOC = AC16;
NET sram_flash_data_[2] LOC = AC15;
NET sram_flash_data_[1] LOC = AC13;
NET sram_flash_data_[0] LOC = AD13;
 
NET sram_flash_oe_n_ LOC = AC6;
NET sram_flash_we_n_ LOC = AB6;
 
NET sram_bw_[3] LOC = Y3; #Y4;
NET sram_bw_[2] LOC = Y4; #Y3;
NET sram_bw_[1] LOC = Y5; #Y6;
NET sram_bw_[0] LOC = Y6; #Y5;
 
NET sram_cen_ LOC = V7;
 
NET flash_ce2_ LOC = W7;
 
#NET flash_byte_n LOC = N22;
#NET flash_audio_reset_n LOC = AD10;
 
 
#NET leds_[0] LOC = G5; #GPLED0
#NET leds_[1] LOC = G6; #GPLED1
#NET leds_[2] LOC = A11; #GPLED2
#NET leds_[3] LOC = A12; #GPLED3
 
# North-East-South-West-Center LEDs
#NET leds_[4] LOC = C6; # C LED
#NET leds_[5] LOC = F9; # W LED
#NET leds_[6] LOC = A5; # S LED
#NET leds_[7] LOC = E10; # E LED
#NET leds_[8] LOC = E2; # N LED
/trunk/impl/virtex4-ml403ep/memory/clocks.xaw
0,0 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.4e
$8ax77=(`fgn#wkzs.reg*vugox#ugcioz,p`usW|kyx"!llnahw+~f81;96>!0016?5(5:;;0=;5>0/2341=68';87<>?8:35#m@7N980=U?430977>2)081>;6O]CIUJ^41<I[]QSB@CY^ABWFGCAGMTOAE>8:CQS_YHFESTOAEFN^G[P@TIIE;>7L\XZ^MMH\YDDBCES[OCUD3a?DTPRVEE@TQKCL]PSLRD@@DLSNBD119BVR\XGGFRSIJ]_B224>GU_SUDBAWPDEP\G4763HX\VRAALX]G@WYDDB;=7L\XZ^MMH\YCL[UNHJKBOEG22>GU_SUDBAWPDEP\BIOWNEE[=?5NRVX\KKJ^WMNYSD@FT058EWQ]WFDGURJKR^PFW@RSQYO:96O]W[]LJI_XNKUNTYK]N@N26>GU_SUDBAWPIOQW[KSJ9l1J^ZTPOONZ[OOS\LXT\F<_K^LLJJOTM8h0M_YU_NLO]ZLN\]OYSXGPNNLLMVC6?2KY[WQ@NM[\V@EHFOCLS]GAS078EWQ]WFDGUR\JSDV\HJANK880M_YU_NLO]ZTB\HXLIY?7;@PT^ZIIDPU]MAGK_EDP[HICMh1J_^AL_VKWLc=F_SUH@FLZFU[SA4713H]QSNBDBTDW]UC6WGENHDZ>3:CT^ZEKCVE^X][[_U[SAf=F_SUM@BY[YQG;?DQ]WYKYXi5NW[]P]KRO\FEG86L@TI68FP@@<2IGG=64CMI3[GSAm2IGG=QMUGE\MKUS02IGG=Q@UU48GIM609<0OAE=7178GIM5P11H@F<W1926?FJL19?0OAEKV89@HNBQWK_Mj6MCKET\FP@@W@DXXn5LLJFU[AOQAMO27NBDDW]LQQ3<KEAMN55LLJDA[LH23JF@JU64CMIE\4>712IGGKVPBTDe?FJLNQUIYKIPIOQWg>EKCORTHDXFDDg8GIMAPVG^@YG_LX;8GIMAPVE^X85LLJKM54=DDBCESIGYIEG\F\Y5j2IGGD@PICWEC46<KEABBRGMUGE\MKUSn2IGGD@PICWECZIR\11H@FGA_HL`?FJLAGU[I_G@Dd9@HNOIWZXHSYW_E008GIMH]]U[DL]J_RJJBQe<KEATJHKKB@AH=>EHEDC_XHJ8;BPFEQCC=2NJHI\;;EAOO2=CKDUJH[m4DBO\EAPXAGY_=>5KCL]BQQIDIECI^LZFOO37?AEJWYOYJB\BAOAF[HICM:1OICj4DDQHARYFLC_XX<<4DGQ\BWCV]LDHURC@DD08@Lg<LEFTMCJPFY31?AJKWOXN]XKACX]NKAC53ME?7I\KY078@PR^WJSH@HQLOSPFGQOHF:1O[H94D^TBHPC?3LR_I_@NL`9EEFRHZPUAJ85IAMQF=>@EWZE^^NKl;GGF@GGDCVH^J45IIO]VJLRTi2LDYYQZNHVPe>@H]]U]MA[J1:K6?LDRNN20ECZJROCO54=MA]^N^RGAPTV\P\VB>2FDMIKK6:NLGNCCi2FDOFKK_NWW7>JH_01FMUQ\PDGG7>KORk1FSL@K_E]PPW1<EV\J@XK8;OGWSJTL<2DDBH<4NR38K1=HLMX37B^_ORKWAg=W@HYNS^FFFU;8TLHOIZH^_l5_IOKPCKBBL11[ECYFDUJ;?UTNE]S[I<>4PSMS[UOIAZKHXDXJ5:RPGIM13YYOCCK;;QQFJ==W[@DHHHM<;SQWf>UNOLR_I_@NL79PMKAKMj1XXL\[UQ]TELRe3ZSEOE\@NNWP57=TQZ^NAR]VNBJQKKIR[:1_C]:4TSWF<>STMVH^JJ74URG\FP@@[<1]EHY>b:ZBSZPBZZCDB<j4XHNJJ]+_LK*;"<.\TT@#4+7'IZIBE>5WSU48\adXAm;;7Ujb_LcikwPbzzcdb<>4Xeo\Ilhhz_oydaa5:Y3>5[13R:1=8S:;Z292X2<i{}q?6jlmc9uawungg*:"=:4vifo55=k=|mt<<"11de23>zHIz?;6NOx18E>3<6sZ>o649598827702m?09m>68{o;1>4=i1:0?7)7>:9d8yV2d20=1544>3346a3<5i:nm7^8m:859=<<6;;<>i;4=ac7e?V2d20=1544>3346a3<5l<;97^8m:859=<<6;;<3n44<6bd8W1e=1>0257?<27:a=?509j1o5:4?:082V2c20=1544>3346a3<5i:2<7{Z7d;295?7=jrY?h778:8;95641=l<1>l=77:`;=?6=83?1nv*j:8:8 70=1h1/>:46b:&1<??73-2n6;5m5083>4>=83:p(:j5519'b?533-;;65;4$0096g=#9h0396*>b;68 41=?>1/=>4=b:&20?4a3-;>6?l4$0493==#910:7)?6:958 4c=>81/=k491:&14?063->i645+368a?!5a2m1/8=4n;%60>37<,=2196*;9;7e?!2f2>>0(8<58`9'16<1n2.>9767;%75>3c<,<31:h5+5b8;e>"2m3n0(;>58:&56?0>3-<?6:>4$77930=#>?0h7)8n:638 24=i2.<57?4$94924=#0k03o6*>1;58 73==11/><4=9:&2`?4<,8i1?6g;2;29 2e=1=1/;h47a:9j7<<72-=h64:4$6g9<d=<a=o1<7*8c;;5?!1e21k0(:o58`98m01=83.<o77:;%5a>=g<,>k14l54i4f94?"0k33?7)9m:9c8?l33290/;n464:&4f?>f32c?j7>5$6a9=1=#?k03m65f8283>!1d20>0(:l58`98m=7=83.<o77;;%5a>=g<3`296=4+7b8:0>"0j32j76g8f;29 2e=1=1/;o47a:9l6g<72-=h64:4$6g9<d=#::09m6*=4;40?>i4;3:1(:m59598k7`=83.<o77;;:m04?6=,>i15954o2694?"0k33?7)9j:9c8 75=:h10c>?50;&4g??332e8>7>5$6a9=1=<g:h1<7*8c;;7?!1b21k0(?=52`98k6e=83.<o77;;:m6f?6=,>i15954o4c94?"0k33>7)9n:9c8?j0d290/;n464:&4a?>f32e3<7>5$6a9=1=<uk>>6=4=:183!1c2?20e;950;&4g??33-=n65o4;n55>5<#?j0286*8e;:b?>{e:m0;6?4?:1y'3a<5i2c=;7>5$6a9=1=#?l03m65`7783>!1d20>0(:k58`98yg5b29096=4?{%5g>7g<a?=1<7*8c;;7?!1b21k07b99:18'3f<><2.<i76n;:a73<72;0;6=u+7e81e>o1?3:1(:m5959'3`<?i21d;;4?:%5`><2<,>o14l54}r67>5<5s4?:69<4=57933=#:;0?:6s|3`83>7}:=808563=d;55?!452;o0q~<l:1818362;h01?j5669~w63=838p18?5359>73<1?2wx?i4?:3y>14<4j278i788;|q5`?6=9r7>=78l;%:7>20<uz><6=4>{<66>31<,1>1::5rs5394?7|5:o1;;5+85842>{t;10;6<u237842>"?<3==7p};6;294~"?<3==7p}=e;294~"?<3==7psa3083>4}zf:81<7?t}o10>5<6std887>51zm70<728qvb>850;3xyk50290:wp`<8;295~{i;00;6<urn2c94?7|ug9i6=4>{|~yEFDs==1;o:mfb36yEFEs9wKL]ur@A
/trunk/impl/virtex4-ml403ep/memory/README
0,0 → 1,21
To test the RAM/ROM controller, create a project inside Xilinx ISE with the
following files:
* clocks.xaw
* clock.v
* mem_ctrl.v
* mem_cntrlr_test.v
* ml403.ucf
 
To test the video controller, with the mem map, create a empty project with
these files:
* clocks.xaw
* clock.v
* mem_ctrl.v
* mem_map_test.v
* mem_map.v
* ml403-with-tft.ucf
* ../../spartan3an-sk/rtl/vga/char_rom_b16.v
* ../../spartan3an-sk/rtl/vga/ram2k_b16_attr.v
* ../../spartan3an-sk/rtl/vga/ram2k_b16.v
* ../../spartan3an-sk/rtl/vga/vdu.v
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.