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URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

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  • This comparison shows the changes necessary to convert path 
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    from Rev 80 to Rev 81
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Rev 80 → Rev 81

/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/smartgen/pmem_2kB.v
14,8 → 14,7
VCC VCC_1_net(.Y(VCC));
GND GND_1_net(.Y(GND));
RAM4K9 #( .MEMORYFILE() )
pmem_2kB_R0C0(.ADDRA11(GND), .ADDRA10(WADDR[10]),
RAM4K9 pmem_2kB_R0C0(.ADDRA11(GND), .ADDRA10(WADDR[10]),
.ADDRA9(WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]),
.ADDRA6(WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]),
.ADDRA3(WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]),
36,8 → 35,7
.DOUTA0(), .DOUTB8(), .DOUTB7(), .DOUTB6(), .DOUTB5(),
.DOUTB4(), .DOUTB3(), .DOUTB2(), .DOUTB1(RD[1]), .DOUTB0(
RD[0]));
RAM4K9 #( .MEMORYFILE() )
pmem_2kB_R0C1(.ADDRA11(GND), .ADDRA10(WADDR[10]),
RAM4K9 pmem_2kB_R0C1(.ADDRA11(GND), .ADDRA10(WADDR[10]),
.ADDRA9(WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]),
.ADDRA6(WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]),
.ADDRA3(WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]),
58,8 → 56,7
.DOUTA0(), .DOUTB8(), .DOUTB7(), .DOUTB6(), .DOUTB5(),
.DOUTB4(), .DOUTB3(), .DOUTB2(), .DOUTB1(RD[3]), .DOUTB0(
RD[2]));
RAM4K9 #( .MEMORYFILE() )
pmem_2kB_R0C3(.ADDRA11(GND), .ADDRA10(WADDR[10]),
RAM4K9 pmem_2kB_R0C3(.ADDRA11(GND), .ADDRA10(WADDR[10]),
.ADDRA9(WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]),
.ADDRA6(WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]),
.ADDRA3(WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]),
80,8 → 77,7
.DOUTA0(), .DOUTB8(), .DOUTB7(), .DOUTB6(), .DOUTB5(),
.DOUTB4(), .DOUTB3(), .DOUTB2(), .DOUTB1(RD[7]), .DOUTB0(
RD[6]));
RAM4K9 #( .MEMORYFILE() )
pmem_2kB_R0C2(.ADDRA11(GND), .ADDRA10(WADDR[10]),
RAM4K9 pmem_2kB_R0C2(.ADDRA11(GND), .ADDRA10(WADDR[10]),
.ADDRA9(WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]),
.ADDRA6(WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]),
.ADDRA3(WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]),
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/smartgen/dmem_128B.v
14,8 → 14,7
VCC VCC_1_net(.Y(VCC));
GND GND_1_net(.Y(GND));
RAM4K9 #( .MEMORYFILE() )
dmem_128B_R0C0(.ADDRA11(GND), .ADDRA10(GND), .ADDRA9(
RAM4K9 dmem_128B_R0C0(.ADDRA11(GND), .ADDRA10(GND), .ADDRA9(
GND), .ADDRA8(GND), .ADDRA7(GND), .ADDRA6(WADDR[6]),
.ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]), .ADDRA3(WADDR[3]),
.ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]), .ADDRA0(WADDR[0]),
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openMSP430_fpga.v
134,16 → 134,16
 
 
parameter FCLKA = 48.0;
parameter M = 7'd8;
parameter N = 7'd3;
parameter U = 5'd8;
parameter M = 7'd6;
parameter N = 7'd9;
parameter U = 5'd2;
parameter V = 5'd1;
parameter W = 5'd1;
 
parameter FVCO = FCLKA*M/N; // 128 MHz
parameter FVCO = FCLKA*M/N; // 32 MHz
parameter FGLA = FVCO/U; // 16 MHz
parameter FGLB = FVCO/V; // 128 MHz
parameter FGLC = FVCO/W; // 128 MHz
parameter FGLB = FVCO/V; // 32 MHz
parameter FGLC = FVCO/W; // 32 MHz
 
wire [4:0] oadiv = U-5'h01;
wire [4:0] obdiv = V-5'h01;
257,11 → 257,35
 
.XDLYSEL (1'b0), // System Delay Select (0: no dly; 1:inserts system dly)
 
.VCOSEL0 (1'b1), // VCO gear control
.VCOSEL1 (1'b1),
.VCOSEL2 (1'b1)
.VCOSEL0 (1'b1), // PLL lock acquisition time (0: Fast with high tracking jitter; 1: Slow with low tracking jitter)
 
.VCOSEL1 (1'b1), // VCO gear control (see table below)
.VCOSEL2 (1'b0)
);
 
//-------------+--------------------------------------------------------------+
// | VCOSEL[2:1] |
// |---------------+---------------+--------------+---------------|
// | 00 | 01 | 10 | 11 |
// VOLTAGE |---------------+---------------+--------------+---------------|
// | Min. Max. | Min. Max. | Min. Max. | Min. Max. |
// | (MHz) (MHz) | (MHz) (MHz) | (MHz) (MHz) | (MHz) (MHz) |
//-------------+---------------+---------------+--------------+---------------|
// IGLOO and IGLOO PLUS |
//-------------+---------------+---------------+--------------+---------------|
 
 
//-------------+---------------+---------------+--------------+---------------|
// ProASIC3L, RT ProASIC3, and Military ProASIC3/L |
//-------------+---------------+---------------+--------------+---------------|
 
 
//-------------+---------------+---------------+--------------+---------------|
// ProASIC3 and Fusion |
//-------------+---------------+---------------+--------------+---------------|
 
//-------------+---------------+---------------+--------------+---------------+
 
//=============================================================================
// 3) PROGRAM AND DATA MEMORIES
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_files.pdc
8,7 → 8,7
 
# CLOCK & RESET
#------------------------------------------------
set_io clk_osc -pinname E4
set_io oscclk -pinname E4
set_io porst_n -pinname V7
set_io pbrst_n -pinname T9
 
15,12 → 15,12
 
# GPIOA
#------------------------------------------------
set_io gpioa\[0\] -pinname D5 ;# GPIOA_0
set_io gpioa\[1\] -pinname D6 ;# GPIOA_1
set_io gpioa\[2\] -pinname D10 ;# GPIOA_2
set_io gpioa\[3\] -pinname G10 ;# GPIOA_3
set_io gpioa\[4\] -pinname G11 ;# GPIOA_4
set_io gpioa\[4\] -pinname E11 ;# GPIOA_5
set_io din_x -pinname D5 ;# GPIOA_0
set_io sclk_x -pinname D6 ;# GPIOA_1
set_io sync_n_x -pinname D10 ;# GPIOA_2
set_io din_y -pinname G10 ;# GPIOA_3
set_io sclk_y -pinname G11 ;# GPIOA_4
set_io sync_n_y -pinname E11 ;# GPIOA_5
 
 
# UART INTERFACE
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/build_fpga.tcl
40,7 → 40,7
###############################################################################
 
# Set tools
set SYNPLICITY "C:\\\\Actel\\\\Libero_v8.5\\\\Synplify\\\\synplify_96A\\\\bin\\\\synplify.exe"
set SYNPLICITY "C:\\\\Actel\\\\Libero_v8.5\\\\Synplify\\\\synplify_96A\\\\bin\\\\synplify_pro.exe"
set LIBERO_DESIGNER "C:\\\\Actel\\\\Libero_v8.5\\\\Designer\\\\bin\\\\designer.exe"
 
# Set the FPGA: architecture, model, package_syn package_libero, speed-grade
49,6 → 49,10
# RTL Top Level module
set designTop "openMSP430_fpga"
 
# RTL include files
set rtlIncludeFiles "../../../rtl/verilog/openmsp430/timescale.v \
../../../rtl/verilog/openmsp430/openMSP430_defines.v \
../../../rtl/verilog/openmsp430/openMSP430_undefines.v"
 
###############################################################################
# CLEANUP #
64,9 → 68,13
file mkdir ./WORK
cd ./WORK
 
 
# Copy RTL include files
foreach rtlFile $rtlIncludeFiles {
file copy $rtlFile .
}
###############################################################################
# PERFORM SYNTHESIS #
# GENERATE SYNTHESIS SCRIPT #
###############################################################################
 
# Copy Synplify tcl command files
88,39 → 96,8
puts $f_synplify_tcl $synplify_tcl
close $f_synplify_tcl
 
# Start synthesis
puts "START SYNTHESIS..."
flush stdout
set synplify_done 0
while {[string eq $synplify_done 0]} {
 
sleep 10
eval exec $SYNPLICITY synplify.tcl
sleep 30
 
# Wait until EDIF file is generated
set synplify_timeout 0
while {!([file exists "./rev_1/design_files.edn"] | ($synplify_timeout==100))} {
set synplify_timeout [expr $synplify_timeout+1]
}
if ($synplify_timeout<100) {
set synplify_done 1
}
 
# Kill the Synplify task with taskkill since it can't be properly closed with the synplify.tcl script
sleep 10
eval exec taskkill /IM synplify.exe
sleep 20
if {[string eq $synplify_done 0]} {
sleep 180
}
}
puts "SYNTHESIS DONE..."
flush stdout
 
 
###############################################################################
# PERFORM PLACE & ROUTE #
# GENERATE PLACE & ROUTE SCRIPT #
###############################################################################
 
# Copy Libero Designer tcl command files
139,8 → 116,35
set f_libero_designer_tcl [open "libero_designer.tcl" w]
puts $f_libero_designer_tcl $libero_designer_tcl
close $f_libero_designer_tcl
 
###############################################################################
# RUN SYNTHESIS #
###############################################################################
 
# Start synthesis
puts "START SYNTHESIS..."
flush stdout
sleep 10
eval exec $SYNPLICITY synplify.tcl
sleep 30
 
# Wait until EDIF file is generated
while {!([file exists "./rev_1/design_files.edn"])} {
sleep 10
}
 
# Kill the Synplify task with taskkill since it can't be properly closed with the synplify.tcl script
sleep 10
eval exec taskkill /IM synplify.exe
sleep 20
 
puts "SYNTHESIS DONE..."
flush stdout
 
###############################################################################
# RUN PLACE & ROUTE #
###############################################################################
 
# Run place & route
puts "START PLACE & ROUTE..."
flush stdout
148,7 → 152,6
puts "PLACE & ROUTE DONE..."
flush stdout
 
 
###############################################################################
# REPORT SUMMARY #
###############################################################################
175,7 → 178,7
regexp {(Core Information:.*?)I/O Function:} $areaFile whole_match area2
puts $area1
puts $area2
puts $f_logFile "===================================================================================="
puts "===================================================================================="
 
cd ../
sleep 3

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