OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 80 to Rev 81
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Rev 80 → Rev 81

/trunk/bench/verilog/system.v
39,6 → 39,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.13 2003/01/21 16:06:50 mihad
// Bug fixes, testcases added.
//
// Revision 1.12 2002/10/21 13:04:30 mihad
// Changed BIST signal names etc..
//
18925,8 → 18928,8
disable main ;
end
 
// completion is present if wbr fifo for sure, since write proceeded ok, wait for completion to almost expire - 2^^16 cycles - 100
repeat('h1_0000 - 100)
// completion is present if wbr fifo for sure, since write proceeded ok, wait for completion to almost expire - 2^^16 cycles - 110
repeat('h1_0000 - 110)
@(posedge wb_clock) ;
// now perform a read
18978,7 → 18981,7
end
 
// wait for 2^^16 cycles, so monitor won't complain about waiting too long
repeat('h1_0000 - 50)
repeat('h1_0000 - 100)
@(posedge wb_clock) ;
 
// monitor normal single memory read
/trunk/rtl/verilog/pci_wb_master.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2003/01/27 16:49:31 mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.7 2002/12/05 12:19:23 mihad
// *** empty log message ***
//
267,7 → 270,7
// wire for read attempt - 1 when PCI Target is attempting a read and PCIR_FIFO is not full !
// because of transaction ordering, PCI Master must not start read untill all writes are done -> at that
// moment PCIW_FIFO is empty !!! (when read is pending PCI Target will block new reads and writes)
wire r_attempt = ( pci_tar_read_request && !w_attempt);// pciw_fifo_empty_in ) ;
wire r_attempt = ( pci_tar_read_request && !w_attempt && pciw_fifo_empty_in ) ;
 
// Signal is used for reads on WB, when there is retry!
reg first_wb_data_access ;
/trunk/rtl/verilog/pci_wbw_wbr_fifos.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2003/01/27 16:49:31 mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.9 2002/10/18 03:36:37 tadejm
// Changed wrong signal name scanb_sen into scanb_en.
//
531,6 → 534,24
inGreyCount <= #`FF_DELAY inNextGreyCount ;
end
 
wire [(WBW_ADDR_LENGTH-2):0] pci_clk_sync_inGreyCount ;
reg [(WBW_ADDR_LENGTH-2):0] pci_clk_inGreyCount ;
synchronizer_flop #((WBW_ADDR_LENGTH - 1)) i_synchronizer_reg_inGreyCount
(
.data_in (inGreyCount),
.clk_out (pci_clock_in),
.sync_data_out (pci_clk_sync_inGreyCount),
.async_reset (1'b0)
) ;
 
always@(posedge pci_clock_in or posedge wbw_clear)
begin
if (wbw_clear)
pci_clk_inGreyCount <= #`FF_DELAY 1 ;
else
pci_clk_inGreyCount <= # `FF_DELAY pci_clk_sync_inGreyCount ;
end
 
// register holding grey coded count of outgoing transactions
always@(posedge pci_clock_in or posedge wbw_clear)
begin
564,21 → 585,7
wbw_outTransactionCount <= #`FF_DELAY wbw_outTransactionCount + 1'b1 ;
end
 
// synchronize transaction ready output to reading clock
// transaction ready is set when incoming transaction count is not equal to outgoing transaction count (what goes in must come out logic)
// transaction ready is cleared when whole transaction is pulled out of fifo (otherwise it could stay set for additional cycle and result in wrong op.)
wire wbw_transaction_ready_flop_i = inGreyCount != outGreyCount ;
assign wbw_transaction_ready_out = pci_clk_inGreyCount != outGreyCount ;
 
meta_flop #(0) i_meta_flop_wbw_transaction_ready
(
.rst_i (wbw_clear),
.clk_i (pci_clock_in),
.ld_i (out_count_en),
.ld_val_i (1'b0),
.en_i (1'b1),
.d_i (wbw_transaction_ready_flop_i),
.meta_q_o (wbw_transaction_ready_out)
) ;
 
endmodule
 
/trunk/rtl/verilog/pci_pciw_pcir_fifos.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2003/01/27 16:49:31 mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.10 2002/10/18 03:36:37 tadejm
// Changed wrong signal name scanb_sen into scanb_en.
//
544,7 → 547,7
wire [(PCIW_ADDR_LENGTH-2):0] outNextGreyCount = {pciw_outTransactionCount[(PCIW_ADDR_LENGTH-2)], pciw_outTransactionCount[(PCIW_ADDR_LENGTH-2):1] ^ pciw_outTransactionCount[(PCIW_ADDR_LENGTH-3):0]} ;
 
// input transaction counter is incremented when whole transaction is written to fifo. This is indicated by last control bit written to last transaction location
wire in_count_en = pciw_wallow && pciw_last_in ;
wire in_count_en = pciw_wallow && pciw_last_in ;
 
// output transaction counter is incremented when whole transaction is pulled out of fifo. This is indicated when location with last control bit set is read
wire out_count_en = pciw_rallow && pciw_last_out ;
561,9 → 564,27
inGreyCount <= #`FF_DELAY inNextGreyCount ;
end
 
wire [(PCIW_ADDR_LENGTH-2):0] wb_clk_sync_inGreyCount ;
reg [(PCIW_ADDR_LENGTH-2):0] wb_clk_inGreyCount ;
synchronizer_flop #((PCIW_ADDR_LENGTH - 1)) i_synchronizer_reg_inGreyCount
(
.data_in (inGreyCount),
.clk_out (wb_clock_in),
.sync_data_out (wb_clk_sync_inGreyCount),
.async_reset (1'b0)
) ;
 
always@(posedge wb_clock_in or posedge pciw_clear)
begin
if (pciw_clear)
wb_clk_inGreyCount <= #`FF_DELAY 1 ;
else
wb_clk_inGreyCount <= # `FF_DELAY wb_clk_sync_inGreyCount ;
end
 
always@(posedge wb_clock_in or posedge pciw_clear)
begin
if (pciw_clear)
begin
outGreyCount[(PCIW_ADDR_LENGTH-2)] <= #`FF_DELAY 1'b1 ;
outGreyCount[(PCIW_ADDR_LENGTH-3):0] <= #`FF_DELAY {(PCIW_ADDR_LENGTH-2),1'b0} ;
591,22 → 612,8
pciw_outTransactionCount <= #`FF_DELAY pciw_outTransactionCount + 1'b1 ;
end
 
// transaction is ready when incoming transaction count is not equal to outgoing transaction count ( what comes in must come out )
// anytime last entry of transaction is pulled out of fifo, transaction ready flag is cleared for at least one clock to prevent wrong operation
// ( otherwise transaction ready would stay set for one additional clock even though next transaction was not ready )
assign pciw_transaction_ready_out = wb_clk_inGreyCount != outGreyCount ;
 
wire pciw_transaction_ready_flop_i = inGreyCount != outGreyCount ;
meta_flop #(0) i_meta_flop_transaction_ready
(
.rst_i (pciw_clear),
.clk_i (wb_clock_in),
.ld_i (out_count_en),
.ld_val_i (1'b0),
.en_i (1'b1),
.d_i (pciw_transaction_ready_flop_i),
.meta_q_o (pciw_transaction_ready_out)
) ;
 
assign pcir_transaction_ready_out = 1'b0 ;
 
endmodule
/trunk/sim/rtl_sim/run/run_pci_sim_regr.scr
275,6 → 275,10
echo "\tNO_CNF_IMAGE, WB_IMAGE2, WB_IMAGE3, WB_IMAGE4, WB_IMAGE5. "
echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_LARGE_GENERIC -DEFINE WB_DECODE_MEDIUM -DEFINE PCI_DECODE_MAX -DEFINE WB_DECODE_MED -DEFINE PCI33 -DEFINE WB_CLK10 -DEFINE ACTIVE_HIGH_OE -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE WB_IMAGE2 -DEFINE WB_IMAGE3 -DEFINE WB_IMAGE4 -DEFINE WB_IMAGE5" > ./defines.args
endif
if ($arg_dis_comp_exp_test) then
echo "-DEFINE DISABLE_COMPLETION_EXPIRED_TESTS" >> ./defines.args
endif
else
if (($arg_xilinx == 1) && ($arg_artisan == 1)) then
if ($iter == 1) then
365,6 → 369,10
echo "\tNO_CNF_IMAGE, WB_IMAGE2, WB_IMAGE3, WB_IMAGE4, WB_IMAGE5. "
echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_LARGE_GENERIC -DEFINE WB_DECODE_MEDIUM -DEFINE PCI_DECODE_MAX -DEFINE WB_DECODE_MED -DEFINE PCI33 -DEFINE WB_CLK10 -DEFINE ACTIVE_HIGH_OE -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE WB_IMAGE2 -DEFINE WB_IMAGE3 -DEFINE WB_IMAGE4 -DEFINE WB_IMAGE5" > ./defines.args
endif
 
if ($arg_dis_comp_exp_test) then
echo "-DEFINE DISABLE_COMPLETION_EXPIRED_TESTS" >> ./defines.args
endif
else
if ($iter == 1) then
echo "<<< Defines:"
454,6 → 462,11
echo "\tNO_CNF_IMAGE, WB_IMAGE2, WB_IMAGE3, WB_IMAGE4, WB_IMAGE5. "
echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_LARGE_GENERIC -DEFINE WB_DECODE_MEDIUM -DEFINE PCI_DECODE_MAX -DEFINE WB_DECODE_MED -DEFINE PCI33 -DEFINE WB_CLK10 -DEFINE ACTIVE_HIGH_OE -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE WB_IMAGE2 -DEFINE WB_IMAGE3 -DEFINE WB_IMAGE4 -DEFINE WB_IMAGE5" > ./defines.args
endif
 
if ($arg_dis_comp_exp_test) then
echo "-DEFINE DISABLE_COMPLETION_EXPIRED_TESTS" >> ./defines.args
endif
 
endif
endif
endif

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