OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 81 to Rev 82
    ↔ Reverse comparison
  •

Rev 81 → Rev 82

/trunk/rtl/verilog/oc8051_icache.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/10/24 13:34:02 simont
// add parameters for instruction cache
//
// Revision 1.1 2002/10/23 16:55:36 simont
// fix bugs in instruction interface
//
211,13 → 214,13
wr1 <= #1 1'b0;
adr_w <= #1 6'd0;
vaild <= #1 16'd0;
end if (stb_b && !hit && !stb_o && !wr1) begin
end else if (stb_b && !hit && !stb_o && !wr1) begin
cyc <= #1 'd0;
cyc_o <= #1 1'b1;
stb_o <= #1 1'b1;
data1_i<= #1 32'h0;
wr1 <= #1 1'b0;
end if (stb_o && ack_i) begin
end else if (stb_o && ack_i) begin
data1_i<= #1 dat_i;
wr1 <= #1 1'b1;
adr_w <= #1 adr_o[ADR_WIDTH+1:2];
232,32 → 235,6
cyc_o <= #1 1'b1;
stb_o <= #1 1'b1;
end
 
 
/* case (cyc)
2'b00: begin
cyc <= #1 2'b01;
cyc_o <= #1 1'b1;
stb_o <= #1 1'b1;
end
2'b01: begin
cyc <= #1 2'b10;
cyc_o <= #1 1'b1;
stb_o <= #1 1'b1;
end
2'b10: begin
cyc <= #1 2'b11;
cyc_o <= #1 1'b1;
stb_o <= #1 1'b1;
end
default: begin
cyc <= #1 2'b00;
cyc_o <= #1 1'b0;
stb_o <= #1 1'b0;
con_buf[mis_adr[7:4]] <= #1 mis_adr[15:8];
vaild[mis_adr[7:4]] <= #1 1'b1;
end
endcase*/
end else begin
wr1 <= #1 1'b0;
end
/trunk/rtl/verilog/oc8051_defines.v
48,7 → 48,7
//
// oc8051 cache
//
`define OC8051_CACHE
//`define OC8051_CACHE
 
//
// operation codes for alu
85,8 → 85,8
`define OC8051_SFR_P3 8'hb0 //port 3
`define OC8051_SFR_DPTR_LO 8'h82 // data pointer high bits
`define OC8051_SFR_DPTR_HI 8'h83 // data pointer low bits
`define OC8051_SFR_IP 8'hb8 // interrupt priority control
`define OC8051_SFR_IE 8'ha8 // interrupt enable control
`define OC8051_SFR_IP0 8'hb8 // interrupt priority
`define OC8051_SFR_IEN0 8'ha8 // interrupt enable 0
`define OC8051_SFR_TMOD 8'h89 // timer/counter mode
`define OC8051_SFR_TCON 8'h88 // timer/counter control
`define OC8051_SFR_TH0 8'h8c // timer/counter 0 high bits
93,11 → 93,30
`define OC8051_SFR_TL0 8'h8a // timer/counter 0 low bits
`define OC8051_SFR_TH1 8'h8d // timer/counter 1 high bits
`define OC8051_SFR_TL1 8'h8b // timer/counter 1 low bits
`define OC8051_SFR_SCON 8'h98 // serial control
`define OC8051_SFR_SBUF 8'h99 // serial data buffer
 
`define OC8051_SFR_SCON 8'h98 // serial control 0
`define OC8051_SFR_SBUF 8'h99 // serial data buffer 0
`define OC8051_SFR_SADDR 8'ha9 // serila address register 0
`define OC8051_SFR_SADEN 8'hb9 // serila address enable 0
 
`define OC8051_SFR_PCON 8'h87 // power control
`define OC8051_SFR_SP 8'h81 // stack pointer
 
 
 
`define OC8051_SFR_IE 8'ha8 // interrupt enable
`define OC8051_SFR_IP 8'hb7 // interrupt priority
 
`define OC8051_SFR_RCAP2H 8'hcb // timer 2 capture high
`define OC8051_SFR_RCAP2L 8'hca // timer 2 capture low
 
`define OC8051_SFR_T2CON 8'hc8 // timer 2 control register
`define OC8051_SFR_T2MOD 8'hc9 // timer 2 mode control
`define OC8051_SFR_TH2 8'hcd // timer 2 high
`define OC8051_SFR_TL2 8'hcc // timer 2 low
 
 
 
//
// sfr bit addresses
//
108,29 → 127,14
`define OC8051_SFR_B_P2 5'b10100 //port 2
`define OC8051_SFR_B_P3 5'b10110 //port 3
`define OC8051_SFR_B_B 5'b11110 // b register
`define OC8051_SFR_B_IP 5'b10111 // interrupt priority control
`define OC8051_SFR_B_IE 5'b10101 // interrupt enable control
`define OC8051_SFR_B_IP 5'b10111 // interrupt priority control 0
`define OC8051_SFR_B_IE 5'b10101 // interrupt enable control 0
`define OC8051_SFR_B_SCON 5'b10011 // serial control
`define OC8051_SFR_B_TCON 5'b10001 // timer/counter control
`define OC8051_SFR_B_TCON 5'b10001 // timer/counter control
`define OC8051_SFR_B_T2CON 5'b11001 // timer/counter2 control
 
//
// alu source select
//
`define OC8051_ASS_RAM 2'b00 // RAM
`define OC8051_ASS_ACC 2'b01 // accumulator
`define OC8051_ASS_XRAM 2'b10 // external RAM -- source1
`define OC8051_ASS_ZERO 2'b10 // 8'h00 -- source2
`define OC8051_ASS_IMM 2'b11 // immediate data -- source1
`define OC8051_ASS_DC 2'b00 //
 
//
// alu source 3 select
//
`define OC8051_AS3_PC 1'b1 // program clunter
`define OC8051_AS3_DP 1'b0 // data pointer
`define OC8051_AS3_DC 1'b0 //
 
//
//carry input in alu
//
`define OC8051_CY_0 2'b00 // 1'b0;
215,7 → 219,7
`define OC8051_JB 8'b0010_0000 // jump if bit set
`define OC8051_JBC 8'b0001_0000 // jump if bit set and clear bit
`define OC8051_JC 8'b0100_0000 // jump if carry is set
`define OC8051_JMP 8'b0111_0011 // jump indirect
`define OC8051_JMP_D 8'b0111_0011 // jump indirect
`define OC8051_JNB 8'b0011_0000 // jump if bit not set
`define OC8051_JNC 8'b0101_0000 // jump if carry not set
`define OC8051_JNZ 8'b0111_0000 // jump if accumulator not zero
266,7 → 270,7
//
// default values (used after reset)
//
`define OC8051_RST_PC 16'h0000 // program counter
`define OC8051_RST_PC 23'h0 // program counter
`define OC8051_RST_ACC 8'h00 // accumulator
`define OC8051_RST_B 8'h00 // b register
`define OC8051_RST_PSW 8'h00 // program status word
289,62 → 293,103
`define OC8051_RST_SBUF 8'b0000_0000 // serial data buffer
`define OC8051_RST_PCON 8'b0000_0000 // power control register
 
 
 
`define OC8051_RST_RCAP2H 8'h00 // timer 2 capture high
`define OC8051_RST_RCAP2L 8'h00 // timer 2 capture low
 
`define OC8051_RST_T2CON 8'h00 // timer 2 control register
`define OC8051_RST_T2MOD 8'h00 // timer 2 mode control
`define OC8051_RST_TH2 8'h00 // timer 2 high
`define OC8051_RST_TL2 8'h00 // timer 2 low
 
 
//
// alu source 1 select
//
`define OC8051_AS1_RAM 3'b000 // RAM
`define OC8051_AS1_OP1 3'b111 //
`define OC8051_AS1_OP2 3'b001 //
`define OC8051_AS1_OP3 3'b010 //
`define OC8051_AS1_ACC 3'b011 // accumulator
`define OC8051_AS1_PCH 3'b100 //
`define OC8051_AS1_PCL 3'b101 //
`define OC8051_AS1_DC 3'b000 //
 
//
// alu source 2 select
//
`define OC8051_AS2_RAM 3'b000 // RAM
`define OC8051_AS2_ACC 3'b001 // accumulator
`define OC8051_AS2_ZERO 3'b010 // 8'h00
`define OC8051_AS2_OP2 3'b011 //
`define OC8051_AS2_PCL 3'b100 //
 
`define OC8051_AS2_DC 3'b000 //
 
//
// alu source 3 select
//
`define OC8051_AS3_DP 1'b0 // data pointer
`define OC8051_AS3_PC 1'b1 // program clunter
//`define OC8051_AS3_PCU 3'b101 // program clunter not registered
`define OC8051_AS3_DC 1'b0 //
 
 
//
//write sfr
//
`define OC8051_WRS_N 3'b000 //no
`define OC8051_WRS_ACC1 3'b001 // acc destination 1
`define OC8051_WRS_ACC2 3'b010 // acc destination 2
`define OC8051_WRS_DPTR 3'b011 // data pointer
`define OC8051_WRS_BA 3'b100 // a, b register
 
 
//
// ram read select
//
 
`define OC8051_RRS_RN 2'b00 // registers
`define OC8051_RRS_I 2'b01 // indirect addressing
`define OC8051_RRS_D 2'b10 // direct addressing
`define OC8051_RRS_SP 2'b11 // stack pointer
`define OC8051_RRS_DC 2'b00 // don't c
`define OC8051_RRS_RN 3'b000 // registers
`define OC8051_RRS_I 3'b001 // indirect addressing (op2)
`define OC8051_RRS_D 3'b010 // direct addressing
`define OC8051_RRS_SP 3'b011 // stack pointer
 
`define OC8051_RRS_B 3'b100 // b register
`define OC8051_RRS_DPTR 3'b101 // data pointer
 
`define OC8051_RRS_DC 3'b000 // don't c
 
//
// ram write select
//
 
`define OC8051_RWS_RN 3'b000 // registers
`define OC8051_RWS_D 3'b001 // direct addressing
`define OC8051_RWS_I 3'b010 // indirect addressing
`define OC8051_RWS_D 3'b001 // direct addressing
`define OC8051_RWS_I 3'b010 // indirect addressing
`define OC8051_RWS_SP 3'b011 // stack pointer
`define OC8051_RWS_ACC 3'b100 // accumulator
`define OC8051_RWS_D3 3'b101 // direct address (op3)
`define OC8051_RWS_DPTR 3'b110 // data pointer (high + low)
`define OC8051_RWS_B 3'b111 // b register
`define OC8051_RWS_D1 3'b110 // direct address (op1)
`define OC8051_RWS_DC 3'b000 //
 
//
// immediate data select
//
 
`define OC8051_IDS_OP2 3'b000 // operand 2
`define OC8051_IDS_OP3 3'b001 // operand 3
`define OC8051_IDS_PCH 3'b010 // pc high
`define OC8051_IDS_PCL 3'b011 // pc low
`define OC8051_IDS_OP3_PCL 3'b100 // op3 and pc low
`define OC8051_IDS_OP3_OP2 3'b101 // op3 and op2
`define OC8051_IDS_OP2_PCL 3'b110 // op2 and PC LOW
`define OC8051_IDS_OP1 3'b111 // operand 1
`define OC8051_IDS_DC 3'b000 //
 
 
//
// pc in select
//
`define OC8051_PIS_DC 2'b00 // dont c
`define OC8051_PIS_SP 2'b00 // stack ( des1 -- serial)
`define OC8051_PIS_ALU 2'b01 // alu {des1, des2}
`define OC8051_PIS_I11 2'b10 // 11 bit immediate
`define OC8051_PIS_I16 2'b11 // 16 bit immediate
`define OC8051_PIS_DC 3'b000 // dont c
`define OC8051_PIS_AL 3'b000 // alu low
`define OC8051_PIS_AH 3'b001 // alu high
`define OC8051_PIS_ALU 3'b010 // alu {des1, des2}
`define OC8051_PIS_I11 3'b011 // 11 bit immediate
`define OC8051_PIS_I16 3'b100 // 16 bit immediate
 
//
// compare source select
//
`define OC8051_CSS_AZ 2'b00 // eq = accumulator == zero
`define OC8051_CSS_AZ 2'b00 // eq = accumulator == zero
`define OC8051_CSS_DES 2'b01 // eq = destination == zero
`define OC8051_CSS_CY 2'b10 // eq = cy
`define OC8051_CSS_CY 2'b10 // eq = cy
`define OC8051_CSS_BIT 2'b11 // eq = b_in
`define OC8051_CSS_DC 2'b00 // don't care
`define OC8051_CSS_DC 2'b00 // don't care
 
 
//
367,28 → 412,24
`define OC8051_RAS_PC 1'b0 // program counter
`define OC8051_RAS_DES 1'b1 // alu destination
 
//
// write accumulator
//
`define OC8051_WA_N 1'b0 // not
`define OC8051_WA_Y 1'b1 // yes
////
//// write accumulator
////
//`define OC8051_WA_N 1'b0 // not
//`define OC8051_WA_Y 1'b1 // yes
 
 
//
//external ram address select
//memory action select
//
`define OC8051_EAS_DPTR 1'b0 // data pointer
`define OC8051_EAS_RI 1'b1 // register R0 or R1
`define OC8051_EAS_DC 1'b0
`define OC8051_MAS_DPTR_R 3'b000 // read from external rom: acc=(dptr)
`define OC8051_MAS_DPTR_W 3'b001 // write to external rom: (dptr)=acc
`define OC8051_MAS_RI_R 3'b010 // read from external rom: acc=(Ri)
`define OC8051_MAS_RI_W 3'b011 // write to external rom: (Ri)=acc
`define OC8051_MAS_CODE 3'b100 // read from program memory
`define OC8051_MAS_NO 3'b111 // no action
 
//
//write ac from des2
//
`define OC8051_WAD_N 1'b0 //
`define OC8051_WAD_Y 1'b1 //
 
 
 
////////////////////////////////////////////////////
 
//
405,19 → 446,20
// Interrupt numbers (vectors)
//
 
`define OC8051_INT_X0 8'h03 // external interrupt 0
`define OC8051_INT_T0 8'h0b // T/C 0 owerflow interrupt
`define OC8051_INT_X1 8'h13 // external interrupt 1
`define OC8051_INT_T1 8'h1b // T/C 1 owerflow interrupt
`define OC8051_INT_X0 8'h03 // external interrupt 0
`define OC8051_INT_X1 8'h13 // external interrupt 1
`define OC8051_INT_UART 8'h23 // interrupt from uart
`define OC8051_INT_UART 8'h23 // uart interrupt
`define OC8051_INT_T2 8'h2b // T/C 2 owerflow interrupt
 
 
//
// interrupt levels
//
 
`define OC8051_ILEV_NO 2'b00 // no interrupts
`define OC8051_ILEV_L0 2'b01 // interrupt on level 0
`define OC8051_ILEV_L1 2'b10 // interrupt on level 1
`define OC8051_ILEV_L0 1'b0 // interrupt on level 0
`define OC8051_ILEV_L1 1'b1 // interrupt on level 1
 
//
// interrupt sources
427,7 → 469,8
`define OC8051_ISRC_TF0 3'b010 // t/c owerflov 0
`define OC8051_ISRC_IE1 3'b011 // EXTERNAL INTERRUPT 1
`define OC8051_ISRC_TF1 3'b100 // t/c owerflov 1
`define OC8051_ISRC_UART 3'b101 // UART Interrupt
`define OC8051_ISRC_UART 3'b101 // UART Interrupt
`define OC8051_ISRC_T2 3'b110 // t/c owerflov 2
 
 
 
445,3 → 488,4
 
`define OC8051_RMW_Y 1'b1 // yes
`define OC8051_RMW_N 1'b0 // no
 
/trunk/rtl/verilog/oc8051_indi_addr.v
1,111 → 1,154
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 indirect address ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// Contains ragister 0 and register 1. used for indirrect ////
//// addressing. ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
 
module oc8051_indi_addr (clk, rst, addr, data_in, wr, wr_bit, data_out, sel, bank);
//
// clk (in) clock
// rst (in) reset
// addr (in) write address [oc8051_ram_wr_sel.out]
// data_in (in) data input (alu destination1) [oc8051_alu.des1]
// wr (in) write [oc8051_decoder.wr -r]
// wr_bit (in) write bit addresable [oc8051_decoder.bit_addr -r]
// data_out (out) data output [oc8051_ram_rd_sel.ri, oc8051_ram_wr_sel.ri -r]
// sel (in) select register [oc8051_op_select.op1_out[0] ]
// bank (in) select register bank: [oc8051_psw.data_out[4:3] ]
//
 
 
input clk, rst, wr, sel, wr_bit;
input [1:0] bank;
input [7:0] addr, data_in;
 
output [7:0] data_out;
 
reg [7:0] buff [7:0];
 
//
//write to buffer
always @(posedge clk or posedge rst)
begin
if (rst) begin
buff[3'b000] = #1 8'h00;
buff[3'b001] = #1 8'h00;
buff[3'b010] = #1 8'h00;
buff[3'b011] = #1 8'h00;
buff[3'b100] = #1 8'h00;
buff[3'b101] = #1 8'h00;
buff[3'b110] = #1 8'h00;
buff[3'b111] = #1 8'h00;
end else begin
if ((wr) & !(wr_bit)) begin
case (addr)
8'h00: buff[3'b000] = #1 data_in;
8'h01: buff[3'b001] = #1 data_in;
8'h08: buff[3'b010] = #1 data_in;
8'h09: buff[3'b011] = #1 data_in;
8'h10: buff[3'b100] = #1 data_in;
8'h11: buff[3'b101] = #1 data_in;
8'h18: buff[3'b110] = #1 data_in;
8'h19: buff[3'b111] = #1 data_in;
endcase
end
end
end
 
//
//read from buffer
assign data_out = (({3'b000, bank, 2'b00, sel}==addr) & (wr)) ?
data_in : buff[{bank, sel}];
 
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 indirect address ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// Contains ragister 0 and register 1. used for indirrect ////
//// addressing. ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/09/30 17:33:59 simont
// prepared header
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
 
module oc8051_indi_addr (clk, rst, rd_addr, wr_addr, data_in, wr, wr_bit, rn_out, ri_out, sel, bank);
//
// clk (in) clock
// rst (in) reset
// addr (in) write address [oc8051_ram_wr_sel.out]
// data_in (in) data input (alu destination1) [oc8051_alu.des1]
// wr (in) write [oc8051_decoder.wr -r]
// wr_bit (in) write bit addresable [oc8051_decoder.bit_addr -r]
// data_out (out) data output [oc8051_ram_rd_sel.ri, oc8051_ram_wr_sel.ri -r]
// sel (in) select register [oc8051_op_select.op1_out[0] ]
// bank (in) select register bank: [oc8051_psw.data_out[4:3] ]
//
 
 
input clk, rst, wr, wr_bit;
input [1:0] bank;
input [2:0] sel;
input [7:0] data_in;
input [7:0] rd_addr, wr_addr;
 
output [7:0] rn_out, ri_out;
 
reg [7:0] rn_out;
 
reg [7:0] buff [31:0];
reg wr_bit_r;
wire rd_ram, rd_ind;
 
 
wire tmp;
assign tmp = ~|wr_addr[7:5];
//
//write to buffer
always @(posedge clk or posedge rst)
begin
if (rst) begin
buff[0] <= #1 8'h00;
buff[1] <= #1 8'h00;
buff[2] <= #1 8'h00;
buff[3] <= #1 8'h00;
buff[4] <= #1 8'h00;
buff[5] <= #1 8'h00;
buff[6] <= #1 8'h00;
buff[7] <= #1 8'h00;
buff[8] <= #1 8'h00;
buff[9] <= #1 8'h00;
buff[10] <= #1 8'h00;
buff[11] <= #1 8'h00;
buff[12] <= #1 8'h00;
buff[13] <= #1 8'h00;
buff[14] <= #1 8'h00;
buff[15] <= #1 8'h00;
buff[16] <= #1 8'h00;
buff[17] <= #1 8'h00;
buff[18] <= #1 8'h00;
buff[19] <= #1 8'h00;
buff[20] <= #1 8'h00;
buff[21] <= #1 8'h00;
buff[22] <= #1 8'h00;
buff[23] <= #1 8'h00;
buff[24] <= #1 8'h00;
buff[25] <= #1 8'h00;
buff[26] <= #1 8'h00;
buff[27] <= #1 8'h00;
buff[28] <= #1 8'h00;
buff[29] <= #1 8'h00;
buff[30] <= #1 8'h00;
buff[31] <= #1 8'h00;
end else if ((wr) && !(wr_bit_r) && (tmp)) begin
buff[wr_addr[4:0]] <= #1 data_in;
end
end
 
//
//read from buffer
assign rd_ram = (rd_addr== wr_addr);
assign rd_ind = ({3'h0, bank, 2'b00, sel[0]}==wr_addr);
assign ri_out = ( rd_ind & (wr) & !wr_bit) ? data_in : buff[{bank, 2'b00, sel[0]}];
 
always @(posedge clk or posedge rst)
if (rst) begin
rn_out <= #1 8'h00;
end else if ( rd_ram & (wr) & !wr_bit) begin
rn_out <= #1 data_in;
end else begin
rn_out <= #1 buff[rd_addr[4:0]];
end
 
 
always @(posedge clk or posedge rst)
if (rst) begin
wr_bit_r <= #1 1'b0;
end else begin
wr_bit_r <= #1 wr_bit;
end
 
endmodule
/trunk/rtl/verilog/oc8051_alu.v
1,360 → 1,366
//////////////////////////////////////////////////////////////////////
//// ////
//// alu for 8051 Core ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// Implementation of aritmetic unit according to ////
//// 8051 IP core specification document. Uses divide.v and ////
//// multiply.v ////
//// ////
//// To Do: ////
//// pc signed add ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
 
module oc8051_alu (clk, rst, op_code, src1, src2, src3, srcCy, srcAc, bit_in, des1, des2, des1_r, desCy, desAc, desOv);
//
// op_code (in) operation code [oc8051_decoder.alu_op -r]
// src1 (in) first operand [oc8051_alu_src1_sel.des]
// src2 (in) second operand [oc8051_alu_src2_sel.des]
// src3 (in) third operand [oc8051_alu_src3_sel.des]
// srcCy (in) carry input [oc8051_cy_select.data_out]
// srcAc (in) auxiliary carry input [oc8051_psw.data_out[6] ]
// bit_in (in) bit input, used for logic operatins on bits [oc8051_ram_sel.bit_out]
// des1 (out)
// des1_r (out)
// des2 (out)
// desCy (out) carry output [oc8051_ram_top.bit_data_in, oc8051_acc.bit_in, oc8051_b_register.bit_in, oc8051_psw.cy_in, oc8051_ports.bit_in]
// desAc (out) auxiliary carry output [oc8051_psw.ac_in]
// desOv (out) Overflow output [oc8051_psw.ov_in]
//
 
input srcCy, srcAc, bit_in, clk, rst; input [3:0] op_code; input [7:0] src1, src2, src3;
output desCy, desAc, desOv;
output [7:0] des1, des2;
output [7:0] des1_r;
 
reg desCy, desAc, desOv;
reg [7:0] des1, des2;
 
reg [7:0] des1_r;
 
//
//add
//
wire [4:0] add1, add2, add3, add4;
wire [3:0] add5, add6, add7, add8;
wire [1:0] add9, adda, addb, addc;
 
//
//sub
//
wire [4:0] sub1, sub2, sub3, sub4;
wire [3:0] sub5, sub6, sub7, sub8;
wire [1:0] sub9, suba, subb, subc;
 
//
//mul
//
wire [7:0] mulsrc1, mulsrc2;
wire mulOv;
reg enable_mul;
 
//
//div
//
wire [7:0] divsrc1,divsrc2;
wire divOv;
reg enable_div;
 
//
//da
//
reg da_tmp;
//reg [8:0] da1;
 
oc8051_multiply oc8051_mul1(.clk(clk), .rst(rst), .enable(enable_mul), .src1(src1), .src2(src2), .des1(mulsrc1), .des2(mulsrc2), .desOv(mulOv));
oc8051_divide oc8051_div1(.clk(clk), .rst(rst), .enable(enable_div), .src1(src1), .src2(src2), .des1(divsrc1), .des2(divsrc2), .desOv(divOv));
 
/* Add */
assign add1 = {1'b0,src1[3:0]};
assign add2 = {1'b0,src2[3:0]};
assign add3 = {3'b000,srcCy};
assign add4 = add1+add2+add3;
 
assign add5 = {1'b0,src1[6:4]};
assign add6 = {1'b0,src2[6:4]};
assign add7 = {1'b0,1'b0,1'b0,add4[4]};
assign add8 = add5+add6+add7;
 
assign add9 = {1'b0,src1[7]};
assign adda = {1'b0,src2[7]};
assign addb = {1'b0,add8[3]};
assign addc = add9+adda+addb;
 
/* Sub */
assign sub1 = {1'b1,src1[3:0]};
assign sub2 = {1'b0,src2[3:0]};
assign sub3 = {1'b0,1'b0,1'b0,srcCy};
assign sub4 = sub1-sub2-sub3;
 
assign sub5 = {1'b1,src1[6:4]};
assign sub6 = {1'b0,src2[6:4]};
assign sub7 = {1'b0,1'b0,1'b0, !sub4[4]};
assign sub8 = sub5-sub6-sub7;
 
assign sub9 = {1'b1,src1[7]};
assign suba = {1'b0,src2[7]};
assign subb = {1'b0,!sub8[3]};
assign subc = sub9-suba-subb;
 
 
always @(op_code or src1 or src2 or srcCy or srcAc or bit_in or src3 or mulsrc1 or mulsrc2 or mulOv or divsrc1 or divsrc2 or divOv or addc or add8 or add4 or sub4 or sub8 or subc or da_tmp)
begin
 
case (op_code)
//operation add
`OC8051_ALU_ADD: begin
des1 = {addc[0],add8[2:0],add4[3:0]};
des2 = src3+ {7'b0, addc[1]};
desCy = addc[1];
desAc = add4[4];
desOv = addc[1] ^ add8[3];
 
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation subtract
`OC8051_ALU_SUB: begin
des1 = {subc[0],sub8[2:0],sub4[3:0]};
des2 = 8'h00;
desCy = !subc[1];
desAc = !sub4[4];
desOv = !subc[1] ^ sub8[3];
 
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation multiply
`OC8051_ALU_MUL: begin
des1 = mulsrc1;
des2 = mulsrc2;
desOv = mulOv;
desCy = 1'b0;
desAc = 1'bx;
enable_mul = 1'b1;
enable_div = 1'b0;
end
//operation divide
`OC8051_ALU_DIV: begin
des1 = divsrc1;
des2 = divsrc2;
desOv = divOv;
desAc = 1'bx;
desCy = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b1;
end
//operation decimal adjustment
`OC8051_ALU_DA: begin
/* da1= {1'b0, src1};
if (srcAc==1'b1 | da1[3:0]>4'b1001) da1= da1+ 9'b0_0000_0110;
 
da1[8]= da1[8] | srcCy;
 
if (da1[8]==1'b1) da1=da1+ 9'b0_0110_0000;
des1=da1[7:0];
des2=8'h00;
desCy=da1[8];*/
 
if (srcAc==1'b1 | src1[3:0]>4'b1001) {da_tmp, des1[3:0]} = {1'b0, src1[3:0]}+ 5'b00110;
else {da_tmp, des1[3:0]} = {1'b0, src1[3:0]};
 
if (srcCy==1'b1 | src1[7:4]>4'b1001)
{desCy, des1[7:4]} = {srcCy, src1[7:4]}+ 5'b00110 + {4'b0, da_tmp};
else {desCy, des1[7:4]} = {srcCy, src1[7:4]} + {4'b0, da_tmp};
 
des2 = 8'h00;
desAc = 1'b0;
desOv = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation not
// bit operation not
`OC8051_ALU_NOT: begin
des1 = ~src1;
des2 = 8'h00;
desCy = !srcCy;
desAc = 1'bx;
desOv = 1'bx;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation and
//bit operation and
`OC8051_ALU_AND: begin
des1 = src1 & src2;
des2 = 8'h00;
desCy = srcCy & bit_in;
desAc = 1'bx;
desOv = 1'bx;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation xor
// bit operation xor
`OC8051_ALU_XOR: begin
des1 = src1 ^ src2;
des2 = 8'h00;
desCy = srcCy ^ bit_in;
desAc = 1'bx;
desOv = 1'bx;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation or
// bit operation or
`OC8051_ALU_OR: begin
des1 = src1 | src2;
des2 = 8'h00;
desCy = srcCy | bit_in;
desAc = 1'bx;
desOv = 1'bx;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation rotate left
// bit operation cy= cy or (not ram)
`OC8051_ALU_RL: begin
des1 = {src1[6:0], src1[7]};
des2 = 8'h00;
desCy = srcCy | !bit_in;
desAc = 1'bx;
desOv = 1'bx;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation rotate left with carry and swap nibbles
`OC8051_ALU_RLC: begin
des1 = {src1[6:0], srcCy};
des2 = {src1[3:0], src1[7:4]};
desCy = src1[7];
desAc = 1'b0;
desOv = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation rotate right
`OC8051_ALU_RR: begin
des1 = {src1[0], src1[7:1]};
des2 = 8'h00;
desCy = srcCy & !bit_in;
desAc = 1'b0;
desOv = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation rotate right with carry
`OC8051_ALU_RRC: begin
des1 = {srcCy, src1[7:1]};
des2 = 8'h00;
desCy = src1[0];
desAc = 1'b0;
desOv = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation pcs Add
`OC8051_ALU_PCS: begin
if (src1[7]) begin
des1 = src2+src1;
des2 = src3;
end else {des2, des1} = {src3,src2} + {8'h00, src1};
desCy = 1'b0;
desAc = 1'b0;
desOv = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation exchange
//if carry = 0 exchange low order digit
`OC8051_ALU_XCH: begin
if (srcCy)
begin
des1 = src2;
des2 = src1;
end else begin
des1 = {src1[7:4],src2[3:0]};
des2 = {src2[7:4],src1[3:0]};
end
desCy = 1'b0;
desAc = 1'b0;
desOv = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b0;
end
default: begin
des1 = src1;
des2 = src2;
desCy = srcCy;
desAc = srcAc;
desOv = 1'bx;
enable_mul = 1'b0;
enable_div = 1'b0;
end
endcase
end
 
always @(posedge clk or posedge rst)
if (rst) begin
des1_r <= #1 8'h0;
end else begin
des1_r <= #1 des1;
end
 
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// alu for 8051 Core ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// Implementation of aritmetic unit according to ////
//// 8051 IP core specification document. Uses divide.v and ////
//// multiply.v ////
//// ////
//// To Do: ////
//// pc signed add ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2002/09/30 17:33:59 simont
// prepared header
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
 
module oc8051_alu (clk, rst, op_code, rd, src1, src2, src3, srcCy, srcAc, bit_in, des1, des2, des1_r, desCy,
desAc, desOv);
//
// op_code (in) operation code [oc8051_decoder.alu_op -r]
// src1 (in) first operand [oc8051_alu_src1_sel.des]
// src2 (in) second operand [oc8051_alu_src2_sel.des]
// src3 (in) third operand [oc8051_alu_src3_sel.des]
// srcCy (in) carry input [oc8051_cy_select.data_out]
// srcAc (in) auxiliary carry input [oc8051_psw.data_out[6] ]
// bit_in (in) bit input, used for logic operatins on bits [oc8051_ram_sel.bit_out]
// des1 (out)
// des1_r (out)
// des2 (out)
// desCy (out) carry output [oc8051_ram_top.bit_data_in, oc8051_acc.bit_in, oc8051_b_register.bit_in, oc8051_psw.cy_in, oc8051_ports.bit_in]
// desAc (out) auxiliary carry output [oc8051_psw.ac_in]
// desOv (out) Overflow output [oc8051_psw.ov_in]
//
 
input srcCy, srcAc, bit_in, clk, rst, rd;
input [3:0] op_code;
input [7:0] src1, src2, src3;
output desCy, desAc, desOv;
output [7:0] des1, des2;
output [7:0] des1_r;
 
reg desCy, desAc, desOv;
reg [7:0] des1, des2;
 
reg [7:0] des1_r;
 
 
reg rd_r;
//
//add
//
wire [4:0] add1, add2, add3, add4;
wire [3:0] add5, add6, add7, add8;
wire [1:0] add9, adda, addb, addc;
 
//
//sub
//
wire [4:0] sub1, sub2, sub3, sub4;
wire [3:0] sub5, sub6, sub7, sub8;
wire [1:0] sub9, suba, subb, subc;
 
//
//mul
//
wire [7:0] mulsrc1, mulsrc2;
wire mulOv;
reg enable_mul;
 
//
//div
//
wire [7:0] divsrc1,divsrc2;
wire divOv;
reg enable_div;
 
//
//da
//
reg da_tmp;
//reg [8:0] da1;
 
oc8051_multiply oc8051_mul1(.clk(clk), .rst(rst), .enable(enable_mul), .src1(src1), .src2(src2), .des1(mulsrc1), .des2(mulsrc2), .desOv(mulOv));
oc8051_divide oc8051_div1(.clk(clk), .rst(rst), .enable(enable_div), .src1(src1), .src2(src2), .des1(divsrc1), .des2(divsrc2), .desOv(divOv));
 
/* Add */
assign add1 = {1'b0,src1[3:0]};
assign add2 = {1'b0,src2[3:0]};
assign add3 = {3'b000,srcCy};
assign add4 = add1+add2+add3;
 
assign add5 = {1'b0,src1[6:4]};
assign add6 = {1'b0,src2[6:4]};
assign add7 = {1'b0,1'b0,1'b0,add4[4]};
assign add8 = add5+add6+add7;
 
assign add9 = {1'b0,src1[7]};
assign adda = {1'b0,src2[7]};
assign addb = {1'b0,add8[3]};
assign addc = add9+adda+addb;
 
/* Sub */
assign sub1 = {1'b1,src1[3:0]};
assign sub2 = {1'b0,src2[3:0]};
assign sub3 = {1'b0,1'b0,1'b0,srcCy};
assign sub4 = sub1-sub2-sub3;
 
assign sub5 = {1'b1,src1[6:4]};
assign sub6 = {1'b0,src2[6:4]};
assign sub7 = {1'b0,1'b0,1'b0, !sub4[4]};
assign sub8 = sub5-sub6-sub7;
 
assign sub9 = {1'b1,src1[7]};
assign suba = {1'b0,src2[7]};
assign subb = {1'b0,!sub8[3]};
assign subc = sub9-suba-subb;
 
 
always @(op_code or src1 or src2 or srcCy or srcAc or bit_in or src3 or mulsrc1 or mulsrc2 or mulOv or divsrc1 or divsrc2 or divOv or addc or add8 or add4 or sub4 or sub8 or subc or da_tmp)
begin
 
case (op_code)
//operation add
`OC8051_ALU_ADD: begin
des1 = {addc[0],add8[2:0],add4[3:0]};
des2 = src3+ {7'b0, addc[1]};
desCy = addc[1];
desAc = add4[4];
desOv = addc[1] ^ add8[3];
 
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation subtract
`OC8051_ALU_SUB: begin
des1 = {subc[0],sub8[2:0],sub4[3:0]};
des2 = 8'h00;
desCy = !subc[1];
desAc = !sub4[4];
desOv = !subc[1] ^ sub8[3];
 
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation multiply
`OC8051_ALU_MUL: begin
des1 = mulsrc1;
des2 = mulsrc2;
desOv = mulOv;
desCy = 1'b0;
desAc = 1'bx;
enable_mul = 1'b1;
enable_div = 1'b0;
end
//operation divide
`OC8051_ALU_DIV: begin
des1 = divsrc1;
des2 = divsrc2;
desOv = divOv;
desAc = 1'bx;
desCy = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b1;
end
//operation decimal adjustment
`OC8051_ALU_DA: begin
 
if (srcAc==1'b1 | src1[3:0]>4'b1001) {da_tmp, des1[3:0]} = {1'b0, src1[3:0]}+ 5'b00110;
else {da_tmp, des1[3:0]} = {1'b0, src1[3:0]};
 
if (srcCy==1'b1 | src1[7:4]>4'b1001)
{desCy, des1[7:4]} = {srcCy, src1[7:4]}+ 5'b00110 + {4'b0, da_tmp};
else {desCy, des1[7:4]} = {srcCy, src1[7:4]} + {4'b0, da_tmp};
 
des2 = 8'h00;
desAc = 1'b0;
desOv = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation not
// bit operation not
`OC8051_ALU_NOT: begin
des1 = ~src1;
des2 = 8'h00;
desCy = !srcCy;
desAc = 1'bx;
desOv = 1'bx;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation and
//bit operation and
`OC8051_ALU_AND: begin
des1 = src1 & src2;
des2 = 8'h00;
desCy = srcCy & bit_in;
desAc = 1'bx;
desOv = 1'bx;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation xor
// bit operation xor
`OC8051_ALU_XOR: begin
des1 = src1 ^ src2;
des2 = 8'h00;
desCy = srcCy ^ bit_in;
desAc = 1'bx;
desOv = 1'bx;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation or
// bit operation or
`OC8051_ALU_OR: begin
des1 = src1 | src2;
des2 = 8'h00;
desCy = srcCy | bit_in;
desAc = 1'bx;
desOv = 1'bx;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation rotate left
// bit operation cy= cy or (not ram)
`OC8051_ALU_RL: begin
des1 = {src1[6:0], src1[7]};
des2 = 8'h00;
desCy = srcCy | !bit_in;
desAc = 1'bx;
desOv = 1'bx;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation rotate left with carry and swap nibbles
`OC8051_ALU_RLC: begin
des1 = {src1[6:0], srcCy};
des2 = {src1[3:0], src1[7:4]};
desCy = src1[7];
desAc = 1'b0;
desOv = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation rotate right
`OC8051_ALU_RR: begin
des1 = {src1[0], src1[7:1]};
des2 = 8'h00;
desCy = srcCy & !bit_in;
desAc = 1'b0;
desOv = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation rotate right with carry
`OC8051_ALU_RRC: begin
des1 = {srcCy, src1[7:1]};
des2 = 8'h00;
desCy = src1[0];
desAc = 1'b0;
desOv = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation pcs Add
`OC8051_ALU_PCS: begin
if (src1[7]) begin
des1 = src2+src1;
des2 = src3;
end else {des2, des1} = {src3,src2} + {8'h00, src1};
desCy = 1'b0;
desAc = 1'b0;
desOv = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation exchange
//if carry = 0 exchange low order digit
`OC8051_ALU_XCH: begin
if (srcCy)
begin
des1 = src2;
des2 = src1;
end else begin
des1 = {src1[7:4],src2[3:0]};
des2 = {src2[7:4],src1[3:0]};
end
desCy = 1'b0;
desAc = 1'b0;
desOv = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b0;
end
default: begin
des1 = src1;
des2 = src2;
desCy = srcCy;
desAc = srcAc;
desOv = 1'bx;
enable_mul = 1'b0;
enable_div = 1'b0;
end
endcase
end
 
always @(posedge clk or posedge rst)
if (rst) begin
des1_r <= #1 8'h0;
end else if (rd_r) begin
des1_r <= #1 des1;
end
 
always @(posedge clk or posedge rst)
if (rst) begin
rd_r <= #1 8'h0;
end else begin
rd_r <= #1 rd;
end
 
endmodule
/trunk/rtl/verilog/oc8051_sp.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/11/05 17:23:54 simont
// add module oc8051_sfr, 256 bytes internal ram
//
// Revision 1.3 2002/09/30 17:33:59 simont
// prepared header
//
57,60 → 60,61
 
 
 
module oc8051_sp (clk, rst, ram_rd_sel, ram_wr_sel, wr_addr, wr, wr_bit, data_in, data_out);
//
// clk (in) clock
// rst (in) reset
// ram_rd_sel (in) ram read select, used tu calculate next value [oc8051_decoder.ram_rd_sel]
// ram_wr_sel (in) ram write select, used tu calculate next value [oc8051_decoder.ram_wr_sel -r]
// wr (in) write [oc8051_decoder.wr -r]
// wr_bit (in) write bit addresable [oc8051_decoder.bit_addr -r]
// data_in (in) data input [oc8051_alu.des1]
// wr_addr (in) write address (if is addres of sp and white high must be written to sp) [oc8051_ram_wr_sel.out]
// data_out (out) data output
//
module oc8051_sp (clk, rst, ram_rd_sel, ram_wr_sel, wr_addr, wr, wr_bit, data_in, data_out, sp_out, sp_w);
 
 
input clk, rst, wr, wr_bit;
input [1:0] ram_rd_sel;
input [2:0] ram_wr_sel;
input [2:0] ram_rd_sel, ram_wr_sel;
input [7:0] data_in, wr_addr;
output [7:0] data_out;
output [7:0] sp_out, sp_w;
 
reg [7:0] data_out;
reg [7:0] temp;
reg pop, write;
wire [7:0] temp1;
reg [7:0] sp_out, sp_w;
reg pop;
wire write;
wire [7:0] sp_t;
 
assign temp1 = write ? data_in : temp;
reg [7:0] sp;
 
always @(wr_addr or wr or wr_bit)
begin
if ((wr_addr==`OC8051_SFR_SP) & (wr) & !(wr_bit))
write = 1'b1;
else
write = 1'b0;
end
 
assign write = ((wr_addr==`OC8051_SFR_SP) & (wr) & !(wr_bit));
 
assign sp_t= write ? data_in : sp;
 
assign data_out = sp;
 
always @(posedge clk or posedge rst)
begin
if (rst)
temp <= #1 `OC8051_RST_SP;
sp <= #1 `OC8051_RST_SP;
else if (write)
sp <= #1 data_in;
else
temp <= #1 data_out;
sp <= #1 sp_out;
end
 
always @(temp1 or ram_wr_sel or pop or write)
 
always @(sp or ram_wr_sel)
begin
//
// push
if (ram_wr_sel==`OC8051_RWS_SP) data_out = temp1+8'h01;
else if (write) data_out = temp1;
else data_out = temp1 - {7'b0, pop};
if (ram_wr_sel==`OC8051_RWS_SP) sp_w = sp + 8'h01;
else sp_w = sp;
 
end
 
 
always @(sp_t or ram_wr_sel or pop or write)
begin
//
// push
if (write) sp_out = sp_t;
else if (ram_wr_sel==`OC8051_RWS_SP) sp_out = sp_t + 8'h01;
else sp_out = sp_t - {7'b0, pop};
 
end
 
 
always @(posedge clk or posedge rst)
begin
if (rst)
/trunk/rtl/verilog/oc8051_b_register.v
1,107 → 1,114
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 cores b register ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// b register for 8051 core ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_b_register (clk, rst, bit_in, bit_out, data_in, wr, wr_bit, wr_addr, rd_addr, data_out);
//
// clk (in) clock
// rst (in) reset
// bit_in (in) bit input - used in case of writing bits to b register (bit adddressable memory space - alu carry) [oc8051_alu.desCy]
// data_in (in) data input - used to write to b register [oc8051_alu.des1]
// wr (in) write - actine high [oc8051_decoder.wr -r]
// wr_bit (in) write bit addresable - actine high [oc8051_decoder.bit_addr -r]
// wr_addr (in) write address [oc8051_ram_wr_sel.out]
// data_out (out) data output [oc8051_ram_sel.b_reg]
//
 
 
input clk, rst, wr, wr_bit, bit_in;
input [2:0] rd_addr;
input [7:0] wr_addr, data_in;
 
output bit_out;
output [7:0] data_out;
 
reg bit_out;
reg [7:0] data_out;
 
//
//writing to b
//must check if write high and correct address
always @(posedge clk or posedge rst)
begin
if (rst)
data_out <= #1 `OC8051_RST_B;
else if (wr) begin
if (!wr_bit) begin
if (wr_addr==`OC8051_SFR_B)
data_out <= #1 data_in;
end else begin
if (wr_addr[7:3]==`OC8051_SFR_B_B)
data_out[wr_addr[2:0]] <= #1 bit_in;
end
end
end
 
always @(posedge clk or posedge rst)
begin
if (rst) bit_out <= #1 1'b0;
else if ((rd_addr==wr_addr[2:0]) & wr & wr_bit) begin
bit_out <= #1 bit_in;
end else if ((wr_addr==`OC8051_SFR_B) & wr & !wr_bit) begin
bit_out <= #1 data_in[rd_addr];
end else bit_out <= #1 data_out[rd_addr];
end
 
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 cores b register ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// b register for 8051 core ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2002/09/30 17:33:59 simont
// prepared header
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_b_register (clk, rst, bit_in, bit_out, data_in, wr, wr_bit,
wr_addr, rd_addr, data_out, wr_sfr);
//
// clk (in) clock
// rst (in) reset
// bit_in (in) bit input - used in case of writing bits to b register (bit adddressable memory space - alu carry) [oc8051_alu.desCy]
// data_in (in) data input - used to write to b register [oc8051_alu.des1]
// wr (in) write - actine high [oc8051_decoder.wr -r]
// wr_bit (in) write bit addresable - actine high [oc8051_decoder.bit_addr -r]
// wr_addr (in) write address [oc8051_ram_wr_sel.out]
// data_out (out) data output [oc8051_ram_sel.b_reg]
// wr_sfr
//
 
 
input clk, rst, wr, wr_bit, bit_in;
input [2:0] rd_addr, wr_sfr;
input [7:0] wr_addr, data_in;
 
output bit_out;
output [7:0] data_out;
 
reg bit_out;
reg [7:0] data_out;
 
//
//writing to b
//must check if write high and correct address
always @(posedge clk or posedge rst)
begin
if (rst)
data_out <= #1 `OC8051_RST_B;
else if (wr_sfr==`OC8051_WRS_BA)
data_out <= #1 data_in;
else if (wr) begin
if (!wr_bit) begin
if (wr_addr==`OC8051_SFR_B)
data_out <= #1 data_in;
end else begin
if (wr_addr[7:3]==`OC8051_SFR_B_B)
data_out[wr_addr[2:0]] <= #1 bit_in;
end
end
end
 
always @(posedge clk or posedge rst)
begin
if (rst) bit_out <= #1 1'b0;
else if ((rd_addr==wr_addr[2:0]) & wr & wr_bit) begin
bit_out <= #1 bit_in;
end else if ((wr_addr==`OC8051_SFR_B) & wr & !wr_bit) begin
bit_out <= #1 data_in[rd_addr];
end else bit_out <= #1 data_out[rd_addr];
end
 
endmodule
/trunk/rtl/verilog/oc8051_acc.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2002/11/05 17:23:54 simont
// add module oc8051_sfr, 256 bytes internal ram
//
// Revision 1.7 2002/09/30 17:33:59 simont
// prepared header
//
56,8 → 59,8
`include "oc8051_defines.v"
 
 
module oc8051_acc (clk, rst, bit_in, data_in, data2_in, wr, wr_bit, wad2, wr_addr, rd_addr,
data_out, bit_out, p, rd_x, xdata);
module oc8051_acc (clk, rst, bit_in, data_in, data2_in, wr, wr_bit, wr_addr, rd_addr,
data_out, bit_out, p, wr_sfr);
// clk (in) clock
// rst (in) reset
// bit_in (in) bit input - used in case of writing bits to acc (bit adddressable memory space - alu carry) [oc8051_alu.desCy]
65,18 → 68,17
// data2_in (in) data 2 input - write to acc, from alu detination 2 - instuctions mul and div [oc8051_alu.des2]
// wr (in) write - actine high [oc8051_decoder.wr -r]
// wr_bit (in) write bit addresable - actine high [oc8051_decoder.bit_addr -r]
// wad2 (in) write data 2 [oc8051_decoder.wad2 -r]
// wr_addr (in) write address (if is addres of acc and white high must be written to acc) [oc8051_ram_wr_sel.out]
// data_out (out) data output [oc8051_alu_src1_sel.acc oc8051_alu_src2_sel.acc oc8051_comp.acc oc8051_ram_sel.acc]
// p (out) parity [oc8051_psw.p]
// rd_x (in) read external
// xdata (in) external data input
// mx_ext (in) mx extension
// wr_sfr
//
 
 
input clk, rst, wr, wr_bit, wad2, bit_in, rd_x;
input [2:0] rd_addr;
input [7:0] wr_addr, data_in, data2_in, xdata;
input clk, rst, wr, wr_bit, bit_in;
input [2:0] rd_addr, wr_sfr;
input [7:0] wr_addr, data_in, data2_in;
 
output p, bit_out;
output [7:0] data_out;
95,10 → 97,10
begin
if (rst)
data_out <= #1 `OC8051_RST_ACC;
else if (rd_x)
data_out <= #1 xdata;
else if (wad2)
else if ((wr_sfr==`OC8051_WRS_ACC2) || (wr_sfr==`OC8051_WRS_BA))
data_out <= #1 data2_in;
else if ((wr_sfr==`OC8051_WRS_ACC1))
data_out <= #1 data_in;
else if (wr) begin
if (!wr_bit) begin
if (wr_addr==`OC8051_SFR_ACC)
115,8 → 117,10
if (rst) bit_out <= #1 1'b0;
else if ((rd_addr==wr_addr[2:0]) & wr & wr_bit) begin
bit_out <= #1 bit_in;
end else if ((wr_addr==`OC8051_SFR_ACC) & wr & !wr_bit) begin
end else if (((wr_addr==`OC8051_SFR_ACC) & wr & !wr_bit) || (wr_sfr==`OC8051_WRS_ACC1)) begin
bit_out <= #1 data_in[rd_addr];
end else if ((wr_sfr==`OC8051_WRS_ACC2) || (wr_sfr==`OC8051_WRS_BA)) begin
bit_out <= #1 data2_in[rd_addr];
end else bit_out <= #1 data_out[rd_addr];
end
 
/trunk/rtl/verilog/oc8051_sfr.v
44,7 → 44,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/11/05 17:22:27 simont
// initial import
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
51,10 → 54,10
// synopsys translate_on
 
 
module oc8051_sfr (rst, clk, adr0, adr1, dat0, dat1, dat2, we, bit_in, bit_out, wr_bit, wad2, acc,
rd_x, xdata, ram_wr_sel, ram_rd_sel, sp, bank_sel, desAc, desOv, psw_set, srcAc, cy, rmw,
p0_out, p1_out, p2_out, p3_out, p0_in, p1_in, p2_in, p3_in, rxd, txd, int_ack, intr, int0,
int1, reti, int_src, t0, t1, dptr_hi, dptr_lo);
module oc8051_sfr (rst, clk, adr0, adr1, dat0, dat1, dat2, we, bit_in, bit_out, wr_bit,
wr_sfr, acc, ram_wr_sel, ram_rd_sel, sp, sp_w, bank_sel, desAc, desOv, psw_set, srcAc, cy, rmw,
p0_out, p1_out, p2_out, p3_out, p0_in, p1_in, p2_in, p3_in, rxd, txd, int_ack, intr, int0,
int1, reti, int_src, t0, t1, dptr_hi, dptr_lo, t2, t2ex);
//
// rst (in) reset - pin
// clk (in) clock - pin
68,13 → 71,11
// wr_bit
// ram_rd_sel
// ram_wr_sel
// wr_sfr
//////////
//
// acc:
// wad2
// acc
// rd_x
// xdata
//////////
//
// sp:
112,6 → 113,8
// timers/counters:
// t0
// t1
// t2
// t2ex
//
//////////
//
118,37 → 121,47
// dptr:
// dptr_hi
// dptr_lo
//
//////////
//
 
 
 
 
input rst, clk, we, bit_in, desAc, desOv, rmw, rxd, t2, t2ex;
input int_ack, int0, int1, reti, wr_bit, t0, t1;
input [1:0] psw_set;
input [2:0] ram_rd_sel, ram_wr_sel, wr_sfr;
input [7:0] adr0, adr1, dat1, dat2, p0_in, p1_in, p2_in, p3_in;
 
input rst, clk, we, bit_in, wad2, desAc, desOv, rmw, rxd, int_ack, int0, int1, reti, wr_bit, rd_x;
input [1:0] ram_rd_sel, psw_set;
input [2:0] ram_wr_sel;
input [7:0] adr0, adr1, dat1, dat2, p0_in, p1_in, p2_in, p3_in, xdata;
output bit_out, txd, intr, srcAc, cy;
output [1:0] bank_sel;
output [7:0] dat0, p0_out, p1_out, p2_out, p3_out, int_src, dptr_hi, dptr_lo, acc;
output [7:0] sp, sp_w;
 
output bit_out, txd, intr, t0, t1, srcAc, cy;
output [1:0] bank_sel;
output [7:0] dat0, p0_out, p1_out, p2_out, p3_out, int_src, dptr_hi, dptr_lo, acc, sp;
 
reg bit_out;
reg [7:0] dat0, sp_r, adr0_r;
reg [7:0] dat0, adr0_r;
 
reg wr_bit_r;
reg [2:0] ram_wr_sel_r;
wire acc_bit, b_bit, psw_bit, port_bit, uart_bit, int_bit;
wire acc_bit, b_bit, psw_bit, port_bit, uart_bit, int_bit, tc2_bit, pca_bit;
wire p, int_uart, tf0, tf1, tr0, tr1;
wire [7:0] b_reg, psw, ports, uart, int_out, tc_out;
wire dps, rclk, tclk, brate2, tc2_int;
wire [7:0] b_reg, psw, ports, uart, int_out, tc_out, tc2, sp_out;
 
 
assign cy = psw[7];
assign srcAc = psw [6];
 
 
 
//
// accumulator
// ACC
oc8051_acc oc8051_acc1(.clk(clk), .rst(rst), .bit_in(bit_in), .data_in(dat1),
.data2_in(dat2), .wr(we), .wr_bit(wr_bit), .wad2(wad2),
.wr_addr(adr1), .rd_addr(adr0[2:0]), .data_out(acc), .bit_out(acc_bit), .p(p),
.rd_x(rd_x), .xdata(xdata));
.data2_in(dat2), .wr(we), .wr_bit(wr_bit_r), .wr_sfr(wr_sfr),
.wr_addr(adr1), .rd_addr(adr0[2:0]), .data_out(acc), .bit_out(acc_bit), .p(p));
 
 
//
155,28 → 168,29
// b register
// B
oc8051_b_register oc8051_b_register (.clk(clk), .rst(rst), .bit_in(bit_in), .bit_out(b_bit),
.data_in(dat1), .wr(we), .wr_bit(wr_bit), .wr_addr(adr1), .rd_addr(adr0[2:0]),
.data_out(b_reg));
.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .wr_addr(adr1), .rd_addr(adr0[2:0]),
.data_out(b_reg), .wr_sfr(wr_sfr));
 
//
//stack pointer
// SP
oc8051_sp oc8051_sp1(.clk(clk), .rst(rst), .ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel),
.wr_addr(adr1), .wr(we), .wr_bit(wr_bit), .data_in(dat1),
.data_out(sp));
.wr_addr(adr1), .wr(we), .wr_bit(wr_bit_r), .data_in(dat1),
.data_out(sp_out), .sp_out(sp), .sp_w(sp_w));
 
//
//data pointer
// DPTR, DPH, DPL
oc8051_dptr oc8051_dptr1(.clk(clk), .rst(rst), .addr(adr1), .data_in(dat1),
.data2_in(dat2), .wr(we), .wr_bit(wr_bit), .wd2(ram_wr_sel_r),
.data_hi(dptr_hi), .data_lo(dptr_lo));
.data2_in(dat2), .wr(we), .wr_bit(wr_bit_r),
.data_hi(dptr_hi), .data_lo(dptr_lo), .wr_sfr(wr_sfr));
 
 
//
//program status word
// PSW
oc8051_psw oc8051_psw1 (.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0[2:0]), .data_in(dat1),
.wr(we), .wr_bit(wr_bit), .data_out(psw), .bit_out(psw_bit), .p(p), .cy_in(bit_in),
.wr(we), .wr_bit(wr_bit_r), .data_out(psw), .bit_out(psw_bit), .p(p), .cy_in(bit_in),
.ac_in(desAc), .ov_in(desOv), .set(psw_set), .bank_sel(bank_sel));
 
//
183,7 → 197,7
// ports
// P0, P1, P2, P3
oc8051_ports oc8051_ports1(.clk(clk), .rst(rst), .bit_in(bit_in), .data_in(dat1), .wr(we),
.wr_bit(wr_bit), .wr_addr(adr1), .rd_addr(adr0), .rmw(rmw),
.wr_bit(wr_bit_r), .wr_addr(adr1), .rd_addr(adr0), .rmw(rmw),
.data_out(ports), .bit_out(port_bit), .p0_out(p0_out), .p1_out(p1_out),
.p2_out(p2_out), .p3_out(p3_out), .p0_in(p0_in), .p1_in(p1_in), .p2_in(p2_in),
.p3_in(p3_in));
192,8 → 206,8
// serial interface
// SCON, SBUF
oc8051_uart oc8051_uatr1 (.clk(clk), .rst(rst), .bit_in(bit_in), .rd_addr(adr0),
.data_in(dat1), .wr(we), .wr_bit(wr_bit), .wr_addr(adr1),
.data_out(uart), .bit_out(uart_bit), .rxd(rxd), .txd(txd), .intr(int_uart),
.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .wr_addr(adr1),
.data_out(uart), .bit_out(uart_bit), .rxd(rxd), .txd(txd), .intr(uart_int),
.t1_ow(tf1));
 
//
200,78 → 214,99
// interrupt control
// IP, IE, TCON
oc0851_int oc8051_int1 (.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0), .bit_in(bit_in),
.ack(int_ack), .intr(intr), .data_in(dat1), .data_out(int_out), .bit_out(int_bit),
.wr(we), .wr_bit(wr_bit), .tf0(tf0), .tf1(tf1), .ie0(int0), .ie1(int1),
.reti(reti), .int_vec(int_src), .tr0(tr0), .tr1(tr1), .uart(int_uart));
.ack(int_ack), .data_in(dat1), .data_out(int_out), .bit_out(int_bit),
.wr(we), .wr_bit(wr_bit_r),
.tf0(tf0), .tf1(tf1), .t2_int(tc2_int), .tr0(tr0), .tr1(tr1),
.ie0(int0), .ie1(int1),
.uart_int(uart_int),
.reti(reti), .intr(intr), .int_vec(int_src));
 
 
//
// timer/counter control
// TH0, TH1, TL0, TH1, TMOD
oc8051_tc oc8051_tc1(.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0),
.data_in(dat1), .wr(we), .wr_bit(wr_bit), .ie0(int0), .ie1(int1), .tr0(tr0),
.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .ie0(int0), .ie1(int1), .tr0(tr0),
.tr1(tr1), .t0(t0), .t1(t1), .data_out(tc_out), .tf0(tf0), .tf1(tf1));
 
//
// timer/counter 2
// TH2, TH2, RCAPL2L, RCAPL2H, T2CON, T2MOD
oc8051_tc2 oc8051_tc21(.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0_r), .data_in(dat1), .wr(we),
.wr_bit(wr_bit_r), .bit_in(bit_in), .t2(t2), .t2ex(t2ex), .data_out(tc2), .bit_out(tc2_bit),
.rclk(rclk), .tclk(tclk), .brate2(brate2), .tc2_int(tc2_int));
 
 
 
always @(posedge clk or posedge rst)
if (rst) begin
sp_r <= #1 8'h00;
adr0_r <= #1 8'h00;
ram_wr_sel_r <= #1 3'b000;
wr_bit_r <= #1 1'b0;
end else begin
sp_r <= #1 sp;
adr0_r <= #1 adr0;
ram_wr_sel_r <= #1 ram_wr_sel;
wr_bit_r <= #1 wr_bit;
end
 
//
//set output in case of address (byte)
always @(adr0_r or psw or acc or dptr_hi or ports or sp_r or b_reg or uart or tc_out or int_out or dptr_lo)
always @(adr0_r or psw or acc or dptr_hi or ports or sp_out or b_reg or uart or
tc_out or tc2 or int_out or dptr_lo)
begin
case (adr0_r)
`OC8051_SFR_ACC: dat0 = acc;
`OC8051_SFR_PSW: dat0 = psw;
`OC8051_SFR_P0: dat0 = ports;
`OC8051_SFR_P1: dat0 = ports;
`OC8051_SFR_P2: dat0 = ports;
`OC8051_SFR_P3: dat0 = ports;
`OC8051_SFR_SP: dat0 = sp_r;
`OC8051_SFR_B: dat0 = b_reg;
`OC8051_SFR_DPTR_HI: dat0 = dptr_hi;
`OC8051_SFR_DPTR_LO: dat0 = dptr_lo;
`OC8051_SFR_SCON: dat0 = uart;
`OC8051_SFR_SBUF: dat0 = uart;
`OC8051_SFR_PCON: dat0 = uart;
`OC8051_SFR_TH0: dat0 = tc_out;
`OC8051_SFR_TH1: dat0 = tc_out;
`OC8051_SFR_TL0: dat0 = tc_out;
`OC8051_SFR_TL1: dat0 = tc_out;
`OC8051_SFR_TMOD: dat0 = tc_out;
`OC8051_SFR_IP: dat0 = int_out;
`OC8051_SFR_IE: dat0 = int_out;
`OC8051_SFR_TCON: dat0 = int_out;
default: dat0 = 8'h00;
endcase
case (adr0_r)
`OC8051_SFR_ACC: dat0 = acc;
`OC8051_SFR_PSW: dat0 = psw;
`OC8051_SFR_P0: dat0 = ports;
`OC8051_SFR_P1: dat0 = ports;
`OC8051_SFR_P2: dat0 = ports;
`OC8051_SFR_P3: dat0 = ports;
`OC8051_SFR_SP: dat0 = sp_out;
`OC8051_SFR_B: dat0 = b_reg;
`OC8051_SFR_DPTR_HI: dat0 = dptr_hi;
`OC8051_SFR_DPTR_LO: dat0 = dptr_lo;
`OC8051_SFR_SCON: dat0 = uart;
`OC8051_SFR_SBUF: dat0 = uart;
`OC8051_SFR_PCON: dat0 = uart;
`OC8051_SFR_TH0: dat0 = tc_out;
`OC8051_SFR_TH1: dat0 = tc_out;
`OC8051_SFR_TL0: dat0 = tc_out;
`OC8051_SFR_TL1: dat0 = tc_out;
`OC8051_SFR_TMOD: dat0 = tc_out;
`OC8051_SFR_IP: dat0 = int_out;
`OC8051_SFR_IE: dat0 = int_out;
`OC8051_SFR_TCON: dat0 = int_out;
`OC8051_SFR_RCAP2H: dat0 = tc2;
`OC8051_SFR_RCAP2L: dat0 = tc2;
`OC8051_SFR_TH2: dat0 = tc2;
`OC8051_SFR_TL2: dat0 = tc2;
`OC8051_SFR_T2MOD: dat0 = tc2;
`OC8051_SFR_T2CON: dat0 = tc2;
 
default: dat0 = 8'h00;
endcase
end
 
 
//
//set output in case of address (bit)
always @(adr0_r or b_bit or acc_bit or psw_bit or int_bit or port_bit or uart_bit)
always @(adr0_r or b_bit or acc_bit or psw_bit or int_bit or port_bit or uart_bit or tc2_bit)
begin
case (adr0_r[7:3])
`OC8051_SFR_B_ACC: bit_out = acc_bit;
`OC8051_SFR_B_PSW: bit_out = psw_bit;
`OC8051_SFR_B_P0: bit_out = port_bit;
`OC8051_SFR_B_P1: bit_out = port_bit;
`OC8051_SFR_B_P2: bit_out = port_bit;
`OC8051_SFR_B_P3: bit_out = port_bit;
`OC8051_SFR_B_B: bit_out = b_bit;
`OC8051_SFR_B_IP: bit_out = int_bit;
`OC8051_SFR_B_IE: bit_out = int_bit;
`OC8051_SFR_B_TCON: bit_out = int_bit;
`OC8051_SFR_B_SCON: bit_out = uart_bit;
default: bit_out = 1'b0;
endcase
case (adr0_r[7:3])
`OC8051_SFR_B_ACC: bit_out = acc_bit;
`OC8051_SFR_B_PSW: bit_out = psw_bit;
`OC8051_SFR_B_P0: bit_out = port_bit;
`OC8051_SFR_B_P1: bit_out = port_bit;
`OC8051_SFR_B_P2: bit_out = port_bit;
`OC8051_SFR_B_P3: bit_out = port_bit;
`OC8051_SFR_B_B: bit_out = b_bit;
`OC8051_SFR_B_IP: bit_out = int_bit;
`OC8051_SFR_B_IE: bit_out = int_bit;
`OC8051_SFR_B_TCON: bit_out = int_bit;
`OC8051_SFR_B_SCON: bit_out = uart_bit;
`OC8051_SFR_B_T2CON: bit_out = tc2_bit;
default: bit_out = 1'b0;
endcase
end
 
endmodule
/trunk/rtl/verilog/oc8051_int.v
1,344 → 1,375
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 cores interrupt control module ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// contains sfr's: tcon, ip, ie; ////
//// interrupt handling ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// - Jaka Simsic, jakas@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
 
 
//clk clock (pin)
//rst reset (pin)
//wr_addr address for selecting different registers (input)
//data_in data input (input)
//wr read/write signal (input)
//tf0 signal for timer interrupt 0 (input)
//tf1 signal for timer interrupt 1 (input)
//ie0 signal for external interrupt 0 (input)
//ie1 signal for external interrupt 1 (input)
//reti return from interrupt signal (input)
//int_src describes interrupt source (output)
//ip ip register (internal)
//ie ie register (internal)
//tcon tcon register (internal)
 
 
 
 
`include "oc8051_defines.v"
 
//synopsys translate_off
`include "oc8051_timescale.v"
//synopsys translate_on
 
 
 
module oc0851_int (clk, wr_addr, rd_addr, data_in, bit_in, data_out, bit_out, wr, wr_bit, tf0, tf1, intr, ie0, ie1, rst, reti, int_vec, tr0, tr1, uart, ack);
input [7:0] wr_addr, data_in, rd_addr;
input wr, tf0, tf1, ie0, ie1, clk, rst, reti, wr_bit, bit_in, uart, ack;
 
output tr0, tr1, intr, bit_out;
output [7:0] int_vec, data_out;
 
reg [7:0] ip, ie, int_vec, data_out;
 
reg [3:0] tcon_s;
reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0, bit_out;
wire [7:0] tcon;
 
//
// isrc_cur current interrupt source
// isrc_w waiting interrupt source
reg [2:0] isrc_cur, isrc_w;
 
//
// contains witch level of interrupts is running
reg [1:0] int_levl, int_levl_w;
 
//
// int_l0 waiting interrupts on level 0
// int_l1 waiting interrupts on level 1
wire [4:0] int_l0, int_l1;
wire il0, il1;
 
//reg set_tf0, set_tf1, set_ie0, set_ie1;
reg tf0_buff, tf1_buff, ie0_buff, ie1_buff;
//reg tf0_ack, tf1_ack, ie0_ack, ie1_ack;
 
assign tcon = {tcon_tf1, tcon_s[3], tcon_tf0, tcon_s[2], tcon_ie1, tcon_s[1], tcon_ie0, tcon_s[0]};
assign tr0 = tcon_s[2];
assign tr1 = tcon_s[3];
assign intr = |int_vec;
 
assign int_l0 = ~ip[4:0] & ie[4:0] & {uart, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};
assign int_l1 = ip[4:0] & ie[4:0] & {uart, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};
assign il0 = |int_l0;
assign il1 = |int_l1;
 
always @(posedge clk or posedge rst)
begin
if (rst) begin
ip <=#1 `OC8051_RST_IP;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
ip <= #1 data_in;
end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
ip[wr_addr[2:0]] <= #1 bit_in;
end
 
always @(posedge clk or posedge rst)
begin
if (rst) begin
ie <=#1 `OC8051_RST_IE;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
ie <= #1 data_in;
end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE))
ie[wr_addr[2:0]] <= #1 bit_in;
end
 
//
// tcon_s
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
// tcon_s <=#1 {`OC8051_RST_TCON[6], `OC8051_RST_TCON[4], `OC8051_RST_TCON[2], `OC8051_RST_TCON[0]};
tcon_s <=#1 4'b0000;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};
end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
case (wr_addr[2:0])
3'b000: tcon_s[0] <= #1 bit_in;
3'b010: tcon_s[1] <= #1 bit_in;
3'b100: tcon_s[2] <= #1 bit_in;
3'b110: tcon_s[3] <= #1 bit_in;
endcase
end
end
 
//
// tf1 (tmod.7)
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
// tcon_tf1 <=#1 `OC8051_RST_TCON[7];
tcon_tf1 <=#1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
tcon_tf1 <= #1 data_in[7];
end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
tcon_tf1 <= #1 bit_in;
end else if (!(tf1_buff) & (tf1)) begin
tcon_tf1 <= #1 1'b1;
end else if (ack & (isrc_cur==`OC8051_ISRC_TF1)) begin
tcon_tf1 <= #1 1'b0;
end
end
 
//
// tf0 (tmod.5)
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
// tcon_tf0 <=#1 `OC8051_RST_TCON[5];
tcon_tf0 <=#1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
tcon_tf0 <= #1 data_in[5];
end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
tcon_tf0 <= #1 bit_in;
end else if (!(tf0_buff) & (tf0)) begin
tcon_tf0 <= #1 1'b1;
end else if (ack & (isrc_cur==`OC8051_ISRC_TF0)) begin
tcon_tf0 <= #1 1'b0;
end
end
 
 
//
// ie0 (tmod.1)
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
// tcon_ie0 <=#1 `OC8051_RST_TCON[1];
tcon_ie0 <=#1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
tcon_ie0 <= #1 data_in[1];
end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
tcon_ie0 <= #1 bit_in;
end else if (((tcon_s[0]) & (ie0_buff) & !(ie0)) | (!(tcon_s[0]) & !(ie0))) begin
tcon_ie0 <= #1 1'b1;
end else if (ack & (isrc_cur==`OC8051_ISRC_IE0) & (tcon_s[0])) begin
tcon_ie0 <= #1 1'b0;
end else if (!(tcon_s[0]) & (ie0)) begin
tcon_ie0 <= #1 1'b0;
end
end
 
 
//
// ie1 (tmod.3)
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
// tcon_ie1 <=#1 `OC8051_RST_TCON[3];
tcon_ie1 <=#1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
tcon_ie1 <= #1 data_in[3];
end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
tcon_ie1 <= #1 bit_in;
end else if (((tcon_s[1]) & (ie1_buff) & !(ie1)) | (!(tcon_s[1]) & !(ie1))) begin
tcon_ie1 <= #1 1'b1;
end else if (ack & (isrc_cur==`OC8051_ISRC_IE1) & (tcon_s[1])) begin
tcon_ie1 <= #1 1'b0;
end else if (!(tcon_s[1]) & (ie1)) begin
tcon_ie1 <= #1 1'b0;
end
end
 
 
always @(posedge clk or posedge rst)
begin
if (rst) begin
int_vec <= #1 8'h00;
isrc_cur <= #1 `OC8051_ISRC_NO;
isrc_w <= #1 `OC8051_ISRC_NO;
int_levl <= #1 `OC8051_ILEV_NO;
int_levl_w <= #1 `OC8051_ILEV_NO;
end else if (reti) begin // return from interrupt
isrc_cur <= #1 isrc_w;
int_levl <= #1 int_levl_w;
end else if ((ie[7]) & (int_levl!=`OC8051_ILEV_L1) & (il1)) begin // interrupt on level 1
isrc_w <= #1 isrc_cur;
int_levl <= #1 `OC8051_ILEV_L1;
int_levl_w <= #1 int_levl;
if (int_l1[0]) begin
int_vec <= #1 `OC8051_INT_X0;
isrc_cur <= #1 `OC8051_ISRC_IE0;
end else if (int_l1[1]) begin
int_vec <= #1 `OC8051_INT_T0;
isrc_cur <= #1 `OC8051_ISRC_TF0;
end else if (int_l1[2]) begin
int_vec <= #1 `OC8051_INT_X1;
isrc_cur <= #1 `OC8051_ISRC_IE1;
end else if (int_l1[3]) begin
int_vec <= #1 `OC8051_INT_T1;
isrc_cur <= #1 `OC8051_ISRC_TF1;
end else if (int_l1[4]) begin
int_vec <= #1 `OC8051_INT_UART;
isrc_cur <= #1 `OC8051_ISRC_UART;
end
end else if ((ie[7]) & (int_levl==`OC8051_ILEV_NO) & (il0)) begin // interrupt on level 0
int_levl <= #1 `OC8051_ILEV_L0;
if (int_l0[0]) begin
int_vec <= #1 `OC8051_INT_X0;
isrc_cur <= #1 `OC8051_ISRC_IE0;
end else if (int_l0[1]) begin
int_vec <= #1 `OC8051_INT_T0;
isrc_cur <= #1 `OC8051_ISRC_TF0;
end else if (int_l0[2]) begin
int_vec <= #1 `OC8051_INT_X1;
isrc_cur <= #1 `OC8051_ISRC_IE1;
end else if (int_l0[3]) begin
int_vec <= #1 `OC8051_INT_T1;
isrc_cur <= #1 `OC8051_ISRC_TF1;
end else if (int_l0[4]) begin
int_vec <= #1 `OC8051_INT_UART;
isrc_cur <= #1 `OC8051_ISRC_UART;
end
end else begin
int_vec <= #1 8'h00;
end
end
 
 
always @(posedge clk or posedge rst)
begin
if (rst) data_out <= #1 8'h0;
else if (wr & !wr_bit & (wr_addr==rd_addr) & (
(wr_addr==`OC8051_SFR_IP) | (wr_addr==`OC8051_SFR_IE) | (wr_addr==`OC8051_SFR_TCON))) begin
data_out <= #1 data_in;
end else begin
case (rd_addr)
`OC8051_SFR_IP: data_out <= #1 ip;
`OC8051_SFR_IE: data_out <= #1 ie;
default: data_out <= #1 tcon;
endcase
end
end
 
always @(posedge clk or posedge rst)
if (rst) begin
tf0_buff <= #1 1'b0;
tf1_buff <= #1 1'b0;
ie0_buff <= #1 1'b0;
ie1_buff <= #1 1'b0;
end else begin
tf0_buff <= #1 tf0;
tf1_buff <= #1 tf1;
ie0_buff <= #1 ie0;
ie1_buff <= #1 ie1;
end
 
always @(posedge clk or posedge rst)
begin
if (rst) bit_out <= #1 1'b0;
else if (wr & wr_bit & (wr_addr==rd_addr)) begin
bit_out <= #1 bit_in;
end else if ((rd_addr[7:3]==wr_addr[7:3]) & wr & !wr_bit) begin
bit_out <= #1 data_in[rd_addr[2:0]];
end else begin
case (rd_addr[7:3])
`OC8051_SFR_B_IP: bit_out <= #1 ip[rd_addr[2:0]];
`OC8051_SFR_B_IE: bit_out <= #1 ie[rd_addr[2:0]];
default: bit_out <= #1 tcon[rd_addr[2:0]];
endcase
end
end
 
 
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 cores interrupt control module ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// contains sfr's: tcon, ip, ie; ////
//// interrupt handling ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// - Jaka Simsic, jakas@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/09/30 17:33:59 simont
// prepared header
//
//
 
 
`include "oc8051_defines.v"
 
//synopsys translate_off
`include "oc8051_timescale.v"
//synopsys translate_on
 
 
 
module oc0851_int (clk, rst, wr_addr, rd_addr, data_in, bit_in, data_out, bit_out, wr, wr_bit,
//timer interrupts
tf0, tf1, t2_int,
tr0, tr1,
//external interrupts
ie0, ie1,
//uart interrupts
uart_int,
//to cpu
intr, reti, int_vec, ack);
 
input [7:0] wr_addr, data_in, rd_addr;
input wr, tf0, tf1, t2_int, ie0, ie1, clk, rst, reti, wr_bit, bit_in, ack, uart_int;
 
output tr0, tr1, intr, bit_out;
output [7:0] int_vec, data_out;
 
reg [7:0] ip, ie, int_vec, data_out;
 
reg [3:0] tcon_s;
reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0, bit_out;
wire [7:0] tcon;
 
//
// isrc processing interrupt sources
// int_dept
wire [2:0] isrc_cur;
reg [2:0] isrc [1:0];
reg int_dept;
wire int_dept_1;
reg int_proc;
reg [1:0] int_lev [1:0];
wire cur_lev;
 
assign isrc_cur = int_proc ? isrc[int_dept_1] : 2'h0;
assign int_dept_1 = int_dept - 1'b1;
assign cur_lev = int_lev[int_dept_1];
 
//
// contains witch level of interrupts is running
//reg [1:0] int_levl, int_levl_w;
 
//
// int_ln waiting interrupts on level n
// ip_ln interrupts on level n
// int_src interrupt sources
wire [5:0] int_l0, int_l1;
wire [5:0] ip_l0, ip_l1;
wire [5:0] int_src;
wire il0, il1;
 
 
reg tf0_buff, tf1_buff, ie0_buff, ie1_buff;
 
//
//interrupt priority
assign ip_l0 = ~ip[5:0];
assign ip_l1 = ip[5:0];
 
assign int_src = {t2_int, uart_int, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};
 
//
// waiting interrupts
assign int_l0 = ip_l0 & {ie[5:0]} & int_src;
assign int_l1 = ip_l1 & {ie[5:0]} & int_src;
assign il0 = |int_l0;
assign il1 = |int_l1;
 
//
// TCON
assign tcon = {tcon_tf1, tcon_s[3], tcon_tf0, tcon_s[2], tcon_ie1, tcon_s[1], tcon_ie0, tcon_s[0]};
assign tr0 = tcon_s[2];
assign tr1 = tcon_s[3];
assign intr = |int_vec;
 
 
//
// IP
always @(posedge clk or posedge rst)
begin
if (rst) begin
ip <=#1 `OC8051_RST_IP;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
ip <= #1 data_in;
end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
ip[wr_addr[2:0]] <= #1 bit_in;
end
 
//
// IE
always @(posedge clk or posedge rst)
begin
if (rst) begin
ie <=#1 `OC8051_RST_IE;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
ie <= #1 data_in;
end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE))
ie[wr_addr[2:0]] <= #1 bit_in;
end
 
//
// tcon_s
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
tcon_s <=#1 4'b0000;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};
end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
case (wr_addr[2:0])
3'b000: tcon_s[0] <= #1 bit_in;
3'b010: tcon_s[1] <= #1 bit_in;
3'b100: tcon_s[2] <= #1 bit_in;
3'b110: tcon_s[3] <= #1 bit_in;
endcase
end
end
 
//
// tf1 (tmod.7)
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
tcon_tf1 <=#1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
tcon_tf1 <= #1 data_in[7];
end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
tcon_tf1 <= #1 bit_in;
end else if (!(tf1_buff) & (tf1)) begin
tcon_tf1 <= #1 1'b1;
end else if (ack & (isrc_cur==`OC8051_ISRC_TF1)) begin
tcon_tf1 <= #1 1'b0;
end
end
 
//
// tf0 (tmod.5)
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
tcon_tf0 <=#1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
tcon_tf0 <= #1 data_in[5];
end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
tcon_tf0 <= #1 bit_in;
end else if (!(tf0_buff) & (tf0)) begin
tcon_tf0 <= #1 1'b1;
end else if (ack & (isrc_cur==`OC8051_ISRC_TF0)) begin
tcon_tf0 <= #1 1'b0;
end
end
 
 
//
// ie0 (tmod.1)
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
tcon_ie0 <=#1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
tcon_ie0 <= #1 data_in[1];
end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
tcon_ie0 <= #1 bit_in;
end else if (((tcon_s[0]) & (ie0_buff) & !(ie0)) | (!(tcon_s[0]) & !(ie0))) begin
tcon_ie0 <= #1 1'b1;
end else if (ack & (isrc_cur==`OC8051_ISRC_IE0) & (tcon_s[0])) begin
tcon_ie0 <= #1 1'b0;
end else if (!(tcon_s[0]) & (ie0)) begin
tcon_ie0 <= #1 1'b0;
end
end
 
 
//
// ie1 (tmod.3)
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
// tcon_ie1 <=#1 `OC8051_RST_TCON[3];
tcon_ie1 <=#1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
tcon_ie1 <= #1 data_in[3];
end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
tcon_ie1 <= #1 bit_in;
end else if (((tcon_s[1]) & (ie1_buff) & !(ie1)) | (!(tcon_s[1]) & !(ie1))) begin
tcon_ie1 <= #1 1'b1;
end else if (ack & (isrc_cur==`OC8051_ISRC_IE1) & (tcon_s[1])) begin
tcon_ie1 <= #1 1'b0;
end else if (!(tcon_s[1]) & (ie1)) begin
tcon_ie1 <= #1 1'b0;
end
end
 
//
// interrupt processing
always @(posedge clk or posedge rst)
begin
if (rst) begin
int_vec <= #1 8'h00;
int_dept <= #1 1'b0;
isrc[0] <= #1 3'h0;
isrc[1] <= #1 3'h0;
int_proc <= #1 1'b0;
int_lev[0] <= #1 1'b0;
int_lev[1] <= #1 1'b0;
end else if (reti) begin // return from interrupt
if (int_dept==2'b01)
int_proc <= #1 1'b0;
int_dept <= #1 int_dept - 2'b01;
end else if (((ie[7]) & (!cur_lev) || !int_proc) & il1) begin // interrupt on level 1
int_proc <= #1 1'b1;
int_lev[int_dept] <= #1 `OC8051_ILEV_L1;
int_dept <= #1 int_dept + 2'b01;
if (int_l1[0]) begin
int_vec <= #1 `OC8051_INT_X0;
isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
end else if (int_l1[1]) begin
int_vec <= #1 `OC8051_INT_T0;
isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
end else if (int_l1[2]) begin
int_vec <= #1 `OC8051_INT_X1;
isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
end else if (int_l1[3]) begin
int_vec <= #1 `OC8051_INT_T1;
isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
end else if (int_l1[4]) begin
int_vec <= #1 `OC8051_INT_UART;
isrc[int_dept] <= #1 `OC8051_ISRC_UART;
end else if (int_l1[5]) begin
int_vec <= #1 `OC8051_INT_T2;
isrc[int_dept] <= #1 `OC8051_ISRC_T2;
end
 
end else if ((ie[7]) & !int_proc & il0) begin // interrupt on level 0
int_proc <= #1 1'b1;
int_lev[int_dept] <= #1 `OC8051_ILEV_L0;
int_dept <= #1 int_dept + 2'b01;
if (int_l0[0]) begin
int_vec <= #1 `OC8051_INT_X0;
isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
end else if (int_l0[1]) begin
int_vec <= #1 `OC8051_INT_T0;
isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
end else if (int_l0[2]) begin
int_vec <= #1 `OC8051_INT_X1;
isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
end else if (int_l0[3]) begin
int_vec <= #1 `OC8051_INT_T1;
isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
end else if (int_l0[4]) begin
int_vec <= #1 `OC8051_INT_UART;
isrc[int_dept] <= #1 `OC8051_ISRC_UART;
end else if (int_l0[5]) begin
int_vec <= #1 `OC8051_INT_T2;
isrc[int_dept] <= #1 `OC8051_ISRC_T2;
end
end else begin
int_vec <= #1 8'h00;
end
end
 
 
always @(posedge clk or posedge rst)
begin
if (rst) data_out <= #1 8'h0;
else if (wr & !wr_bit & (wr_addr==rd_addr) & (
(wr_addr==`OC8051_SFR_IP) | (wr_addr==`OC8051_SFR_IE) | (wr_addr==`OC8051_SFR_TCON))) begin
data_out <= #1 data_in;
end else begin
case (rd_addr)
`OC8051_SFR_IP: data_out <= #1 ip;
`OC8051_SFR_IE: data_out <= #1 ie0;
default: data_out <= #1 tcon;
endcase
end
end
 
always @(posedge clk or posedge rst)
if (rst) begin
tf0_buff <= #1 1'b0;
tf1_buff <= #1 1'b0;
ie0_buff <= #1 1'b0;
ie1_buff <= #1 1'b0;
end else begin
tf0_buff <= #1 tf0;
tf1_buff <= #1 tf1;
ie0_buff <= #1 ie0;
ie1_buff <= #1 ie1;
end
 
always @(posedge clk or posedge rst)
begin
if (rst) bit_out <= #1 1'b0;
else if (wr & wr_bit & (wr_addr==rd_addr)) begin
bit_out <= #1 bit_in;
end else if ((rd_addr[7:3]==wr_addr[7:3]) & wr & !wr_bit) begin
bit_out <= #1 data_in[rd_addr[2:0]];
end else begin
case (rd_addr[7:3])
`OC8051_SFR_B_IP: bit_out <= #1 ip[rd_addr[2:0]];
`OC8051_SFR_B_IE: bit_out <= #1 ie[rd_addr[2:0]];
default: bit_out <= #1 tcon[rd_addr[2:0]];
endcase
end
end
 
 
endmodule
/trunk/rtl/verilog/oc8051_ram_top.v
1,138 → 1,143
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 data ram ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// data ram ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_ram_top (clk, rst, rd_addr, rd_data, wr_addr, bit_addr, wr_data, wr, bit_data_in, bit_data_out);
//
// clk (in) clock
// rd_addr (in) read addres [oc8051_ram_rd_sel.out]
// rd_data (out) read data [oc8051_ram_sel.in_ram]
// wr_addr (in) write addres [oc8051_ram_wr_sel.out]
// bit_addr (in) bit addresable instruction [oc8051_decoder.bit_addr -r]
// wr_data (in) write data [oc8051_alu.des1]
// wr (in) write [oc8051_decoder.wr -r]
// bit_data_in (in) bit data input [oc8051_alu.desCy]
// bit_data_out (out) bit data output [oc8051_ram_sel.bit_in]
//
 
input clk, wr, bit_addr, bit_data_in, rst;
input [7:0] rd_addr, wr_addr, wr_data;
output bit_data_out;
output [7:0] rd_data;
 
 
// rd_addr_m read address modified
// wr_addr_m write address modified
// wr_data_m write data modified
reg [7:0] rd_addr_m, wr_addr_m, wr_data_m;
 
// bit_addr_r bit addresable instruction (registerd)
reg bit_addr_r;
reg [2:0] bit_select;
 
assign bit_data_out = rd_data[bit_select];
 
 
 
oc8051_ram oc8051_ram1(.clk(clk), .rst(rst), .rd_addr(rd_addr_m), .rd_data(rd_data), .wr_addr(wr_addr_m),
.wr_data(wr_data_m), .wr(wr));
 
 
always @(posedge clk or posedge rst)
if (rst) begin
bit_addr_r <= #1 1'b0;
bit_select <= #1 3'b0;
end else begin
bit_addr_r <= #1 bit_addr;
bit_select <= #1 rd_addr[2:0];
end
 
always @(rd_addr or bit_addr)
begin
case ({bit_addr, rd_addr[7]})
2'b10: rd_addr_m = {4'b0010, rd_addr[6:3]};
2'b11: rd_addr_m = {1'b1, rd_addr[6:3], 3'b000};
default: rd_addr_m = rd_addr;
endcase
end
 
always @(wr_addr or bit_addr_r)
begin
casex ({bit_addr_r, wr_addr[7]})
2'b10: wr_addr_m = {4'b0010, wr_addr[6:3]};
2'b11: wr_addr_m = {1'b1, wr_addr[6:3], 3'b000};
default: wr_addr_m = wr_addr;
endcase
end
 
always @(rd_data or bit_select or bit_data_in or wr_data or bit_addr_r)
begin
if (bit_addr_r) begin
case (bit_select)
3'b000: wr_data_m = {rd_data[7:1], bit_data_in};
3'b001: wr_data_m = {rd_data[7:2], bit_data_in, rd_data[0]};
3'b010: wr_data_m = {rd_data[7:3], bit_data_in, rd_data[1:0]};
3'b011: wr_data_m = {rd_data[7:4], bit_data_in, rd_data[2:0]};
3'b100: wr_data_m = {rd_data[7:5], bit_data_in, rd_data[3:0]};
3'b101: wr_data_m = {rd_data[7:6], bit_data_in, rd_data[4:0]};
3'b110: wr_data_m = {rd_data[7], bit_data_in, rd_data[5:0]};
default: wr_data_m = {bit_data_in, rd_data[6:0]};
endcase
end else
wr_data_m = wr_data;
end
 
 
 
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 data ram ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// data ram ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/09/30 17:33:59 simont
// prepared header
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_ram_top (clk, rst, rd_addr, rd_data, wr_addr, bit_addr, wr_data, wr, bit_data_in, bit_data_out);
//
// clk (in) clock
// rd_addr (in) read addres [oc8051_ram_rd_sel.out]
// rd_data (out) read data [oc8051_ram_sel.in_ram]
// wr_addr (in) write addres [oc8051_ram_wr_sel.out]
// bit_addr (in) bit addresable instruction [oc8051_decoder.bit_addr -r]
// wr_data (in) write data [oc8051_alu.des1]
// wr (in) write [oc8051_decoder.wr -r]
// bit_data_in (in) bit data input [oc8051_alu.desCy]
// bit_data_out (out) bit data output [oc8051_ram_sel.bit_in]
//
 
input clk, wr, bit_addr, bit_data_in, rst;
input [7:0] wr_data;
input [7:0] rd_addr, wr_addr;
output bit_data_out;
output [7:0] rd_data;
 
 
// rd_addr_m read address modified
// wr_addr_m write address modified
// wr_data_m write data modified
reg [7:0] wr_data_m;
reg [7:0] rd_addr_m, wr_addr_m;
 
// bit_addr_r bit addresable instruction (registerd)
reg bit_addr_r;
reg [2:0] bit_select;
 
assign bit_data_out = rd_data[bit_select];
 
 
 
oc8051_ram oc8051_ram1(.clk(clk), .rst(rst), .rd_addr(rd_addr_m), .rd_data(rd_data), .wr_addr(wr_addr_m),
.wr_data(wr_data_m), .wr(wr));
 
 
always @(posedge clk or posedge rst)
if (rst) begin
bit_addr_r <= #1 1'b0;
bit_select <= #1 3'b0;
end else begin
bit_addr_r <= #1 bit_addr;
bit_select <= #1 rd_addr[2:0];
end
 
always @(rd_addr or bit_addr)
begin
case ({bit_addr, rd_addr[7]})
2'b10: rd_addr_m = {4'b0010, rd_addr[6:3]};
2'b11: rd_addr_m = {1'b1, rd_addr[6:3], 3'b000};
default: rd_addr_m = rd_addr;
endcase
end
 
always @(wr_addr or bit_addr_r)
begin
casex ({bit_addr_r, wr_addr[7]})
2'b10: wr_addr_m = {8'h00, 4'b0010, wr_addr[6:3]};
2'b11: wr_addr_m = {8'h00, 1'b1, wr_addr[6:3], 3'b000};
default: wr_addr_m = wr_addr;
endcase
end
 
always @(rd_data or bit_select or bit_data_in or wr_data or bit_addr_r)
begin
if (bit_addr_r) begin
case (bit_select)
3'b000: wr_data_m = {rd_data[7:1], bit_data_in};
3'b001: wr_data_m = {rd_data[7:2], bit_data_in, rd_data[0]};
3'b010: wr_data_m = {rd_data[7:3], bit_data_in, rd_data[1:0]};
3'b011: wr_data_m = {rd_data[7:4], bit_data_in, rd_data[2:0]};
3'b100: wr_data_m = {rd_data[7:5], bit_data_in, rd_data[3:0]};
3'b101: wr_data_m = {rd_data[7:6], bit_data_in, rd_data[4:0]};
3'b110: wr_data_m = {rd_data[7], bit_data_in, rd_data[5:0]};
default: wr_data_m = {bit_data_in, rd_data[6:0]};
endcase
end else
wr_data_m = wr_data;
end
 
 
 
endmodule
/trunk/rtl/verilog/oc8051_wb_iinterface.v
44,8 → 44,11
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/10/28 16:42:08 simont
// initial import
//
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
68,7 → 71,7
// ack_o (out) acknowledge
// cyc_i (in) cycle
input stb_i, cyc_i;
input [15:0] adr_i;
input [22:0] adr_i;
output ack_o;
output [31:0] dat_o;
 
83,18 → 86,18
input ack_i;
input [31:0] dat_i;
output stb_o, cyc_o;
output [15:0] adr_o;
output [22:0] adr_o;
 
//
// internal bufers and wires
//
reg [15:0] adr;
reg [22:0] adr;
reg stb;
 
assign ack_o = ack_i;
assign dat_o = dat_i;
assign stb_o = stb_i || ack_i;
assign cyc_o = stb_o;
assign stb_o = stb || ack_i;
assign cyc_o = stb;
assign adr_o = ack_i ? adr : adr_i;
 
always @(posedge clk or posedge rst)
/trunk/rtl/verilog/oc8051_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.17 2002/11/05 17:23:54 simont
// add module oc8051_sfr, 256 bytes internal ram
//
// Revision 1.16 2002/10/28 14:55:00 simont
// fix bug in interface to external data ram
//
63,11 → 66,11
// synopsys translate_on
 
 
module oc8051_top (rst, clk, int0, int1, ea, iadr_o, idat_i,istb_o, iack_i, dat_i,
icyc_o, dat_o, adr_o, we_o, ack_i, stb_o, cyc_o, p0_in, p1_in, p2_in, p3_in, p0_out,
p1_out, p2_out, p3_out, rxd, txd, t0, t1);
module oc8051_top (rst_i, clk, int0, int1, ea, iadr_o, idat_i,istb_o, iack_i, ddat_i,
icyc_o, ddat_o, dadr_o, dwe_o, dack_i, dstb_o, dcyc_o, p0_in, p1_in, p2_in, p3_in, p0_out,
p1_out, p2_out, p3_out, rxd, txd, t0, t1, t2, t2ex);
//
// rst (in) reset - pin
// rst_i (in) reset - pin
// clk (in) clock - pin
// iadr_o (out) program rom addres (pin + internal)
// int0 (in) external interrupt 0
75,8 → 78,8
// dat_i (in) exteranal ram input
// dat_o (out) exteranal ram output
// adr_o (out) external address
// we_o (out) write to external ram
// stb_o
// dwe_o (out) write to external ram
// dstb_o
// ack_i
// idat_i (in) data from external program rom
// istb_o (out) strobe to program rom
92,59 → 95,53
 
 
 
input rst, clk, int0, int1, ea, rxd, t0, t1, ack_i, iack_i;
input [7:0] dat_i, p0_in, p1_in, p2_in, p3_in;
input rst_i, clk, int0, int1, ea, rxd, t0, t1, dack_i, iack_i, t2, t2ex;
input [7:0] ddat_i, p0_in, p1_in, p2_in, p3_in;
input [31:0] idat_i;
 
output we_o, txd, stb_o, cyc_o, istb_o, icyc_o;
output [7:0] dat_o, p0_out, p1_out, p2_out, p3_out;
//output [15:0] rom_addr, ext_addr;
output [15:0] adr_o, iadr_o;
output dwe_o, txd, dstb_o, dcyc_o, istb_o, icyc_o;
output [7:0] ddat_o, p0_out, p1_out, p2_out, p3_out;
 
wire [7:0] op1_i, op2_i, op3_i, dptr_hi, dptr_lo, ri, data_out, sp;
output [15:0] dadr_o, iadr_o;
 
wire [7:0] op1_i, op2_i, op3_i, dptr_hi, dptr_lo, ri, rn_mem, data_out;
wire [7:0] op1, op2, op3;
wire [7:0] acc, p0_out, p1_out, p2_out, p3_out;
wire [7:0] sp, sp_w;
 
wire [15:0] pc;
 
//
// data output is always from accumulator
assign dat_o = acc;
wire rst;
assign rst = rst_i;
 
assign cyc_o = stb_o;
assign dcyc_o = dstb_o;
assign icyc_o = istb_o;
 
 
assign op1 = idat_i[31:24];
assign op2 = idat_i[23:16];
assign op3 = idat_i[15:8];
 
//
// ram_rd_sel ram read (internal)
// ram_wr_sel ram write (internal)
// src_sel1, src_sel2 from decoder to register
// imm_sel immediate select
wire [1:0] ram_rd_sel, src_sel1, src_sel2;
wire [2:0] ram_wr_sel, imm_sel;
wire src_sel3;
wire [2:0] ram_rd_sel, ram_wr_sel, wr_sfr;
wire [2:0] src_sel2, src_sel1;
 
//
// wr_addr ram write addres
// ram_out data from ram
// sp stack pointer output
// rd_addr data ram read addres
// rd_addr_r data ram read addres registerd
wire [7:0] wr_addr, ram_data, ram_out, rd_addr, rd_addr_r, sfr_out;
wire [7:0] ram_data, ram_out, sfr_out, wr_dat;
wire [7:0] wr_addr, rd_addr;
wire sfr_bit;
 
 
//
// src_sel1_r, src_sel2_r src select, registred
// cy_sel carry select; from decoder to cy_selct1
// rom_addr_sel rom addres select; alu or pc
// ext_adddr_sel external addres select; data pointer or Ri
// write_p output from decoder; write to external ram, go to register;
wire [1:0] src_sel1_r, src_sel2_r, cy_sel, cy_sel_r, bank_sel;
wire src_sel3, src_sel3_r, rom_addr_sel, ext_addr_sel, rmw, ea_int, wr_xaddr;
wire [1:0] cy_sel, bank_sel;
wire rom_addr_sel, rmw, ea_int;
 
//
// int_uart interrupt from uart
157,9 → 154,11
 
//
//alu_op alu operation (from decoder)
//alu_op_r alu operation (registerd)
//psw_set write to psw or not; from decoder to psw (through register)
wire [3:0] alu_op, alu_op_r; wire [1:0] psw_set, psw_set_r;
wire mem_wait;
wire [2:0] mem_act;
wire [3:0] alu_op;
wire [1:0] psw_set;
 
//
// immediate1_r from imediate_sel1 to alu_src1_sel1
170,10 → 169,10
// desCy carry out
// desAc
// desOv overflow
// wr, wr_r write to data ram
wire [7:0] src1, src2, src3, des1, des2, des1_r;
wire desCy, desAc, desOv, alu_cy, wr, wr_r;
wire [7:0] immediate1_r, immediate2_r;
// wr write to data ram
wire [7:0] src1, src2, des1, des2, des1_r;
wire [7:0] src3;
wire desCy, desAc, desOv, alu_cy, wr, wr_o;
 
 
//
180,7 → 179,7
// rd read program rom
// pc_wr_sel program counter write select (from decoder to pc)
wire rd, pc_wr;
wire [1:0] pc_wr_sel;
wire [2:0] pc_wr_sel;
 
//
// op1_n from op_select to decoder
187,15 → 186,14
// op2_n, output of op_select, to immediate_sel1, pc1, comp1
// op3_n, output of op_select, to immediate_sel1, ram_wr_sel1
// op2_dr, output of op_select, to ram_rd_sel1, ram_wr_sel1
wire [7:0] op1_n, op2_n, op2_dr, op3_n, pc_hi_r;
//wire [2:0] op1_r;
wire [7:0] op1_n, op2_n, op3_n;
 
//
// comp_sel select source1 and source2 to compare
// eq result (from comp1 to decoder)
// wad2, wad2_r write to accumulator from destination 2
wire [1:0] comp_sel;
wire eq, wad2, wad2_r, nop, srcAc, cy, rd_ind, wr_ind;
wire eq, srcAc, cy, rd_ind, wr_ind;
wire [2:0] op1_cur;
 
 
//
202,90 → 200,46
// bit_addr bit addresable instruction
// bit_data bit data from ram to ram_select
// bit_out bit data from ram_select to alu and cy_select
wire bit_addr, bit_data, bit_out, bit_addr_r;
wire bit_addr, bit_data, bit_out, bit_addr_o;
 
//
wire pc_wait;
 
 
//
//registers
oc8051_reg8 oc8051_reg8_pc_hi(.clk(clk), .rst(rst), .din(pc[15:8]), .dout(pc_hi_r));
 
oc8051_reg2 oc8051_reg2_src_sel1(.clk(clk), .rst(rst), .din(src_sel1), .dout(src_sel1_r));
oc8051_reg2 oc8051_reg2_src_sel2(.clk(clk), .rst(rst), .din(src_sel2), .dout(src_sel2_r));
oc8051_reg1 oc8051_reg1_sre_sel3(.clk(clk), .rst(rst), .din(src_sel3), .dout(src_sel3_r));
 
oc8051_reg1 oc8051_reg1_wr (.clk(clk), .rst(rst), .din(wr), .dout(wr_r));
 
oc8051_reg4 oc8051_reg4_alu_op(.clk(clk), .rst(rst), .din(alu_op), .dout(alu_op_r));
 
oc8051_reg1 oc8051_reg1_bit_addr(.clk(clk), .rst(rst), .din(bit_addr), .dout(bit_addr_r));
 
oc8051_reg1 oc8051_reg1_wad2(.clk(clk), .rst(rst), .din(wad2), .dout(wad2_r));
oc8051_reg2 oc8051_reg2_cy(.clk(clk), .rst(rst), .din(cy_sel), .dout(cy_sel_r));
oc8051_reg2 oc8051_psw_reg (.clk(clk), .rst(rst), .din(psw_set), .dout(psw_set_r));
oc8051_reg8 oc8051_reg8_rd_ram (.clk(clk), .rst(rst), .din(rd_addr), .dout(rd_addr_r));
 
 
 
 
//
//program counter
oc8051_pc oc8051_pc1(.rst(rst), .clk(clk), .pc_out(pc), .alu({des2,des1}),
.pc_wr_sel(pc_wr_sel), .op1(op1_n), .op2(op2_n), .op3(op3_n), .wr(pc_wr),
.rd((pc_wait && !(istb_o && !iack_i))), .intr(intr));
 
//
// decoder
oc8051_decoder oc8051_decoder1(.clk(clk), .rst(rst), .op_in(op1_n),
oc8051_decoder oc8051_decoder1(.clk(clk), .rst(rst), .op_in(op1_n), .op1_c(op1_cur),
.ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel), .bit_addr(bit_addr),
.src_sel1(src_sel1), .wr_xaddr(wr_xaddr), .src_sel2(src_sel2),
.src_sel1(src_sel1), .src_sel2(src_sel2),
.src_sel3(src_sel3), .alu_op(alu_op), .psw_set(psw_set),
.imm_sel(imm_sel), .cy_sel(cy_sel), .wr(wr), .pc_wr(pc_wr),
.cy_sel(cy_sel), .wr(wr), .pc_wr(pc_wr),
.pc_sel(pc_wr_sel), .comp_sel(comp_sel), .eq(eq),
.rom_addr_sel(rom_addr_sel), .ext_addr_sel(ext_addr_sel),
.wad2(wad2), .rd(rd), .we_o(we_o), .reti(reti), .rmw(rmw),
.stb_o(stb_o), .ack_i(ack_i), .istb(istb), .ea(ea && ea_int),
.iack(iack_i), .pc_wait(pc_wait), .nop(nop));
.wr_sfr(wr_sfr), .rd(rd), .rmw(rmw),
.istb(istb), .mem_act(mem_act), .mem_wait(mem_wait));
 
 
 
//
// internal ram address select
oc8051_ram_adr_sel oc8051_ram_rd_sel1 (.rst(rst), .clk(clk), .rd_sel(ram_rd_sel),
.wr_sel(ram_wr_sel), .sp(sp), .ri(ri), .rn({bank_sel, op1_n[2:0]}), .imm(op2_dr),
.imm2(op3_n), .rd_addr(rd_addr), .wr_addr(wr_addr), .rd_ind(rd_ind), .wr_ind(wr_ind));
 
 
 
//
//alu
oc8051_alu oc8051_alu1(.rst(rst), .clk(clk), .op_code(alu_op_r), .src1(src1), .src2(src2), .src3(src3),
.srcCy(alu_cy), .srcAc(srcAc), .des1(des1), .des2(des2), .des1_r(des1_r), .desCy(desCy),
.desAc(desAc), .desOv(desOv), .bit_in(bit_out));
oc8051_alu oc8051_alu1(.rst(rst), .clk(clk), .op_code(alu_op), .rd(rd),
.src1(src1), .src2(src2), .src3(src3), .srcCy(alu_cy), .srcAc(srcAc),
.des1(des1), .des2(des2), .des1_r(des1_r), .desCy(desCy),
.desAc(desAc), .desOv(desOv), .bit_in(bit_out));
 
 
//
//
oc8051_immediate_sel oc8051_immediate_sel1(.clk(clk), .rst(rst), .sel(imm_sel), .op1(op1_n), .op2(op2_n),
.op3(op3_n), .pch(pc_hi_r), .pcl(pc[7:0]), .out1(immediate1_r), .out2(immediate2_r));
 
//
//data ram
oc8051_ram_top oc8051_ram_top1(.clk(clk), .rst(rst), .rd_addr(rd_addr), .rd_data(ram_data),
.wr_addr(wr_addr), .bit_addr(bit_addr), .wr_data(des1), .wr(wr_r && (!wr_addr[7] || wr_ind)),
.wr_addr(wr_addr), .bit_addr(bit_addr_o), .wr_data(wr_dat), .wr(wr_o && (!wr_addr[7] || wr_ind)),
.bit_data_in(desCy), .bit_data_out(bit_data));
 
//
//
oc8051_alu_src1_sel oc8051_alu_src1_sel1(.sel(src_sel1_r), .immediate(immediate1_r),
.acc(acc), .ram(ram_out), .ext(dat_i), .des(src1));
oc8051_alu_src2_sel oc8051_alu_src2_sel1(.sel(src_sel2_r), .immediate(immediate2_r),
.acc(acc), .ram(ram_out), .des(src2));
oc8051_alu_src3_sel oc8051_alu_src3_sel1(.sel(src_sel3_r), .pc(pc_hi_r),
.dptr(dptr_hi), .des(src3));
 
oc8051_alu_src_sel oc8051_alu_src_sel1(.clk(clk), .rst(rst), .rd(rd),
.sel1(src_sel1), .sel2(src_sel2), .sel3(src_sel3),
.acc(acc), .ram(ram_out), .pc(pc), .dptr({dptr_hi, dptr_lo}),
.op1(op1_n), .op2(op2_n), .op3(op3_n),
.src1(src1), .src2(src2), .src3(src3));
 
 
//
//
oc8051_comp oc8051_comp1(.sel(comp_sel), .eq(eq), .b_in(bit_out), .cy(cy), .acc(acc), .des(des1_r));
298,48 → 252,59
 
//
//
oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel_r), .cy_in(cy), .data_in(bit_out),
oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel), .cy_in(cy), .data_in(bit_out),
.data_out(alu_cy));
//
//
oc8051_indi_addr oc8051_indi_addr1 (.clk(clk), .rst(rst), .addr(wr_addr),
.data_in(des1), .wr(wr_r), .wr_bit(bit_addr_r), .data_out(ri),
.sel(op1_n[0]), .bank(bank_sel));
oc8051_indi_addr oc8051_indi_addr1 (.clk(clk), .rst(rst), .rd_addr(rd_addr), .wr_addr(wr_addr),
.data_in(wr_dat), .wr(wr_o), .wr_bit(bit_addr_o), .rn_out(rn_mem),
.ri_out(ri), .sel(op1_cur), .bank(bank_sel));
 
//
//
oc8051_rom_addr_sel oc8051_rom_addr_sel1(.clk(clk), .rst(rst), .iack_i(iack_i),
.ea(ea && ea_int), .sel(rom_addr_sel), .des1(des1), .des2(des2),
.pc(pc), .out_addr(iadr_o));
 
//
//
oc8051_ext_addr_sel oc8051_ext_addr_sel1(.clk(clk), .rst(rst), .sel(ext_addr_sel),
.dptr_hi(dptr_hi), .dptr_lo(dptr_lo), .ri(ri), .addr_out(adr_o),
.wr(wr_xaddr), .stb(stb_o));
//
//
oc8051_ram_sel oc8051_ram_sel1(.addr(rd_addr_r), .bit_in(bit_data), .in_ram(ram_data), .rd_ind(rd_ind),
.sfr(sfr_out), .sfr_bit(sfr_bit), .bit_out(bit_out), .out_data(ram_out));
oc8051_memory_interface oc8051_memory_interface1(.clk(clk), .rst(rst),
.wr_i(wr), .wr_o(wr_o), .wr_bit_i(bit_addr), .wr_bit_o(bit_addr_o), .wr_dat(wr_dat),
//rom_addr_sel
.iack_i(iack_i), .des1(des1), .des2(des2),
.iadr_o(iadr_o), .sp_w(sp_w),
 
//ext_addr_sel
.dptr({dptr_hi, dptr_lo}), .ri(ri), .rn_mem(rn_mem), .dadr_o(dadr_o), .ddat_o(ddat_o),
.dwe_o(dwe_o), .dstb_o(dstb_o), .ddat_i(ddat_i), .acc(acc), .dack_i(dack_i),
 
//ram_addr_sel
.rd_sel(ram_rd_sel), .wr_sel(ram_wr_sel), .sp(sp), .rn({bank_sel, op1_n[2:0]}),
.rd_addr(rd_addr), .wr_addr(wr_addr), .rd_ind(rd_ind), .wr_ind(wr_ind),
 
//op_select
.ea(ea), .ea_int(ea_int),
.op1_i(op1_i), .op2_i(op2_i), .op3_i(op3_i),
.idat_i(idat_i),
.op1_out(op1_n), .op2_out(op2_n), .op3_out(op3_n),
.intr(intr), .int_v(int_src), .rd(rd), .int_ack(int_ack), .istb(istb),
.istb_o(istb_o),
 
//pc
.pc_wr_sel(pc_wr_sel), .pc_wr(pc_wr), .pc(pc),
.mem_act(mem_act), .mem_wait(mem_wait),
.bit_in(bit_data), .in_ram(ram_data),
.sfr(sfr_out), .sfr_bit(sfr_bit), .bit_out(bit_out), .iram_out(ram_out),
.reti(reti));
 
 
//
//
oc8051_op_select oc8051_op_select1(.clk(clk), .rst(rst), .ea(ea), .ea_int(ea_int), .op1_i(op1_i),
.op2_i(op2_i), .op3_i(op3_i), .op1_x(op1), .op2_x(op2), .op3_x(op3),
.op1_out(op1_n), .op2_out(op2_n), .op2_direct(op2_dr), .op3_out(op3_n),
.intr(intr), .int_v(int_src), .rd(rd), .ack(int_ack), .istb(istb),
.istb_o(istb_o), .iack_i(iack_i), .nop(nop));
 
 
oc8051_sfr oc8051_sfr1(.rst(rst), .clk(clk), .adr0(rd_addr), .adr1(wr_addr), .dat0(sfr_out),
.dat1(des1), .dat2(des2), .we(wr_r && !wr_ind), .bit_in(desCy), .bit_out(sfr_bit), .wr_bit(bit_addr_r),
.ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel),
oc8051_sfr oc8051_sfr1(.rst(rst), .clk(clk), .adr0(rd_addr[7:0]), .adr1(wr_addr[7:0]),
.dat0(sfr_out), .dat1(wr_dat), .dat2(des2), .we(wr_o && !wr_ind), .bit_in(desCy),
.bit_out(sfr_bit), .wr_bit(bit_addr_o), .ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel), .wr_sfr(wr_sfr),
// acc
.wad2(wad2_r), .acc(acc), .rd_x(stb_o && !we_o && ack_i), .xdata(dat_i),
.acc(acc),
// sp
.sp(sp),
.sp(sp), .sp_w(sp_w),
// psw
.bank_sel(bank_sel), .desAc(desAc), .desOv(desOv), .psw_set(psw_set_r),
.bank_sel(bank_sel), .desAc(desAc), .desOv(desOv), .psw_set(psw_set),
.srcAc(srcAc), .cy(cy),
// ports
.rmw(rmw), .p0_out(p0_out), .p1_out(p1_out), .p2_out(p2_out), .p3_out(p3_out),
349,8 → 314,9
// int
.int_ack(int_ack), .intr(intr), .int0(int0), .int1(int1), .reti(reti), .int_src(int_src),
// t/c
.t0(t0), .t1(t1),
.t0(t0), .t1(t1), .t2(t2), .t2ex(t2ex),
// dptr
.dptr_hi(dptr_hi), .dptr_lo(dptr_lo));
 
 
endmodule
/trunk/rtl/verilog/oc8051_decoder.v
1,3374 → 1,3287
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 core decoder ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// Main 8051 core module. decodes instruction and creates ////
//// control sigals. ////
//// ////
//// To Do: ////
//// optimize state machine, especially IDS ASS and AS3 ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 core decoder ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// Main 8051 core module. decodes instruction and creates ////
//// control sigals. ////
//// ////
//// To Do: ////
//// optimize state machine, especially IDS ASS and AS3 ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.13 2002/10/23 16:53:39 simont
// fix bugs in instruction interface
//
// Revision 1.12 2002/10/17 18:50:00 simont
// cahnge interface to instruction rom
//
// Revision 1.11 2002/09/30 17:33:59 simont
// prepared header
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
 
module oc8051_decoder (clk, rst, op_in, eq, ram_rd_sel, ram_wr_sel, bit_addr,
wr, src_sel1, src_sel2, src_sel3, alu_op, psw_set, cy_sel, imm_sel, pc_wr,
pc_sel, comp_sel, rom_addr_sel, ext_addr_sel, wad2, rd, we_o, reti,
rmw, stb_o, ack_i, wr_xaddr, istb, ea, iack, pc_wait, nop);
//
//
 
//
// clk (in) clock
// rst (in) reset
// op_in (in) operation code [oc8051_op_select.op1]
// eq (in) compare result [oc8051_comp.eq]
// ram_rd_sel (out) select, whitch address will be send to ram for read [oc8051_ram_rd_sel.sel, oc8051_sp.ram_rd_sel]
// ram_wr_sel (out) select, whitch address will be send to ram for write [oc8051_ram_wr_sel.sel -r, oc8051_sp.ram_wr_sel -r]
// wr (out) write - if 1 then we will write to ram [oc8051_ram_top.wr -r, oc8051_acc.wr -r, oc8051_b_register.wr -r, oc8051_sp.wr-r, oc8051_dptr.wr -r, oc8051_psw.wr -r, oc8051_indi_addr.wr -r, oc8051_ports.wr -r]
// src_sel1 (out) select alu source 1 [oc8051_alu_src1_sel.sel -r]
// src_sel2 (out) select alu source 2 [oc8051_alu_src2_sel.sel -r]
// src_sel3 (out) select alu source 3 [oc8051_alu_src3_sel.sel -r]
// alu_op (out) alu operation [oc8051_alu.op_code -r]
// psw_set (out) will we remember cy, ac, ov from alu [oc8051_psw.set -r]
// cy_sel (out) carry in alu select [oc8051_cy_select.cy_sel -r]
// comp_sel (out) compare source select [oc8051_comp.sel]
// bit_addr (out) if instruction is bit addresable [oc8051_ram_top.bit_addr -r, oc8051_acc.wr_bit -r, oc8051_b_register.wr_bit-r, oc8051_sp.wr_bit -r, oc8051_dptr.wr_bit -r, oc8051_psw.wr_bit -r, oc8051_indi_addr.wr_bit -r, oc8051_ports.wr_bit -r]
// wad2 (out) write acc from destination 2 [oc8051_acc.wad2 -r]
// imm_sel (out) immediate select [oc8051_immediate_sel.sel -r]
// pc_wr (out) pc write [oc8051_pc.wr]
// pc_sel (out) pc select [oc8051_pc.pc_wr_sel]
// rom_addr_sel (out) rom address select (alu destination or pc) [oc8051_rom_addr_sel.select]
// ext_addr_sel (out) external address select (dptr or Ri) [oc8051_ext_addr_sel.select]
// rd (out) read from rom [oc8051_pc.rd, oc8051_op_select.rd]
// we_o (out) write to external rom [pin]
// reti (out) return from interrupt [pin]
// rmw (out) read modify write feature [oc8051_ports.rmw]
// istb (out) strobe to instruction rom
// ea (in) extrnal access
// iack (in) scknowlage from external rom
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_decoder (clk, rst, op_in, op1_c,
ram_rd_sel, ram_wr_sel, bit_addr, wr, wr_sfr,
src_sel1, src_sel2, src_sel3,
alu_op, psw_set, eq, cy_sel, comp_sel,
pc_wr, pc_sel, rd, rmw, istb, mem_act, mem_wait);
 
//
// clk (in) clock
// rst (in) reset
// op_in (in) operation code [oc8051_op_select.op1]
// eq (in) compare result [oc8051_comp.eq]
// ram_rd_sel (out) select, whitch address will be send to ram for read [oc8051_ram_rd_sel.sel, oc8051_sp.ram_rd_sel]
// ram_wr_sel (out) select, whitch address will be send to ram for write [oc8051_ram_wr_sel.sel -r, oc8051_sp.ram_wr_sel -r]
// wr (out) write - if 1 then we will write to ram [oc8051_ram_top.wr -r, oc8051_acc.wr -r, oc8051_b_register.wr -r, oc8051_sp.wr-r, oc8051_dptr.wr -r, oc8051_psw.wr -r, oc8051_indi_addr.wr -r, oc8051_ports.wr -r]
// src_sel1 (out) select alu source 1 [oc8051_alu_src1_sel.sel -r]
// src_sel2 (out) select alu source 2 [oc8051_alu_src2_sel.sel -r]
// src_sel3 (out) select alu source 3 [oc8051_alu_src3_sel.sel -r]
// alu_op (out) alu operation [oc8051_alu.op_code -r]
// psw_set (out) will we remember cy, ac, ov from alu [oc8051_psw.set -r]
// cy_sel (out) carry in alu select [oc8051_cy_select.cy_sel -r]
// comp_sel (out) compare source select [oc8051_comp.sel]
// bit_addr (out) if instruction is bit addresable [oc8051_ram_top.bit_addr -r, oc8051_acc.wr_bit -r, oc8051_b_register.wr_bit-r, oc8051_sp.wr_bit -r, oc8051_dptr.wr_bit -r, oc8051_psw.wr_bit -r, oc8051_indi_addr.wr_bit -r, oc8051_ports.wr_bit -r]
// pc_wr (out) pc write [oc8051_pc.wr]
// pc_sel (out) pc select [oc8051_pc.pc_wr_sel]
// rd (out) read from rom [oc8051_pc.rd, oc8051_op_select.rd]
// reti (out) return from interrupt [pin]
// rmw (out) read modify write feature [oc8051_ports.rmw]
// pc_wait (out)
// nop (out) insert nops
//
 
input clk, rst, eq, ack_i, iack, ea;
input [7:0] op_in;
 
output wr, reti, we_o, bit_addr, src_sel3, rom_addr_sel, ext_addr_sel,
pc_wr, wad2, rmw, stb_o, wr_xaddr, istb, pc_wait;
output [1:0] ram_rd_sel, src_sel1, src_sel2, psw_set, cy_sel, pc_sel, comp_sel;
output [2:0] ram_wr_sel, imm_sel;
output [3:0] alu_op;
output rd, nop;
 
reg reti, write_x, rmw, stb_buff, we_buff, istb_t;
reg wr, bit_addr, src_sel3, rom_addr_sel, ext_addr_sel, pc_wr, wad2, stb, stbw, wr_xaddr;
reg [1:0] comp_sel, psw_set, ram_rd_sel, src_sel1, src_sel2, pc_sel, cy_sel;
reg [3:0] alu_op;
reg [2:0] ram_wr_sel, imm_sel;
 
//
// state if 2'b00 then normal execution, sle instructin that need more than one clock
// op instruction buffer
reg [1:0] state;
reg [7:0] op;
reg stb_i;
//
 
input clk, rst, eq, mem_wait;
input [7:0] op_in;
 
output wr, bit_addr, pc_wr, rmw, istb, src_sel3;
output [1:0] psw_set, cy_sel, comp_sel;
output [2:0] mem_act, src_sel1, src_sel2, ram_rd_sel, ram_wr_sel, pc_sel, wr_sfr, op1_c;
output [3:0] alu_op;
output rd;
 
reg rmw;
reg src_sel3, wr, bit_addr, pc_wr;
reg [1:0] comp_sel, psw_set, cy_sel;
reg [3:0] alu_op;
reg [2:0] src_sel2, mem_act, src_sel1, ram_wr_sel, ram_rd_sel, pc_sel, wr_sfr;
 
//
// state if 2'b00 then normal execution, sle instructin that need more than one clock
// op instruction buffer
reg [1:0] state;
reg [7:0] op;
wire [7:0] op_cur;
 
//
// if state = 2'b00 then read nex instruction
assign rd = !state[0] && !state[1] && !stb_o;
 
assign istb = ((!state[1]) && stb_i) || istb_t;
assign nop = (!state[1]) || istb_t;
reg stb_i;
 
 
assign stb_o = stb_buff || stbw;
assign we_o = we_buff;
//assign we_o = write_x || we_buff;
assign rd = !state[0] && !state[1];// && !stb_o;
 
assign op_cur = (state[0] || state[1] || stb_o) ? op : op_in;
assign istb = (!state[1]) && stb_i;
 
assign pc_wait = !istb_t && rd;
 
//
// main block
// case of instruction set control signals
always @(op_cur or eq or state or op or stb_o or istb_t)
begin
if (stb_o) begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
imm_sel = `OC8051_IDS_DC;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
 
 
assign op_cur = (state[0] || state[1] || mem_wait) ? op : op_in;
assign op1_c = op_cur[2:0];
 
 
//
// main block
// unregisterd outputs
always @(op_cur or eq or state or mem_wait)
begin
case (state)
2'b01: begin
casex (op_cur)
`OC8051_MOVC_DP :begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end else begin
case (state)
2'b01: begin
casex (op_cur)
`OC8051_ACALL :begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_SP;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
imm_sel = `OC8051_IDS_PCH;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
bit_addr = 1'b0;
end
`OC8051_MOVC_PC :begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
 
end
`OC8051_AJMP : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
imm_sel = `OC8051_IDS_DC;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_ACALL :begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
 
end
`OC8051_LCALL :begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_SP;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
imm_sel = `OC8051_IDS_PCH;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_AJMP : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
 
end
`OC8051_DIV : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_B;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_DIV;
wr = 1'b1;
psw_set = `OC8051_PS_OV;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
end
`OC8051_LCALL :begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
wad2 = `OC8051_WAD_Y;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_MUL : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_B;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_MUL;
wr = 1'b1;
psw_set = `OC8051_PS_OV;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_DIV : begin
ram_rd_sel = `OC8051_RRS_B;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_Y;
rom_addr_sel = `OC8051_RAS_PC;
end
default begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_MUL : begin
ram_rd_sel = `OC8051_RRS_B;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
endcase
end
2'b10:
casex (op_cur)
`OC8051_CJNE_R : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DES;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
default begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_CJNE_I : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DES;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
endcase
end
2'b10:
casex (op_cur)
`OC8051_RET : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_Y;
pc_sel = `OC8051_PIS_AL;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_CJNE_D : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DES;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_RETI : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_Y;
pc_sel = `OC8051_PIS_AL;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_CJNE_C : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DES;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_CJNE_R : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
comp_sel = `OC8051_CSS_DES;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_DJNZ_R : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DES;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_CJNE_I : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
comp_sel = `OC8051_CSS_DES;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
 
end
`OC8051_DJNZ_D : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DES;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_CJNE_D : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
comp_sel = `OC8051_CSS_DES;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
 
end
`OC8051_JB : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = eq;
pc_sel = `OC8051_PIS_ALU;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_BIT;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_CJNE_C : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
comp_sel = `OC8051_CSS_DES;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
 
end
`OC8051_JBC : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = eq;
pc_sel = `OC8051_PIS_ALU;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_BIT;
rmw = `OC8051_RMW_N; bit_addr = 1'b1;
bit_addr = 1'b0;
end
`OC8051_DJNZ_R : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
comp_sel = `OC8051_CSS_DES;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_JC : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = eq;
pc_sel = `OC8051_PIS_ALU;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_CY;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_DJNZ_D : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
comp_sel = `OC8051_CSS_DES;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_JMP : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_Y;
pc_sel = `OC8051_PIS_ALU;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_BIT;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_JB : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = eq;
pc_sel = `OC8051_PIS_ALU;
comp_sel = `OC8051_CSS_BIT;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_JNB : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_BIT;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_JBC : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = eq;
pc_sel = `OC8051_PIS_ALU;
comp_sel = `OC8051_CSS_BIT;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_JNC : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_CY;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b1;
end
`OC8051_JC : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = eq;
pc_sel = `OC8051_PIS_ALU;
comp_sel = `OC8051_CSS_CY;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_JNZ : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_AZ;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_JMP_D : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_Y;
pc_sel = `OC8051_PIS_ALU;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_JZ : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = eq;
pc_sel = `OC8051_PIS_ALU;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_AZ;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_JNB : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
comp_sel = `OC8051_CSS_BIT;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
 
end
`OC8051_MOVC_DP :begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP1;
src_sel3 = `OC8051_AS3_DP;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b1;
end
`OC8051_JNC : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
comp_sel = `OC8051_CSS_CY;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
 
end
`OC8051_MOVC_PC :begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP1;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_JNZ : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
comp_sel = `OC8051_CSS_AZ;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_SJMP : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_Y;
pc_sel = `OC8051_PIS_ALU;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_JZ : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = eq;
pc_sel = `OC8051_PIS_ALU;
comp_sel = `OC8051_CSS_AZ;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_DIV : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_B;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_DIV;
wr = 1'b0;
psw_set = `OC8051_PS_OV;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_SJMP : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_Y;
pc_sel = `OC8051_PIS_ALU;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_MUL : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_B;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_MUL;
wr = 1'b0;
psw_set = `OC8051_PS_OV;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
bit_addr = 1'b0;
end
`OC8051_DIV : begin
ram_rd_sel = `OC8051_RRS_B;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
rom_addr_sel = `OC8051_RAS_PC;
end
default begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_MUL : begin
ram_rd_sel = `OC8051_RRS_B;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
endcase
 
2'b11:
casex (op_cur)
`OC8051_MOVC_DP :begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DP;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
default begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_DES;
 
end
`OC8051_MOVC_PC :begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
endcase
 
2'b11:
casex (op_cur)
`OC8051_CJNE_R : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_DES;
end
`OC8051_CJNE_R : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_IMM;
alu_op = `OC8051_ALU_PCS;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP3_PCL;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_CJNE_I : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_CJNE_I : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_IMM;
alu_op = `OC8051_ALU_PCS;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP3_PCL;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_CJNE_D : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_CJNE_D : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_IMM;
alu_op = `OC8051_ALU_PCS;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP3_PCL;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_CJNE_C : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_CJNE_C : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_IMM;
alu_op = `OC8051_ALU_PCS;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP3_PCL;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_DJNZ_R : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_DJNZ_R : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_IMM;
alu_op = `OC8051_ALU_PCS;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2_PCL;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_DJNZ_D : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_DJNZ_D : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_IMM;
alu_op = `OC8051_ALU_PCS;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP3_PCL;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_RET : begin
ram_rd_sel = `OC8051_RRS_SP;
pc_wr = `OC8051_PCW_Y;
pc_sel = `OC8051_PIS_AH;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
bit_addr = 1'b0;
end
`OC8051_RETI : begin
ram_rd_sel = `OC8051_RRS_SP;
pc_wr = `OC8051_PCW_Y;
pc_sel = `OC8051_PIS_AH;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_RET : begin
ram_rd_sel = `OC8051_RRS_SP;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_Y;
pc_sel = `OC8051_PIS_SP;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_DIV : begin
ram_rd_sel = `OC8051_RRS_B;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_RETI : begin
ram_rd_sel = `OC8051_RRS_SP;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_Y;
pc_sel = `OC8051_PIS_SP;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_MUL : begin
ram_rd_sel = `OC8051_RRS_B;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_DIV : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_B;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_DIV;
wr = 1'b0;
psw_set = `OC8051_PS_OV;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
default begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_MUL : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_B;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_MUL;
wr = 1'b0;
psw_set = `OC8051_PS_OV;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
default begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
endcase
default: begin
casex (op_cur)
`OC8051_ACALL :begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_SP;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
imm_sel = `OC8051_IDS_PCL;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_Y;
pc_sel = `OC8051_PIS_I11;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
endcase
default: begin
casex (op_cur)
`OC8051_ACALL :begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_Y;
pc_sel = `OC8051_PIS_I11;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_AJMP : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
imm_sel = `OC8051_IDS_DC;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_Y;
pc_sel = `OC8051_PIS_I11;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_AJMP : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_Y;
pc_sel = `OC8051_PIS_I11;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_ADD_R : begin
ram_rd_sel = `OC8051_RRS_RN;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_ADD;
wr = 1'b1;
psw_set = `OC8051_PS_AC;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_ADD_R : begin
ram_rd_sel = `OC8051_RRS_RN;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_ADDC_R : begin
ram_rd_sel = `OC8051_RRS_RN;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_ADD;
wr = 1'b1;
psw_set = `OC8051_PS_AC;
cy_sel = `OC8051_CY_PSW;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_ADDC_R : begin
ram_rd_sel = `OC8051_RRS_RN;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_ANL_R : begin
ram_rd_sel = `OC8051_RRS_RN;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_AND;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_ANL_R : begin
ram_rd_sel = `OC8051_RRS_RN;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_CJNE_R : begin
ram_rd_sel = `OC8051_RRS_RN;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_IMM;
alu_op = `OC8051_ALU_SUB;
wr = 1'b0;
psw_set = `OC8051_PS_CY;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_CJNE_R : begin
ram_rd_sel = `OC8051_RRS_RN;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_DEC_R : begin
ram_rd_sel = `OC8051_RRS_RN;
ram_wr_sel = `OC8051_RWS_RN;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ZERO;
alu_op = `OC8051_ALU_SUB;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_1;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_DEC_R : begin
ram_rd_sel = `OC8051_RRS_RN;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_DJNZ_R : begin
ram_rd_sel = `OC8051_RRS_RN;
ram_wr_sel = `OC8051_RWS_RN;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ZERO;
alu_op = `OC8051_ALU_SUB;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_1;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_DJNZ_R : begin
ram_rd_sel = `OC8051_RRS_RN;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_INC_R : begin
ram_rd_sel = `OC8051_RRS_RN;
ram_wr_sel = `OC8051_RWS_RN;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ZERO;
alu_op = `OC8051_ALU_ADD;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_1;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_INC_R : begin
ram_rd_sel = `OC8051_RRS_RN;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_MOV_R : begin
ram_rd_sel = `OC8051_RRS_RN;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_MOV_R : begin
ram_rd_sel = `OC8051_RRS_RN;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
 
`OC8051_MOV_AR : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_RN;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_MOV_AR : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_MOV_DR : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_RN;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_MOV_DR : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_MOV_CR : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_RN;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_MOV_CR : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_MOV_RD : begin
ram_rd_sel = `OC8051_RRS_RN;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_MOV_RD : begin
ram_rd_sel = `OC8051_RRS_RN;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_ORL_R : begin
ram_rd_sel = `OC8051_RRS_RN;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_OR;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_ORL_R : begin
ram_rd_sel = `OC8051_RRS_RN;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_SUBB_R : begin
ram_rd_sel = `OC8051_RRS_RN;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_SUB;
wr = 1'b1;
psw_set = `OC8051_PS_AC;
cy_sel = `OC8051_CY_PSW;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_SUBB_R : begin
ram_rd_sel = `OC8051_RRS_RN;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_XCH_R : begin
ram_rd_sel = `OC8051_RRS_RN;
ram_wr_sel = `OC8051_RWS_RN;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_XCH;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_1;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_XCH_R : begin
ram_rd_sel = `OC8051_RRS_RN;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_Y;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_XRL_R : begin
ram_rd_sel = `OC8051_RRS_RN;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_XOR;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_XRL_R : begin
ram_rd_sel = `OC8051_RRS_RN;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
 
//op_code [7:1]
`OC8051_ADD_I : begin
ram_rd_sel = `OC8051_RRS_I;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_ADD;
wr = 1'b1;
psw_set = `OC8051_PS_AC;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
 
//op_code [7:1]
`OC8051_ADD_I : begin
ram_rd_sel = `OC8051_RRS_I;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_ADDC_I : begin
ram_rd_sel = `OC8051_RRS_I;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_ADD;
wr = 1'b1;
psw_set = `OC8051_PS_AC;
cy_sel = `OC8051_CY_PSW;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_ADDC_I : begin
ram_rd_sel = `OC8051_RRS_I;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_ANL_I : begin
ram_rd_sel = `OC8051_RRS_I;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_AND;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_ANL_I : begin
ram_rd_sel = `OC8051_RRS_I;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_CJNE_I : begin
ram_rd_sel = `OC8051_RRS_I;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_IMM;
alu_op = `OC8051_ALU_SUB;
wr = 1'b0;
psw_set = `OC8051_PS_CY;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_CJNE_I : begin
ram_rd_sel = `OC8051_RRS_I;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_DEC_I : begin
ram_rd_sel = `OC8051_RRS_I;
ram_wr_sel = `OC8051_RWS_I;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ZERO;
alu_op = `OC8051_ALU_SUB;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_1;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_DEC_I : begin
ram_rd_sel = `OC8051_RRS_I;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_INC_I : begin
ram_rd_sel = `OC8051_RRS_I;
ram_wr_sel = `OC8051_RWS_I;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ZERO;
alu_op = `OC8051_ALU_ADD;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_1;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_INC_I : begin
ram_rd_sel = `OC8051_RRS_I;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_MOV_I : begin
ram_rd_sel = `OC8051_RRS_I;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_MOV_I : begin
ram_rd_sel = `OC8051_RRS_I;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_MOV_ID : begin
ram_rd_sel = `OC8051_RRS_I;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_MOV_ID : begin
ram_rd_sel = `OC8051_RRS_I;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_MOV_AI : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_I;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_MOV_AI : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_MOV_DI : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_I;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_MOV_DI : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_MOV_CI : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_I;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_MOV_CI : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_MOVX_IA : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_XRAM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_MOVX_IA : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
bit_addr = 1'b0;
end
`OC8051_MOVX_AI :begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
bit_addr = 1'b0;
end
`OC8051_ORL_I : begin
ram_rd_sel = `OC8051_RRS_I;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_MOVX_AI :begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_SUBB_I : begin
ram_rd_sel = `OC8051_RRS_I;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_ORL_I : begin
ram_rd_sel = `OC8051_RRS_I;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_OR;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_XCH_I : begin
ram_rd_sel = `OC8051_RRS_I;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_SUBB_I : begin
ram_rd_sel = `OC8051_RRS_I;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_SUB;
wr = 1'b1;
psw_set = `OC8051_PS_AC;
cy_sel = `OC8051_CY_PSW;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_XCHD :begin
ram_rd_sel = `OC8051_RRS_I;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_XCH_I : begin
ram_rd_sel = `OC8051_RRS_I;
ram_wr_sel = `OC8051_RWS_I;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_XCH;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_1;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_XRL_I : begin
ram_rd_sel = `OC8051_RRS_I;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_Y;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_XCHD :begin
ram_rd_sel = `OC8051_RRS_I;
ram_wr_sel = `OC8051_RWS_I;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_XCH;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
 
//op_code [7:0]
`OC8051_ADD_D : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_Y;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_XRL_I : begin
ram_rd_sel = `OC8051_RRS_I;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_XOR;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_ADD_C : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
 
//op_code [7:0]
`OC8051_ADD_D : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_ADD;
wr = 1'b1;
psw_set = `OC8051_PS_AC;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_ADDC_D : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_ADD_C : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_ADD;
wr = 1'b1;
psw_set = `OC8051_PS_AC;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_ADDC_C : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_ADDC_D : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_ADD;
wr = 1'b1;
psw_set = `OC8051_PS_AC;
cy_sel = `OC8051_CY_PSW;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_ANL_D : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_ADDC_C : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_ADD;
wr = 1'b1;
psw_set = `OC8051_PS_AC;
cy_sel = `OC8051_CY_PSW;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_ANL_C : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_ANL_D : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_AND;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_ANL_DD : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_ANL_C : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_AND;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_ANL_DC : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_ANL_DD : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_AND;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_ANL_B : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_ANL_DC : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_AND;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP3;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b1;
end
`OC8051_ANL_NB : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_ANL_B : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_AND;
wr = 1'b0;
psw_set = `OC8051_PS_CY;
cy_sel = `OC8051_CY_PSW;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b1;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_ANL_NB : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_RR;
wr = 1'b0;
psw_set = `OC8051_PS_CY;
cy_sel = `OC8051_CY_PSW;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b1;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_CJNE_D : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_SUB;
wr = 1'b0;
psw_set = `OC8051_PS_CY;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b1;
end
`OC8051_CJNE_D : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_CJNE_C : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_IMM;
alu_op = `OC8051_ALU_SUB;
wr = 1'b0;
psw_set = `OC8051_PS_CY;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_CJNE_C : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_CLR_A : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_SUB;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_CLR_A : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_CLR_C : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_CY;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_CLR_C : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_CLR_B : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b1;
bit_addr = 1'b0;
end
`OC8051_CLR_B : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_CPL_A : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOT;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP3; ///****
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b1;
end
`OC8051_CPL_A : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_CPL_C : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOT;
wr = 1'b0;
psw_set = `OC8051_PS_CY;
cy_sel = `OC8051_CY_PSW;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP3; ///*****
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_CPL_C : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_CPL_B : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOT;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_RAM;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP3; ///***
bit_addr = 1'b0;
end
`OC8051_CPL_B : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_DA : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_DA;
wr = 1'b1;
psw_set = `OC8051_PS_CY;
cy_sel = `OC8051_CY_PSW;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b1;
end
`OC8051_DA : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_DEC_A : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_ZERO;
alu_op = `OC8051_ALU_SUB;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_1;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_DEC_A : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_DEC_D : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ZERO;
alu_op = `OC8051_ALU_SUB;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_1;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_DEC_D : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_DIV : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_B;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_DIV;
wr = 1'b0;
psw_set = `OC8051_PS_OV;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_DIV : begin
ram_rd_sel = `OC8051_RRS_B;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_DJNZ_D : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ZERO;
alu_op = `OC8051_ALU_SUB;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_1;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_DJNZ_D : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_INC_A : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_ZERO;
alu_op = `OC8051_ALU_ADD;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_1;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_INC_A : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_INC_D : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ZERO;
alu_op = `OC8051_ALU_ADD;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_1;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_INC_D : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_INC_DP : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_DPTR;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ZERO;
alu_op = `OC8051_ALU_ADD;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_1;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DP;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_INC_DP : begin
ram_rd_sel = `OC8051_RRS_DPTR;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_JB : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_IMM;
alu_op = `OC8051_ALU_PCS;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP3_PCL;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_BIT;
rmw = `OC8051_RMW_N; bit_addr = 1'b1;
bit_addr = 1'b0;
end
`OC8051_JB : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_BIT;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_JBC :begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_IMM;
alu_op = `OC8051_ALU_PCS;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP3_PCL;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_BIT;
rmw = `OC8051_RMW_Y; bit_addr = 1'b1;
bit_addr = 1'b1;
end
`OC8051_JBC :begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_BIT;
rmw = `OC8051_RMW_Y;
stb_i = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_JC : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_IMM;
alu_op = `OC8051_ALU_PCS;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2_PCL;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_CY;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b1;
end
`OC8051_JC : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_CY;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_JMP : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_ADD;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DP;
comp_sel = `OC8051_CSS_BIT;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_JMP_D : begin
ram_rd_sel = `OC8051_RRS_DPTR;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_JNB : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_IMM;
alu_op = `OC8051_ALU_PCS;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP3_PCL;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_BIT;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_JNB : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_BIT;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_JNC : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_IMM;
alu_op = `OC8051_ALU_PCS;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2_PCL;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_CY;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b1;
end
`OC8051_JNC : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_CY;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_JNZ :begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_IMM;
alu_op = `OC8051_ALU_PCS;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2_PCL;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_AZ;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_JNZ :begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_AZ;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_JZ : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_IMM;
alu_op = `OC8051_ALU_PCS;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2_PCL;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_AZ;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
bit_addr = 1'b0;
end
`OC8051_JZ : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_AZ;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_LCALL :begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_SP;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
imm_sel = `OC8051_IDS_PCL;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_Y;
pc_sel = `OC8051_PIS_I16;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_LCALL :begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_Y;
pc_sel = `OC8051_PIS_I16;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_LJMP : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
imm_sel = `OC8051_IDS_DC;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_Y;
pc_sel = `OC8051_PIS_I16;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_LJMP : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_Y;
pc_sel = `OC8051_PIS_I16;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_MOV_D : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_MOV_D : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_MOV_C : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_MOV_C : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
 
`OC8051_MOV_DA : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
 
`OC8051_MOV_DA : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_MOV_DD : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_D3;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_MOV_DD : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_MOV_CD : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP3;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_MOV_CD : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_MOV_BC : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_CY;
cy_sel = `OC8051_CY_RAM;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b1;
bit_addr = 1'b0;
end
`OC8051_MOV_BC : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_MOV_CB : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_PSW;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP3;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b1;
bit_addr = 1'b1;
end
`OC8051_MOV_CB : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_MOV_DP : begin ///***
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DPTR;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_IMM;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP3_OP2;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b1;
end
`OC8051_MOV_DP : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_MOVC_DP :begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_ADD;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DP;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_MOVC_DP :begin
ram_rd_sel = `OC8051_RRS_DPTR;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_MOVC_PC : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_ADD;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_PCL;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_MOVC_PC : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_MOVX_PA : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_XRAM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_MOVX_AP : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_XRAM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_MUL : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_B;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_MUL;
wr = 1'b0;
psw_set = `OC8051_PS_OV;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_MOVX_PA : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_ORL_D : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_OR;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_MOVX_AP : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
bit_addr = 1'b0;
end
`OC8051_MUL : begin
ram_rd_sel = `OC8051_RRS_B;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
bit_addr = 1'b0;
end
`OC8051_ORL_D : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_ORL_C : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_OR;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_ORL_C : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_ORL_AD : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_OR;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_ORL_AD : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_ORL_CD : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_OR;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP3;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_ORL_CD : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_ORL_B : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_OR;
wr = 1'b0;
psw_set = `OC8051_PS_CY;
cy_sel = `OC8051_CY_PSW;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b1;
bit_addr = 1'b0;
end
`OC8051_ORL_B : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_ORL_NB : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_RL;
wr = 1'b0;
psw_set = `OC8051_PS_CY;
cy_sel = `OC8051_CY_PSW;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b1;
bit_addr = 1'b1;
end
`OC8051_ORL_NB : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_POP : begin
ram_rd_sel = `OC8051_RRS_SP;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b1;
end
`OC8051_POP : begin
ram_rd_sel = `OC8051_RRS_SP;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_PUSH : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_SP;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_PUSH : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_RET : begin
ram_rd_sel = `OC8051_RRS_SP;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_RET : begin
ram_rd_sel = `OC8051_RRS_SP;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_RETI : begin
ram_rd_sel = `OC8051_RRS_SP;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_RETI : begin
ram_rd_sel = `OC8051_RRS_SP;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_RL : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_RL;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_RL : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_RLC : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_RLC;
wr = 1'b1;
psw_set = `OC8051_PS_CY;
cy_sel = `OC8051_CY_PSW;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_RLC : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_RR : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_RR;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_RR : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_RRC : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_RRC;
wr = 1'b1;
psw_set = `OC8051_PS_CY;
cy_sel = `OC8051_CY_PSW;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_RRC : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_SETB_C : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_CY;
cy_sel = `OC8051_CY_1;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_SETB_C : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_SETB_B : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_1;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b1;
bit_addr = 1'b0;
end
`OC8051_SETB_B : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_SJMP : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_IMM;
alu_op = `OC8051_ALU_PCS;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2_PCL;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b1;
end
`OC8051_SJMP : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_SUBB_D : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_SUB;
wr = 1'b1;
psw_set = `OC8051_PS_AC;
cy_sel = `OC8051_CY_PSW;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_SUBB_D : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_SUBB_C : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_IMM;
alu_op = `OC8051_ALU_SUB;
wr = 1'b1;
psw_set = `OC8051_PS_AC;
cy_sel = `OC8051_CY_PSW;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_SUBB_C : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_SWAP : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_RLC;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_SWAP : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_Y;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_XCH_D : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_XCH;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_1;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_XCH_D : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_Y;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_XRL_D : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_XOR;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_XRL_D : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_XRL_C : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_XOR;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_XRL_C : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_XRL_AD : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_XOR;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_XRL_AD : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
`OC8051_XRL_CD : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_XOR;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP3;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y; bit_addr = 1'b0;
bit_addr = 1'b0;
end
`OC8051_XRL_CD : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_Y;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
default: begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
imm_sel = `OC8051_IDS_DC;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
bit_addr = 1'b0;
end
default: begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
end
 
endcase
end
endcase
end
end
 
//
// remember current instruction
always @(posedge clk or posedge rst)
if (rst) op <= #1 2'b00;
else if (state==2'b00) op <= #1 op_in;
 
//
// in case of instructions that needs more than one clock set state
always @(posedge clk or posedge rst)
begin
if (rst)
state <= #1 2'b01;
else if (istb_t && !iack) begin
state <= #1 2'b10;
end else begin
case (state)
2'b10: state <= #1 2'b01;
2'b11: state <= #1 2'b10;
2'b00:
casex (op_in)
`OC8051_ACALL :state <= #1 2'b01;
`OC8051_AJMP : state <= #1 2'b01;
`OC8051_CJNE_R :state <= #1 2'b11;
`OC8051_CJNE_I :state <= #1 2'b11;
`OC8051_CJNE_D : state <= #1 2'b11;
`OC8051_CJNE_C : state <= #1 2'b11;
`OC8051_LJMP : state <= #1 2'b01;
`OC8051_DJNZ_R :state <= #1 2'b11;
`OC8051_DJNZ_D :state <= #1 2'b11;
`OC8051_LCALL :state <= #1 2'b01;
`OC8051_MOVC_DP :state <= #1 2'b11;
`OC8051_MOVC_PC :state <= #1 2'b11;
`OC8051_RET : state <= #1 2'b11;
`OC8051_RETI : state <= #1 2'b11;
`OC8051_SJMP : state <= #1 2'b10;
`OC8051_JB : state <= #1 2'b10;
`OC8051_JBC : state <= #1 2'b10;
`OC8051_JC : state <= #1 2'b10;
`OC8051_JMP : state <= #1 2'b10;
`OC8051_JNC : state <= #1 2'b10;
`OC8051_JNB : state <= #1 2'b10;
`OC8051_JNZ : state <= #1 2'b10;
`OC8051_JZ : state <= #1 2'b10;
`OC8051_DIV : state <= #1 2'b11;
`OC8051_MUL : state <= #1 2'b11;
default: state <= #1 2'b00;
endcase
default: state <= #1 2'b00;
endcase
end
end
 
//
//in case of reti
always @(posedge clk or posedge rst)
if (rst) reti <= #1 1'b0;
else if (op==`OC8051_RETI) reti <= #1 1'b1;
else reti <= #1 1'b0;
 
//
//in case of writing to external ram
always @(op_in or rd)
begin
if (rd)
begin
casex (op_in)
`OC8051_MOVX_AI : begin
stb = 1'b0;
write_x = 1'b1;
end
`OC8051_MOVX_AP : begin
stb = 1'b0;
write_x = 1'b1;
end
`OC8051_MOVX_IA : begin
stb = 1'b1;
write_x = 1'b0;
end
`OC8051_MOVX_PA : begin
stb = 1'b1;
write_x = 1'b0;
end
default : begin
stb = 1'b0;
write_x = 1'b0;
end
endcase
end else begin
write_x = 1'b0;
stb =1'b0;
end
end
 
always @(op_in)
begin
casex (op_in)
`OC8051_MOVX_AI : begin
ext_addr_sel = `OC8051_EAS_RI;
wr_xaddr = 1'b1;
end
`OC8051_MOVX_AP : begin
ext_addr_sel = `OC8051_EAS_DPTR;
wr_xaddr = 1'b1;
end
`OC8051_MOVX_IA : begin
ext_addr_sel = `OC8051_EAS_RI;
wr_xaddr = 1'b1;
end
`OC8051_MOVX_PA : begin
ext_addr_sel = `OC8051_EAS_DPTR;
wr_xaddr = 1'b1;
end
default: begin
wr_xaddr = 1'b0;
ext_addr_sel = `OC8051_EAS_DPTR;
end
endcase
end
 
 
always @(posedge clk or posedge rst)
begin
if (rst) begin
stbw <= #1 1'b0;
end else
stbw <= #1 write_x;
end
 
 
always @(posedge clk or posedge rst)
begin
if (rst) begin
stb_buff <= #1 1'b0;
we_buff <= #1 1'b0;
end else if (ack_i) begin
stb_buff <= #1 1'b0;
we_buff <= #1 1'b0;
end else if (stb || stbw) begin
stb_buff <= #1 1'b1;
end else if (write_x) begin
we_buff <= #1 1'b1;
end
end
bit_addr = 1'b0;
end
endcase
end
endcase
end
 
 
 
 
 
 
 
 
 
 
//
//
// registerd outputs
 
always @(posedge clk or posedge rst)
begin
if (rst) begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end else begin
case (state)
2'b01: begin
casex (op_cur)
`OC8051_MOVC_DP :begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP1;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DP;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_MOVC_PC :begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP1;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_MOVX_PA : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP1;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_MOVX_IA : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP1;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_ACALL :begin
ram_wr_sel <= #1 `OC8051_RWS_SP;
src_sel1 <= #1 `OC8051_AS1_PCH;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_AJMP : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_LCALL :begin
ram_wr_sel <= #1 `OC8051_RWS_SP;
src_sel1 <= #1 `OC8051_AS1_PCH;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_DIV : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_DIV;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_OV;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_BA;
end
`OC8051_MUL : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_MUL;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_OV;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_BA;
end
default begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
endcase
end
2'b10:
casex (op_cur)
`OC8051_CJNE_R : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_CJNE_I : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_CJNE_D : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_CJNE_C : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_DJNZ_R : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_DJNZ_D : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_JB : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_JBC : begin
ram_wr_sel <= #1 `OC8051_RWS_D;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_JC : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_JMP_D : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_JNB : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_JNC : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_JNZ : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_JZ : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_SJMP : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_DIV : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_DIV;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_OV;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_MUL : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_MUL;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_OV;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
default begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
endcase
 
2'b11:
casex (op_cur)
`OC8051_CJNE_R : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP3;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_CJNE_I : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP3;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_CJNE_D : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP3;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_CJNE_C : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP3;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_DJNZ_R : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP2;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_DJNZ_D : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP3;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_RET : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_RETI : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_DIV : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_DIV;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_OV;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_MUL : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_MUL;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_OV;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
default begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
endcase
default: begin
casex (op_cur)
`OC8051_ACALL :begin
ram_wr_sel <= #1 `OC8051_RWS_SP;
src_sel1 <= #1 `OC8051_AS1_PCL;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_AJMP : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_ADD_R : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_ADD;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_AC;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_ADDC_R : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_ADD;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_AC;
cy_sel <= #1 `OC8051_CY_PSW;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_ANL_R : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_AND;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_CJNE_R : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_OP2;
alu_op <= #1 `OC8051_ALU_SUB;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_CY;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_DEC_R : begin
ram_wr_sel <= #1 `OC8051_RWS_RN;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ZERO;
alu_op <= #1 `OC8051_ALU_SUB;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_1;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_DJNZ_R : begin
ram_wr_sel <= #1 `OC8051_RWS_RN;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ZERO;
alu_op <= #1 `OC8051_ALU_SUB;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_1;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_INC_R : begin
ram_wr_sel <= #1 `OC8051_RWS_RN;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ZERO;
alu_op <= #1 `OC8051_ALU_ADD;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_1;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_MOV_R : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_MOV_AR : begin
ram_wr_sel <= #1 `OC8051_RWS_RN;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_MOV_DR : begin
ram_wr_sel <= #1 `OC8051_RWS_RN;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_MOV_CR : begin
ram_wr_sel <= #1 `OC8051_RWS_RN;
src_sel1 <= #1 `OC8051_AS1_OP2;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_MOV_RD : begin
ram_wr_sel <= #1 `OC8051_RWS_D;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_ORL_R : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ACC;
alu_op <= #1 `OC8051_ALU_OR;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_SUBB_R : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_SUB;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_AC;
cy_sel <= #1 `OC8051_CY_PSW;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_XCH_R : begin
ram_wr_sel <= #1 `OC8051_RWS_RN;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ACC;
alu_op <= #1 `OC8051_ALU_XCH;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_1;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC2;
end
`OC8051_XRL_R : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ACC;
alu_op <= #1 `OC8051_ALU_XOR;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
 
//op_code [7:1]
`OC8051_ADD_I : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_ADD;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_AC;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_ADDC_I : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_ADD;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_AC;
cy_sel <= #1 `OC8051_CY_PSW;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_ANL_I : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_AND;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_CJNE_I : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_OP2;
alu_op <= #1 `OC8051_ALU_SUB;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_CY;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_DEC_I : begin
ram_wr_sel <= #1 `OC8051_RWS_I;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ZERO;
alu_op <= #1 `OC8051_ALU_SUB;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_1;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_INC_I : begin
ram_wr_sel <= #1 `OC8051_RWS_I;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ZERO;
alu_op <= #1 `OC8051_ALU_ADD;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_1;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_MOV_I : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_MOV_ID : begin
ram_wr_sel <= #1 `OC8051_RWS_D;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_MOV_AI : begin
ram_wr_sel <= #1 `OC8051_RWS_I;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_MOV_DI : begin
ram_wr_sel <= #1 `OC8051_RWS_I;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_MOV_CI : begin
ram_wr_sel <= #1 `OC8051_RWS_I;
src_sel1 <= #1 `OC8051_AS1_OP2;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_MOVX_IA : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_MOVX_AI :begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_ORL_I : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ACC;
alu_op <= #1 `OC8051_ALU_OR;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_SUBB_I : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_SUB;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_AC;
cy_sel <= #1 `OC8051_CY_PSW;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_XCH_I : begin
ram_wr_sel <= #1 `OC8051_RWS_I;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ACC;
alu_op <= #1 `OC8051_ALU_XCH;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_1;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC2;
end
`OC8051_XCHD :begin
ram_wr_sel <= #1 `OC8051_RWS_I;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ACC;
alu_op <= #1 `OC8051_ALU_XCH;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC2;
end
`OC8051_XRL_I : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ACC;
alu_op <= #1 `OC8051_ALU_XOR;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
 
//op_code [7:0]
`OC8051_ADD_D : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_ADD;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_AC;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_ADD_C : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP2;
src_sel2 <= #1 `OC8051_AS2_ACC;
alu_op <= #1 `OC8051_ALU_ADD;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_AC;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_ADDC_D : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_ADD;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_AC;
cy_sel <= #1 `OC8051_CY_PSW;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_ADDC_C : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP2;
src_sel2 <= #1 `OC8051_AS2_ACC;
alu_op <= #1 `OC8051_ALU_ADD;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_AC;
cy_sel <= #1 `OC8051_CY_PSW;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_ANL_D : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_AND;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_ANL_C : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP2;
src_sel2 <= #1 `OC8051_AS2_ACC;
alu_op <= #1 `OC8051_ALU_AND;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_ANL_DD : begin
ram_wr_sel <= #1 `OC8051_RWS_D;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_AND;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_ANL_DC : begin
ram_wr_sel <= #1 `OC8051_RWS_D;
src_sel1 <= #1 `OC8051_AS1_OP3;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_AND;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_ANL_B : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_AND;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_CY;
cy_sel <= #1 `OC8051_CY_PSW;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_ANL_NB : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_RR;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_CY;
cy_sel <= #1 `OC8051_CY_PSW;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_CJNE_D : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_SUB;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_CY;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_CJNE_C : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_OP2;
alu_op <= #1 `OC8051_ALU_SUB;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_CY;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_CLR_A : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_ACC;
alu_op <= #1 `OC8051_ALU_SUB;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_CLR_C : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_CY;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_CLR_B : begin
ram_wr_sel <= #1 `OC8051_RWS_D;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_CPL_A : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOT;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_CPL_C : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOT;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_CY;
cy_sel <= #1 `OC8051_CY_PSW;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_CPL_B : begin
ram_wr_sel <= #1 `OC8051_RWS_D;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOT;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_RAM;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_DA : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_DA;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_CY;
cy_sel <= #1 `OC8051_CY_PSW;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_DEC_A : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_ZERO;
alu_op <= #1 `OC8051_ALU_SUB;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_1;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_DEC_D : begin
ram_wr_sel <= #1 `OC8051_RWS_D;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ZERO;
alu_op <= #1 `OC8051_ALU_SUB;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_1;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_DIV : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_DIV;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_OV;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_DJNZ_D : begin
ram_wr_sel <= #1 `OC8051_RWS_D;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ZERO;
alu_op <= #1 `OC8051_ALU_SUB;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_1;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_INC_A : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_ZERO;
alu_op <= #1 `OC8051_ALU_ADD;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_1;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_INC_D : begin
ram_wr_sel <= #1 `OC8051_RWS_D;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ZERO;
alu_op <= #1 `OC8051_ALU_ADD;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_1;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_INC_DP : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ZERO;
alu_op <= #1 `OC8051_ALU_ADD;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_1;
src_sel3 <= #1 `OC8051_AS3_DP;
wr_sfr <= #1 `OC8051_WRS_DPTR;
end
`OC8051_JB : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP3;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_JBC :begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP3;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_JC : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP2;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_JMP_D : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_ADD;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DP;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_JNB : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP3;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_JNC : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP2;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_JNZ :begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP2;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_JZ : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP2;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_LCALL :begin
ram_wr_sel <= #1 `OC8051_RWS_SP;
src_sel1 <= #1 `OC8051_AS1_PCL;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_LJMP : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_MOV_D : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_MOV_C : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP2;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_MOV_DA : begin
ram_wr_sel <= #1 `OC8051_RWS_D;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_MOV_DD : begin
ram_wr_sel <= #1 `OC8051_RWS_D3;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_MOV_CD : begin
ram_wr_sel <= #1 `OC8051_RWS_D;
src_sel1 <= #1 `OC8051_AS1_OP3;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_MOV_BC : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_CY;
cy_sel <= #1 `OC8051_CY_RAM;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_MOV_CB : begin
ram_wr_sel <= #1 `OC8051_RWS_D;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_PSW;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_MOV_DP : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP3;
src_sel2 <= #1 `OC8051_AS2_OP2;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_DPTR;
end
`OC8051_MOVC_DP :begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_ADD;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DP;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_MOVC_PC : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_PCL;
src_sel2 <= #1 `OC8051_AS2_ACC;
alu_op <= #1 `OC8051_ALU_ADD;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_MOVX_PA : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_MOVX_AP : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_MUL : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_MUL;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_OV;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_ORL_D : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ACC;
alu_op <= #1 `OC8051_ALU_OR;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_ORL_C : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP2;
src_sel2 <= #1 `OC8051_AS2_ACC;
alu_op <= #1 `OC8051_ALU_OR;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_ORL_AD : begin
ram_wr_sel <= #1 `OC8051_RWS_D;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ACC;
alu_op <= #1 `OC8051_ALU_OR;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_ORL_CD : begin
ram_wr_sel <= #1 `OC8051_RWS_D;
src_sel1 <= #1 `OC8051_AS1_OP3;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_OR;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_ORL_B : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_OR;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_CY;
cy_sel <= #1 `OC8051_CY_PSW;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_ORL_NB : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_RL;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_CY;
cy_sel <= #1 `OC8051_CY_PSW;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_POP : begin
ram_wr_sel <= #1 `OC8051_RWS_D;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_PUSH : begin
ram_wr_sel <= #1 `OC8051_RWS_SP;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_RET : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_RETI : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_RL : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_RL;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_RLC : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_RLC;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_CY;
cy_sel <= #1 `OC8051_CY_PSW;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_RR : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_RR;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_RRC : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_RRC;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_CY;
cy_sel <= #1 `OC8051_CY_PSW;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_SETB_C : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_CY;
cy_sel <= #1 `OC8051_CY_1;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_SETB_B : begin
ram_wr_sel <= #1 `OC8051_RWS_D;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_1;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_SJMP : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP2;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_SUBB_D : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_SUB;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_AC;
cy_sel <= #1 `OC8051_CY_PSW;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_SUBB_C : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_OP2;
alu_op <= #1 `OC8051_ALU_SUB;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_AC;
cy_sel <= #1 `OC8051_CY_PSW;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_SWAP : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_RLC;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC2;
end
`OC8051_XCH_D : begin
ram_wr_sel <= #1 `OC8051_RWS_D;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ACC;
alu_op <= #1 `OC8051_ALU_XCH;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_1;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC2;
end
`OC8051_XRL_D : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ACC;
alu_op <= #1 `OC8051_ALU_XOR;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_XRL_C : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP2;
src_sel2 <= #1 `OC8051_AS2_ACC;
alu_op <= #1 `OC8051_ALU_XOR;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
`OC8051_XRL_AD : begin
ram_wr_sel <= #1 `OC8051_RWS_D;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ACC;
alu_op <= #1 `OC8051_ALU_XOR;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_XRL_CD : begin
ram_wr_sel <= #1 `OC8051_RWS_D;
src_sel1 <= #1 `OC8051_AS1_OP3;
src_sel2 <= #1 `OC8051_AS2_RAM;
alu_op <= #1 `OC8051_ALU_XOR;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
default: begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
endcase
end
endcase
end
end
 
 
//
// remember current instruction
always @(posedge clk or posedge rst)
if (rst) op <= #1 2'b00;
else if (state==2'b00) op <= #1 op_in;
 
//
// in case of instructions that needs more than one clock set state
always @(posedge clk or posedge rst)
begin
if (rst)
istb_t <= #1 1'b0;
else if (iack)
istb_t <= #1 1'b0;
else if (((op_cur== `OC8051_MOVC_DP) || (op_cur == `OC8051_MOVC_PC)) && !ea)
istb_t <= #1 1'b1;
state <= #1 2'b01;
else if (!mem_wait) begin
case (state)
2'b10: state <= #1 2'b01;
2'b11: state <= #1 2'b10;
2'b00:
casex (op_in)
`OC8051_ACALL :state <= #1 2'b01;
`OC8051_AJMP : state <= #1 2'b01;
`OC8051_CJNE_R :state <= #1 2'b11;
`OC8051_CJNE_I :state <= #1 2'b11;
`OC8051_CJNE_D : state <= #1 2'b11;
`OC8051_CJNE_C : state <= #1 2'b11;
`OC8051_LJMP : state <= #1 2'b01;
`OC8051_DJNZ_R :state <= #1 2'b11;
`OC8051_DJNZ_D :state <= #1 2'b11;
`OC8051_LCALL :state <= #1 2'b01;
`OC8051_MOVC_DP :state <= #1 2'b11;
`OC8051_MOVC_PC :state <= #1 2'b11;
`OC8051_MOVX_IA :state <= #1 2'b10;
`OC8051_MOVX_AI :state <= #1 2'b10;
`OC8051_MOVX_PA :state <= #1 2'b10;
`OC8051_MOVX_AP :state <= #1 2'b10;
`OC8051_RET : state <= #1 2'b11;
`OC8051_RETI : state <= #1 2'b11;
`OC8051_SJMP : state <= #1 2'b10;
`OC8051_JB : state <= #1 2'b10;
`OC8051_JBC : state <= #1 2'b10;
`OC8051_JC : state <= #1 2'b10;
`OC8051_JMP_D : state <= #1 2'b10;
`OC8051_JNC : state <= #1 2'b10;
`OC8051_JNB : state <= #1 2'b10;
`OC8051_JNZ : state <= #1 2'b10;
`OC8051_JZ : state <= #1 2'b10;
`OC8051_DIV : state <= #1 2'b11;
`OC8051_MUL : state <= #1 2'b11;
default: state <= #1 2'b00;
endcase
default: state <= #1 2'b00;
endcase
end
end
 
endmodule
 
 
 
//
//in case of writing to external ram
always @(posedge clk or posedge rst)
begin
if (rst) begin
mem_act <= #1 `OC8051_MAS_NO;
end else if (!rd) begin
mem_act <= #1 `OC8051_MAS_NO;
end else
casex (op_cur)
`OC8051_MOVX_AI : mem_act <= #1 `OC8051_MAS_RI_W;
`OC8051_MOVX_AP : mem_act <= #1 `OC8051_MAS_DPTR_W;
`OC8051_MOVX_IA : mem_act <= #1 `OC8051_MAS_RI_R;
`OC8051_MOVX_PA : mem_act <= #1 `OC8051_MAS_DPTR_R;
`OC8051_MOVC_DP : mem_act <= #1 `OC8051_MAS_CODE;
`OC8051_MOVC_PC : mem_act <= #1 `OC8051_MAS_CODE;
default : mem_act <= #1 `OC8051_MAS_NO;
endcase
end
 
endmodule
 
 
/trunk/rtl/verilog/oc8051_tc.v
1,216 → 1,221
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 cores timer/counter control ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// timers and counters handling for 8051 core ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
`include "oc8051_defines.v"
 
//synopsys translate_off
`include "oc8051_timescale.v"
//synopsys translate_on
 
 
 
module oc8051_tc (clk, rst, wr_addr, rd_addr, data_in, wr, wr_bit, ie0, ie1, tr0, tr1, t0, t1, data_out,
tf0, tf1);
input [7:0] wr_addr, data_in, rd_addr;
input clk, rst, wr, wr_bit, ie0, ie1, tr0, tr1, t0, t1;
output [7:0] data_out;
output tf0, tf1;
reg [7:0] tmod, tl0, th0, tl1, th1, data_out;
reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;
 
wire tc0_add, tc1_add;
 
assign tc0_add = (tr0 & (!tmod[3] | !ie0) & (!(tmod[2]) | (tmod[2] & !t0 & t0_buff)));
assign tc1_add = (tr1 & (!tmod[7] | !ie1) & (!(tmod[6]) | (tmod[6] & !t1 & t1_buff)));
assign tf1= tf1_0 | tf1_1;
 
//
// read or write from one of the addresses in tmod
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
tmod <=#1 `OC8051_RST_TMOD;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TMOD))
tmod <= #1 data_in;
end
 
//
// TIMER COUNTER 0
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
tl0 <=#1 `OC8051_RST_TL0;
th0 <=#1 `OC8051_RST_TH0;
tf0 <= #1 1'b0;
tf1_0 <= #1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL0)) begin
tl0 <= #1 data_in;
tf0 <= #1 1'b0;
tf1_0 <= #1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH0)) begin
th0 <= #1 data_in;
tf0 <= #1 1'b0;
tf1_0 <= #1 1'b0;
end else begin
case (tmod[1:0])
`OC8051_MODE0: begin // mode 0
tf1_0 <= #1 1'b0;
if (tc0_add)
{tf0, th0,tl0[4:0]} <= #1 {1'b0, th0, tl0[4:0]}+ 1'b1;
end
`OC8051_MODE1: begin // mode 1
tf1_0 <= #1 1'b0;
if (tc0_add)
{tf0, th0,tl0} <= #1 {1'b0, th0, tl0}+ 1'b1;
end
 
`OC8051_MODE2: begin // mode 2
tf1_0 <= #1 1'b0;
if (tc0_add) begin
if (tl0 == 8'b1111_1111) begin
tf0 <=#1 1'b1;
tl0 <=#1 th0;
end
else begin
tl0 <=#1 tl0 + 8'h1;
tf0 <= #1 1'b0;
end
end
end
`OC8051_MODE3: begin // mode 3
 
if (tc0_add)
{tf0, tl0} <= #1 {1'b0, tl0} +1'b1;
if (tr1)
{tf1_0, th0} <= #1 {1'b0, th0} +1'b1;
 
end
default:begin
tf0 <= #1 1'b0;
tf1_0 <= #1 1'b0;
end
endcase
end
end
 
//
// TIMER COUNTER 1
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
tl1 <=#1 `OC8051_RST_TL1;
th1 <=#1 `OC8051_RST_TH1;
tf1_1 <= #1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL1)) begin
tl1 <= #1 data_in;
tf1_1 <= #1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH1)) begin
th1 <= #1 data_in;
tf1_1 <= #1 1'b0;
end else begin
case (tmod[5:4])
`OC8051_MODE0: begin // mode 0
if (tc1_add)
{tf1_1, th1,tl1[4:0]} <= #1 {1'b0, th1, tl1[4:0]}+ 1'b1;
end
`OC8051_MODE1: begin // mode 1
if (tc1_add)
{tf1_1, th1,tl1} <= #1 {1'b0, th1, tl1}+ 1'b1;
end
 
`OC8051_MODE2: begin // mode 2
if (tc1_add) begin
if (tl1 == 8'b1111_1111) begin
tf1_1 <=#1 1'b1;
tl1 <=#1 th1;
end
else begin
tl1 <=#1 tl1 + 8'h1;
tf1_1 <= #1 1'b0;
end
end
end
default:begin
tf1_1 <= #1 1'b0;
end
endcase
end
end
 
always @(posedge clk or posedge rst)
begin
if (rst) data_out <= #1 8'h0;
else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_TH0) |
(wr_addr==`OC8051_SFR_TH1)|(wr_addr==`OC8051_SFR_TL0)|(wr_addr==`OC8051_SFR_TL1)|
(wr_addr==`OC8051_SFR_TMOD))) begin
data_out <= #1 data_in;
end else begin
case (rd_addr)
`OC8051_SFR_TH0: data_out <= #1 th0;
`OC8051_SFR_TH1: data_out <= #1 th1;
`OC8051_SFR_TL0: data_out <= #1 tl0;
`OC8051_SFR_TL1: data_out <= #1 tl1;
default: data_out <= #1 tmod;
endcase
end
end
 
 
always @(posedge clk or posedge rst)
if (rst) begin
t0_buff <= #1 1'b0;
t1_buff <= #1 1'b0;
end else begin
t0_buff <= #1 t0;
t1_buff <= #1 t1;
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 cores timer/counter control ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// timers and counters handling for 8051 core ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/09/30 17:33:59 simont
// prepared header
//
//
 
`include "oc8051_defines.v"
 
//synopsys translate_off
`include "oc8051_timescale.v"
//synopsys translate_on
 
 
 
module oc8051_tc (clk, rst, wr_addr, rd_addr, data_in, wr, wr_bit, ie0, ie1, tr0, tr1, t0, t1, data_out,
tf0, tf1);
 
input [7:0] wr_addr, data_in, rd_addr;
input clk, rst, wr, wr_bit, ie0, ie1, tr0, tr1, t0, t1;
output [7:0] data_out;
output tf0, tf1;
 
reg [7:0] tmod, tl0, th0, tl1, th1, data_out;
reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;
 
wire tc0_add, tc1_add;
 
assign tc0_add = (tr0 & (!tmod[3] | !ie0) & (!(tmod[2]) | (tmod[2] & !t0 & t0_buff)));
assign tc1_add = (tr1 & (!tmod[7] | !ie1) & (!(tmod[6]) | (tmod[6] & !t1 & t1_buff)));
assign tf1= tf1_0 | tf1_1;
 
//
// read or write from one of the addresses in tmod
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
tmod <=#1 `OC8051_RST_TMOD;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TMOD))
tmod <= #1 data_in;
end
 
//
// TIMER COUNTER 0
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
tl0 <=#1 `OC8051_RST_TL0;
th0 <=#1 `OC8051_RST_TH0;
tf0 <= #1 1'b0;
tf1_0 <= #1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL0)) begin
tl0 <= #1 data_in;
tf0 <= #1 1'b0;
tf1_0 <= #1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH0)) begin
th0 <= #1 data_in;
tf0 <= #1 1'b0;
tf1_0 <= #1 1'b0;
end else begin
case (tmod[1:0])
`OC8051_MODE0: begin // mode 0
tf1_0 <= #1 1'b0;
if (tc0_add)
{tf0, th0,tl0[4:0]} <= #1 {1'b0, th0, tl0[4:0]}+ 1'b1;
end
`OC8051_MODE1: begin // mode 1
tf1_0 <= #1 1'b0;
if (tc0_add)
{tf0, th0,tl0} <= #1 {1'b0, th0, tl0}+ 1'b1;
end
 
`OC8051_MODE2: begin // mode 2
tf1_0 <= #1 1'b0;
if (tc0_add) begin
if (tl0 == 8'b1111_1111) begin
tf0 <=#1 1'b1;
tl0 <=#1 th0;
end
else begin
tl0 <=#1 tl0 + 8'h1;
tf0 <= #1 1'b0;
end
end
end
`OC8051_MODE3: begin // mode 3
 
if (tc0_add)
{tf0, tl0} <= #1 {1'b0, tl0} +1'b1;
 
if (tr1)
{tf1_0, th0} <= #1 {1'b0, th0} +1'b1;
 
end
default:begin
tf0 <= #1 1'b0;
tf1_0 <= #1 1'b0;
end
endcase
end
end
 
//
// TIMER COUNTER 1
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
tl1 <=#1 `OC8051_RST_TL1;
th1 <=#1 `OC8051_RST_TH1;
tf1_1 <= #1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL1)) begin
tl1 <= #1 data_in;
tf1_1 <= #1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH1)) begin
th1 <= #1 data_in;
tf1_1 <= #1 1'b0;
end else begin
case (tmod[5:4])
`OC8051_MODE0: begin // mode 0
if (tc1_add)
{tf1_1, th1,tl1[4:0]} <= #1 {1'b0, th1, tl1[4:0]}+ 1'b1;
end
`OC8051_MODE1: begin // mode 1
if (tc1_add)
{tf1_1, th1,tl1} <= #1 {1'b0, th1, tl1}+ 1'b1;
end
 
`OC8051_MODE2: begin // mode 2
if (tc1_add) begin
if (tl1 == 8'b1111_1111) begin
tf1_1 <=#1 1'b1;
tl1 <=#1 th1;
end
else begin
tl1 <=#1 tl1 + 8'h1;
tf1_1 <= #1 1'b0;
end
end
end
default:begin
tf1_1 <= #1 1'b0;
end
endcase
end
end
 
always @(posedge clk or posedge rst)
begin
if (rst) data_out <= #1 8'h0;
else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_TH0) |
(wr_addr==`OC8051_SFR_TH1)|(wr_addr==`OC8051_SFR_TL0)|(wr_addr==`OC8051_SFR_TL1)|
(wr_addr==`OC8051_SFR_TMOD))) begin
data_out <= #1 data_in;
end else begin
case (rd_addr)
`OC8051_SFR_TH0: data_out <= #1 th0;
`OC8051_SFR_TH1: data_out <= #1 th1;
`OC8051_SFR_TL0: data_out <= #1 tl0;
`OC8051_SFR_TL1: data_out <= #1 tl1;
default: data_out <= #1 tmod;
endcase
end
end
 
 
always @(posedge clk or posedge rst)
if (rst) begin
t0_buff <= #1 1'b0;
t1_buff <= #1 1'b0;
end else begin
t0_buff <= #1 t0;
t1_buff <= #1 t1;
end
endmodule
/trunk/rtl/verilog/oc8051_ports.v
1,171 → 1,174
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 port output ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// 8051 special function registers: port 0:3 - output ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_ports (clk, rst, bit_in, data_in, wr, wr_bit, wr_addr, rd_addr, rmw, data_out, bit_out, p0_out, p1_out, p2_out, p3_out,
p0_in, p1_in, p2_in, p3_in);
//
// clk (in) clock
// rst (in) reset
// bit_in (in) bit input [oc8051_alu.desCy]
// data_in (in) data input (from alu destiantion 1) [oc8051_alu.des1]
// wr (in) write [oc8051_decoder.wr -r]
// wr_bit (in) write bit addresable [oc8051_decoder.bit_addr -r]
// wr_addr (in) write address [oc8051_ram_wr_sel.out]
// rd_addr (in) read address [oc8051_ram_rd_sel.out]
// rmw (in) read modify write feature [oc8051_decoder.rmw]
// data_out (out) data output [oc8051_ram_sel.ports_in]
// p0_out, p1_out, p2_out, p3_out (out) port outputs [pin]
// p0_in, p1_in, p2_in, p3_in (in) port inputs [pin]
//
 
 
input clk, rst, wr, wr_bit, bit_in, rmw;
input [7:0] wr_addr, rd_addr, data_in, p0_in, p1_in, p2_in, p3_in;
 
output bit_out;
output [7:0] data_out, p0_out, p1_out, p2_out, p3_out;
 
reg bit_out;
reg [7:0] data_out, p0_out, p1_out, p2_out, p3_out;
 
//
// case of writing to port
always @(posedge clk or posedge rst)
begin
if (rst) begin
p0_out <= #1 `OC8051_RST_P0;
p1_out <= #1 `OC8051_RST_P1;
p2_out <= #1 `OC8051_RST_P2;
p3_out <= #1 `OC8051_RST_P3;
end else if (wr) begin
if (!wr_bit) begin
case (wr_addr)
//
// bytaddresable
`OC8051_SFR_P0: p0_out <= #1 data_in;
`OC8051_SFR_P1: p1_out <= #1 data_in;
`OC8051_SFR_P2: p2_out <= #1 data_in;
`OC8051_SFR_P3: p3_out <= #1 data_in;
endcase
end else begin
case (wr_addr[7:3])
 
//
// bit addressable
`OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= #1 bit_in;
`OC8051_SFR_B_P1: p1_out[wr_addr[2:0]] <= #1 bit_in;
`OC8051_SFR_B_P2: p2_out[wr_addr[2:0]] <= #1 bit_in;
`OC8051_SFR_B_P3: p3_out[wr_addr[2:0]] <= #1 bit_in;
endcase
end
end
end
 
//always @(p0_out or p0_in or p1_out or p1_in or p2_out or p2_in or p3_out or p3_in or rmw)
always @(posedge clk or posedge rst)
begin
if (rst)
data_out <= #1 8'h0;
else if (rmw) begin
if ((rd_addr==wr_addr) & wr & !wr_bit)
data_out <= #1 data_in;
else begin
case (rd_addr[5:4])
2'b00: data_out <= #1 p0_out;
2'b01: data_out <= #1 p1_out;
2'b10: data_out <= #1 p2_out;
2'b11: data_out <= #1 p3_out;
endcase
end
end else
case (rd_addr[5:4])
2'b00: data_out <= #1 p0_in;
2'b01: data_out <= #1 p1_in;
2'b10: data_out <= #1 p2_in;
2'b11: data_out <= #1 p3_in;
endcase
end
 
//always @(rmw or rd_addr or p0_out or p1_out or p2_out or p3_out or p0_in or p1_in or p2_in or p3_in)
always @(posedge clk or posedge rst)
begin
if (rst)
bit_out <= #1 1'b0;
else if (rmw) begin
if ((wr_addr==rd_addr) & wr & wr_bit)
bit_out <= #1 bit_in;
else if ((wr_addr[7:3]==rd_addr[7:3]) & wr & !wr_bit)
bit_out <= #1 data_in[rd_addr[2:0]];
else begin
case (rd_addr[7:3])
`OC8051_SFR_B_P0: bit_out <= #1 p0_out[rd_addr[2:0]];
`OC8051_SFR_B_P1: bit_out <= #1 p1_out[rd_addr[2:0]];
`OC8051_SFR_B_P2: bit_out <= #1 p2_out[rd_addr[2:0]];
default: bit_out <= #1 p3_out[rd_addr[2:0]];
endcase
end
end else begin
case (rd_addr[7:3])
`OC8051_SFR_B_P0: bit_out <= #1 p0_in[rd_addr[2:0]];
`OC8051_SFR_B_P1: bit_out <= #1 p1_in[rd_addr[2:0]];
`OC8051_SFR_B_P2: bit_out <= #1 p2_in[rd_addr[2:0]];
default: bit_out <= #1 p3_in[rd_addr[2:0]];
endcase
end
end
 
endmodule
 
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 port output ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// 8051 special function registers: port 0:3 - output ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2002/09/30 17:33:59 simont
// prepared header
//
//
 
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_ports (clk, rst, bit_in, data_in, wr, wr_bit, wr_addr, rd_addr, rmw, data_out, bit_out, p0_out, p1_out, p2_out, p3_out,
p0_in, p1_in, p2_in, p3_in);
//
// clk (in) clock
// rst (in) reset
// bit_in (in) bit input [oc8051_alu.desCy]
// data_in (in) data input (from alu destiantion 1) [oc8051_alu.des1]
// wr (in) write [oc8051_decoder.wr -r]
// wr_bit (in) write bit addresable [oc8051_decoder.bit_addr -r]
// wr_addr (in) write address [oc8051_ram_wr_sel.out]
// rd_addr (in) read address [oc8051_ram_rd_sel.out]
// rmw (in) read modify write feature [oc8051_decoder.rmw]
// data_out (out) data output [oc8051_ram_sel.ports_in]
// p0_out, p1_out, p2_out, p3_out (out) port outputs [pin]
// p0_in, p1_in, p2_in, p3_in (in) port inputs [pin]
//
 
 
input clk, rst, wr, wr_bit, bit_in, rmw;
input [7:0] wr_addr, rd_addr, data_in, p0_in, p1_in, p2_in, p3_in;
 
output bit_out;
output [7:0] data_out, p0_out, p1_out, p2_out, p3_out;
 
reg bit_out;
reg [7:0] data_out, p0_out, p1_out, p2_out, p3_out;
 
//
// case of writing to port
always @(posedge clk or posedge rst)
begin
if (rst) begin
p0_out <= #1 `OC8051_RST_P0;
p1_out <= #1 `OC8051_RST_P1;
p2_out <= #1 `OC8051_RST_P2;
p3_out <= #1 `OC8051_RST_P3;
end else if (wr) begin
if (!wr_bit) begin
case (wr_addr)
//
// bytaddresable
`OC8051_SFR_P0: p0_out <= #1 data_in;
`OC8051_SFR_P1: p1_out <= #1 data_in;
`OC8051_SFR_P2: p2_out <= #1 data_in;
`OC8051_SFR_P3: p3_out <= #1 data_in;
endcase
end else begin
case (wr_addr[7:3])
 
//
// bit addressable
`OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= #1 bit_in;
`OC8051_SFR_B_P1: p1_out[wr_addr[2:0]] <= #1 bit_in;
`OC8051_SFR_B_P2: p2_out[wr_addr[2:0]] <= #1 bit_in;
`OC8051_SFR_B_P3: p3_out[wr_addr[2:0]] <= #1 bit_in;
endcase
end
end
end
 
//always @(p0_out or p0_in or p1_out or p1_in or p2_out or p2_in or p3_out or p3_in or rmw)
always @(posedge clk or posedge rst)
begin
if (rst)
data_out <= #1 8'h0;
else if (rmw) begin
if ((rd_addr==wr_addr) & wr & !wr_bit)
data_out <= #1 data_in;
else begin
case (rd_addr[5:4])
2'b00: data_out <= #1 p0_out;
2'b01: data_out <= #1 p1_out;
2'b10: data_out <= #1 p2_out;
2'b11: data_out <= #1 p3_out;
endcase
end
end else
case (rd_addr[5:4])
2'b00: data_out <= #1 p0_in;
2'b01: data_out <= #1 p1_in;
2'b10: data_out <= #1 p2_in;
2'b11: data_out <= #1 p3_in;
endcase
end
 
//always @(rmw or rd_addr or p0_out or p1_out or p2_out or p3_out or p0_in or p1_in or p2_in or p3_in)
always @(posedge clk or posedge rst)
begin
if (rst)
bit_out <= #1 1'b0;
else if (rmw) begin
if ((wr_addr==rd_addr) & wr & wr_bit)
bit_out <= #1 bit_in;
else if ((wr_addr[7:3]==rd_addr[7:3]) & wr)
bit_out <= #1 data_in[rd_addr[2:0]];
else begin
case (rd_addr[7:3])
`OC8051_SFR_B_P0: bit_out <= #1 p0_out[rd_addr[2:0]];
`OC8051_SFR_B_P1: bit_out <= #1 p1_out[rd_addr[2:0]];
`OC8051_SFR_B_P2: bit_out <= #1 p2_out[rd_addr[2:0]];
default: bit_out <= #1 p3_out[rd_addr[2:0]];
endcase
end
end else begin
case (rd_addr[7:3])
`OC8051_SFR_B_P0: bit_out <= #1 p0_in[rd_addr[2:0]];
`OC8051_SFR_B_P1: bit_out <= #1 p1_in[rd_addr[2:0]];
`OC8051_SFR_B_P2: bit_out <= #1 p2_in[rd_addr[2:0]];
default: bit_out <= #1 p3_in[rd_addr[2:0]];
endcase
end
end
 
endmodule
 
/trunk/rtl/verilog/oc8051_dptr.v
1,98 → 1,101
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 data pointer ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// 8051 special function register: data pointer ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_dptr(clk, rst, addr, data_in, data2_in, wr, wd2, wr_bit, data_hi, data_lo);
//
// clk (in) clock
// rst (in) reset
// addr (in) write address input [oc8051_ram_wr_sel.out]
// data_in (in) destination 1 from alu [oc8051_alu.des1]
// data2_in (in) destination 2 from alu [oc8051_alu.des2]
// wr (in) write to ram [oc8051_decoder.wr -r]
// wd2 (in) write from destination 2 [oc8051_decoder.ram_wr_sel -r]
// wr_bit (in) write bit addresable [oc8051_decoder.bit_addr -r]
// data_hi (out) output (high bits) [oc8051_alu_src3_sel.dptr, oc8051_ext_addr_sel.dptr_hi, oc8051_ram_sel.dptr_hi]
// data_lo (out) output (low bits) [oc8051_ext_addr_sel.dptr_lo]
//
 
 
input clk, rst, wr, wr_bit;
input [2:0] wd2;
input [7:0] addr, data_in, data2_in;
 
output [7:0] data_hi, data_lo;
 
reg [7:0] data_hi, data_lo;
 
always @(posedge clk or posedge rst)
begin
if (rst) begin
data_hi <= #1 `OC8051_RST_DPH;
data_lo <= #1 `OC8051_RST_DPL;
end else if (wd2==`OC8051_RWS_DPTR) begin
//
//write from destination 2 and 1
data_hi <= #1 data2_in;
data_lo <= #1 data_in;
end else if ((addr==`OC8051_SFR_DPTR_HI) & (wr) & !(wr_bit))
//
//case of writing to dptr
data_hi <= #1 data_in;
else if ((addr==`OC8051_SFR_DPTR_LO) & (wr) & !(wr_bit))
data_lo <= #1 data_in;
end
 
endmodule
 
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 data pointer ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// 8051 special function register: data pointer ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/09/30 17:33:59 simont
// prepared header
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_dptr(clk, rst, addr, data_in, data2_in, wr, wr_sfr, wr_bit, data_hi, data_lo);
//
// clk (in) clock
// rst (in) reset
// addr (in) write address input [oc8051_ram_wr_sel.out]
// data_in (in) destination 1 from alu [oc8051_alu.des1]
// data2_in (in) destination 2 from alu [oc8051_alu.des2]
// wr (in) write to ram [oc8051_decoder.wr -r]
// wd2 (in) write from destination 2 [oc8051_decoder.ram_wr_sel -r]
// wr_bit (in) write bit addresable [oc8051_decoder.bit_addr -r]
// data_hi (out) output (high bits) [oc8051_alu_src3_sel.dptr, oc8051_ext_addr_sel.dptr_hi, oc8051_ram_sel.dptr_hi]
// data_lo (out) output (low bits) [oc8051_ext_addr_sel.dptr_lo]
//
 
 
input clk, rst, wr, wr_bit;
input [2:0] wr_sfr;
input [7:0] addr, data_in, data2_in;
 
output [7:0] data_hi, data_lo;
 
reg [7:0] data_hi, data_lo;
 
always @(posedge clk or posedge rst)
begin
if (rst) begin
data_hi <= #1 `OC8051_RST_DPH;
data_lo <= #1 `OC8051_RST_DPL;
end else if (wr_sfr==`OC8051_WRS_DPTR) begin
//
//write from destination 2 and 1
data_hi <= #1 data2_in;
data_lo <= #1 data_in;
end else if ((addr==`OC8051_SFR_DPTR_HI) & (wr) & !(wr_bit))
//
//case of writing to dptr
data_hi <= #1 data_in;
else if ((addr==`OC8051_SFR_DPTR_LO) & (wr) & !(wr_bit))
data_lo <= #1 data_in;
end
 
endmodule
 
/trunk/rtl/verilog/oc8051_psw.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2002/11/05 17:23:54 simont
// add module oc8051_sfr, 256 bytes internal ram
//
// Revision 1.7 2002/09/30 17:33:59 simont
// prepared header
//
57,7 → 60,8
`include "oc8051_defines.v"
 
 
module oc8051_psw (clk, rst, wr_addr, rd_addr, data_in, wr, wr_bit, data_out, bit_out, p, cy_in, ac_in, ov_in, set, bank_sel);
module oc8051_psw (clk, rst, wr_addr, rd_addr, data_in, wr, wr_bit, data_out, bit_out, p,
cy_in, ac_in, ov_in, set, bank_sel);
//
// clk (in) clock
// rst (in) reset
90,6 → 94,7
assign wr_psw = (wr & (wr_addr==`OC8051_SFR_PSW) && !wr_bit);
 
assign bank_sel = wr_psw ? data_in[4:3]:data[4:3];
//assign bank_sel = data[4:3];
assign data_out = data;
 
//
/trunk/rtl/verilog/oc8051_uart.v
1,422 → 1,425
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 cores serial interface ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// uart for 8051 core ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
module oc8051_uart (rst, clk, bit_in, rd_addr, data_in, bit_out, wr, wr_bit, wr_addr, data_out,
rxd, txd, intr, t1_ow);
 
input rst, clk, bit_in, wr, rxd, wr_bit, t1_ow;
input [7:0] rd_addr, data_in, wr_addr;
 
output txd, intr, bit_out;
output [7:0] data_out;
 
reg txd, bit_out;
reg [7:0] data_out;
 
reg tr_start, trans, trans_buf, t1_ow_buf;
reg [5:0] smod_cnt_r, smod_cnt_t;
reg receive, receive_buf, rxd_buf, r_int;
//
reg [7:0] sbuf_rxd, sbuf_txd, scon, pcon;
reg [10:0] sbuf_rxd_tmp;
//
//tr_count trancive counter
//re_count receive counter
reg [3:0] tr_count, re_count, re_count_buff;
 
 
assign intr = scon[1] | scon [0];
 
//
//serial port control register
//
always @(posedge clk or posedge rst)
begin
if (rst)
scon <= #1 `OC8051_RST_SCON;
else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
scon <= #1 data_in;
else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
scon[wr_addr[2:0]] <= #1 bit_in;
else if ((trans_buf) & !(trans))
scon[1] <= #1 1'b1;
else if ((receive_buf) & !(receive) & !(sbuf_rxd_tmp[0])) begin
case (scon[7:6])
2'b00: scon[0] <= #1 1'b1;
default: begin
if ((sbuf_rxd_tmp[9]) | !(scon[5])) scon[0] <= #1 1'b1;
scon[2] <= #1 sbuf_rxd_tmp[9];
end
endcase
end
 
end
 
//
//serial port buffer (transmit)
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
sbuf_txd <= #1 `OC8051_RST_SBUF;
tr_start <= #1 1'b0;
end else if ((wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit)) begin
sbuf_txd <= #1 data_in;
tr_start <= #1 1'b1;
end else tr_start <= #1 1'b0;
end
 
//
// transmit
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
txd <= #1 1'b1;
tr_count <= #1 4'd0;
trans <= #1 1'b0;
smod_cnt_t <= #1 6'h0;
//
// start transmiting
//
end else if (tr_start) begin
case (scon[7:6])
2'b00: begin // mode 0
txd <= #1 sbuf_txd[0];
tr_count <= #1 4'd1;
end
2'b10: begin
txd <= #1 1'b0;
tr_count <= #1 4'd0;
end
default: begin // mode 1 and mode 3
tr_count <= #1 4'b1111;
end
endcase
trans <= #1 1'b1;
smod_cnt_t <= #1 6'h0;
//
// transmiting/
//
end else if (trans)
begin
case (scon[7:6])
2'b00: begin //mode 0
if (smod_cnt_t == 6'd12) begin
if (tr_count==4'd8)
begin
trans <= #1 1'b0;
txd <= #1 1'b1;
end else begin
txd <= #1 sbuf_txd[tr_count];
tr_count <= #1 tr_count + 4'b1;
end
smod_cnt_t <= #1 6'h0;
end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;
end
2'b01: begin // mode 1
if ((t1_ow) & !(t1_ow_buf))
begin
if (((pcon[7]) & (smod_cnt_t == 6'd15))| (!(pcon[7]) & (smod_cnt_t==6'd31)))
begin
case (tr_count)
4'd8: txd <= #1 1'b1; // stop bit
4'd9: trans <= #1 1'b0;
4'b1111: txd <= #1 1'b0; //start bit
default: txd <= #1 sbuf_txd[tr_count];
endcase
tr_count <= #1 tr_count + 4'b1;
smod_cnt_t <= #1 6'h0;
end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;
end
end
2'b10: begin // mode 2
//
// if smod (pcon[7]) is 1 count to 4 else count to 6
//
if (((pcon[7]) & (smod_cnt_t==6'd31)) | (!(pcon[7]) & (smod_cnt_t==6'd63))) begin
case (tr_count)
4'd8: begin
txd <= #1 scon[3];
end
4'd9: begin
txd <= #1 1'b1; //stop bit
end
4'd10: begin
trans <= #1 1'b0;
end
default: begin
txd <= #1 sbuf_txd[tr_count];
end
endcase
tr_count <= #1 tr_count+1'b1;
smod_cnt_t <= #1 6'h00;
end else begin
smod_cnt_t <= #1 smod_cnt_t + 6'h01;
end
end
default: begin // mode 3
if ((t1_ow) & !(t1_ow_buf))
begin
if (((pcon[7]) & (smod_cnt_t == 6'd15))| (!(pcon[7]) & (smod_cnt_t==6'd31)))
begin
case (tr_count)
4'd8: begin
txd <= #1 scon[3];
end
4'd9: begin
txd <= #1 1'b1; //stop bit
end
4'd10: begin
trans <= #1 1'b0;
end
4'b1111: txd <= #1 1'b0; //start bit
default: begin
txd <= #1 sbuf_txd[tr_count];
end
endcase
tr_count <= #1 tr_count+1'b1;
smod_cnt_t <= #1 6'h00;
end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;
end
end
endcase
end else
txd <= #1 1'b1;
end
 
//
//power control register
//
always @(posedge clk or posedge rst)
begin
if (rst)
begin
pcon <= #1 `OC8051_RST_PCON;
end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
pcon <= #1 data_in;
end
 
//
//serial port buffer (receive)
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
re_count <= #1 4'd0;
receive <= #1 1'b0;
sbuf_rxd <= #1 8'h00;
sbuf_rxd_tmp <= #1 11'd0;
smod_cnt_r <= #1 6'h00;
r_int <= #1 1'b0;
end else if (receive) begin
case (scon[7:6])
2'b00: begin // mode 0
if (smod_cnt_r==6'd12) begin
if (re_count==4'd8) begin
receive <= #1 1'b0;
r_int <= #1 1'b1;
sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
end else begin
sbuf_rxd_tmp[re_count + 4'd1] <= #1 rxd;
r_int <= #1 1'b0;
end
re_count <= #1 re_count + 4'd1;
smod_cnt_r <= #1 6'h00;
end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;
end
2'b01: begin // mode 1
if ((t1_ow) & !(t1_ow_buf))
begin
if (((pcon[7]) & (smod_cnt_r == 6'd15))| (!(pcon[7]) & (smod_cnt_r==6'd31)))
begin
r_int <= #1 1'b0;
re_count <= #1 re_count + 4'd1;
smod_cnt_r <= #1 6'h00;
sbuf_rxd_tmp[re_count_buff] <= #1 rxd;
if ((re_count==4'd0) && (rxd))
receive <= #1 1'b0;
 
end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;
end else begin
r_int <= #1 1'b1;
if (re_count == 4'd10)
begin
sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
receive <= #1 1'b0;
r_int <= #1 1'b1;
end else r_int <= #1 1'b0;
end
end
2'b10: begin // mode 2
if (((pcon[7]) & (smod_cnt_r==6'd31)) | (!(pcon[7]) & (smod_cnt_r==6'd63))) begin
r_int <= #1 1'b0;
re_count <= #1 re_count + 4'd1;
smod_cnt_r <= #1 6'h00;
sbuf_rxd_tmp[re_count_buff] <= #1 rxd;
re_count <= #1 re_count + 4'd1;
end else begin
smod_cnt_r <= #1 smod_cnt_r + 6'h1;
if (re_count==4'd11) begin
sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
receive <= #1 1'b0;
end else
r_int <= #1 1'b0;
end
end
default: begin // mode 3
if ((t1_ow) & !(t1_ow_buf))
begin
if (((pcon[7]) & (smod_cnt_r == 6'd15))| (!(pcon[7]) & (smod_cnt_r==6'd31)))
begin
sbuf_rxd_tmp[re_count] <= #1 rxd;
r_int <= #1 1'b0;
re_count <= #1 re_count + 4'd1;
smod_cnt_r <= #1 6'h00;
end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;
end else begin
if (re_count==4'd11) begin
sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
receive <= #1 1'b0;
r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
end else begin
r_int <= #1 1'b0;
end
end
end
endcase
end else begin
case (scon[7:6])
2'b00: begin
if ((scon[4]) && !(scon[0]) && !(r_int)) begin
receive <= #1 1'b1;
smod_cnt_r <= #1 6'h6;
end
end
2'b10: begin
if ((scon[4]) && !(rxd)) begin
receive <= #1 1'b1;
if (pcon[7])
smod_cnt_r <= #1 6'd15;
else smod_cnt_r <= #1 6'd31;
end
end
default: begin
if ((scon[4]) && (!rxd)) begin
if (pcon[7])
smod_cnt_r <= #1 6'd7;
else smod_cnt_r <= #1 6'd15;
receive <= #1 1'b1;
end
end
endcase
sbuf_rxd_tmp <= #1 11'd0;
re_count <= #1 4'd0;
r_int <= #1 1'b0;
end
end
 
//
//
//
always @(posedge clk or posedge rst)
begin
if (rst) data_out <= #1 8'h0;
else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_PCON) |
(wr_addr==`OC8051_SFR_SCON))) begin
data_out <= #1 data_in;
end else begin
case (rd_addr)
`OC8051_SFR_SBUF: data_out <= #1 sbuf_rxd;
`OC8051_SFR_PCON: data_out <= #1 pcon;
default: data_out <= #1 scon;
endcase
end
end
 
 
always @(posedge clk or posedge rst)
begin
if (rst) begin
trans_buf <= #1 1'b0;
receive_buf <= #1 1'b0;
t1_ow_buf <= #1 1'b0;
rxd_buf <= #1 1'b0;
end else begin
trans_buf <= #1 trans;
receive_buf <= #1 receive;
t1_ow_buf <= #1 t1_ow;
rxd_buf <= #1 rxd;
end
end
 
always @(posedge clk or posedge rst)
begin
if (rst) bit_out <= #1 1'b0;
else if (wr & wr_bit & (rd_addr==wr_addr) & (wr_addr[7:3]==`OC8051_SFR_B_SCON)) begin
bit_out <= #1 bit_in;
end else
bit_out <= #1 scon[rd_addr[2:0]];
end
 
always @(posedge clk or posedge rst)
if (rst)
re_count_buff <= #1 4'h4;
else re_count_buff <= #1 re_count;
 
endmodule
 
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 cores serial interface ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// uart for 8051 core ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2002/09/30 17:33:59 simont
// prepared header
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
module oc8051_uart (rst, clk, bit_in, rd_addr, data_in, bit_out, wr, wr_bit, wr_addr, data_out,
rxd, txd, intr, t1_ow);
 
input rst, clk, bit_in, wr, rxd, wr_bit, t1_ow;
input [7:0] rd_addr, data_in, wr_addr;
 
output txd, intr, bit_out;
output [7:0] data_out;
 
reg txd, bit_out;
reg [7:0] data_out;
 
reg tr_start, trans, trans_buf, t1_ow_buf;
reg [5:0] smod_cnt_r, smod_cnt_t;
reg receive, receive_buf, rxd_buf, r_int;
//
reg [7:0] sbuf_rxd, sbuf_txd, scon, pcon;
reg [10:0] sbuf_rxd_tmp;
//
//tr_count trancive counter
//re_count receive counter
reg [3:0] tr_count, re_count, re_count_buff;
 
 
assign intr = scon[1] | scon [0];
 
//
//serial port control register
//
always @(posedge clk or posedge rst)
begin
if (rst)
scon <= #1 `OC8051_RST_SCON;
else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
scon <= #1 data_in;
else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
scon[wr_addr[2:0]] <= #1 bit_in;
else if ((trans_buf) & !(trans))
scon[1] <= #1 1'b1;
else if ((receive_buf) & !(receive) & !(sbuf_rxd_tmp[0])) begin
case (scon[7:6])
2'b00: scon[0] <= #1 1'b1;
default: begin
if ((sbuf_rxd_tmp[9]) | !(scon[5])) scon[0] <= #1 1'b1;
scon[2] <= #1 sbuf_rxd_tmp[9];
end
endcase
end
 
end
 
//
//serial port buffer (transmit)
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
sbuf_txd <= #1 `OC8051_RST_SBUF;
tr_start <= #1 1'b0;
end else if ((wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit)) begin
sbuf_txd <= #1 data_in;
tr_start <= #1 1'b1;
end else tr_start <= #1 1'b0;
end
 
//
// transmit
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
txd <= #1 1'b1;
tr_count <= #1 4'd0;
trans <= #1 1'b0;
smod_cnt_t <= #1 6'h0;
//
// start transmiting
//
end else if (tr_start) begin
case (scon[7:6])
2'b00: begin // mode 0
txd <= #1 sbuf_txd[0];
tr_count <= #1 4'd1;
end
2'b10: begin
txd <= #1 1'b0;
tr_count <= #1 4'd0;
end
default: begin // mode 1 and mode 3
tr_count <= #1 4'b1111;
end
endcase
trans <= #1 1'b1;
smod_cnt_t <= #1 6'h0;
//
// transmiting/
//
end else if (trans)
begin
case (scon[7:6])
2'b00: begin //mode 0
if (smod_cnt_t == 6'd12) begin
if (tr_count==4'd8)
begin
trans <= #1 1'b0;
txd <= #1 1'b1;
end else begin
txd <= #1 sbuf_txd[tr_count];
tr_count <= #1 tr_count + 4'b1;
end
smod_cnt_t <= #1 6'h0;
end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;
end
2'b01: begin // mode 1
if ((t1_ow) & !(t1_ow_buf))
begin
if (((pcon[7]) & (smod_cnt_t == 6'd15))| (!(pcon[7]) & (smod_cnt_t==6'd31)))
begin
case (tr_count)
4'd8: txd <= #1 1'b1; // stop bit
4'd9: trans <= #1 1'b0;
4'b1111: txd <= #1 1'b0; //start bit
default: txd <= #1 sbuf_txd[tr_count];
endcase
tr_count <= #1 tr_count + 4'b1;
smod_cnt_t <= #1 6'h0;
end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;
end
end
2'b10: begin // mode 2
//
// if smod (pcon[7]) is 1 count to 4 else count to 6
//
if (((pcon[7]) & (smod_cnt_t==6'd31)) | (!(pcon[7]) & (smod_cnt_t==6'd63))) begin
case (tr_count)
4'd8: begin
txd <= #1 scon[3];
end
4'd9: begin
txd <= #1 1'b1; //stop bit
end
4'd10: begin
trans <= #1 1'b0;
end
default: begin
txd <= #1 sbuf_txd[tr_count];
end
endcase
tr_count <= #1 tr_count+1'b1;
smod_cnt_t <= #1 6'h00;
end else begin
smod_cnt_t <= #1 smod_cnt_t + 6'h01;
end
end
default: begin // mode 3
if ((t1_ow) & !(t1_ow_buf))
begin
if (((pcon[7]) & (smod_cnt_t == 6'd15))| (!(pcon[7]) & (smod_cnt_t==6'd31)))
begin
case (tr_count)
4'd8: begin
txd <= #1 scon[3];
end
4'd9: begin
txd <= #1 1'b1; //stop bit
end
4'd10: begin
trans <= #1 1'b0;
end
4'b1111: txd <= #1 1'b0; //start bit
default: begin
txd <= #1 sbuf_txd[tr_count];
end
endcase
tr_count <= #1 tr_count+1'b1;
smod_cnt_t <= #1 6'h00;
end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;
end
end
endcase
end else
txd <= #1 1'b1;
end
 
//
//power control register
//
always @(posedge clk or posedge rst)
begin
if (rst)
begin
pcon <= #1 `OC8051_RST_PCON;
end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
pcon <= #1 data_in;
end
 
//
//serial port buffer (receive)
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
re_count <= #1 4'd0;
receive <= #1 1'b0;
sbuf_rxd <= #1 8'h00;
sbuf_rxd_tmp <= #1 11'd0;
smod_cnt_r <= #1 6'h00;
r_int <= #1 1'b0;
end else if (receive) begin
case (scon[7:6])
2'b00: begin // mode 0
if (smod_cnt_r==6'd12) begin
if (re_count==4'd8) begin
receive <= #1 1'b0;
r_int <= #1 1'b1;
sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
end else begin
sbuf_rxd_tmp[re_count + 4'd1] <= #1 rxd;
r_int <= #1 1'b0;
end
re_count <= #1 re_count + 4'd1;
smod_cnt_r <= #1 6'h00;
end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;
end
2'b01: begin // mode 1
if ((t1_ow) & !(t1_ow_buf))
begin
if (((pcon[7]) & (smod_cnt_r == 6'd15))| (!(pcon[7]) & (smod_cnt_r==6'd31)))
begin
r_int <= #1 1'b0;
re_count <= #1 re_count + 4'd1;
smod_cnt_r <= #1 6'h00;
sbuf_rxd_tmp[re_count_buff] <= #1 rxd;
if ((re_count==4'd0) && (rxd))
receive <= #1 1'b0;
 
end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;
end else begin
r_int <= #1 1'b1;
if (re_count == 4'd10)
begin
sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
receive <= #1 1'b0;
r_int <= #1 1'b1;
end else r_int <= #1 1'b0;
end
end
2'b10: begin // mode 2
if (((pcon[7]) & (smod_cnt_r==6'd31)) | (!(pcon[7]) & (smod_cnt_r==6'd63))) begin
r_int <= #1 1'b0;
re_count <= #1 re_count + 4'd1;
smod_cnt_r <= #1 6'h00;
sbuf_rxd_tmp[re_count_buff] <= #1 rxd;
re_count <= #1 re_count + 4'd1;
end else begin
smod_cnt_r <= #1 smod_cnt_r + 6'h1;
if (re_count==4'd11) begin
sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
receive <= #1 1'b0;
end else
r_int <= #1 1'b0;
end
end
default: begin // mode 3
if ((t1_ow) & !(t1_ow_buf))
begin
if (((pcon[7]) & (smod_cnt_r == 6'd15))| (!(pcon[7]) & (smod_cnt_r==6'd31)))
begin
sbuf_rxd_tmp[re_count] <= #1 rxd;
r_int <= #1 1'b0;
re_count <= #1 re_count + 4'd1;
smod_cnt_r <= #1 6'h00;
end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;
end else begin
if (re_count==4'd11) begin
sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
receive <= #1 1'b0;
r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
end else begin
r_int <= #1 1'b0;
end
end
end
endcase
end else begin
case (scon[7:6])
2'b00: begin
if ((scon[4]) && !(scon[0]) && !(r_int)) begin
receive <= #1 1'b1;
smod_cnt_r <= #1 6'h6;
end
end
2'b10: begin
if ((scon[4]) && !(rxd)) begin
receive <= #1 1'b1;
if (pcon[7])
smod_cnt_r <= #1 6'd15;
else smod_cnt_r <= #1 6'd31;
end
end
default: begin
if ((scon[4]) && (!rxd)) begin
if (pcon[7])
smod_cnt_r <= #1 6'd7;
else smod_cnt_r <= #1 6'd15;
receive <= #1 1'b1;
end
end
endcase
 
sbuf_rxd_tmp <= #1 11'd0;
re_count <= #1 4'd0;
r_int <= #1 1'b0;
end
end
 
//
//
//
always @(posedge clk or posedge rst)
begin
if (rst) data_out <= #1 8'h0;
else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_PCON) |
(wr_addr==`OC8051_SFR_SCON))) begin
data_out <= #1 data_in;
end else begin
case (rd_addr)
`OC8051_SFR_SBUF: data_out <= #1 sbuf_rxd;
`OC8051_SFR_PCON: data_out <= #1 pcon;
default: data_out <= #1 scon;
endcase
end
end
 
 
always @(posedge clk or posedge rst)
begin
if (rst) begin
trans_buf <= #1 1'b0;
receive_buf <= #1 1'b0;
t1_ow_buf <= #1 1'b0;
rxd_buf <= #1 1'b0;
end else begin
trans_buf <= #1 trans;
receive_buf <= #1 receive;
t1_ow_buf <= #1 t1_ow;
rxd_buf <= #1 rxd;
end
end
 
always @(posedge clk or posedge rst)
begin
if (rst) bit_out <= #1 1'b0;
else if (wr & wr_bit & (rd_addr==wr_addr) & (wr_addr[7:3]==`OC8051_SFR_B_SCON)) begin
bit_out <= #1 bit_in;
end else
bit_out <= #1 scon[rd_addr[2:0]];
end
 
always @(posedge clk or posedge rst)
if (rst)
re_count_buff <= #1 4'h4;
else re_count_buff <= #1 re_count;
 
endmodule
 
/trunk/sim/rtl_sim/run/oc8051_defines.v
45,6 → 45,10
// ver: 1
//
 
//
// oc8051 cache
//
`define OC8051_CACHE
 
//
// operation codes for alu
81,8 → 85,8
`define OC8051_SFR_P3 8'hb0 //port 3
`define OC8051_SFR_DPTR_LO 8'h82 // data pointer high bits
`define OC8051_SFR_DPTR_HI 8'h83 // data pointer low bits
`define OC8051_SFR_IP 8'hb8 // interrupt priority control
`define OC8051_SFR_IE 8'ha8 // interrupt enable control
`define OC8051_SFR_IP0 8'hb8 // interrupt priority
`define OC8051_SFR_IEN0 8'ha8 // interrupt enable 0
`define OC8051_SFR_TMOD 8'h89 // timer/counter mode
`define OC8051_SFR_TCON 8'h88 // timer/counter control
`define OC8051_SFR_TH0 8'h8c // timer/counter 0 high bits
89,11 → 93,30
`define OC8051_SFR_TL0 8'h8a // timer/counter 0 low bits
`define OC8051_SFR_TH1 8'h8d // timer/counter 1 high bits
`define OC8051_SFR_TL1 8'h8b // timer/counter 1 low bits
`define OC8051_SFR_SCON 8'h98 // serial control
`define OC8051_SFR_SBUF 8'h99 // serial data buffer
 
`define OC8051_SFR_SCON 8'h98 // serial control 0
`define OC8051_SFR_SBUF 8'h99 // serial data buffer 0
`define OC8051_SFR_SADDR 8'ha9 // serila address register 0
`define OC8051_SFR_SADEN 8'hb9 // serila address enable 0
 
`define OC8051_SFR_PCON 8'h87 // power control
`define OC8051_SFR_SP 8'h81 // stack pointer
 
 
 
`define OC8051_SFR_IE 8'ha8 // interrupt enable
`define OC8051_SFR_IP 8'hb7 // interrupt priority
 
`define OC8051_SFR_RCAP2H 8'hcb // timer 2 capture high
`define OC8051_SFR_RCAP2L 8'hca // timer 2 capture low
 
`define OC8051_SFR_T2CON 8'hc8 // timer 2 control register
`define OC8051_SFR_T2MOD 8'hc9 // timer 2 mode control
`define OC8051_SFR_TH2 8'hcd // timer 2 high
`define OC8051_SFR_TL2 8'hcc // timer 2 low
 
 
 
//
// sfr bit addresses
//
104,29 → 127,14
`define OC8051_SFR_B_P2 5'b10100 //port 2
`define OC8051_SFR_B_P3 5'b10110 //port 3
`define OC8051_SFR_B_B 5'b11110 // b register
`define OC8051_SFR_B_IP 5'b10111 // interrupt priority control
`define OC8051_SFR_B_IE 5'b10101 // interrupt enable control
`define OC8051_SFR_B_IP 5'b10111 // interrupt priority control 0
`define OC8051_SFR_B_IE 5'b10101 // interrupt enable control 0
`define OC8051_SFR_B_SCON 5'b10011 // serial control
`define OC8051_SFR_B_TCON 5'b10001 // timer/counter control
`define OC8051_SFR_B_TCON 5'b10001 // timer/counter control
`define OC8051_SFR_B_T2CON 5'b11001 // timer/counter2 control
 
//
// alu source select
//
`define OC8051_ASS_RAM 2'b00 // RAM
`define OC8051_ASS_ACC 2'b01 // accumulator
`define OC8051_ASS_XRAM 2'b10 // external RAM -- source1
`define OC8051_ASS_ZERO 2'b10 // 8'h00 -- source2
`define OC8051_ASS_IMM 2'b11 // immediate data -- source1
`define OC8051_ASS_DC 2'b00 //
 
//
// alu source 3 select
//
`define OC8051_AS3_PC 1'b1 // program clunter
`define OC8051_AS3_DP 1'b0 // data pointer
`define OC8051_AS3_DC 1'b0 //
 
//
//carry input in alu
//
`define OC8051_CY_0 2'b00 // 1'b0;
211,7 → 219,7
`define OC8051_JB 8'b0010_0000 // jump if bit set
`define OC8051_JBC 8'b0001_0000 // jump if bit set and clear bit
`define OC8051_JC 8'b0100_0000 // jump if carry is set
`define OC8051_JMP 8'b0111_0011 // jump indirect
`define OC8051_JMP_D 8'b0111_0011 // jump indirect
`define OC8051_JNB 8'b0011_0000 // jump if bit not set
`define OC8051_JNC 8'b0101_0000 // jump if carry not set
`define OC8051_JNZ 8'b0111_0000 // jump if accumulator not zero
262,7 → 270,7
//
// default values (used after reset)
//
`define OC8051_RST_PC 16'h0000 // program counter
`define OC8051_RST_PC 23'h0 // program counter
`define OC8051_RST_ACC 8'h00 // accumulator
`define OC8051_RST_B 8'h00 // b register
`define OC8051_RST_PSW 8'h00 // program status word
285,62 → 293,103
`define OC8051_RST_SBUF 8'b0000_0000 // serial data buffer
`define OC8051_RST_PCON 8'b0000_0000 // power control register
 
 
 
`define OC8051_RST_RCAP2H 8'h00 // timer 2 capture high
`define OC8051_RST_RCAP2L 8'h00 // timer 2 capture low
 
`define OC8051_RST_T2CON 8'h00 // timer 2 control register
`define OC8051_RST_T2MOD 8'h00 // timer 2 mode control
`define OC8051_RST_TH2 8'h00 // timer 2 high
`define OC8051_RST_TL2 8'h00 // timer 2 low
 
 
//
// alu source 1 select
//
`define OC8051_AS1_RAM 3'b000 // RAM
`define OC8051_AS1_OP1 3'b111 //
`define OC8051_AS1_OP2 3'b001 //
`define OC8051_AS1_OP3 3'b010 //
`define OC8051_AS1_ACC 3'b011 // accumulator
`define OC8051_AS1_PCH 3'b100 //
`define OC8051_AS1_PCL 3'b101 //
`define OC8051_AS1_DC 3'b000 //
 
//
// alu source 2 select
//
`define OC8051_AS2_RAM 3'b000 // RAM
`define OC8051_AS2_ACC 3'b001 // accumulator
`define OC8051_AS2_ZERO 3'b010 // 8'h00
`define OC8051_AS2_OP2 3'b011 //
`define OC8051_AS2_PCL 3'b100 //
 
`define OC8051_AS2_DC 3'b000 //
 
//
// alu source 3 select
//
`define OC8051_AS3_DP 1'b0 // data pointer
`define OC8051_AS3_PC 1'b1 // program clunter
//`define OC8051_AS3_PCU 3'b101 // program clunter not registered
`define OC8051_AS3_DC 1'b0 //
 
 
//
//write sfr
//
`define OC8051_WRS_N 3'b000 //no
`define OC8051_WRS_ACC1 3'b001 // acc destination 1
`define OC8051_WRS_ACC2 3'b010 // acc destination 2
`define OC8051_WRS_DPTR 3'b011 // data pointer
`define OC8051_WRS_BA 3'b100 // a, b register
 
 
//
// ram read select
//
 
`define OC8051_RRS_RN 2'b00 // registers
`define OC8051_RRS_I 2'b01 // indirect addressing
`define OC8051_RRS_D 2'b10 // direct addressing
`define OC8051_RRS_SP 2'b11 // stack pointer
`define OC8051_RRS_DC 2'b00 // don't c
`define OC8051_RRS_RN 3'b000 // registers
`define OC8051_RRS_I 3'b001 // indirect addressing (op2)
`define OC8051_RRS_D 3'b010 // direct addressing
`define OC8051_RRS_SP 3'b011 // stack pointer
 
`define OC8051_RRS_B 3'b100 // b register
`define OC8051_RRS_DPTR 3'b101 // data pointer
 
`define OC8051_RRS_DC 3'b000 // don't c
 
//
// ram write select
//
 
`define OC8051_RWS_RN 3'b000 // registers
`define OC8051_RWS_D 3'b001 // direct addressing
`define OC8051_RWS_I 3'b010 // indirect addressing
`define OC8051_RWS_D 3'b001 // direct addressing
`define OC8051_RWS_I 3'b010 // indirect addressing
`define OC8051_RWS_SP 3'b011 // stack pointer
`define OC8051_RWS_ACC 3'b100 // accumulator
`define OC8051_RWS_D3 3'b101 // direct address (op3)
`define OC8051_RWS_DPTR 3'b110 // data pointer (high + low)
`define OC8051_RWS_B 3'b111 // b register
`define OC8051_RWS_D1 3'b110 // direct address (op1)
`define OC8051_RWS_DC 3'b000 //
 
//
// immediate data select
//
 
`define OC8051_IDS_OP2 3'b000 // operand 2
`define OC8051_IDS_OP3 3'b001 // operand 3
`define OC8051_IDS_PCH 3'b010 // pc high
`define OC8051_IDS_PCL 3'b011 // pc low
`define OC8051_IDS_OP3_PCL 3'b100 // op3 and pc low
`define OC8051_IDS_OP3_OP2 3'b101 // op3 and op2
`define OC8051_IDS_OP2_PCL 3'b110 // op2 and PC LOW
`define OC8051_IDS_OP1 3'b111 // operand 1
`define OC8051_IDS_DC 3'b000 //
 
 
//
// pc in select
//
`define OC8051_PIS_DC 2'b00 // dont c
`define OC8051_PIS_SP 2'b00 // stack ( des1 -- serial)
`define OC8051_PIS_ALU 2'b01 // alu {des1, des2}
`define OC8051_PIS_I11 2'b10 // 11 bit immediate
`define OC8051_PIS_I16 2'b11 // 16 bit immediate
`define OC8051_PIS_DC 3'b000 // dont c
`define OC8051_PIS_AL 3'b000 // alu low
`define OC8051_PIS_AH 3'b001 // alu high
`define OC8051_PIS_ALU 3'b010 // alu {des1, des2}
`define OC8051_PIS_I11 3'b011 // 11 bit immediate
`define OC8051_PIS_I16 3'b100 // 16 bit immediate
 
//
// compare source select
//
`define OC8051_CSS_AZ 2'b00 // eq = accumulator == zero
`define OC8051_CSS_AZ 2'b00 // eq = accumulator == zero
`define OC8051_CSS_DES 2'b01 // eq = destination == zero
`define OC8051_CSS_CY 2'b10 // eq = cy
`define OC8051_CSS_CY 2'b10 // eq = cy
`define OC8051_CSS_BIT 2'b11 // eq = b_in
`define OC8051_CSS_DC 2'b00 // don't care
`define OC8051_CSS_DC 2'b00 // don't care
 
 
//
363,28 → 412,24
`define OC8051_RAS_PC 1'b0 // program counter
`define OC8051_RAS_DES 1'b1 // alu destination
 
//
// write accumulator
//
`define OC8051_WA_N 1'b0 // not
`define OC8051_WA_Y 1'b1 // yes
////
//// write accumulator
////
//`define OC8051_WA_N 1'b0 // not
//`define OC8051_WA_Y 1'b1 // yes
 
 
//
//external ram address select
//memory action select
//
`define OC8051_EAS_DPTR 1'b0 // data pointer
`define OC8051_EAS_RI 1'b1 // register R0 or R1
`define OC8051_EAS_DC 1'b0
`define OC8051_MAS_DPTR_R 3'b000 // read from external rom: acc=(dptr)
`define OC8051_MAS_DPTR_W 3'b001 // write to external rom: (dptr)=acc
`define OC8051_MAS_RI_R 3'b010 // read from external rom: acc=(Ri)
`define OC8051_MAS_RI_W 3'b011 // write to external rom: (Ri)=acc
`define OC8051_MAS_CODE 3'b100 // read from program memory
`define OC8051_MAS_NO 3'b111 // no action
 
//
//write ac from des2
//
`define OC8051_WAD_N 1'b0 //
`define OC8051_WAD_Y 1'b1 //
 
 
 
////////////////////////////////////////////////////
 
//
401,19 → 446,20
// Interrupt numbers (vectors)
//
 
`define OC8051_INT_X0 8'h03 // external interrupt 0
`define OC8051_INT_T0 8'h0b // T/C 0 owerflow interrupt
`define OC8051_INT_X1 8'h13 // external interrupt 1
`define OC8051_INT_T1 8'h1b // T/C 1 owerflow interrupt
`define OC8051_INT_X0 8'h03 // external interrupt 0
`define OC8051_INT_X1 8'h13 // external interrupt 1
`define OC8051_INT_UART 8'h23 // interrupt from uart
`define OC8051_INT_UART 8'h23 // uart interrupt
`define OC8051_INT_T2 8'h2b // T/C 2 owerflow interrupt
 
 
//
// interrupt levels
//
 
`define OC8051_ILEV_NO 2'b00 // no interrupts
`define OC8051_ILEV_L0 2'b01 // interrupt on level 0
`define OC8051_ILEV_L1 2'b10 // interrupt on level 1
`define OC8051_ILEV_L0 1'b0 // interrupt on level 0
`define OC8051_ILEV_L1 1'b1 // interrupt on level 1
 
//
// interrupt sources
423,7 → 469,8
`define OC8051_ISRC_TF0 3'b010 // t/c owerflov 0
`define OC8051_ISRC_IE1 3'b011 // EXTERNAL INTERRUPT 1
`define OC8051_ISRC_TF1 3'b100 // t/c owerflov 1
`define OC8051_ISRC_UART 3'b101 // UART Interrupt
`define OC8051_ISRC_UART 3'b101 // UART Interrupt
`define OC8051_ISRC_T2 3'b110 // t/c owerflov 2
 
 
 
441,3 → 488,4
 
`define OC8051_RMW_Y 1'b1 // yes
`define OC8051_RMW_N 1'b0 // no
 
/trunk/sim/rtl_sim/run/make_verilog
1,3 → 488,4
verilog ../../../bench/verilog/oc8051_tb.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/verilog/oc8051_alu_src1_sel.v ../../../rtl/verilog/oc8051_alu_src2_sel.v ../../../rtl/verilog/oc8051_alu_src3_sel.v ../../../rtl/verilog/oc8051_alu.v ../../../rtl/verilog/oc8051_decoder.v ../../../rtl/verilog/oc8051_divide.v ../../../rtl/verilog/oc8051_immediate_sel.v ../../../rtl/verilog/oc8051_multiply.v ../../../rtl/verilog/oc8051_op_select.v ../../../rtl/verilog/oc8051_pc.v ../../../rtl/verilog/oc8051_reg8.v ../../../rtl/verilog/oc8051_reg2.v ../../../rtl/verilog/oc8051_reg1.v ../../../rtl/verilog/oc8051_reg4.v ../../../rtl/verilog/oc8051_ram_wr_sel.v ../../../rtl/verilog/oc8051_ram_rd_sel.v ../../../rtl/verilog/oc8051_ram_top.v ../../../sim/rtl_sim/src/verilog/oc8051_ram.v ../../../sim/rtl_sim/src/verilog/oc8051_xram.v ../../../rtl/verilog/oc8051_acc.v ../../../rtl/verilog/oc8051_comp.v ../../../rtl/verilog/oc8051_sp.v ../../../sim/rtl_sim/src/verilog/oc8051_uart_test.v ../../../sim/rtl_sim/src/verilog/oc8051_rom.v ../../../sim/rtl_sim/src/verilog/oc8051_xrom.v ../../../rtl/verilog/oc8051_dptr.v ../../../rtl/verilog/oc8051_cy_select.v ../../../rtl/verilog/oc8051_psw.v ../../../rtl/verilog/oc8051_indi_addr.v ../../../rtl/verilog/oc8051_rom_addr_sel.v ../../../rtl/verilog/oc8051_ext_addr_sel.v ../../../rtl/verilog/oc8051_reg3.v ../../../rtl/verilog/oc8051_ram_sel.v ../../../rtl/verilog/oc8051_ports.v ../../../rtl/verilog/oc8051_b_register.v ../../../rtl/verilog/oc8051_uart.v ../../../rtl/verilog/oc8051_int.v ../../../rtl/verilog/oc8051_tc.v ../../../rtl/verilog/oc8051_icache.v ../../../sim/rtl_sim/src/verilog/oc8051_cache_ram.v
verilog ../../../bench/verilog/oc8051_tb.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/verilog/oc8051_alu_src_sel.v ../../../rtl/verilog/oc8051_alu.v ../../../rtl/verilog/oc8051_decoder.v ../../../rtl/verilog/oc8051_divide.v ../../../rtl/verilog/oc8051_multiply.v ../../../rtl/verilog/oc8051_memory_interface.v ../../../rtl/verilog/oc8051_ram_top.v ../../../sim/rtl_sim/src/verilog/oc8051_ram.v ../../../sim/rtl_sim/src/verilog/oc8051_xram.v ../../../rtl/verilog/oc8051_acc.v ../../../rtl/verilog/oc8051_comp.v ../../../rtl/verilog/oc8051_sp.v ../../../sim/rtl_sim/src/verilog/oc8051_uart_test.v ../../../sim/rtl_sim/src/verilog/oc8051_rom.v ../../../sim/rtl_sim/src/verilog/oc8051_xrom.v ../../../rtl/verilog/oc8051_dptr.v ../../../rtl/verilog/oc8051_cy_select.v ../../../rtl/verilog/oc8051_psw.v ../../../rtl/verilog/oc8051_indi_addr.v ../../../rtl/verilog/oc8051_ports.v ../../../rtl/verilog/oc8051_b_register.v ../../../rtl/verilog/oc8051_uart.v ../../../rtl/verilog/oc8051_int.v ../../../rtl/verilog/oc8051_tc.v ../../../rtl/verilog/oc8051_tc2.v ../../../rtl/verilog/oc8051_icache.v ../../../sim/rtl_sim/src/verilog/oc8051_cache_ram.v ../../../rtl/verilog/oc8051_wb_iinterface.v ../../../rtl/verilog/oc8051_sfr.v ../../../../../../pci/bench/verilog/wb_bus_mon.v
/trunk/sim/rtl_sim/run/run
6,8 → 6,7
set all_testsx = 0;
 
 
set internal_tests=(testall lcall negcnt gcd int2bin cast divmul fib sort sqroot div16u test_xram xram_m timer_test counter_test interrupt_test serial_test r_bank)
 
set internal_tests=(testall lcall negcnt gcd int2bin cast divmul fib sort sqroot div16u test_xram xram_m timer_test counter_test timer2_test interrupt_test serial_test r_bank)
set external_tests=(testall lcall negcnt gcd int2bin cast divmul fib sort sqroot div16u test_xram xram_m interrupt_test r_bank xrom_test)
 
# Prepare all .args files
88,6 → 87,7
endif
mv ../out/ncsim.out ../out/${internal_test}.out
mv verilog.dump ../out/wave/${internal_test}.dump
mv log_file ../out/wb/${internal_test}
end
 
echo ""
120,6 → 120,7
@ all_testsx += 1;
endif
mv ../out/ncsim.out ../out/x_${external_test}.out
mv log_file ../out/wb/x_${external_test}
end
 
echo ""
/trunk/sim/rtl_sim/run/make
1,6 → 120,7
../../../bench/verilog/oc8051_tb.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/verilog/oc8051_alu_src1_sel.v ../../../rtl/verilog/oc8051_alu_src2_sel.v ../../../rtl/verilog/oc8051_alu_src3_sel.v ../../../rtl/verilog/oc8051_alu.v ../../../rtl/verilog/oc8051_decoder.v ../../../rtl/verilog/oc8051_divide.v ../../../rtl/verilog/oc8051_immediate_sel.v ../../../rtl/verilog/oc8051_multiply.v ../../../rtl/verilog/oc8051_op_select.v ../../../rtl/verilog/oc8051_pc.v ../../../rtl/verilog/oc8051_reg8.v ../../../rtl/verilog/oc8051_reg2.v ../../../rtl/verilog/oc8051_reg1.v ../../../rtl/verilog/oc8051_reg4.v ../../../rtl/verilog/oc8051_ram_wr_sel.v ../../../rtl/verilog/oc8051_ram_rd_sel.v ../../../rtl/verilog/oc8051_ram_top.v ../../../sim/rtl_sim/src/verilog/oc8051_xram.v ../../../sim/rtl_sim/src/verilog/oc8051_ram.v ../../../rtl/verilog/oc8051_acc.v ../../../rtl/verilog/oc8051_comp.v ../../../rtl/verilog/oc8051_sp.v ../../../sim/rtl_sim/src/verilog/oc8051_uart_test.v ../../../sim/rtl_sim/src/verilog/oc8051_rom.v ../../../sim/rtl_sim/src/verilog/oc8051_xrom.v ../../../rtl/verilog/oc8051_dptr.v ../../../rtl/verilog/oc8051_cy_select.v ../../../rtl/verilog/oc8051_psw.v ../../../rtl/verilog/oc8051_indi_addr.v ../../../rtl/verilog/oc8051_rom_addr_sel.v ../../../rtl/verilog/oc8051_ext_addr_sel.v ../../../rtl/verilog/oc8051_reg3.v ../../../rtl/verilog/oc8051_ram_sel.v ../../../rtl/verilog/oc8051_ports.v ../../../rtl/verilog/oc8051_b_register.v ../../../rtl/verilog/oc8051_uart.v ../../../rtl/verilog/oc8051_int.v ../../../rtl/verilog/oc8051_tc.v ../../../rtl/verilog/oc8051_icache.v ../src/verilog/oc8051_cache_ram.v
../../../bench/verilog/oc8051_tb.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/verilog/oc8051_alu_src_sel.v ../../../rtl/verilog/oc8051_alu.v ../../../rtl/verilog/oc8051_decoder.v ../../../rtl/verilog/oc8051_divide.v ../../../rtl/verilog/oc8051_multiply.v ../../../rtl/verilog/oc8051_memory_interface.v ../../../rtl/verilog/oc8051_ram_top.v ../../../sim/rtl_sim/src/verilog/oc8051_xram.v ../../../sim/rtl_sim/src/verilog/oc8051_ram.v ../../../rtl/verilog/oc8051_acc.v ../../../rtl/verilog/oc8051_comp.v ../../../rtl/verilog/oc8051_sp.v ../../../sim/rtl_sim/src/verilog/oc8051_uart_test.v ../../../sim/rtl_sim/src/verilog/oc8051_rom.v ../../../sim/rtl_sim/src/verilog/oc8051_xrom.v ../../../rtl/verilog/oc8051_dptr.v ../../../rtl/verilog/oc8051_cy_select.v ../../../rtl/verilog/oc8051_psw.v ../../../rtl/verilog/oc8051_indi_addr.v ../../../rtl/verilog/oc8051_ports.v ../../../rtl/verilog/oc8051_b_register.v ../../../rtl/verilog/oc8051_uart.v ../../../rtl/verilog/oc8051_int.v ../../../rtl/verilog/oc8051_tc.v ../../../rtl/verilog/oc8051_tc2.v ../../../rtl/verilog/oc8051_icache.v ../src/verilog/oc8051_cache_ram.v ../../../rtl/verilog/oc8051_wb_iinterface.v ../../../rtl/verilog/oc8051_sfr.v ../../../../../../pci/bench/verilog/wb_bus_mon.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.