URL
https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk
Subversion Repositories versatile_mem_ctrl
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- from Rev 81 to Rev 82
- ↔ Reverse comparison
Rev 81 → Rev 82
/versatile_mem_ctrl/trunk/bench/tb.v
321,8 → 321,8
begin |
#0 sdram_clk = 1'b0; |
forever |
//#4 sdram_clk = !sdram_clk; // 125 MHz |
#5 sdram_clk = !sdram_clk; // 100 MHz |
#4 sdram_clk = !sdram_clk; // 125 MHz |
//#5 sdram_clk = !sdram_clk; // 100 MHz |
end |
|
endmodule // versatile_mem_ctrl_tb |
/versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_ip.v
171,7 → 171,7
|
|
// Write-domain to read-domain synchronizer |
always @ (posedge wclk or posedge rst) |
always @ (posedge rclk or posedge rst) |
if (rst) |
{wptr2,wptr1} <= {4'b0000,4'b0000}; |
else |
2729,17 → 2729,17
.clk1_divide_by(1), |
.clk1_duty_cycle(50), |
.clk1_multiply_by(1), |
.clk1_phase_shift("1250"), |
.clk1_phase_shift("2000"), |
.clk2_divide_by(1), |
.clk2_duty_cycle(50), |
.clk2_multiply_by(1), |
.clk2_phase_shift("2500"), |
.clk2_phase_shift("4000"), |
.clk3_divide_by(1), |
.clk3_duty_cycle(50), |
.clk3_multiply_by(1), |
.clk3_phase_shift("3750"), |
.clk3_phase_shift("6000"), |
.compensate_clock("CLK0"), |
.inclk0_input_frequency(5000), |
.inclk0_input_frequency(8000), |
.intended_device_family("Stratix III"), |
.lpm_hint("UNUSED"), |
.lpm_type("altpll"), |
3147,7 → 3147,7
`endif // INT_CLOCKED_DATA_CAPTURE |
|
|
`ifdef DEL_DQS_DATA_CAPTURE_1 |
`ifdef DQS_DATA_CAPTURE |
|
wire [1:0] dqs_iodelay, dqs_n_iodelay; |
|
3185,120 → 3185,8
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assign rx_dat_o = dq_rx_reg; |
|
`endif // DEL_DQS_DATA_CAPTURE_1 |
`endif // DQS_DATA_CAPTURE |
|
|
`ifdef DEL_DQS_DATA_CAPTURE_2 |
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wire [15:0] dq_iodelay; |
wire [1:0] dqs_iodelay, dqs_n_iodelay; |
wire [15:0] dq_iddr_fall, dq_iddr_rise; |
reg [15:0] dq_fall_1, dq_rise_1; |
reg [15:0] dq_fall_2, dq_rise_2; |
reg [15:0] dq_fall_3, dq_rise_3; |
|
|
// Delay data |
// IODELAY is available in the Xilinx Virtex FPGAs |
/*IODELAY # ( |
.DELAY_SRC(), |
.IDELAY_TYPE(), |
.HIGH_PERFORMANCE_MODE(), |
.IDELAY_VALUE(), |
.ODELAY_VALUE()) |
u_idelay_dq ( |
.DATAOUT(), |
.C(), |
.CE(), |
.DATAIN(), |
.IDATAIN(), |
.INC(), |
.ODATAIN(), |
.RST(), |
.T());*/ |
// IODELAY is NOT available in the Xilinx Spartan FPGAs, |
// equivalent delay can be implemented using a chain of LUT |
/*lut_delay lut_delay_dq ( |
.clk_i(), |
.d_i(dq_iobuf), |
.d_o(dq_iodelay));*/ |
|
// IDDR FF |
generate |
for (i=0; i<16; i=i+1) begin:iddr_dq |
ddr_ff_in ddr_ff_in_inst_0 ( |
.Q0(dq_iddr_fall[i]), |
.Q1(dq_iddr_rise[i]), |
.C0(dqs_iodelay[0]), |
.C1(dqs_n_iodelay[0]), |
.CE(1'b1), |
.D(dq_iobuf[i]), |
.R(rst), |
.S(1'b0)); |
end |
endgenerate |
|
// Rise & fall clocked FF |
always @ (posedge clk_0 or posedge rst) |
if (rst) begin |
dq_fall_1 <= 16'h0; |
dq_rise_1 <= 16'h0; |
end else begin |
dq_fall_1 <= dq_iddr_fall; |
dq_rise_1 <= dq_iddr_rise; |
end |
|
always @ (posedge clk_180 or posedge rst) |
if (rst) begin |
dq_fall_2 <= 16'h0; |
dq_rise_2 <= 16'h0; |
end else begin |
dq_fall_2 <= dq_iddr_fall; |
dq_rise_2 <= dq_iddr_rise; |
end |
|
// Fall sync FF |
always @ (posedge clk_0 or posedge rst) |
if (rst) begin |
dq_fall_3 <= 16'h0; |
dq_rise_3 <= 16'h0; |
end else begin |
dq_fall_3 <= dq_fall_2; |
dq_rise_3 <= dq_rise_2; |
end |
|
// Mux |
assign rx_dat_o[31:16] = dq_fall_1; |
assign rx_dat_o[15:0] = dq_rise_1; |
|
// DDR DQS to IODUFDS |
// Delay DQS |
// IODELAY is NOT available in the Xilinx Spartan FPGAs, |
// equivalent delay can be implemented using a chain of LUTs |
/* |
generate |
for (i=0; i<2; i=i+1) begin:lut_delay_dqs |
lut_delay lut_delay_dqs ( |
.d_i(dqs_iobuf[i]), |
.d_o(dqs_iodelay[i])); |
end |
endgenerate |
generate |
for (i=0; i<2; i=i+1) begin:lut_delay_dqs_n |
lut_delay lut_delay_dqs_n ( |
.d_i(dqs_n_iobuf[i]), |
.d_o(dqs_n_iodelay[i])); |
end |
endgenerate |
*/ |
|
assign # 2 dqs_iodelay = dqs_iobuf; |
assign # 2 dqs_n_iodelay = dqs_n_iobuf; |
|
|
// BUFIO (?) |
`endif // DEL_DQS_DATA_CAPTURE_2 |
|
`endif // XILINX |
|
|
3384,26 → 3272,43
assign rx_dat_o = dq_rx_reg; |
`endif // INT_CLOCKED_DATA_CAPTURE |
|
`ifdef DEL_DQS_DATA_CAPTURE_1 |
// Delay DQS |
// DDR FF |
`endif // DEL_DQS_DATA_CAPTURE_1 |
|
`ifdef DQS_DATA_CAPTURE |
|
`ifdef DEL_DQS_DATA_CAPTURE_2 |
// DDR data to IOBUFFER |
// Delay data (?) |
// DDR FF |
// Rise & fall clocked FF |
// Fall sync FF |
// Mux |
// DDR DQS to IODUFDS |
// Delay DQS |
// BUFIO (?) |
`endif // DEL_DQS_DATA_CAPTURE_2 |
wire [1:0] dqs_iodelay, dqs_n_iodelay; |
|
// Delay DQS |
assign # 2 dqs_iodelay = dqs_io; |
assign # 2 dqs_n_iodelay = dqs_n_io; |
|
// IDDR FF |
generate |
for (i=0; i<16; i=i+1) begin:iddr_dq |
ddr_ff_in ddr_ff_in_inst_0 ( |
.Q0(dq_rx[i]), |
.Q1(dq_rx[i+16]), |
.C0(dqs_n_iodelay[0]), |
.C1(dqs_iodelay[0]), |
.CE(1'b1), |
.D(dq_io[i]), |
.R(rst), |
.S(1'b0)); |
end |
endgenerate |
|
// Data to Rx FIFO |
always @ (posedge clk_180 or posedge rst) |
if (rst) |
dq_rx_reg <= 32'h0; |
else |
dq_rx_reg <= dq_rx; |
|
assign rx_dat_o = dq_rx_reg; |
|
`endif // DQS_DATA_CAPTURE |
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`endif // ALTERA |
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endmodule // versatile_mem_ctrl_ddr |
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/versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_ddr.v
250,7 → 250,7
`endif // INT_CLOCKED_DATA_CAPTURE |
|
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`ifdef DEL_DQS_DATA_CAPTURE_1 |
`ifdef DQS_DATA_CAPTURE |
|
wire [1:0] dqs_iodelay, dqs_n_iodelay; |
|
288,120 → 288,8
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assign rx_dat_o = dq_rx_reg; |
|
`endif // DEL_DQS_DATA_CAPTURE_1 |
`endif // DQS_DATA_CAPTURE |
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`ifdef DEL_DQS_DATA_CAPTURE_2 |
|
wire [15:0] dq_iodelay; |
wire [1:0] dqs_iodelay, dqs_n_iodelay; |
wire [15:0] dq_iddr_fall, dq_iddr_rise; |
reg [15:0] dq_fall_1, dq_rise_1; |
reg [15:0] dq_fall_2, dq_rise_2; |
reg [15:0] dq_fall_3, dq_rise_3; |
|
|
// Delay data |
// IODELAY is available in the Xilinx Virtex FPGAs |
/*IODELAY # ( |
.DELAY_SRC(), |
.IDELAY_TYPE(), |
.HIGH_PERFORMANCE_MODE(), |
.IDELAY_VALUE(), |
.ODELAY_VALUE()) |
u_idelay_dq ( |
.DATAOUT(), |
.C(), |
.CE(), |
.DATAIN(), |
.IDATAIN(), |
.INC(), |
.ODATAIN(), |
.RST(), |
.T());*/ |
// IODELAY is NOT available in the Xilinx Spartan FPGAs, |
// equivalent delay can be implemented using a chain of LUT |
/*lut_delay lut_delay_dq ( |
.clk_i(), |
.d_i(dq_iobuf), |
.d_o(dq_iodelay));*/ |
|
// IDDR FF |
generate |
for (i=0; i<16; i=i+1) begin:iddr_dq |
ddr_ff_in ddr_ff_in_inst_0 ( |
.Q0(dq_iddr_fall[i]), |
.Q1(dq_iddr_rise[i]), |
.C0(dqs_iodelay[0]), |
.C1(dqs_n_iodelay[0]), |
.CE(1'b1), |
.D(dq_iobuf[i]), |
.R(rst), |
.S(1'b0)); |
end |
endgenerate |
|
// Rise & fall clocked FF |
always @ (posedge clk_0 or posedge rst) |
if (rst) begin |
dq_fall_1 <= 16'h0; |
dq_rise_1 <= 16'h0; |
end else begin |
dq_fall_1 <= dq_iddr_fall; |
dq_rise_1 <= dq_iddr_rise; |
end |
|
always @ (posedge clk_180 or posedge rst) |
if (rst) begin |
dq_fall_2 <= 16'h0; |
dq_rise_2 <= 16'h0; |
end else begin |
dq_fall_2 <= dq_iddr_fall; |
dq_rise_2 <= dq_iddr_rise; |
end |
|
// Fall sync FF |
always @ (posedge clk_0 or posedge rst) |
if (rst) begin |
dq_fall_3 <= 16'h0; |
dq_rise_3 <= 16'h0; |
end else begin |
dq_fall_3 <= dq_fall_2; |
dq_rise_3 <= dq_rise_2; |
end |
|
// Mux |
assign rx_dat_o[31:16] = dq_fall_1; |
assign rx_dat_o[15:0] = dq_rise_1; |
|
// DDR DQS to IODUFDS |
// Delay DQS |
// IODELAY is NOT available in the Xilinx Spartan FPGAs, |
// equivalent delay can be implemented using a chain of LUTs |
/* |
generate |
for (i=0; i<2; i=i+1) begin:lut_delay_dqs |
lut_delay lut_delay_dqs ( |
.d_i(dqs_iobuf[i]), |
.d_o(dqs_iodelay[i])); |
end |
endgenerate |
generate |
for (i=0; i<2; i=i+1) begin:lut_delay_dqs_n |
lut_delay lut_delay_dqs_n ( |
.d_i(dqs_n_iobuf[i]), |
.d_o(dqs_n_iodelay[i])); |
end |
endgenerate |
*/ |
|
assign # 2 dqs_iodelay = dqs_iobuf; |
assign # 2 dqs_n_iodelay = dqs_n_iobuf; |
|
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// BUFIO (?) |
`endif // DEL_DQS_DATA_CAPTURE_2 |
|
`endif // XILINX |
|
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487,26 → 375,43
assign rx_dat_o = dq_rx_reg; |
`endif // INT_CLOCKED_DATA_CAPTURE |
|
`ifdef DEL_DQS_DATA_CAPTURE_1 |
// Delay DQS |
// DDR FF |
`endif // DEL_DQS_DATA_CAPTURE_1 |
|
`ifdef DQS_DATA_CAPTURE |
|
`ifdef DEL_DQS_DATA_CAPTURE_2 |
// DDR data to IOBUFFER |
// Delay data (?) |
// DDR FF |
// Rise & fall clocked FF |
// Fall sync FF |
// Mux |
// DDR DQS to IODUFDS |
// Delay DQS |
// BUFIO (?) |
`endif // DEL_DQS_DATA_CAPTURE_2 |
wire [1:0] dqs_iodelay, dqs_n_iodelay; |
|
// Delay DQS |
assign # 2 dqs_iodelay = dqs_io; |
assign # 2 dqs_n_iodelay = dqs_n_io; |
|
// IDDR FF |
generate |
for (i=0; i<16; i=i+1) begin:iddr_dq |
ddr_ff_in ddr_ff_in_inst_0 ( |
.Q0(dq_rx[i]), |
.Q1(dq_rx[i+16]), |
.C0(dqs_n_iodelay[0]), |
.C1(dqs_iodelay[0]), |
.CE(1'b1), |
.D(dq_io[i]), |
.R(rst), |
.S(1'b0)); |
end |
endgenerate |
|
// Data to Rx FIFO |
always @ (posedge clk_180 or posedge rst) |
if (rst) |
dq_rx_reg <= 32'h0; |
else |
dq_rx_reg <= dq_rx; |
|
assign rx_dat_o = dq_rx_reg; |
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`endif // DQS_DATA_CAPTURE |
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`endif // ALTERA |
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endmodule // versatile_mem_ctrl_ddr |
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/versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_defines.v
4,9 → 4,8
//`define GENERIC_PRIMITIVES |
//`define SDR_16 |
`define DDR_16 |
`define INT_CLOCKED_DATA_CAPTURE |
//`define DEL_DQS_DATA_CAPTURE_1 |
//`define DEL_DQS_DATA_CAPTURE_2 |
//`define INT_CLOCKED_DATA_CAPTURE |
`define DQS_DATA_CAPTURE |
|
`define PORT0 |
`define PORT1 |
/versatile_mem_ctrl/trunk/rtl/verilog/sdr_16.v
308,7 → 308,7
|
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// Write-domain to read-domain synchronizer |
always @ (posedge wclk or posedge rst) |
always @ (posedge rclk or posedge rst) |
if (rst) |
{wptr2,wptr1} <= {4'b0000,4'b0000}; |
else |
/versatile_mem_ctrl/trunk/rtl/verilog/dcm_pll.v
140,17 → 140,17
.clk1_divide_by(1), |
.clk1_duty_cycle(50), |
.clk1_multiply_by(1), |
.clk1_phase_shift("1250"), |
.clk1_phase_shift("2000"), |
.clk2_divide_by(1), |
.clk2_duty_cycle(50), |
.clk2_multiply_by(1), |
.clk2_phase_shift("2500"), |
.clk2_phase_shift("4000"), |
.clk3_divide_by(1), |
.clk3_duty_cycle(50), |
.clk3_multiply_by(1), |
.clk3_phase_shift("3750"), |
.clk3_phase_shift("6000"), |
.compensate_clock("CLK0"), |
.inclk0_input_frequency(5000), |
.inclk0_input_frequency(8000), |
.intended_device_family("Stratix III"), |
.lpm_hint("UNUSED"), |
.lpm_type("altpll"), |
/versatile_mem_ctrl/trunk/sim/rtl_sim/bin/wave_ddr.do
133,45 → 133,44
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[2]} |
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[1]} |
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[0]} |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/rst |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/clk |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -divider State |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -divider Input |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/bl_ack |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/burst_adr |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/fifo_empty |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/fifo_re_d |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/fifo_sel |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/next_row_open |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/ref_delay_ack |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/ref_req |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/stall |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic -radix hexadecimal {/versatile_mem_ctrl_tb/dut/ddr_16_0/tx_fifo_dat_o[5]} |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/ddr_16_0/tx_fifo_dat_o |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -divider Output |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/ddr_16_0/a |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/adr_init |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/bl_en |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/close_cur_row |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/cmd |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/cs_n |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/fifo_re |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/open_ba |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/open_cur_row |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/open_row |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/read |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/ref_ack |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/ref_delay |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/state_idle |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/write |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -divider {Other usefull signals (Non-FSM)} |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/fifo_sel_domain_reg |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_dat_o |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/state_idle |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo_re_i |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo_re |
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/burst_mask |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/rst |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/clk |
add wave -noupdate -group {MAIN STATE MACHINE} -divider State |
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename |
add wave -noupdate -group {MAIN STATE MACHINE} -divider Input |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/bl_ack |
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/burst_adr |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/fifo_empty |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/fifo_re_d |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/next_row_open |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/ref_delay_ack |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/ref_req |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/stall |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic -radix hexadecimal {/versatile_mem_ctrl_tb/dut/ddr_16_0/tx_fifo_dat_o[5]} |
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/ddr_16_0/tx_fifo_dat_o |
add wave -noupdate -group {MAIN STATE MACHINE} -divider Output |
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/ddr_16_0/a |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/adr_init |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/bl_en |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/close_cur_row |
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/cmd |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/cs_n |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/fifo_re |
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/open_ba |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/open_cur_row |
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/open_row |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/read |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/ref_ack |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/ref_delay |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/state_idle |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/write |
add wave -noupdate -group {MAIN STATE MACHINE} -divider {Other usefull signals (Non-FSM)} |
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/fifo_sel_domain_reg |
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_dat_o |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/state_idle |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo_re_i |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo_re |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/burst_mask |
add wave -noupdate -group {BURST ADDRESS} -divider State |
add wave -noupdate -group {BURST ADDRESS} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename |
add wave -noupdate -group {BURST ADDRESS} -divider {Burst Address} |
298,7 → 297,6
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/cas_pad_o |
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/we_pad_o |
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/odt_pad_o |
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/wb_rst |
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_en |
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dqm_en |
add wave -noupdate -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/tx_dat_i |
314,27 → 312,27
add wave -noupdate -group {OPEN BANKS & ROWS} -format Literal /versatile_mem_ctrl_tb/dut/next_row |
add wave -noupdate -group {OPEN BANKS & ROWS} -format Literal /versatile_mem_ctrl_tb/dut/next_bank |
add wave -noupdate -group {OPEN BANKS & ROWS} -format Logic /versatile_mem_ctrl_tb/dut/next_row_open |
add wave -noupdate -expand -group {FIFO Pointers & Flags} -divider FIFO_0_1 |
add wave -noupdate -expand -group {FIFO Pointers & Flags} -divider FIFO_0_0 |
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Literal -radix unsigned {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_adr[0]/egresscmp/wptr_bin} |
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Literal -radix unsigned {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_adr[0]/egresscmp/rptr_bin} |
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Literal -radix unsigned {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_adr[0]/egresscmp/ptr_diff} |
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_adr[0]/egresscmp/fifo_empty} |
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_adr[0]/egresscmp/fifo_full} |
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_adr[0]/egresscmp/fifo_flag} |
add wave -noupdate -expand -group {FIFO Pointers & Flags} -divider FIFO_1_1 |
add wave -noupdate -expand -group {FIFO Pointers & Flags} -divider FIFO_1_0 |
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Literal -radix unsigned {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/wptr_bin} |
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Literal -radix unsigned {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/rptr_bin} |
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Literal -radix unsigned {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/ptr_diff} |
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/fifo_empty} |
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/fifo_full} |
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/fifo_flag} |
add wave -noupdate -expand -group {FIFO Pointers & Flags} -divider {FIFO Flags on top-level} |
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_empty |
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_flag |
add wave -noupdate -group {FIFO Pointers & Flags} -divider FIFO_0_1 |
add wave -noupdate -group {FIFO Pointers & Flags} -divider FIFO_0_0 |
add wave -noupdate -group {FIFO Pointers & Flags} -format Literal -radix unsigned {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_adr[0]/egresscmp/wptr_bin} |
add wave -noupdate -group {FIFO Pointers & Flags} -format Literal -radix unsigned {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_adr[0]/egresscmp/rptr_bin} |
add wave -noupdate -group {FIFO Pointers & Flags} -format Literal -radix unsigned {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_adr[0]/egresscmp/ptr_diff} |
add wave -noupdate -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_adr[0]/egresscmp/fifo_empty} |
add wave -noupdate -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_adr[0]/egresscmp/fifo_full} |
add wave -noupdate -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_adr[0]/egresscmp/fifo_flag} |
add wave -noupdate -group {FIFO Pointers & Flags} -divider FIFO_1_1 |
add wave -noupdate -group {FIFO Pointers & Flags} -divider FIFO_1_0 |
add wave -noupdate -group {FIFO Pointers & Flags} -format Literal -radix unsigned {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/wptr_bin} |
add wave -noupdate -group {FIFO Pointers & Flags} -format Literal -radix unsigned {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/rptr_bin} |
add wave -noupdate -group {FIFO Pointers & Flags} -format Literal -radix unsigned {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/ptr_diff} |
add wave -noupdate -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/fifo_empty} |
add wave -noupdate -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/fifo_full} |
add wave -noupdate -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/fifo_flag} |
add wave -noupdate -group {FIFO Pointers & Flags} -divider {FIFO Flags on top-level} |
add wave -noupdate -group {FIFO Pointers & Flags} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_empty |
add wave -noupdate -group {FIFO Pointers & Flags} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_flag |
TreeUpdate [SetDefaultTree] |
WaveRestoreCursors {{Cursor 1} {300596000 ps} 0} |
WaveRestoreCursors {{Cursor 1} {301340000 ps} 0} |
configure wave -namecolwidth 441 |
configure wave -valuecolwidth 151 |
configure wave -justifyvalue left |
349,4 → 347,4
configure wave -timeline 0 |
configure wave -timelineunits ns |
update |
WaveRestoreZoom {300581153 ps} {300790631 ps} |
WaveRestoreZoom {300901312 ps} {301778688 ps} |