URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 82 to Rev 83
- ↔ Reverse comparison
Rev 82 → Rev 83
/trunk/or1ksim/cpu/or32/execute.c
41,6 → 41,9
/* Instruction queue */ |
struct iqueue_entry iqueue[20]; |
|
/* Is current insn in execution a delay insn? */ |
int delay_insn; |
|
/* Benchmark multi issue execution */ |
int multissue[20]; |
int supercycles; |
61,7 → 64,7
unsigned long pc_phy; |
|
/* Temporary program counter */ |
unsigned long pctemp; |
unsigned long pcnext; |
|
/* CCR */ |
int flag; |
312,8 → 315,8
memset(iqueue, 0, sizeof(iqueue)); |
memset(icomplet, 0, sizeof(icomplet)); |
mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_EXR); |
pctemp = eval_label("_main"); |
pc = pctemp; |
pcnext = eval_label("_main"); |
pc = pcnext; |
pc_phy = pc; |
debug("reset ..."); |
set_reg32(STACK_REG, (MEMORY_START + MEMORY_LEN) - STACK_SIZE); |
339,8 → 342,8
iqueue[0].dependsrc2 = NULL; |
|
/* Increment program counter. */ |
pc = pctemp; |
pctemp += 4; |
pc = pcnext; |
pcnext += 4; |
|
/* Simulate instruction cache and IMMU. */ |
pc_phy = simulate_ic_mmu_fetch(pc); |
360,7 → 363,8
|
void decode(struct iqueue_entry *cur) |
{ |
|
int next_delay_insn = 0; |
|
cur->dependdst = cur->op1; |
cur->dependsrc1 = cur->op2; /* for calculating register */ |
cur->dependsrc2 = cur->op3; /* dependency */ |
527,39 → 531,44
char *endptr; |
strtol(cur->op1, &endptr, 0); |
if (*endptr == '\0') { |
debug("\nl.j relative: pc=%x pctemp=%x\n", pc, pctemp); |
pctemp = pc + (signed)eval_operand(cur->op1) * 4 - 4; |
debug("\nl.j relative: pc=%x pcnext=%x\n", pc, pcnext); |
pcnext = pc + (signed)eval_operand(cur->op1) * 4 - 4; |
} else |
pctemp = eval_operand(cur->op1); |
pcnext = eval_operand(cur->op1); |
cur->func_unit = jump; |
next_delay_insn = 1; |
} else |
if (CURINSN("l.jal")) { |
char *endptr; |
strtol(cur->op1, &endptr, 0); |
if (*endptr == '\0') { |
debug("\nl.jal relative: pc=%x pctemp=%x\n", pc, pctemp); |
pctemp = pc + (signed)eval_operand(cur->op1) * 4 - 4; |
debug("\nl.jal relative: pc=%x pcnext=%x\n", pc, pcnext); |
pcnext = pc + (signed)eval_operand(cur->op1) * 4 - 4; |
} else |
pctemp = eval_operand(cur->op1); |
pcnext = eval_operand(cur->op1); |
|
cur->func_unit = jump; |
set_reg32(LINK_REG, pc + 4); |
slp_func_entry(); |
next_delay_insn = 1; |
} else |
if (CURINSN("l.jalr")) { |
cur->func_unit = jump; |
pctemp = eval_operand(cur->op1); |
pcnext = eval_operand(cur->op1); |
set_reg32(LINK_REG, pc + 4); |
slp_func_exit(); |
next_delay_insn = 1; |
} else |
if (CURINSN("l.jr")) { |
cur->func_unit = jump; |
pctemp = eval_operand(cur->op1); |
pcnext = eval_operand(cur->op1); |
next_delay_insn = 1; |
} else |
if (CURINSN("l.rfe")) { |
cur->func_unit = exception; |
pctemp = mfspr(SPR_EPCR_BASE); |
pcnext = mfspr(SPR_EPCR_BASE); |
mtspr(SPR_SR, mfspr(SPR_ESR_BASE)); |
next_delay_insn = 1; |
} else |
if (CURINSN("l.nop")) { |
cur->func_unit = nop; |
581,14 → 590,15
|
strtol(cur->op1, &endptr, 0); |
if (*endptr == '\0') { |
debug("\nl.bnf relative: pc=%x pctemp=%x\n", pc, pctemp); |
pctemp = pc + (signed)eval_operand(cur->op1) * 4 - 4; |
debug("\nl.bnf relative: pc=%x pcnext=%x\n", pc, pcnext); |
pcnext = pc + (signed)eval_operand(cur->op1) * 4 - 4; |
} else |
pctemp = eval_operand(cur->op1); |
pcnext = eval_operand(cur->op1); |
|
mstats.beqz.taken++; |
bpb_update(cur->insn_addr, 1); |
btic_update(pctemp); |
btic_update(pcnext); |
next_delay_insn = 1; |
} else { |
if (eval_operand(cur->op1) >= pc) |
mstats.sbp_bnf.correct++; |
610,16 → 620,17
|
strtol(cur->op1, &endptr, 0); |
if (*endptr == '\0') { |
debug("\nl.bf relative: pc=%x pctemp=%x\n", pc, pctemp); |
pctemp = pc + (signed)eval_operand(cur->op1) * 4 - 4; |
debug("\nl.bf relative: pc=%x pcnext=%x\n", pc, pcnext); |
pcnext = pc + (signed)eval_operand(cur->op1) * 4 - 4; |
} else |
pctemp = eval_operand(cur->op1); |
pcnext = eval_operand(cur->op1); |
|
if (eval_operand(cur->op1) < pc) |
mstats.sbp_bf.correct++; |
mstats.bnez.taken++; |
bpb_update(cur->insn_addr, 1); |
btic_update(pctemp); |
btic_update(pcnext); |
next_delay_insn = 1; |
} else { |
mstats.bnez.nottaken++; |
bpb_update(cur->insn_addr, 0); |
780,15 → 791,18
/* Dynamic, single stats. */ |
addsstats(iqueue[0].insn, 1, 0); |
|
if ((cur->func_unit == branch) || (cur->func_unit == jump)) |
storecycles += 0; |
|
if (cur->func_unit == store) |
storecycles += 0; |
|
if (cur->func_unit == load) |
loadcycles += 0; |
|
/* |
if ((icomplet[0].func_unit == load) && check_depend()) |
loadcycles++; |
|
*/ |
/* Pseudo multiple issue benchmark */ |
if ((multissue[cur->func_unit] < 1) || (check_depend()) |
|| (issued_per_cycle < 1) |
815,7 → 829,9
} |
multissue[cur->func_unit]--; |
issued_per_cycle--; |
|
|
delay_insn = next_delay_insn; |
|
return; |
} |
|
889,7 → 905,7
printf("Additional LOAD CYCLES: %u STORE CYCLES: %u\n", loadcycles, storecycles); |
printf("l.nop count: %u maxgap: %u\nPC:", nops, nop_maxperiod); |
dumpmemory(pc, pc + 4); |
printf(" (next insn)"); |
printf(" (next insn) %s", (delay_insn?"(delay insn)":"")); |
for(i = 0; i < MAX_GPRS; i++) { |
if (i % 4 == 0) |
printf("\n"); |
/trunk/or1ksim/cpu/common/execute.h
26,4 → 26,4
extern void dumpreg(); |
extern void set_reg32(char *regstr, unsigned long value); |
|
extern unsigned long pctemp; |
extern unsigned long pcnext; |