URL
https://opencores.org/ocsvn/pci/pci/trunk
Subversion Repositories pci
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- This comparison shows the changes necessary to convert path
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- from Rev 82 to Rev 83
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Rev 82 → Rev 83
/trunk/rtl/verilog/pci_parity_check.v
42,6 → 42,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2003/01/27 16:49:31 mihad |
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. |
// |
// Revision 1.4 2002/08/13 11:03:53 mihad |
// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image |
// |
143,8 → 146,8
/*======================================================================================================================= |
CBE lines' parity is needed for overall parity calculation |
=======================================================================================================================*/ |
wire par_cbe_out = pci_cbe_out_in[3] ^^ pci_cbe_out_in[2] ^^ pci_cbe_out_in[1] ^^ pci_cbe_out_in[0] ; |
wire par_cbe_in = pci_cbe_reg_in[3] ^^ pci_cbe_reg_in[2] ^^ pci_cbe_reg_in[1] ^^ pci_cbe_reg_in[0] ; |
wire par_cbe_out = pci_cbe_out_in[3] ^ pci_cbe_out_in[2] ^ pci_cbe_out_in[1] ^ pci_cbe_out_in[0] ; |
wire par_cbe_in = pci_cbe_reg_in[3] ^ pci_cbe_reg_in[2] ^ pci_cbe_reg_in[1] ^ pci_cbe_reg_in[0] ; |
|
/*======================================================================================================================= |
Parity generator - parity is generated and assigned to output on every clock edge. PAR output enable is active |
153,16 → 156,16
=======================================================================================================================*/ |
|
// generate appropriate par signal |
wire data_par = (pci_ad_out_in[31] ^^ pci_ad_out_in[30] ^^ pci_ad_out_in[29] ^^ pci_ad_out_in[28]) ^^ |
(pci_ad_out_in[27] ^^ pci_ad_out_in[26] ^^ pci_ad_out_in[25] ^^ pci_ad_out_in[24]) ^^ |
(pci_ad_out_in[23] ^^ pci_ad_out_in[22] ^^ pci_ad_out_in[21] ^^ pci_ad_out_in[20]) ^^ |
(pci_ad_out_in[19] ^^ pci_ad_out_in[18] ^^ pci_ad_out_in[17] ^^ pci_ad_out_in[16]) ^^ |
(pci_ad_out_in[15] ^^ pci_ad_out_in[14] ^^ pci_ad_out_in[13] ^^ pci_ad_out_in[12]) ^^ |
(pci_ad_out_in[11] ^^ pci_ad_out_in[10] ^^ pci_ad_out_in[9] ^^ pci_ad_out_in[8]) ^^ |
(pci_ad_out_in[7] ^^ pci_ad_out_in[6] ^^ pci_ad_out_in[5] ^^ pci_ad_out_in[4]) ^^ |
(pci_ad_out_in[3] ^^ pci_ad_out_in[2] ^^ pci_ad_out_in[1] ^^ pci_ad_out_in[0]) ; |
wire data_par = (pci_ad_out_in[31] ^ pci_ad_out_in[30] ^ pci_ad_out_in[29] ^ pci_ad_out_in[28]) ^ |
(pci_ad_out_in[27] ^ pci_ad_out_in[26] ^ pci_ad_out_in[25] ^ pci_ad_out_in[24]) ^ |
(pci_ad_out_in[23] ^ pci_ad_out_in[22] ^ pci_ad_out_in[21] ^ pci_ad_out_in[20]) ^ |
(pci_ad_out_in[19] ^ pci_ad_out_in[18] ^ pci_ad_out_in[17] ^ pci_ad_out_in[16]) ^ |
(pci_ad_out_in[15] ^ pci_ad_out_in[14] ^ pci_ad_out_in[13] ^ pci_ad_out_in[12]) ^ |
(pci_ad_out_in[11] ^ pci_ad_out_in[10] ^ pci_ad_out_in[9] ^ pci_ad_out_in[8]) ^ |
(pci_ad_out_in[7] ^ pci_ad_out_in[6] ^ pci_ad_out_in[5] ^ pci_ad_out_in[4]) ^ |
(pci_ad_out_in[3] ^ pci_ad_out_in[2] ^ pci_ad_out_in[1] ^ pci_ad_out_in[0]) ; |
|
wire par_out_only = data_par ^^ par_cbe_out ; |
wire par_out_only = data_par ^ par_cbe_out ; |
|
pci_par_crit par_gen |
( |
189,14 → 192,14
&& ((pci_irdy_en_in && ~pci_trdy_reg_in) || // and master is driving irdy and target is signaling ready |
(pci_trdy_en_in && ~pci_irdy_reg_in)) ; // or target is driving trdy and master is signaling ready |
|
wire data_in_par = (pci_ad_reg_in[31] ^^ pci_ad_reg_in[30] ^^ pci_ad_reg_in[29] ^^ pci_ad_reg_in[28]) ^^ |
(pci_ad_reg_in[27] ^^ pci_ad_reg_in[26] ^^ pci_ad_reg_in[25] ^^ pci_ad_reg_in[24]) ^^ |
(pci_ad_reg_in[23] ^^ pci_ad_reg_in[22] ^^ pci_ad_reg_in[21] ^^ pci_ad_reg_in[20]) ^^ |
(pci_ad_reg_in[19] ^^ pci_ad_reg_in[18] ^^ pci_ad_reg_in[17] ^^ pci_ad_reg_in[16]) ^^ |
(pci_ad_reg_in[15] ^^ pci_ad_reg_in[14] ^^ pci_ad_reg_in[13] ^^ pci_ad_reg_in[12]) ^^ |
(pci_ad_reg_in[11] ^^ pci_ad_reg_in[10] ^^ pci_ad_reg_in[9] ^^ pci_ad_reg_in[8]) ^^ |
(pci_ad_reg_in[7] ^^ pci_ad_reg_in[6] ^^ pci_ad_reg_in[5] ^^ pci_ad_reg_in[4]) ^^ |
(pci_ad_reg_in[3] ^^ pci_ad_reg_in[2] ^^ pci_ad_reg_in[1] ^^ pci_ad_reg_in[0]) ; |
wire data_in_par = (pci_ad_reg_in[31] ^ pci_ad_reg_in[30] ^ pci_ad_reg_in[29] ^ pci_ad_reg_in[28]) ^ |
(pci_ad_reg_in[27] ^ pci_ad_reg_in[26] ^ pci_ad_reg_in[25] ^ pci_ad_reg_in[24]) ^ |
(pci_ad_reg_in[23] ^ pci_ad_reg_in[22] ^ pci_ad_reg_in[21] ^ pci_ad_reg_in[20]) ^ |
(pci_ad_reg_in[19] ^ pci_ad_reg_in[18] ^ pci_ad_reg_in[17] ^ pci_ad_reg_in[16]) ^ |
(pci_ad_reg_in[15] ^ pci_ad_reg_in[14] ^ pci_ad_reg_in[13] ^ pci_ad_reg_in[12]) ^ |
(pci_ad_reg_in[11] ^ pci_ad_reg_in[10] ^ pci_ad_reg_in[9] ^ pci_ad_reg_in[8]) ^ |
(pci_ad_reg_in[7] ^ pci_ad_reg_in[6] ^ pci_ad_reg_in[5] ^ pci_ad_reg_in[4]) ^ |
(pci_ad_reg_in[3] ^ pci_ad_reg_in[2] ^ pci_ad_reg_in[1] ^ pci_ad_reg_in[0]) ; |
|
//wire perr = (cbe_par_reg ^ pci_par_in ^ data_in_par) ; |
wire perr ; |
208,7 → 211,7
// parity error output assignment |
//assign pci_perr_out = ~(perr && perr_generate) ; |
|
wire non_critical_par = par_cbe_in ^^ data_in_par ; |
wire non_critical_par = par_cbe_in ^ data_in_par ; |
|
pci_perr_crit perr_crit_gen |
( |
/trunk/rtl/verilog/pci_serr_en_crit.v
42,6 → 42,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2003/01/27 16:49:31 mihad |
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. |
// |
// Revision 1.3 2002/02/01 15:25:13 mihad |
// Repaired a few bugs, updated specification, added test bench files and design document |
// |
76,6 → 79,6
pci_par_in, |
serr_generate_in ; |
|
assign serr_en_out = serr_generate_in && ( non_critical_par_in ^^ pci_par_in ) ; |
assign serr_en_out = serr_generate_in && ( non_critical_par_in ^ pci_par_in ) ; |
|
endmodule |
/trunk/rtl/verilog/pci_perr_crit.v
42,6 → 42,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2003/01/27 16:49:31 mihad |
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. |
// |
// Revision 1.3 2002/02/01 15:25:13 mihad |
// Repaired a few bugs, updated specification, added test bench files and design document |
// |
78,7 → 81,7
pci_par_in, |
perr_generate_in ; |
|
assign perr_out = (non_critical_par_in ^^ pci_par_in) && perr_generate_in ; |
assign perr_out = (non_critical_par_in ^ pci_par_in) && perr_generate_in ; |
assign perr_n_out = ~perr_out ; |
|
endmodule |
/trunk/rtl/verilog/pci_serr_crit.v
42,6 → 42,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2003/01/27 16:49:31 mihad |
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. |
// |
// Revision 1.3 2002/02/01 15:25:13 mihad |
// Repaired a few bugs, updated specification, added test bench files and design document |
// |
76,6 → 79,6
pci_par_in, |
serr_check_in ; |
|
assign serr_out = ~(serr_check_in && ( non_critical_par_in ^^ pci_par_in )) ; |
assign serr_out = ~(serr_check_in && ( non_critical_par_in ^ pci_par_in )) ; |
|
endmodule |
/trunk/rtl/verilog/pci_par_crit.v
42,6 → 42,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2003/01/27 16:49:31 mihad |
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. |
// |
// Revision 1.3 2002/02/01 15:25:12 mihad |
// Repaired a few bugs, updated specification, added test bench files and design document |
// |
79,6 → 82,6
|
input [3:0] pci_cbe_in ; |
|
assign par_out = pci_cbe_en_in ? par_out_in : ( pci_cbe_in[3] ^^ pci_cbe_in[2] ^^ pci_cbe_in[1] ^^ pci_cbe_in[0] ^^ data_par_in) ; |
assign par_out = pci_cbe_en_in ? par_out_in : ( pci_cbe_in[3] ^ pci_cbe_in[2] ^ pci_cbe_in[1] ^ pci_cbe_in[0] ^ data_par_in) ; |
|
endmodule |
/trunk/rtl/verilog/pci_perr_en_crit.v
42,6 → 42,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2003/01/27 16:49:31 mihad |
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. |
// |
// Revision 1.3 2002/02/01 15:25:13 mihad |
// Repaired a few bugs, updated specification, added test bench files and design document |
// |
83,7 → 86,7
perr_generate_in, |
par_err_response_in ; |
|
wire perr = par_err_response_in && perr_generate_in && ( non_critical_par_in ^^ pci_par_in ) ; |
wire perr = par_err_response_in && perr_generate_in && ( non_critical_par_in ^ pci_par_in ) ; |
|
// PERR# is enabled for two clocks after parity error is detected - one cycle active, another inactive |
reg perr_en_reg_out ; |